TSV7721IYLT [STMICROELECTRONICS]
High bandwidth (22 MHz) low offset (200 μV) 5 V op amp;
| 型号： | TSV7721IYLT |
| 厂家： | 
ST |
| 描述： | High bandwidth (22 MHz) low offset (200 μV) 5 V op amp |
| 文件： | 总40页 (文件大小：4982K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSV7721, TSV7722, TSV7723
Datasheet
High bandwidth (22 MHz) low offset (200 μV) 5 V op amp
Features
•
•
•
•
•
•
•
•
•
Gain bandwidth product 22 MHz, unity gain stable
High accuracy input offset voltage: 50 µV typ., 200 µV max.
Low input bias current: 2 pA typ.
TSV7722
DFN8 2x2 mm
TSV7721
SOT23 -5
Low input voltage noise density: 7 nV/√Hz
Wide supply voltage range: 1.8 V to 5.5 V
Output rail-to-rail
Input common-mode range includes low rail
Automotive grade and shutdown versions available
Benefits:
–
–
High frequency signal conditioning
TSV7723
MiniSO10
TSV7722
MiniSO8
Optimized accuracy for low-side current sensing
Applications
TSV7722
SO8
•
•
•
•
Low-side current measurement
Photodiode amplifiers
Automotive current measurement and sensor signal conditioning
Strain gauges signal conditioning
Description
The TSV7721, TSV7722 and TSV7723 are single and dual 22 MHz-bandwidth unity-
gain-stable amplifiers. The input offset voltage of 200 µV max. (50 µV typ.) at room
temperature, optimized for common-mode close to ground makes the TSV772x ideal
for low-side current measurements.
Maturity
status link
Package
The TSV772x can operate from 1.8 V to 5.5 V single supply and it is fully specified on
a load of 47 pF, therefore allowing easy usage as A/D converters input buffer.
1
1
2
2
2
2
2
2
SOT23-5
SOT23-5
DFN8
TSV7721
The TSV772x series offers rail-to-rail output, excellent speed/power consumption
ratio, and 22 MHz gain bandwidth product, while consuming just 1.7 mA at 5 V.
•
The devices also feature an ultra-low input bias current that enables connection to
photodiodes and other sensors where current is the key value to be measured.
MiniSO8
SO8
TSV7722
TSV7723
These features make the TSV772x series ideal for high-accuracy, high-bandwidth
sensor interfaces.
•
•
MiniSO8
SO8
MiniSO10
Related products
Rail-to-rail amplifier with
higher GBW 50 MHz
TSV792
22 MHz amplifier with 36 V
supply voltage
TSB7192
DS13614 - Rev 3 - May 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
TSV7721, TSV7722, TSV7723
Pin description
1
Pin description
1.1
TSV7721 single operational amplifier
Figure 1. Pin connections (top view)
OUT
VCC-
IN+
1
2
3
5
4
VCC+
IN-
SOT23-5
Table 1. Pin description
Pin n°
Pin name
Description
1
2
3
4
5
OUT
VCC-
IN+
Output channel
Negative supply voltage
Non-inverting input channel
Inverting input channel
Positive supply voltage
IN-
VCC+
DS13614 - Rev 3
page 2/40
TSV7721, TSV7722, TSV7723
TSV7722 dual operational amplifier
1.2
TSV7722 dual operational amplifier
Figure 2. Pin connections (top view)
OUT1
IN1-
1
2
3
4
8
7
6
5
VCC+
OUT2
IN2-
OUT1
IN1-
1
2
3
4
8
7
6
5
VCC+
OUT2
IN2-
NC
IN1+
VCC-
IN1+
VCC-
IN2+
IN2+
MiniSO8 and SO8
DFN8 2 x 2 mm(1)
1. The exposed pad of the DFN8 2x2 can be connected to VCC- or left floating.
Table 2. Pin description
Pin n°
Pin name
OUT1
IN1-
Description
1
2
3
4
5
6
7
8
Output channel 1
Inverting input channel 1
Non-inverting input channel 1
Negative supply voltage
Non-inverting input channel 2
Inverting input channel 2
Output channel 2
IN1+
VCC-
IN2+
IN2-
OUT2
VCC+
Positive supply voltage
DS13614 - Rev 3
page 3/40
TSV7721, TSV7722, TSV7723
TSV7723 dual operational amplifier with shutdown option
1.3
TSV7723 dual operational amplifier with shutdown option
Figure 3. Pin connections (top view)
Table 3. Pin description
Pin n°
Pin name
Description
1
2
3
4
OUT1
IN1-
Output channel 1
Inverting input channel 1
Non-inverting input channel 1
Negative supply voltage
IN1+
VCC-
Enable input channel 1
5
6
EN1
EN2
(amplifier in shutdown mode when EN pin connected to VCC-)
Enable input channel 2
(amplifier in shutdown mode when EN pin connected to VCC-)
7
8
IN2+
IN2-
Non-inverting input channel 2
Inverting input channel 2
Output channel 2
9
OUT2
VCC+
10
Positive supply voltage
DS13614 - Rev 3
page 4/40
TSV7721, TSV7722, TSV7723
Absolute maximum ratings and operating conditions
2
Absolute maximum ratings and operating conditions
Table 4. Absolute maximum ratings
Parameter
Symbol
Value
-0.3 to 6.0
± VCC
Unit
V
Supply voltage (referred to VCC- pin) (1)
V
CC
Differential input voltage (2)
Input pins input voltage (3)
Input pins input current (4)
Storage temperature
V
V
id
V
IN
V
CC
- - 0.3 V to V
+ 0.3 V
V
CC+
I
± 10
mA
°C
IN
T
-65 to 150
stg
Thermal resistance junction-to-ambient (5)
SOT23-5
250
76
DFN8 (2 mm x 2 mm)
MiniSO8
R
th-ja
°C / W
127
113
113
150
4
MiniSO10
SO8
T
Maximum junction temperature
°C
kV
kV
j
HBM: human body model (6)
ESD
CDM: charged device model (7)
1.5
1. All voltage values, except differential voltage, are with respect to VCC- pin.
2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal.
3. Vcc - Vin must not exceed 6 V, Vin must not exceed 6 V.
4. Input current must be limited by a resistor in series with the inputs.
5. Rth are typical values.
6. Human body model: the test HBM is done in accordance with the standards ESDA-JS-001-2017 and Q100-002
7. Charged device model: the test CDM is done in accordance with the standards ESDA-JS-002-2018 and Q100-011
Table 5. Operating conditions
Symbol
Parameter
Min.
Max.
Value
V
V
Supply voltage
1.8
5.5
CC
V
V
– 0.1
V
– 1.1
CC+
Common-mode input voltage range
Operating free air temperature range
V
icm
CC-
T
oper
-40
125
°C
DS13614 - Rev 3
page 5/40
TSV7721, TSV7722, TSV7723
Electrical characteristics
3
Electrical characteristics
Table 6. Electrical characteristics at VCC+ = 5 V, with VCC- = 0 V, Vicm = VCC / 2, T = 25°C, and OUT pin connected to VCC
2 through RL = 10 kΩ (unless otherwise specified)
/
Symbol
Parameter
Conditions
DC Performance
Min.
Typ.
Max.
Unit
T = 25°C
±50
±250
±650
±4
V
Input offset voltage (V
= 0 V)
µV
µV/°C
pA
io
icm
-40°C < T < 125°C
-40°C < T < 125°C
T = 25°C
∆V /∆T
Input offset voltage drift (V
= 0 V)
icm
io
2
I
ib
Input bias current (V
= V /2)
OUT
CC
-40°C < T < 125°C
T = 25°C
75
1
I
Input offset current (V
= V /2)
pA
dB
io
OUT
CC
-40°C < T < 125°C
T = 25°C
20
99
Common-mode rejection ratio
20.log(∆V /∆V ), V = 0 V to
76
74
75
60
85
80
CMR1
CMR2
SVR
icm
io
icm
-40°C < T < 125°C
T = 25°C
V
1.1 V, R > 1 MΩ
L
CC-
Common-mode rejection ratio
20.log(∆V /∆Vio),
dB
icm
-40°C < T < 125°C
T = 25°C
V
= -0.1 V to V - 1.1 V, R > 1 MΩ
CC L
icm
Supply voltage rejection ratio
20.log(∆V /∆V ), V = 1.8 V to 5.5 V,
108
130
dB
dB
CC
io
CC
-40°C < T < 125°C
V
icm
= 0 V, R > 1 MΩ
L
T = 25°C
111
106
Large signal voltage gain V
= 0.3 V to
OUT
A
VD
(V
0.3 V)
CC-
-40°C < T < 125°C
T = 25°C
High level output voltage
(V = V - V
15
25
15
25
V
OH
)
OUT
-40°C < T < 125°C
T = 25°C
OH
CC
mV
V
Low level output voltage
OL
-40°C < T < 125°C
T = 25°C
50
45
45
40
70
65
I
(V
= V
)
CC
sink
OUT
-40°C < T < 125°C
T = 25°C
I
mA
mA
OUT
I
(V
= 0 V)
OUT
source
-40°C < T < 125°C
T = 25°C
1.7
2.2
2.5
Supply current (per channel, V
= V /2,
CC
OUT
I
CC
R > 1 MΩ)
L
-40°C < T < 125°C
AC Performance
GBW
Gain bandwidth product
Unity gain frequency
Phase margin
15
22
19.5
44
C = 47 pF
L
MHz
F
u
Φ
degrees
dB
m
G
m
Gain margin
8
Slew rate (1)
SR
8
11
V/µs
DS13614 - Rev 3
page 6/40
TSV7721, TSV7722, TSV7723
Electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Overload recovery time: trec is defined as
delay between input voltage edge and V
t
70
ns
rec
OUT
reaching 100 mV from initial value
t
To 0.1%, V = 1 V
in p-p
Settling time
270
13
7
ns
s
f = 1 kHz
e
Equivalent input noise voltage
nV/√Hz
n
f = 10 kHz
Channel separation
C
f = 1 kHz
120
dB
pF
S
(for TSV7722 and TSV7723)
Differential
6
C
in
Input capacitance
Common-mode
4.5
Shutdown feature characteristics (TSV7723 only, op-amp in shutdown mode when EN input is low)
T = 25°C
2.5
50
450
4
Supply current per channel in shutdown
mode V = V / 2, R > 1 MΩ, EN =
nA
I
-40°C < T < 85°C
-40°C < T < 125°C
OUT
CC
L
CC
V
CC-
µA
µs
µs
Amplifier turn-on time (other channel
already on)
t
V
= V - to V - + 0.2 V
CC CC
2
7
on
OUT
OUT
t
V
to 200 mV of final value
Initialization time (both channels off)
EN logic high
init
V
2
IH
V
V
EN logic low
0.8
IL
I
EN = V
EN = V
EN current high
1
IH
CC+
pA
I
EN current low
1
IL
CC-
Output leakage in shutdown mode,
T = 25°C
50
15
pA
nA
I
Oleak
EN = V
-40°C < T < 125°C
CC-
1. Slew rate value is calculated as the average between positive and negative slew rates.
DS13614 - Rev 3
page 7/40
TSV7721, TSV7722, TSV7723
Electrical characteristics
Table 7. Electrical characteristics at VCC+ = 3.3 V, with VCC- = 0 V, Vicm = VCC / 2, T = 25°C, and OUT pin connected to
VCC / 2 through RL = 10 kΩ (unless otherwise specified)
Symbol
Parameter
Conditions
DC Performance
Min.
Typ.
Max.
Unit
T = 25°C
±50
±200
±600
±4
V
Input offset voltage (V
= 0 V)
icm
µV
µV/°C
pA
io
-40°C < T < 125°C
-40°C < T < 125°C
T = 25°C
∆V /∆T Input offset voltage drift (V
= 0 V)
io
icm
1.8
60
1
I
Input bias current (V
= V /2)
ib
io
OUT
CC
-40°C < T < 125°C
T = 25°C
I
Input offset current (V
= V /2)
pA
dB
OUT
CC
-40°C < T < 125°C
T = 25°C
20
96
Common-mode rejection ratio
20.log(∆V /∆V ), V = 0 V to
75
71
73
57
CMR1
CMR2
icm
io
icm
-40°C < T < 125°C
T = 25°C
V
1.1 V, R > 1 MΩ
L
CC-
Common-mode rejection ratio
20.log(∆V /∆Vio), V = - 0.1 V to
dB
dB
icm
icm
-40°C < T < 125°C
V
1.1 V, R > 1 MΩ
L
CC-
Large signal voltage gain V
= 0.3 V to
T = 25°C
107
103
128
OUT
A
VD
(V
0.3 V)
-40°C < T < 125°C
T = 25°C
CC-
High level output voltage
(V = V - V
15
25
15
25
V
OH
)
OUT
-40°C < T < 125°C
T = 25°C
OH
CC
mV
V
Low level output voltage
OL
-40°C < T < 125°C
T = 25°C
50
45
45
40
70
65
I
(V
= V
)
CC
sink
OUT
-40°C < T < 125°C
T = 25°C
I
mA
mA
OUT
I
(V
= 0 V)
OUT
source
-40°C < T < 125°C
T = 25°C
Supply current (per channel, V
= V /2,
1.7
2.2
2.5
OUT
CC
I
CC
R > 1 MΩ)
L
-40°C < T < 125°C
AC Performance
GBW
Gain bandwidth product
Unity gain frequency
Phase margin
14
21
18.5
42
MHz
F
u
Φ
C = 47 pF
degrees
dB
m
L
G
Gain margin
8
11
m
Slew rate (1)
SR
7.7
V/µs
ns
t
To 0.1%, V = 1 V
p-p
Settling time
210
13
7
s
in
f = 1 kHz
f = 10 kHz
f = 1 kHz
e
Equivalent input noise voltage
nV/√Hz
dB
n
C
Channel separation (for TSV7722 and TSV7723)
120
S
Shutdown feature characteristics (TSV7723 only, op-amp in shutdown mode when EN input is low)
T = 25°C 2.5
50
I
Supply current per channel in shutdown mode
nA
CC
DS13614 - Rev 3
page 8/40
TSV7721, TSV7722, TSV7723
Electrical characteristics
Symbol
Parameter
= V / 2, R > 1 MΩ, EN = V
CC-
Conditions
-40°C < T < 85°C
-40°C < T < 125°C
Min.
Typ.
Max.
450
4
Unit
nA
I
V
OUT
CC
CC
L
µA
µs
µs
t
on
V
= V - to V - + 0.2 V
CC CC
Amplifier turn-on time (other channel already on)
Initialization time (both channels off)
EN logic high
2
OUT
OUT
t
V
to 200 mV of final value
11
init
V
2
IH
V
V
I
EN logic low
0.8
IL
EN = V
EN = V
EN current high
1
IH
CC+
pA
I
EN current low
1
IL
CC-
Output leakage in shutdown mode,
T = 25°C
50
15
pA
nA
I
Oleak
EN = V
-40°C < T < 125°C
CC-
1. Slew rate value is calculated as the average between positive and negative slew rates.
DS13614 - Rev 3
page 9/40
TSV7721, TSV7722, TSV7723
Electrical characteristics
Table 8. Electrical characteristics at VCC+ = 1.8 V, with VCC- = 0 V, Vicm = 0.7 V, T = 25°C, and OUT pin connected to VCC
2 through RL = 10 kΩ (unless otherwise specified)
/
Symbol
Parameter
Conditions
DC Performance
Min.
Typ.
Max.
Unit
T = 25°C
±50
±250
±650
±4
V
Input offset voltage (V
= 0 V)
µV
µV/°C
pA
io
icm
-40°C < T < 125°C
-40°C < T < 125°C
T = 25°C
∆V /∆T
Input offset voltage drift (V
= 0 V)
icm
io
1
I
ib
Input bias current (V
= V /2)
OUT
CC
-40°C < T < 125°C
T = 25°C
40
1
I
Input offset current (V
= V /2)
pA
dB
io
OUT
CC
-40°C < T < 125°C
T = 25°C
15
93
Common-mode rejection ratio
20.log(∆V /∆V ), V = 0 V to
72
68
70
52
CMR1
CMR2
icm
io
icm
-40°C < T < 125°C
T = 25°C
V
1.1 V, R > 1 MΩ
L
CC-
Common-mode rejection ratio
20.log(∆V /∆Vio),
dB
dB
icm
-40°C < T < 125°C
V
= - 0.1 V to V
1.1 V, R > 1 MΩ
CC- L
icm
T = 25°C
101
97
122
Large signal voltage gain V
= 0.3 V to
OUT
A
VD
(V
0.3 V)
CC-
-40°C < T < 125°C
T = 25°C
High level output voltage
(V = V - V
15
25
15
25
V
OH
)
OUT
-40°C < T < 125°C
T = 25°C
OH
CC
mV
V
Low level output voltage
OL
-40°C < T < 125°C
T = 25°C
35
20
20
10
42
32
I
I
(V
= V
)
sink
OUT
CC
-40°C < T < 125°C
T = 25°C
I
mA
mA
OUT
(V
= 0 V)
OUT
source
-40°C < T < 125°C
T = 25°C
Supply current (per channel,
= V / 2, R > 1 MΩ)
1.7
2.2
2.5
I
CC
V
-40°C < T < 125°C
AC Performance
OUT
CC
L
GBW
Gain bandwidth product
Unity gain frequency
Phase margin
14
21
18
41
MHz
F
u
Φ
C = 47 pF
degrees
dB
m
L
G
Gain margin
8
11
13
7
m
Slew rate (1)
SR
7.6
V/µs
f = 1 kHz
e
Equivalent input noise voltage
nV/√Hz
dB
n
f = 10 kHz
Channel separation
C
f = 1 kHz
120
S
(for TSV7722 and TSV7723)
Shutdown feature characteristics (TSV7723 only, op-amp in shutdown mode when EN input is low)
T = 25°C
2.5
50
Supply current per channel in shutdown
mode V = V / 2, R > 1 MΩ,
nA
I
CC
OUT
CC
L
-40°C < T < 85°C
450
DS13614 - Rev 3
page 10/40
TSV7721, TSV7722, TSV7723
Electrical characteristics
Symbol
Parameter
Conditions
-40°C < T < 125°C
Min.
Typ.
Max.
Unit
I
EN = V
CC-
CC
4
µA
Amplifier turn-on time (other channel
already on)
t
V
= V - to V - + 0.2 V
CC CC
1.5
38
µs
µs
on
OUT
OUT
t
V
to 200 mV of final value
Initialization time (both channels off)
EN logic high
init
V
1.2
IH
V
V
I
EN logic low
0.6
IL
EN = V
EN = V
EN current high
1
IH
CC+
pA
I
EN current low
1
IL
CC-
Output leakage in shutdown mode,
T = 25°C
50
15
pA
nA
I
Oleak
EN = V
-40°C < T < 125°C
CC-
1. Slew rate value is calculated as the average between positive and negative slew rates.
DS13614 - Rev 3
page 11/40
TSV7721, TSV7722, TSV7723
Typical performance characteristics
4
Typical performance characteristics
RL = 10 kΩ connected to VCC / 2 and CL = 47 pF, unless otherwise specified.
Figure 5. Input offset voltage distribution at VCC = 5 V
Figure 4. Supply current vs. supply voltage
Figure 6. Input offset voltage distribution at VCC = 1.8 V
Figure 7. Input offset voltage vs. temperature at VCC = 5 V
Figure 9. Input offset voltage thermal coeff. at VCC=5 V
Figure 8. Input offset voltage vs. temperature at VCC=1.8 V
DS13614 - Rev 3
page 12/40
TSV7721, TSV7722, TSV7723
Typical performance characteristics
Figure 10. Input offset voltage thermal coefficient at
VCC=1.8 V
Figure 11. Input offset voltage vs. supply voltage
Figure 12. Input offset voltage vs. common-mode voltage
at VCC = 5 V
Figure 13. Input offset voltage vs. common-mode voltage
at VCC = 1.8 V
Figure 15. Input bias current vs. common-mode voltage at
VCC = 5 V
Figure 14. Input bias current vs. temp. at VICM = VCC / 2
DS13614 - Rev 3
page 13/40
TSV7721, TSV7722, TSV7723
Typical performance characteristics
Figure 17. Output current versus output voltage at
VCC=1.8 V
Figure 16. Output current vs. output voltage at VCC = 5 V
Figure 18. Output saturation voltage (VOL) vs. supply
voltage
Figure 19. Output saturation voltage (VOH) vs. supply
voltage
Figure 20. Positive slew rate at VCC = 5 V
Figure 21. Negative slew rate at VCC = 5 V
DS13614 - Rev 3
page 14/40
TSV7721, TSV7722, TSV7723
Typical performance characteristics
Figure 23. Open loop bode diagram at VCC = 5 V
Figure 22. Slew rate vs. VCC
Figure 24. Open loop bode diagram at VCC = 1.8 V
Figure 25. Closed loop bode diagram at VCC = 5 V
Figure 27. Phase margin vs. common-mode voltage and
load current at VCC = 5 V
Figure 26. Closed loop bode diagram at VCC = 1.8 V
DS13614 - Rev 3
page 15/40
TSV7721, TSV7722, TSV7723
Typical performance characteristics
Figure 29. Small step response at VCC = 5 V
Figure 31. Desaturation from low rail at VCC = 5 V
Figure 33. Settling time output high to low at VCC = 5 V
Figure 28. Phase margin vs. capacitive load
Figure 30. Small step response at VCC = 1.8 V
Figure 32. Desaturation from high rail at VCC = 5 V
DS13614 - Rev 3
page 16/40
TSV7721, TSV7722, TSV7723
Typical performance characteristics
Figure 34. Settling time output low to high at VCC = 5 V
Figure 35. Small step overshoot vs. load capacitance
Figure 37. Noise vs. frequency
Figure 36. Linearity vs. load resistance at VCC = 5 V
Figure 39. THD+N vs. frequency
Figure 38. Noise versus time at VCC = 5 V
DS13614 - Rev 3
page 17/40
TSV7721, TSV7722, TSV7723
Typical performance characteristics
Figure 41. CMRR vs. frequency at VCC = 5 V
Figure 40. THD+N vs. output voltage
Figure 42. PSRR vs. frequency at VCC = 5 V
Figure 44. Turn-on time at VCC = 5 V
Figure 43. Supply current vs. supply voltage in shutdown
mode
Figure 45. Turn-on time at VCC = 1.8 V
DS13614 - Rev 3
page 18/40
TSV7721, TSV7722, TSV7723
Application information
5
Application information
5.1
Operating voltages
The TSV7722 device can operate from 1.8 to 5.5 V. The parameters are fully specified at 1.8 V, 3.3 V
and 5 V power supplies. However, the parameters are very stable over the full VCC range and several
characterization curves show the TSV7722 device characteristics over the full operating range. Additionally, the
main specifications are guaranteed in extended temperature range from - 40 to 125 °C.
The TSV7722 device is low rail input, and rail-to-rail output. The common-mode operating range is from Vcc-
-
0.1 V, to Vcc+ - 1.1 V. The op amp Vio is trimmed at Vcc = 3.3 V, Vicm = 0 V, and thus the DC precision is optimized
for operation with Vicm close to Vcc-.
5.2
Input offset voltage drift over the temperature
The maximum input voltage drift variation overtemperature is defined as the offset variation related to the offset
value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and
the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be
compensated during production at application level. The maximum input voltage drift overtemperature enables the
system designer to anticipate the effect of temperature variations.
The maximum input voltage drift overtemperature is computed using the following equation:
∆ V
io
∆ T
V
T − V 25°C
io
io
= max
(1)
T − 25°C
Where T = - 40 °C and 125 °C.
The TSV7721, TSV7722, TSV7723 datasheet maximum value is guaranteed by measurements on a
representative sample size ensuring a Cpk (process capability index) greater than 1.3.
5.3
Unused channel
When one of the two channels of the TSV7722 is not used, it must be properly connected in order to avoid
internal oscillations that can negatively impact the signal integrity on the other channel, as well as the current
consumption. Two different configurations can be used:
Gain configuration: the channel can be set in gain, the input can be set to any voltage within the Vicm operating
range.
Comparator configuration: the channel can be set to a comparator configuration (without negative feedback). In
this case, positive and negative inputs can be set to any value provided these values are significantly different
(100 mV or more, to avoid oscillation between positive and negative state).
5.4
EMI rejection
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF
signal rectification. EMIRR is defined in Eq. (2):
V
in pp
EMIRR = 20 . log
(2)
∆ V
io
The TSV7722 has been specially designed to minimize susceptibility to EMIRR and shows a low sensitivity. As
can be seen in Figure 46. EMIRR on In+, In- and Out pins, EMI rejection ratio has been measured on both inputs
and output, from 400 MHz to 2.4 GHz.
DS13614 - Rev 3
page 19/40
TSV7721, TSV7722, TSV7723
Maximum power dissipation
Figure 46. EMIRR on In+, In- and Out pins
EMIRR performances might be improved by adding small capacitances (in the pF range) on the inputs, power
supply and output pins.
These capacitances help to minimize the impedance of these nodes at high frequencies.
5.5
Maximum power dissipation
The usable output load current drive is limited by the maximum power dissipation allowed by the device package.
The absolute maximum junction temperature for the TSV7722 is 150 °C. The junction temperature can be
estimated as follows:
T
= P × θ + T
JA A
(3)
J
D
TJ is the die junction temperature
PD is the power dissipated in the package
θJA is the junction to ambient thermal resistance of the package.
TA is the ambient temperature.
The power dissipated in the package PD is the sum of the quiescent power dissipated and the power dissipated
by the output stage transistor. It is calculated as follows:
P
P
= V × I
+ V
+ V
− V
× ILoad when the op amp is sourcing the current.
× ILoad when the op amp is sinking the current.
D
CC
CC
CC +
OUT
= V × I
− V
CC −
D
CC
CC
OUT
Do not exceed the 150 °C maximum junction temperature for the device. Exceeding the junction temperature limit
can cause degradation in the parametric performance or even destroy the device.
5.6
Capacitive load and stability
Stability analysis must be performed for large capacitive loads over 47 pF; increasing the load capacitance to high
values produces gain peaking in the frequency response, with overshoot and ringing in the step response.
Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads.
For additional capacitive load drive capability in unity-gain configuration, stability can be improved by inserting
a small resistor RISO (10 Ω to 22 Ω) in series with the output (see Figure 35. Small step overshoot vs. load
capacitance). This resistor significantly reduces ringing while maintaining DC performance for purely capacitive
loads. However, if there is a resistive load in parallel with the capacitive load, a voltage divider is created
introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional
to the ratio RISO / RL. RISO modifies the maximum capacitive load acceptable from a stability point of view, as
described in Figure 47. Test configuration for RISO
:
DS13614 - Rev 3
page 20/40
TSV7721, TSV7722, TSV7723
Resistor values for high speed op amp design
Figure 47. Test configuration for RISO
Please note that RISO = 22 Ω is sufficient to make the TSV7722 stable whatever the capacitive load.
5.7
Resistor values for high speed op amp design
Due to its high gain bandwidth product (GBP), this op amp is particularly sensitive to parasitic impedances.
Board parasitics should be taken into account in any sensitive design. Indeed, excessive parasitic (both capacitive
and inductive) in the op amp frequency range can alter performances and stability. These issues can often be
mitigated by lowering the resistive impedances. More specifically, the RC network created by the schematic
resistors (Rf and Rg) and the parasitic capacitances of both the op amp (as documented in Table 6 to Table 8
and illustrated in Figure 48) and the PCB can generate a pole below or in the same order of magnitude than
the closed-loop bandwidth of the circuit. In this case, the feedback circuit is not able to fully play its role at high
frequency, and the application can be unstable. This issue can happen when the schematic gain is low (typically <
5), or the device is used in follower mode with a resistor in the feedback. In these cases, it is advised to use a low
value feedback resistor (Rf), typically 1 kΩ.
Figure 48. Inverting amplifier configuration with parasitic input capacitances
Also, some designs use an input resistor on the positive input, generally of the same value than the input
resistance on the negative input. This resistor can be useful to balance the input currents on the positive and
negative inputs, and reduce the impact of those input currents on precision. However, this is not useful on
the TSV7722 as the input currents are very low. Furthermore, this resistor can also interact with the input
capacitances to generate a pole. The frequency of this pole should be kept higher than the closed-loop bandwidth
frequency. The macromodel provided takes into account the circuit parasitic capacitors. Thus, a transient SPICE
simulation (100 mV step) is an easy way to evaluate the stability of the application. However, this cannot replace
a hardware evaluation of the application circuit.
DS13614 - Rev 3
page 21/40
TSV7721, TSV7722, TSV7723
Settling time
5.8
Settling time
Settling time in an application can be defined as the amount of time between the input changes, and the output
reaching its final value. It is usually defined with a given tolerance, so the output stability is reached when the
output stays within the given range around the final value. In Figure 33. Settling time output high to low at
VCC = 5 V and Figure 34. Settling time output low to high at VCC = 5 V, the settling time is measured in an
inverting configuration, using the so-called “false summing node” circuit.
Figure 49. Settling time measurement configuration
This circuit is used with a step input voltage from a positive or negative value, to 0 V. The measurement point
being (Vin + Vout) / 2, and Vout being in an ideal circuit equal to Vin; the measurement point gives half of the
error on Vout, comparatively to Vin. This error is compared to the tolerance, 0.1% for this circuit, to deduce the
settling time. This characteristic is particularly useful when driving an ADC. It is related to the slew rate, GBP and
stability of the circuit. It also varies with the circuit gain, the circuit load, and the input voltage step value. However,
computing the value of the settling time in a given configuration is not straightforward. The macromodel can give a
good estimation, but prototyping can be needed for fine circuit optimization.
DS13614 - Rev 3
page 22/40
TSV7721, TSV7722, TSV7723
Shutdown function (TSV7723)
5.9
Shutdown function (TSV7723)
The operational amplifier is enabled when the EN pin is pulled high. To disable the amplifier, the EN must be
pulled down to VCC-. When in shutdown mode, the amplifier output is in a high impedance state. The EN pin
must never be left floating, but must be tied to VCC+ or VCC-.
The turn-on time is calculated for an output variation of ± 200 mV (see Figure 47 & Figure 48. Figure 51 shows
the test configurations).
Figure 50. Test configuration
+Vcc
GND
+
Vcc-0.5 V
DUT
-
GND
5.10
PCB layout recommendations
Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load, and power
supply. The power and ground traces are critical as they must provide adequate energy and grounding for
all circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic
inductance. In addition, to minimizing parasitic impedance over the entire surface, a multi-via technique that
connects the bottom and top layer ground planes together in many locations is often used. The copper traces that
connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.
5.11
5.12
Decoupling capacitor
In order to ensure op amp full functionality, it is mandatory to place a decoupling capacitor of at least 22 nF as
close as possible to the op amp supply pins. A good decoupling helps to reduce electromagnetic interference
impact.
Macro model
Accurate macro models of the TSV7722 device are available on the STMicroelectronics’ website at: www.st.com.
These models are a trade-off between accuracy and complexity (that is, time simulation) of the TSV7722
operational amplifier. They emulate the nominal performance of a typical device at 25°C within the specified
operating conditions mentioned in the datasheet. They also help to validate a design approach and to select the
right operational amplifier, but they do not replace on-board measurements.
DS13614 - Rev 3
page 23/40
TSV7721, TSV7722, TSV7723
Typical applications
6
Typical applications
6.1
Low-side current sensing
Power management mechanisms are found in most electronic systems. Current sensing is useful for protecting
applications. The low-side current sensing method consists of placing a sense resistor between the load and
the circuit ground. The resulting voltage drop is amplified using the TSV772x (see Figure 51. Low-side current
sensing schematic).
Figure 51. Low-side current sensing schematic
Vout can be expressed as follows:
R
R
R
R
. R
R
R
g2
+ R
f1
g2 f2
f1
V
= R
. I 1 −
. 1 +
+ I
.
. 1 +
− I . R
f1
(4)
(5)
Out
sℎunt
p
n
R
R
+ R
g2
f2
g1
g2
f2
g1
R
f1
− V . 1 +
io
R
g1
Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, this equation can be simplified as follows:
R
R
R
R
f
f
V
= R
sℎunt
. I .
− V . 1 +
io
+ R . I
io
Out
f
g
g
The main advantage of using the TSV7722 for a low-side current sensing relies on its low Vio, compared to
general purpose operational amplifiers. For the same current and targeted accuracy, the shunt resistor can be
chosen with a lower value, resulting in lower power dissipation, lower drop in the ground path, and lower cost.
Particular attention must be paid to the matching and precision of Rg1, Rg2, Rf1, and Rf2, to maximize the
accuracy of the measurement. Furthermore, on the TSV7722, the Vio is trimmed, and thus reaches his minimum
value, at Vicm = 0 V. This allows optimized precision for low-side current sensing application without precision
degradation due to the CMRR.
DS13614 - Rev 3
page 24/40
TSV7721, TSV7722, TSV7723
Photodiode transimpedance amplification
6.2
Photodiode transimpedance amplification
The TSV7722, with high bandwidth and slew rate, is well suited for photodiode signal conditioning in a
transimpedance amplifier circuit. This application is useful in high performance UV sensors, smoke detectors
or particle sensors.
Figure 52. Photodiode transimpedance amplifier circuit
The transimpedance amplifier circuit converts the small photodiode output current in the nA range, into a voltage
signal readable by an ADC following Eq. (6):
V
= R . I
pℎotodiode
(6)
Out
f
The feedback resistance is usually in the MΩ range, in order to get a large enough voltage output range.
However, together with the diode parasitic capacitance, the op amp input capacitances and the PCB stray
capacitance, this feedback network creates a pole that makes the circuit oscillate. Using a small (few pF)
capacitor in parallel with the feedback resistor is mandatory to stabilize the circuit. The value of this capacitor can
be tuned to optimize the application settling time with a SPICE simulation using the op amp macromodel, or by
prototyping.
For more details on tuning this circuit, please read the application note AN4451.
DS13614 - Rev 3
page 25/40
TSV7721, TSV7722, TSV7723
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
DS13614 - Rev 3
page 26/40
TSV7721, TSV7722, TSV7723
SOT23-5 package information
7.1
SOT23-5 package information
Figure 53. SOT23-5 package outline
Table 9. SOT23-5 package mechanical data
Dimensions
Millimeters
Ref.
Inches
Typ.
Min.
Typ.
Max.
1.45
0.15
1.30
0.50
0.20
3.00
Min.
Max.
0.057
0.006
0.051
0.020
0.020
0.118
A
A1
A2
B
0.90
1.20
0.035
0.047
0.90
0.35
0.09
2.80
1.05
0.40
0.15
2.90
1.90
0.95
2.80
1.60
0.35
0.035
0.014
0.004
0.110
0.041
0.016
0.006
0.114
0.075
0.037
0.110
0.063
0.014
C
D
D1
e
E
2.60
1.50
0.10
0°
3.00
1.75
0.60
10°
0.102
0.059
0.004
0°
0.118
0.069
0.024
10°
F
L
K
DS13614 - Rev 3
page 27/40
TSV7721, TSV7722, TSV7723
DFN8 2x2 package information
7.2
DFN8 2x2 package information
Figure 54. DFN8 2x2 package outline
Table 10. DFN8 2x2 package mechanical data
Dimensions
Millimeters
Ref.
Inches
Typ.
Min.
Typ.
Max.
0.60
0.05
Min.
Max.
0.024
0.002
A
A1
A3
b
0.51
0.55
0.020
0.022
0.15
0.25
2.00
1.60
2.00
0.90
0.50
0.325
0.006
0.010
0.079
0.063
0.079
0.035
0.020
0.013
0.18
1.85
1.45
1.85
0.75
0.30
2.15
1.70
2.15
1.00
0.007
0.073
0.057
0.073
0.030
0.012
0.085
0.067
0.085
0.039
D
D2
E
E2
e
L
0.225
0.425
0.08
0.009
0.017
0.003
ddd
DS13614 - Rev 3
page 28/40
TSV7721, TSV7722, TSV7723
DFN8 2x2 package information
Figure 55. DFN8 2x2 recommended footprint
Note:
The exposed pad of the DFN8 2x2 can be connected to VCC- or left floating.
DS13614 - Rev 3
page 29/40
TSV7721, TSV7722, TSV7723
MiniSO8 package information
7.3
MiniSO8 package information
Figure 56. MiniSO8 package outline
Table 11. MiniSO8 package mechanical data
Dimensions
Millimeters
Ref.
Inches
Typ.
Min.
Typ.
Max.
1.1
Min.
Max.
0.043
0.0006
0.037
0.016
0.009
0.126
0.203
0.122
A
A1
A2
b
0
0.15
0.95
0.40
0.23
3.20
5.15
3.10
0
0.75
0.22
0.08
2.80
4.65
2.80
0.85
0.030
0.009
0.003
0.11
0.033
c
D
3.00
4.90
3.00
0.65
0.60
0.95
0.25
0.118
0.193
0.118
0.026
0.024
0.037
0.010
E
0.183
0.11
E1
e
L
0.40
0°
0.80
0.016
0°
0.031
L1
L2
k
8°
8°
ccc
0.10
0.004
DS13614 - Rev 3
page 30/40
TSV7721, TSV7722, TSV7723
SO-8 package information
7.4
SO-8 package information
Figure 57. SO-8 package outline
0016023_So-807_fig2_Rev10
Table 12. SO-8 mechanical data
mm
Dim.
Min.
Typ.
Max.
1.75
0.25
A
A1
A2
b
0.10
1.25
0.31
0.28
0.10
0.10
4.80
5.80
3.80
0.51
0.48
0.25
0.23
5.00
6.20
4.00
b1
c
c1
D
4.90
6.00
3.90
1.27
E
E1
e
h
0.25
0.40
0.50
1.27
L
L1
L2
k
1.04
0.25
0°
8°
ccc
0.10
DS13614 - Rev 3
page 31/40
TSV7721, TSV7722, TSV7723
MiniSO10 package information
7.5
MiniSO10 package information
Figure 58. MiniSO10 package outline
Table 13. MiniSO10 mechanical data
Dimensions
Millimeters
Ref.
Inches
Typ.
Min.
Typ.
Max.
1.10
0.15
0.94
0.40
0.30
3.10
5.05
3.10
Min.
Max.
0.043
0.006
0.037
0.016
0.012
0.122
0.199
0.122
A
A1
A2
b
0.05
0.78
0.25
0.15
2.90
4.75
2.90
0.10
0.86
0.33
0.23
3.00
4.90
3.00
0.50
0.55
0.95
3 °
0.002
0.031
0.010
0.006
0.114
0.187
0.114
0.004
0.034
0.013
0.009
0.118
0.193
0.118
0.020
0.022
0.037
3 °
c
D
E
E1
e
L
0.40
0 °
0.70
0.016
0 °
0.028
L1
k
6 °
6 °
aaa
0.10
0.004
DS13614 - Rev 3
page 32/40
TSV7721, TSV7722, TSV7723
Ordering information
8
Ordering information
Table 14. Order code
Order code
Temperature range
-40 to +125 °C
Package
Channel
Automotive
Marking
TSV7721ILT
SOT23-5
1
K2A
-40 to +125 °C Automotive
grade(1)
TSV7721IYLT
SOT23-5
1
•
K217
TSV7722IQ2T
TSV7722IST
TSV7722IDT
TSV7723IST
TSV7722IYST
TSV7722IYDT
DFN8 2x2
MiniSO8
SO8
2
2
2
2
2
2
K2A
K2A
-40 to +125°C
TSV7722I
K2A
MiniSO10
MiniSO8
SO8
•
•
K217
-40 to +125 °C Automotive
grade(1)
TSV7722Y
1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC
Q001 & Q 002 or equivalent are ongoing.
DS13614 - Rev 3
page 33/40
TSV7721, TSV7722, TSV7723
Revision history
Table 15. Document revision history
Date
Revision
Changes
20-Jan-2021
1
Initial release.
Updated the "Related products" table in cover page.
Added Section 1 Pin description, Section 1.1 TSV7721 single operational
amplifier, Section 1.2 TSV7722 dual operational amplifier and Section 1.3
TSV7723 dual operational amplifier with shutdown option
16-Mar-2021
2
3
Changed from 2.5 mA to 2.8 mA for "Maximum supply current -40 °C < T < 125
°C and Vcc=5 V, 3.3 V, 1.8 V".
Minor text changes.
Changed name and description pin 5, pin 6 in Figure 3 and Table 3
Updated: V , V , I , I parameter in Table 6, Table 7 and Table 8, Figure 20
IH
IL IH IL
25-May-2021
and Figure 21
Added: Figure 43, Figure 44, Figure 45 and Section 5.9 .
DS13614 - Rev 3
page 34/40
TSV7721, TSV7722, TSV7723
Contents
Contents
1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.1
1.2
1.3
TSV7721 single operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
TSV7722 dual operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
TSV7723 dual operational amplifier with shutdown option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
3
4
5
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Input offset voltage drift over the temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Unused channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
EMI rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Maximum power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Capacitive load and stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Resistor values for high speed op amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Shutdown function (TSV7723). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.10 PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.11 Decoupling capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.12 Macro model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
6
7
6.1
6.2
Low-side current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Photodiode transimpedance amplification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7.1
7.2
7.3
7.4
7.5
DFN8 2x2 mm package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
DFN8 2x2 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
MiniSO10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
DS13614 - Rev 3
page 35/40
TSV7721, TSV7722, TSV7723
Contents
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
DS13614 - Rev 3
page 36/40
TSV7721, TSV7722, TSV7723
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics at VCC+ = 5 V, with VCC- = 0 V, Vicm = VCC / 2, T = 25°C, and OUT pin connected to VCC / 2
through RL = 10 kΩ (unless otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 7.
Table 8.
Table 9.
Electrical characteristics at VCC+ = 3.3 V, with VCC- = 0 V, Vicm = VCC / 2, T = 25°C, and OUT pin connected to VCC /
2 through RL = 10 kΩ (unless otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics at VCC+ = 1.8 V, with VCC- = 0 V, Vicm = 0.7 V, T = 25°C, and OUT pin connected to VCC / 2
through RL = 10 kΩ (unless otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SOT23-5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. DFN8 2x2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. MiniSO8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 13. MiniSO10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 14. Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DS13614 - Rev 3
page 37/40
TSV7721, TSV7722, TSV7723
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Supply current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input offset voltage distribution at VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input offset voltage distribution at VCC = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input offset voltage vs. temperature at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input offset voltage vs. temperature at VCC=1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input offset voltage thermal coeff. at VCC=5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input offset voltage thermal coefficient at VCC=1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input offset voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input offset voltage vs. common-mode voltage at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input offset voltage vs. common-mode voltage at VCC = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input bias current vs. temp. at VICM = VCC / 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input bias current vs. common-mode voltage at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output current vs. output voltage at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output current versus output voltage at VCC=1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output saturation voltage (VOL) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output saturation voltage (VOH) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Positive slew rate at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Negative slew rate at VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Slew rate vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Open loop bode diagram at VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Open loop bode diagram at VCC = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Closed loop bode diagram at VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Closed loop bode diagram at VCC = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Phase margin vs. common-mode voltage and load current at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Phase margin vs. capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Small step response at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Small step response at VCC = 1.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Desaturation from low rail at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Desaturation from high rail at VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Settling time output high to low at VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Settling time output low to high at VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Small step overshoot vs. load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Linearity vs. load resistance at VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Noise vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Noise versus time at VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
THD+N vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
THD+N vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CMRR vs. frequency at VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PSRR vs. frequency at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Supply current vs. supply voltage in shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Turn-on time at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Turn-on time at VCC = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
EMIRR on In+, In- and Out pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Test configuration for RISO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Inverting amplifier configuration with parasitic input capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Settling time measurement configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
DS13614 - Rev 3
page 38/40
TSV7721, TSV7722, TSV7723
List of figures
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Test configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Low-side current sensing schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Photodiode transimpedance amplifier circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SOT23-5 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DFN8 2x2 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DFN8 2x2 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MiniSO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SO-8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
MiniSO10 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DS13614 - Rev 3
page 39/40
TSV7721, TSV7722, TSV7723
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DS13614 - Rev 3
page 40/40
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