TSV522IST [STMICROELECTRONICS]
High merit factor (1.15 MHz for 45 μA) CMOS op amps; 高品质因数（ 1.15 MHz的45 μA ） CMOS运算放大器
| 型号： | TSV522IST |
| 厂家： | 
ST |
| 描述： | High merit factor (1.15 MHz for 45 μA) CMOS op amps |
| 文件： | 总27页 (文件大小：749K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSV521, TSV522, TSV524,
TSV521A, TSV522A, TSV524A
High merit factor (1.15 MHz for 45 µA) CMOS op amps
Datasheet −preliminary data
Features
■ Gain bandwidth product: 1.15 MHz typ. at 5 V
■ Low power consumption: 45 µA typ. at 5 V
■ Rail-to-rail input and output
SC70-5
■ Low input bias current: 1 pA typ.
■ Supply voltage: 2.7 to 5.5 V
■ Low offset voltage: 800 µV max.
■ Unity gain stable on 100 pF capacitor
■ Automotive grade
DF
N
8 2 x 2
MiniSO8
Benefits
■ Increased lifetime in battery powered
applications
■ Easy interfacing with high impedance sensors
Related products
■ See TSV6x series for lower minimum supply
voltage (1.5 V)
QFN16 3 x 3
TSSOP14
■ See LMV82x series for higher gain bandwidth
products (5.5 MHz)
The TSV52x series offers an outstanding
speed/power consumption ratio, 1.15 MHz gain
bandwidth product while consuming only 45 µA at
5 V. The devices are housed in the smallest
industrial packages.
Applications
■ Battery powered applications
■ Portable devices
■ Automotive signal conditioning
■ Active filtering
These features make the TSV52x family ideal for
sensor interfaces, battery supplied and portable
applications. The wide temperature range and
high ESD tolerance facilitate their use in harsh
automotive applications.
■ Medical instrumentation
Description
Table 1.
Device summary
The TSV52x series of operational amplifiers
offers low voltage operation and rail-to-rail input
and output. The TSV521 device is the single
version, the TSV522 device the dual version, and
the TSV524 device the quad version, with pinouts
compatible with industry standards.
Standard V
TSV521
TSV522
TSV524
Enhanced V
TSV521A
TSV522A
TSV524A
io
io
Single
Dual
Quad
June 2012
Doc ID 022743 Rev 1
1/27
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
27
Contents
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Contents
1
2
3
4
Package pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Common mode voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Rail-to-rail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Driving resistive and capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input offset voltage drift over temperature . . . . . . . . . . . . . . . . . . . . . . . . 15
Long term input offset voltage drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PCB layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Macromodel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
6
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27
Doc ID 022743 Rev 1
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Package pin connections
1
Package pin connections
Figure 1.
Pin connections for each package (top view)
IN+
VCC-
IN-
VCC+
1
2
3
5
4
OUT
TSV521
SC70-5
OUT1
VCC+
OUT2
IN2-
3
4
6
5
OUT1
IN1-
VCC+
OUT2
IN2-
IN1-
IN1+
VCC-
IN1+
VCC-
IN2+
IN2+
TSV522
MiniSO8
TSV522
DFN8
IN1+
IN4+
VCC-
NC
VCC+
NC
IN2+
IN3+
TSV524
QFN16
TSV524
TSSOP14
Doc ID 022743 Rev 1
3/27
Absolute maximum ratings and operating conditions
TSV521, TSV522, TSV524, TSV521A,
2
Absolute maximum ratings and operating conditions
Table 2.
Symbol
Absolute maximum ratings (AMR)
Parameter
Value
Unit
(1)
V
Supply voltage
6
V
V
CC
(2)
V
Differential input voltage
V
CC
id
in
(3)
V
Input voltage
V
- 0.2 to V
10
+ 0.2
CC+
V
CC-
(4)
I
Input current
mA
°C
in
T
Storage temperature
-65 to +150
stg
(5) (6)
Thermal resistance junction-to-ambient
,
SC70-5
205
57
45
190
100
DFN8 2 x 2
QFN16 3 x 3
MiniSO8
R
°C/W
thja
TSSOP14
T
Maximum junction temperature
150
4
°C
kV
V
j
(7)
HBM: human body model
(8)
MM: machine model
300
(9)
ESD
CDM: charged device model
1.5
kV
(all packages except SC70-5 and DFN8)
(9)
CDM: charged device model (SC70-5 and DFN8)
Latch-up immunity
1.3
kV
200
mA
1. All voltage values, except differential voltages are with respect to network ground terminal.
2. Differential voltages are the non inverting input terminal with respect to the inverting input terminal.
3. VCC - Vin must not exceed 6 V, Vin must not exceed 6 V.
4. Input current must be limited by a resistor in series with the inputs.
5. Short-circuits can cause excessive heating and destructive dissipation.
6. Rth are typical values.
7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for
all couples of pin combinations with other pins floating.
8. Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two
pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin
combinations with other pins floating.
9. Charged device model: all pins plus package are charged together to the specified voltage and then
discharged directly to ground.
Table 3.
Symbol
Operating conditions
Parameter
Value
Unit
V
Supply voltage
2.7 to 5.5
V
V
CC
V
Common mode input voltage range
Operating free air temperature range
V
- 0.1 to V
+ 0.1
CC+
icm
CC-
T
-40 to +125
°C
oper
4/27
Doc ID 022743 Rev 1
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Electrical characteristics
3
Electrical characteristics
Table 4.
Electrical characteristics at V
= +2.7 V with V
= 0 V, V
= V /2, T = 25 °C, and
CC+
CC-
icm CC
R = 10 kΩ connected to V /2 (unless otherwise specified)
L
CC
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
TSV52xA, T = 25 °C
800
2600
1.5
µV
µV
TSV52xA, -40 °C < T < 125 °C
TSV52x, T = 25 °C
V
Offset voltage
io
mV
mV
µV/°C
pA
TSV52x, -40 °C < T < 125 °C
3.3
(1)
ΔV /ΔT Input offset voltage drift
-40 °C < T < 125 °C
3
1
18
io
(3)
T = 25 °C
10
Input offset current
I
io
ib
(3)
(V = V /2)
out
CC
-40° C < T < 125 °C
T = 25 °C
1
100
pA
(3)
1
10
pA
Input bias current
(V = V /2)
I
(3)
out
CC
-40 °C < T < 125 °C
T = 25 °C
1
100
pA
Common mode rejection
50
46
72
ratio 20 log (ΔV /ΔV )
ic
io
CMR
dB
dB
V
V
= -0.1 V to V +0.1V,
ic
CC
-40 °C < T < 125 °C
= V /2, R = 1 MΩ
out
CC
L
Large signal voltage gain
V = 0.5 V to (V - 0.5V),
out
T = 25 °C
90
60
105
A
vd
CC
-40 °C < T < 125 °C
R = 1 MΩ
L
T = 25 °C
-40 °C < T < 125 °C
3
6
35
50
V
High level output voltage
Low level output voltage
mV
mV
OH
T = 25 °C
-40 °C < T < 125 °C
35
50
V
OL
V
= V , T = 25 °C
12
8
22
out
CC
I
mA
mA
µA
sink
V
= V , -40 °C < T < 125 °C
out
CC
I
I
out
V
= 0 V, T = 25 °C
12
8
18
out
I
source
V
= 0 V, -40 °C < T < 125 °C
out
T = 25 °C
30
30
51
51
Supply current (per channel)
= V /2, R > 1 MΩ
CC
V
out
CC
L
-40 °C < T < 125 °C
AC performance
GBP
Gain bandwidth product
Unity gain frequency
Phase margin
R = 10 kΩ, C = 100 pF
0.62
1
900
55
7
MHz
kHz
L
L
F
R = 10 kΩ, C = 100 pF
L L
u
Φ
R = 10 kΩ, C = 100 pF
degrees
dB
m
L
L
G
Gain margin
R = 10 kΩ, C = 100 pF
L L
m
R = 10 kΩ, C = 100 pF,
L
L
SR
Slew rate
0.74
V/µs
V
= 0.5 V to V - 0.5 V
out
CC
Doc ID 022743 Rev 1
5/27
Electrical characteristics
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Table 4.
Symbol
Electrical characteristics at V
= +2.7 V with V
= 0 V, V
= V /2, T = 25 °C, and
CC+
CC-
icm CC
R = 10 kΩ connected to V /2 (unless otherwise specified) (continued)
L
CC
Parameter
Conditions
Min.
Typ.
Max.
Unit
nV
Equivalent input noise
voltage
f = 1 kHz
f = 10 kHz
61
43
-----------
e
n
Hz
Follower configuration, f = 1 kHz,
in
Total harmonic distortion +
noise
THD+N
R = 100 kΩ, V = V /2,
0.003
%
L
icm
CC
BW = 22 kHz, V = 1 V
out
pp
Table 5.
Symbol
Electrical characteristics at V
= +3.3 V with V
= 0 V, V
= V /2, T = 25 °C, and
CC+
CC-
icm CC
R = 10 kΩ connected to V /2 (unless otherwise specified)
L
CC
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
TSV52xA, T = 25 °C
600
2400
1.3
µV
µV
TSV52xA, -40 °C < T < 125 °C
TSV52x, T = 25 °C
V
Offset voltage
io
mV
TSV52x, -40 °C < T < 125 °C
3.1
mV
(1)
ΔV /ΔT Input offset voltage drift
-40 °C < T < 125 °C
3
18
µV/°C
io
μV
month
Long term input offset
voltage drift
(2)
---------------------------
ΔV
T = 25 °C
0.3
io
(3)
T = 25 °C
1
1
10
pA
Input offset current
I
io
ib
(3)
(V = V /2)
out
CC
-40 °C < T < 125 °C
T = 25 °C
100
pA
(3)
1
10
pA
Input bias current
(V = V /2)
I
(3)
out
CC
-40 °C < T < 125 °C
T = 25 °C
1
100
pA
Common mode rejection
51
47
73
ratio 20 log (ΔV /ΔV )
ic
io
CMR
dB
dB
V
V
= -0.1 V to V +0.1 V,
ic
CC
-40 °C < T < 125 °C
= V /2, R = 1 MΩ
out
CC
L
Large signal voltage gain
V = 0.5 V to (V - 0.5 V),
out
T = 25 °C
91
63
106
A
vd
CC
-40 °C < T < 125 °C
R = 1 MΩ
L
T = 25 °C
-40 °C < T < 125 °C
3
7
35
50
V
High level output voltage
Low level output voltage
mV
mV
OH
T = 25 °C
-40 °C < T < 125 °C
35
50
V
OL
V
= V , T = 25 °C
20
17
19
17
31
out
CC
I
mA
mA
µA
sink
V
= V , -40 °C < T < 125 °C
out
CC
I
out
V
= 0 V, T = 25 °C
27
out
I
source
V
= 0 V, -40 °C < T < 125 °C
out
T = 25 °C
32
32
55
55
Supply current (per channel)
= V /2, R > 1 MΩ
I
CC
V
out
CC
L
-40 °C < T < 125 °C
6/27
Doc ID 022743 Rev 1
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Electrical characteristics
Table 5.
Symbol
Electrical characteristics at V
= +3.3 V with V
= 0 V, V
= V /2, T = 25 °C, and
CC+
CC-
icm CC
R = 10 kΩ connected to V /2 (unless otherwise specified) (continued)
L
CC
Parameter
Conditions
Min.
Typ.
Max.
Unit
AC performance
GBP
Gain bandwidth product
Unity gain frequency
Phase margin
R = 10 kΩ, C = 100 pF
0.64
1
900
55
7
MHz
kHz
L
L
F
R = 10 kΩ, C = 100 pF
L L
u
Φ
R = 10 kΩ, C = 100 pF
degrees
dB
m
L
L
G
Gain margin
R = 10 kΩ, C = 100 pF
L L
m
R = 10 kΩ, C = 100 pF,
L
L
SR
Slew rate
0.75
V/μs
V
= 0.5 V to V - 0.5 V
out
CC
nV
Equivalent input noise
voltage
f = 1 kHz
f = 10 kHz
60
42
-----------
e
n
Hz
Follower configuration, f = 1 kHz,
in
Total harmonic distortion +
noise
THD+N
R = 100 kΩ, V = V /2,
0.003
%
L
icm
CC
BW = 22 kHz, V = 1 V
out
pp
Table 6.
Electrical characteristics at V
= +5 V with V
= 0 V, V
= V /2, T = 25 °C,
icm CC
CC+
CC-
and R = 10 kΩ connected to V /2 (unless otherwise specified)
L
CC
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
TSV52xA, T = 25 °C
600
2400
1
µV
µV
TSV52xA, -40 °C < T < 125 °C
TSV52x, T = 25 °C
V
Offset voltage
io
mV
TSV52x, -40 °C < T < 125 °C
2.8
18
mV
(1)
ΔV /ΔT Input offset voltage drift
-40 °C < T < 125 °C
3
µV/°C
io
μV
month
Long term input offset
voltage drift
(2)
---------------------------
ΔV
T = 25 °C
0.7
io
(3)
T = 25 °C
1
1
10
pA
Input offset current
I
I
io
ib
(3)
(V = V /2)
out
CC
-40 °C < T < 125 °C
T = 25 °C
100
pA
(3)
1
10
pA
Input bias current
(V = V /2)
(3)
out
CC
-40 °C < T < 125 °C
T = 25 °C
1
100
pA
Common mode rejection
54
50
63
58
76
ratio 20 log (ΔV /ΔV )
ic
io
CMR1
CMR2
dB
dB
V
V
= -0.1 V to V +0.1 V,
ic
CC
-40 °C < T < 125 °C
T = 25 °C
= V /2, R = 1 MΩ
out
CC
L
Common mode rejection
84
ratio 20 log (ΔV /ΔV )
ic
io
V
V
= 1 V to V -1 V,
ic
CC
-40 °C < T < 125 °C
= V /2, R = 1 MΩ
out
CC
L
Doc ID 022743 Rev 1
7/27
Electrical characteristics
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Table 6.
Symbol
Electrical characteristics at V
= +5 V with V
= 0 V, V
= V /2, T = 25 °C,
icm CC
CC+
CC-
and R = 10 kΩ connected to V /2 (unless otherwise specified)
L
CC
Parameter
Conditions
Min.
Typ.
Max.
Unit
Supply voltage rejection
T = 25 °C
65
87
ratio 20 log (ΔV /ΔV )
CC
io
SVR
dB
V
V
= 2.7 V to 5.5 V,
CC
out
-40 °C < T < 125 °C
60
= V /2
CC
Large signal voltage gain
= 0.5 V to (V - 0.5 V),
T = 25 °C
94
68
109
A
V
dB
vd
out
CC
-40 °C < T < 125 °C
R = 1 MΩ
L
T = 25 °C
-40 °C < T < 125 °C
5
9
35
50
V
High level output voltage
Low level output voltage
mV
mV
OH
T = 25 °C
-40 °C < T < 125 °C
35
50
V
OL
V
= V , T = 25 °C
36
27
36
27
55
out
CC
I
I
mA
mA
µA
sink
V
= V , -40 °C < T < 125 °C
out
CC
I
I
out
V
= 0 V, T = 25 °C
55
out
source
V
= 0 V, -40 °C < T < 125 °C
out
T = 25 °C
45
45
60
60
Supply current (per channel)
= V /2, R > 1 MΩ
CC
V
out
CC
L
-40 °C < T < 125 °C
AC performance
GBP
Gain bandwidth product
Unity gain frequency
Phase margin
R = 10 kΩ, C = 100 pF
0.73
1.15
900
55
MHz
kHz
L
L
F
R = 10 kΩ, C = 100 pF
L L
u
Φ
R = 10 kΩ, C = 100 pF
degrees
dB
m
L
L
G
Gain margin
R = 10 kΩ, C = 100 pF
7
m
L
L
R = 10 kΩ, C = 100 pF,
L
L
SR
Slew rate
0.89
14
V/μs
V
= 0.5 V to V - 0.5V
out
CC
Low-frequency peak-to-
peak input noise
∫ e
Bandwidth: f = 0.1 to 10 Hz
µV
n
pp
Equivalent input noise
voltage
f = 1 kHz
f = 10 kHz
57
39
nV
-----------
e
n
Hz
Follower configuration, f = 1 kHz,
in
Total harmonic distortion +
noise
THD+N
R = 100 kΩ, V = V /2,
0.002
%
L
icm
CC
BW = 22 kHz, V = 1 V
out
pp
1. See Section 4.6: Input offset voltage drift over temperature on page 15.
2. Typical value is based on the Vio drift observed after 1000 h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration.
3. Guaranteed by design.
8/27
Doc ID 022743 Rev 1
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Electrical characteristics
Figure 2.
Supply current vs. supply voltage Figure 3.
at V = V /2
Input offset voltage distribution at
V
= 5 V, V
= 2.5 V
icm
CC
CC
icm
ꢆꢂ
ꢁꢇ
ꢁꢂ
ꢇ
6
DISTRIBUTION AT 4 ꢈ ꢆꢇ # FOR 6
##
ꢈ ꢇ 6ꢉ 6
ꢈ ꢆꢊꢇ 6
ICM
IO
ꢂ
ꢀꢁꢂꢂꢂ ꢀꢃꢂꢂ ꢀꢄꢂꢂ ꢀꢅꢂꢂ ꢀꢆꢂꢂ
ꢂ
ꢆꢂꢂ ꢅꢂꢂ ꢄꢂꢂ ꢃꢂꢂ ꢁꢂꢂꢂ
!-ꢂꢂꢅꢄꢁ
Figure 4.
Input offset voltage temperature
coefficient distribution
Figure 5.
Input offset voltage vs. input
common mode voltage at V = 5 V
CC
ꢆꢂꢂꢂ
ꢁꢇꢂꢂ
ꢁꢂꢂꢂ
ꢇꢂꢂ
6
ꢈ 6 ꢌꢆ
ꢈ ꢇ 6
ICM ##
6
##
4 ꢈ ꢁꢆꢇ #
4 ꢈ ꢀꢅꢂ #
ꢂ
ꢀꢇꢂꢂ
ꢀꢁꢂꢂꢂ
ꢀꢁꢇꢂꢂ
ꢀꢆꢂꢂꢂ
4 ꢈ ꢆꢇ #
6
ꢈ ꢇꢊꢇ 6
##
ꢂꢊꢂ ꢂꢊꢇ ꢁꢊꢂ ꢁꢊꢇ ꢆꢊꢂ ꢆꢊꢇ ꢍꢊꢂ ꢍꢊꢇ ꢅꢊꢂ ꢅꢊꢇ ꢇꢊꢂ ꢇꢊꢇ
ꢀꢆꢂ ꢀꢁꢃ ꢀꢁꢄ ꢀꢁꢅ ꢀꢁꢆ ꢀꢁꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ
ꢂ
ꢆ
ꢅ
ꢄ
ꢃ
ꢁꢂ ꢁꢆ ꢁꢅ ꢁꢄ ꢁꢃ ꢆꢂ
6
ꢎ6ꢏ
ICM
!-ꢂꢂꢅꢄꢆ
!-ꢂꢂꢅꢄꢍ
Figure 6.
Input offset voltage vs. temperature Figure 7.
at V = 5 V
Output current vs. output voltage at
V
= 2.7 V
CC
CC
ꢍꢂ
ꢍꢂꢂꢂ
4 ꢈ ꢆꢇ #
,IMIT FOR 436ꢇꢆX!
4 ꢈ ꢀꢅꢂ #
ꢆꢇꢂꢂ
ꢆꢂꢂꢂ
ꢁꢇꢂꢂ
ꢁꢂꢂꢂ
ꢇꢂꢂ
ꢆꢂ
,IMIT FOR 436ꢇꢆ8
4 ꢈ ꢁꢆꢇ #
ꢁꢂ
ꢂ
ꢂ
ꢀꢇꢂꢂ
ꢀꢁꢂꢂꢂ
ꢀꢁꢇꢂꢂ
ꢀꢆꢂꢂꢂ
ꢀꢆꢇꢂꢂ
ꢀꢍꢂꢂꢂ
4 ꢈ ꢁꢆꢇ #
4 ꢈ ꢀꢅꢂ #
ꢀꢁꢂ
ꢀꢆꢂ
ꢀꢍꢂ
4 ꢈ ꢆꢇ #
6
ꢈ ꢇ 6ꢉ 6
ꢈ ꢆꢊꢇ 6
##
ICM
6
ꢈ ꢆꢊꢐ 6
##
ꢀꢅꢂ
ꢀꢆꢂ
ꢂ
ꢆꢂ
ꢅꢂ
ꢄꢂ
ꢃꢂ
ꢁꢂꢂ ꢁꢆꢂ
ꢂꢊꢂ ꢂꢊꢍ ꢂꢊꢇ ꢂꢊꢃ ꢁꢊꢂ ꢁꢊꢍ ꢁꢊꢇ ꢁꢊꢃ ꢆꢊꢂ ꢆꢊꢍ ꢆꢊꢇ
/UTPUT VOLTAGE ꢎ6ꢏ
!-ꢂꢂꢅꢄꢅ
!-ꢂꢂꢅꢄꢇ
Doc ID 022743 Rev 1
9/27
Electrical characteristics
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Figure 8.
Output current vs. output voltage at Figure 9.
= 5.5 V
Bode diagram at V
= 2.7 V,
CC
V
R = 10 kΩ
CC
L
ꢍꢇꢂ
ꢍꢂꢂ
ꢆꢇꢂ
ꢆꢂꢂ
ꢁꢇꢂ
ꢁꢂꢂ
ꢇꢂ
ꢐꢇ
ꢇꢂ
4 ꢈ ꢆꢇ #
ꢅꢂ
ꢆꢂ
ꢂ
4 ꢈ ꢀꢅꢂ #
4 ꢈ ꢀꢅꢂ #
4 ꢈ ꢆꢇ #
4 ꢈ ꢁꢆꢇ #
4 ꢈ ꢁꢆꢇ #
ꢆꢇ
'AIN
ꢂ
ꢂ
ꢀꢇꢂ
ꢀꢁꢂꢂ
ꢀꢁꢇꢂ
ꢀꢆꢂꢂ
ꢀꢆꢇꢂ
ꢀꢍꢂꢂ
ꢀꢍꢇꢂ
ꢀꢆꢇ
ꢀꢇꢂ
ꢀꢐꢇ
0HASE
ꢈ ꢆꢊꢐ 6ꢉ 6 ꢈ ꢁꢊꢍꢇ 6ꢉ ' ꢈ ꢀꢁꢂꢂ
4 ꢈ ꢆꢇ #
ꢀꢆꢂ
ꢀꢅꢂ
4 ꢈ ꢁꢆꢇ #
6
ICM
##
ª
ꢉ # ꢈ ꢁꢂꢂ P&ꢉ 6 ꢈ 6 ꢌꢆ
, RL ##
6
ꢈ ꢇꢊꢇ 6
##
4 ꢈ ꢀꢅꢂ #
ꢂꢊꢂ ꢂꢊꢇ ꢁꢊꢂ ꢁꢊꢇ ꢆꢊꢂ ꢆꢊꢇ ꢍꢊꢂ ꢍꢊꢇ ꢅꢊꢂ ꢅꢊꢇ ꢇꢊꢂ ꢇꢊꢇ
ꢁ
ꢁꢂ
ꢁꢂꢂ
ꢁꢂꢂꢂ
ꢁꢂꢂꢂꢂ
/UTPUT VOLTAGE ꢎ6ꢏ
&REQUENCY ꢎK(Zꢏ
!-ꢂꢂꢅꢄꢄ
!-ꢂꢂꢅꢄꢐ
Figure 10. Bode diagram at V
= 2.7 V,
Figure 11. Bode diagram at V
= 5.5 V,
CC
CC
R
= 2 kΩ
R = 10 kΩ
L
L
ꢍꢇꢂ
ꢍꢂꢂ
ꢆꢇꢂ
ꢆꢂꢂ
ꢁꢇꢂ
ꢁꢂꢂ
ꢇꢂ
ꢄꢂ
ꢅꢂ
ꢆꢂ
ꢂ
ꢍꢇꢂ
ꢅꢂ
ꢆꢂ
ꢂ
ꢍꢂꢂ
ꢆꢇꢂ
ꢆꢂꢂ
ꢁꢇꢂ
ꢁꢂꢂ
ꢇꢂ
4 ꢈ ꢀꢅꢂ #
4 ꢈ ꢆꢇ #
4 ꢈ ꢀꢅꢂ #
4 ꢈ ꢆꢇ #
4 ꢈ ꢁꢆꢇ #
4 ꢈ ꢁꢆꢇ #
'AIN
'AIN
ꢂ
ꢂ
0HASE
0HASE
ꢀꢇꢂ
ꢀꢇꢂ
ꢀꢁꢂꢂ
ꢀꢁꢇꢂ
ꢀꢆꢂꢂ
ꢀꢆꢇꢂ
ꢀꢍꢂꢂ
ꢀꢍꢇꢂ
ꢀꢁꢂꢂ
ꢀꢁꢇꢂ
ꢀꢆꢂꢂ
ꢀꢆꢇꢂ
ꢀꢍꢂꢂ
ꢀꢍꢇꢂ
ꢀꢆꢂ
ꢀꢅꢂ
ꢀꢄꢂ
ꢀꢆꢂ
ꢀꢅꢂ
6
ꢈ ꢆꢊꢐ 6ꢉ 6
ꢈ ꢁꢊꢍꢇ 6ꢉ ' ꢈ ꢀꢁꢂꢂ
ICM
##
6
ꢈ ꢇꢊꢇ 6ꢉ 6
ꢈ ꢆꢊꢐꢇ 6ꢉ ' ꢈ ꢀꢁꢂꢂ
ICM
##
ª
ꢉ # ꢈ ꢁꢂꢂ P&ꢉ 6 ꢈ 6 ꢌꢆ
, RL ##
ª
ꢉ # ꢈ ꢁꢂꢂ P&ꢉ 6 ꢈ 6 ꢌꢆ
, RL ##
ꢁ
ꢁꢂ
ꢁꢂꢂ
ꢁꢂꢂꢂ
ꢁꢂꢂꢂꢂ
ꢁ
ꢁꢂ
ꢁꢂꢂ
ꢁꢂꢂꢂ
ꢁꢂꢂꢂꢂ
&REQUENCY ꢎK(Zꢏ
&REQUENCY ꢎK(Zꢏ
!-ꢂꢂꢅꢄꢃ
!-ꢂꢂꢅꢄꢑ
Figure 12. Bode diagram at V
= 5.5 V,
Figure 13. Noise vs. frequency
CC
R = 2 kΩ
L
ꢅꢇꢂ
ꢄꢂ
ꢅꢂ
ꢆꢂ
ꢂ
ꢍꢇꢂ
ꢍꢂꢂ
ꢆꢇꢂ
ꢆꢂꢂ
ꢁꢇꢂ
ꢁꢂꢂ
ꢇꢂ
6
ꢈ ꢇꢊꢇ 6ꢉ 6
ꢈ ꢆꢊꢐꢇ 6
ICM
##
ꢅꢂꢂ
ꢍꢇꢂ
ꢍꢂꢂ
ꢆꢇꢂ
ꢆꢂꢂ
ꢁꢇꢂ
ꢁꢂꢂ
ꢇꢂ
4AMB ꢈ ꢆꢇ #
4 ꢈ ꢀꢅꢂ #
4 ꢈ ꢆꢇ #
'AIN
4 ꢈ ꢁꢆꢇ #
0HASE
ꢂ
ꢀꢇꢂ
ꢀꢁꢂꢂ
ꢀꢁꢇꢂ
ꢀꢆꢂꢂ
ꢀꢆꢇꢂ
ꢀꢍꢂꢂ
ꢀꢍꢇꢂ
ꢀꢆꢂ
ꢀꢅꢂ
ꢀꢄꢂ
6
ꢈ ꢇꢊꢇ 6ꢉ 6 ꢈ ꢆꢊꢐꢇ 6ꢉ ' ꢈ ꢀꢁꢂꢂ
ICM
##
ꢉ # ꢈ ꢁꢂꢂ P&ꢉ 6 ꢈ 6 ꢌꢆ
,
RL ##
ꢂ
ꢁ
ꢁꢂ
ꢁꢂꢂ
ꢁꢂꢂꢂ
ꢁꢂꢂꢂꢂ
ꢁꢂꢂ
ꢁꢂꢂꢂ
ꢁꢂꢂꢂꢂ
!-ꢂꢂꢅꢐꢁ
&REQUENCY ꢎK(Zꢏ
&REQUENCY ꢎ(Zꢏ
!-ꢂꢂꢅꢐꢂ
10/27
Doc ID 022743 Rev 1
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Electrical characteristics
Figure 14. Positive slew rate vs. supply
voltage
Figure 15. Negative slew rate vs. supply
voltage
ꢁꢊꢂ
ꢉ # ꢈ ꢁꢂꢂ P&
,
6
ꢒ FROM ꢂꢊꢍ 6 TO 6
ꢀꢂꢊꢍ 6
IN
##
32 CALCULATED FROM ꢁꢂꢋ TO ꢑꢂꢋ
ꢂꢊꢑ
ꢂꢊꢃ
ꢂꢊꢐ
ꢂꢊꢄ
4 ꢈ ꢆꢇ #
4 ꢈ ꢁꢆꢇ #
4 ꢈ ꢀꢅꢂ #
ꢍꢊꢂ
ꢍꢊꢇ
ꢅꢊꢂ
ꢅꢊꢇ
ꢇꢊꢂ
ꢇꢊꢇ
3UPPLY VOLTAGE ꢎ6ꢏ
!-ꢂꢂꢅꢐꢆ
Figure 16. THD+N vs. frequency at V = 2.7 V Figure 17. THD+N vs. frequency at V = 5.5 V
CC
CC
ꢁ
ꢁ
6
ꢈ ꢁ 6PP
6
ꢈ ꢁ 6
PP
IN
'AIN ꢈ ꢁ
ꢈ 6 ꢌꢆ
IN
'AIN ꢈ ꢁ
6
6
ꢈ 6 ꢌꢆ
ICM
##
ICM
##
ꢂꢊꢁ
ꢂꢊꢁ
ꢂꢊꢂꢁ
ꢁ%ꢀꢍ
ꢂꢊꢂꢁ
ꢁ%ꢀꢍ
ꢁꢂꢂ
ꢁꢂꢂꢂ
ꢁꢂꢂꢂꢂ
ꢁꢂꢂ
ꢁꢂꢂꢂ
ꢁꢂꢂꢂꢂ
&REQUENCY ꢎ(Zꢏ
&REQUENCY ꢎ(Zꢏ
!-ꢂꢂꢅꢐꢅ
!-ꢂꢂꢅꢐꢇ
Figure 18. THD+N vs. output voltage at
= 2.7 V
Figure 19. THD+N vs. output voltage at
= 5.5 V
V
V
CC
CC
ꢁ
ꢁ
ꢂꢊꢁ
ꢂꢊꢁ
ꢂꢊꢂꢁ
ꢁ%ꢀꢍ
ꢂꢊꢂꢁ
ꢁ%ꢀꢍ
F ꢈ ꢁ K(Z
'AIN ꢈ ꢁ
F ꢈ ꢁ K(Z
'AIN ꢈ ꢁ
"7 ꢈ ꢆꢆ K(Z
ꢈ 6 ꢌꢆ
"7 ꢈ ꢆꢆ K(Z
ꢈ 6 ꢌꢆ
6
ICM
##
6
ICM
##
ꢂꢊꢂꢁ
ꢂꢊꢁ
ꢁ
ꢁꢂ
ꢂꢊꢂꢁ
ꢂꢊꢁ
ꢁ
ꢁꢂ
/UTPUT VOLTAGE ꢎ6
ꢏ
PP
/UTPUT VOLTAGE ꢎ6
ꢏ
PP
!-ꢂꢂꢅꢐꢄ
!-ꢂꢂꢅꢐꢐ
Doc ID 022743 Rev 1
11/27
Electrical characteristics
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Figure 20. Output impedance versus frequency in closed-loop configuration
ꢁꢂꢂꢂ
6
ꢈ ꢆꢊꢐ 6 TO ꢇꢊꢇ 6
##
/SCꢊ LEVEL ꢈ ꢂꢊꢂꢄꢇ 6
' ꢈ ꢁ
4 ꢈ ꢆꢇ #
ꢃꢂꢂ
ꢄꢂꢂ
ꢅꢂꢂ
ꢆꢂꢂ
2-3
ꢁꢂ
ꢁꢂꢂ
ꢁꢂꢂꢂ
ꢁꢂꢂꢂꢂ
&REQUENCY ꢎK(Zꢏ
!-ꢂꢂꢅꢐꢃ
Figure 21. Response to a 100 mV input step
Figure 22. Response to a 100 mV input step
for gain = 1 at V = 5.5 V rising
for gain = 1 at V = 5.5 V falling
CC
CC
edge
edge
VCC = 5.5 V, Vicm = 2.75 V
R
L = 10 kΩ, CL = 100 pF
0.5 µs/div., 20 mV/div.
VCC = 5.5 V, Vicm = 2.75 V
R
L = 10 kΩ, CL = 100 pF
0.5 µs/div., 20 mV/div.
Figure 23. PSRR vs. frequency at V = 2.7 V Figure 24. PSRR vs. frequency at V = 5.5 V
CC
CC
ꢀꢁꢂꢂ
ꢀꢃꢂ
ꢀꢄꢂ
ꢀꢅꢂ
ꢀꢆꢂ
ꢂ
ꢀꢁꢂꢂ
ꢀꢃꢂ
ꢀꢄꢂ
ꢀꢅꢂ
ꢀꢆꢂ
ꢂ
6
ꢈ ꢇꢊꢇ 6ꢉ 6
ꢈ ꢆꢊꢐꢇ 6ꢉ ' ꢈ ꢁ
6
ꢈ ꢆꢊꢐ 6ꢉ 6
ꢈ ꢁꢊꢍꢇ 6ꢉ ' ꢈ ꢁ
ICM
##
ICM
ꢉ # ꢈ ꢁꢂꢂ P&ꢉ 6RIPPLE ꢈ ꢁꢂꢂ M6
##
ꢉ# ꢈ ꢁꢂꢂ P&ꢉ 6
,
ꢈ ꢁꢂꢂ M6
,
PP
RIPPLE
PP
ꢁꢂ
ꢁꢂꢂ
ꢁꢂꢂꢂ
ꢁꢂꢂꢂꢂ
ꢁꢂꢂꢂꢂꢂ
ꢁꢂꢂꢂꢂꢂꢂ
ꢁꢂ
ꢁꢂꢂ
ꢁꢂꢂꢂ
ꢁꢂꢂꢂꢂ
ꢁꢂꢂꢂꢂꢂ
ꢁꢂꢂꢂꢂꢂꢂ
&REQUENCY ꢎ(Zꢏ
&REQUENCY ꢎ(Zꢏ
!-ꢂꢂꢅꢐꢑ
!-ꢂꢂꢅꢃꢂ
12/27
Doc ID 022743 Rev 1
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Application information
4
Application information
4.1
Operating voltages
The amplifiers of the TSV52x series can operate from 2.7 to 5.5 V. Their parameters are
fully specified for 2.7, 3.3 and 5 V power supplies. However, the parameters are very stable
in the full V range and several characterization curves show the TSV52x device
CC
characteristics at 2.7 V. Additionally, the main specifications are guaranteed in extended
temperature ranges from -40 to +125 °C.
4.2
Common mode voltage range
The TSV52x devices are built with two complementary PMOS and NMOS input differential
pairs. The devices have a rail-to-rail input and the input common mode range is extended
from V
- 0.1 V to V
+ 0.1 V.
CC-
CC+
The N channel pair is active for input voltage close to the positive rail typically (V
to 100 mv above the positive rail.
- 0.7 V)
CC+
The P channel pair is active for input voltage close to the negative rail typically 100 mV
below the negative rail to V + 0.7 V.
CC-
And between V
+ 0.7 V and V
- 0.7 V the both N and P pairs are active.
CC+
CC-
When the both pairs work together it allows to increase the speed of the TSV52x device.
This architecture improves a lot the merit factor of the whole device. In the transition region,
the performance of CMR, SVR, V (Figure 25 and Figure 26) and THD is slightly degraded.
io
Figure 25. Input offset voltage vs. input
Figure 26. Input offset voltage vs. input
common mode at V = 2.7 V
common mode at V = 5.5 V
CC
CC
ꢂꢊꢂ
ꢀꢂꢊꢁ
ꢀꢂꢊꢆ
ꢀꢂꢊꢍ
ꢀꢂꢊꢅ
ꢀꢂꢊꢇ
ꢀꢂꢊꢄ
ꢀꢂꢊꢐ
ꢀꢂꢊꢃ
ꢂꢊꢁ
ꢂꢊꢂ
ꢀꢂꢊꢁ
ꢀꢂꢊꢆ
ꢀꢂꢊꢍ
ꢀꢂꢊꢅ
ꢀꢂꢊꢇ
ꢀꢂꢊꢄ
ꢀꢂꢊꢐ
ꢀꢂꢊꢃ
ꢂꢊꢂ ꢂꢊꢍ ꢂꢊꢄ ꢂꢊꢑ ꢁꢊꢆ ꢁꢊꢇ ꢁꢊꢃ ꢆꢊꢁ ꢆꢊꢅ ꢆꢊꢐ
ꢂꢊꢂ ꢂꢊꢇ ꢂꢊꢑ ꢁꢊꢅ ꢁꢊꢃ ꢆꢊꢍ ꢆꢊꢐ ꢍꢊꢆ ꢍꢊꢄ ꢅꢊꢂ ꢅꢊꢇ ꢇꢊꢂ ꢇꢊꢅ
6
ꢎ6ꢏ
ICM
6
ꢎ6ꢏ
ICM
!-ꢂꢂꢅꢃꢁ
!-ꢂꢂꢅꢃꢆ
Doc ID 022743 Rev 1
13/27
Application information
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
4.3
Rail-to-rail input
The TSV52x series are guaranteed without phase reversal as shown in Figure 28.
It is extremely important that the current flowing in the input pin does not exceed 10 mA.
In order to limit this current a serial resistor can be added on the V path.
in
Figure 27. Phase reversal test schematic
Figure 28. No phase reversal
ꢄ
ꢇ
ꢇ 6
ꢅ
6
INP
ꢓ
?
6
6
ꢓ
ꢀ
ꢍ
##
##
6
OUT
ꢆ
ꢁ
6
6
ꢈ ꢇꢊꢇ 6
##
INN
ꢈ ꢆꢊꢐꢇ 6
ꢂ
ꢆꢊꢇ 6
ꢀꢁ
ꢀꢆꢊꢂ ꢀꢁꢊꢂ
ꢂꢊꢂ
ꢁꢊꢂ
ꢆꢊꢂ
ꢍꢊꢂ
ꢅꢊꢂ
ꢇꢊꢂ
ꢄꢊꢂ
6
ꢎ6ꢏ
INP
!-ꢂꢂꢅꢃꢍ
!-ꢂꢂꢅꢃꢅ
4.4
4.5
Rail-to-rail output
The operational amplifiers output levels can go close to the rails: 35 mV maximum above
and below the rail when connected to a 10 kΩ resistive load to V /2.
CC
Driving resistive and capacitive loads
To drive high capacitive load, adding in series resistor at the output can improve the stability
of the device (see Figure 29 for recommended in series value). Once the in series resistor
has been selected, the stability of the circuit should be tested on bench and simulated with
simulation models. The R
is placed in parallel with capacitive load. The R
and the
load
load
in series resistor create a voltage divider introducing an error proportional to the ratio
R /R
. By choosing R as low as possible, this error is generally negligible.
s
load
s
14/27
Doc ID 022743 Rev 1
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Figure 29. In series resistor versus capacitive load
Application information
3TABLE
ꢁꢂꢂ
5NSTABLE
ꢁꢂ
6
ꢈ ꢇ 6ꢉ 6 ꢈ ꢆꢊꢇ 6ꢉ 4 ꢈ ꢆꢇ #ꢉ 2
LOAD
ICM
##
-INIMUM SERIAL RESISTOR TO BE ADDED TO A GIVEN
CAPACITIVE LOAD IN ORDER TO ENSURE STABILITY
ꢁ
ꢂꢊꢁ
ꢁꢊꢂ
ꢁꢂꢊꢂ
ꢁꢂꢂꢊꢂ
#APACITIVE LOAD ꢎN&ꢏ
!-ꢂꢂꢅꢃꢇ
4.6
Input offset voltage drift over temperature
The maximum input voltage drift over temperature variation is defined as the offset variation
related to offset value measured at 25 °C. The operational amplifier is one of the main
circuits of the signal conditioning chain, and the amplifier input offset is a major contributor
to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during
production at application level. The maximum input voltage drift over temperature enables
the system designer to anticipate the effects of temperature variations.
The maximum input voltage drift over temperature is computed in Equation 1:
Equation 1
ΔVio
Vio(T) – Vio(25° C)
--------------------------------------------------
T – 25° C
----------- = max
ΔT
with T = -40 °C and 125 °C.
The datasheet maximum value is guaranteed by measurement on a representative sample
size ensuring a Cpk greater than 2.
Doc ID 022743 Rev 1
15/27
Application information
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
4.7
Long term input offset voltage drift
In a product reliability evaluation, two types of stress acceleration are usable:
●
Voltage acceleration, by changing the applied voltage
●
Temperature acceleration, by changing the die temperature (below the maximum
junction temperature allowed by the technology) with the ambient temperature
The voltage acceleration has been defined based on JEDEC results, and is defined by:
Equation 2
AFV = eβ ⋅ (V – V )
S
U
where:
A
ß
V
V
is the voltage acceleration factor
FV
is the voltage acceleration constant in 1/V, constant technology parameter
is the stress voltage used for the accelerated test
is the use voltage for the application
S
U
The temperature acceleration is driven by the Arrhenius model, and is defined by:
Equation 3
Ea
-----
1
1
⎛
⎝
⎞
⎠
⋅
------ – ------
TU TS
AFT = e k
where:
A
E
k
is the temperature acceleration factor
FT
a
is the activation energy of the technology based on failure rate
is the Boltzmann’s constant
T
T
is the temperature of the die when V is used
U
S
U
is the temperature of the die under temperature stress
The final acceleration factor, A , is the multiplication of these two acceleration factors, which
F
is:
Equation 4
A = A x A
FV
F
FT
Based on this A , calculated following the defined usage temperature and usage voltage of
F
the product, the 1000 h duration of the stress corresponds to a number of equivalent months
of usage.
Equation 5
Months = A x 1000 h x 12 months / (24h x 365.25 days)
F
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Doc ID 022743 Rev 1
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Application information
For the operational amplifier, a follower stress condition is used for the reliability evaluation,
with V defined in function of the Maximum operating voltage and the absolute maximum
CC
rating (as recommended by the JEDEC standards).
The V drift, in µV, of the product after 1000 h duration of stress is tracked with parameters
io
at different measurement conditions, as for example:
Equation 6
V
= max. V with V =V /2
op icm CC
CC
Finally, knowing the calculated number of months and with the measured drift value of the
V (corresponding to the electrical characteristics of the respective table) after 1000 h
io
duration of stress, the ratio of the V drift over the square of months, ΔV in µV/√month, is
io
io
defined as the long term drift parameter, the parameter estimating the reliability
performance of the product.
Equation 7
ΔV = V drift / √(months)
io
io
4.8
4.9
PCB layouts
For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible
to the power supply pins.
Macromodel
Accurate macromodels of the TSV52x device are available on STMicroelectronics™ website
at www.st.com. This model is a trade-off between accuracy and complexity (that is, time
simulation) of the TSV52x operational amplifiers. It emulates the nominal performance of
a typical device within the specified operating conditions mentioned in the datasheet. It also
helps to validate a design approach and to select the appropriate operational amplifier, but it
does not replace onboard measurements.
Doc ID 022743 Rev 1
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Package information
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
5
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
18/27
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TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Package information
Figure 30. SC70-5 package outline
SIDE VIEW
DIMENSIONS IN MM
GAUGE PLANE
COPLANAR LEADS
SEATING PLANE
TOP VIEW
Table 7.
Ref
SC70-5 package mechanical data
Dimensions
Millimeters
Typ.
Inches
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
b
0.80
0
1.10
0.10
1.00
0.30
0.22
2.20
2.40
1.35
0.032
0.043
0.004
0.039
0.012
0.009
0.087
0.094
0.053
0.80
0.15
0.10
1.80
1.80
1.15
0.90
0.032
0.006
0.004
0.071
0.071
0.045
0.035
c
D
2.00
2.10
1.25
0.65
1.30
0.36
0.079
0.083
0.049
0.025
0.051
0.014
E
E1
e
e1
L
0.26
0°
0.46
8°
0.010
0.018
<
Doc ID 022743 Rev 1
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Package information
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Figure 31. DFN8 2 x 2 x 0.6, 8 pitch, 0.5 mm package outline
Table 8.
Ref.
DFN8 2 x 2 x 0.6, 8 pitch, 0.5 mm package mechanical data
Dimensions
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
A1
A3
b
0.51
0.55
0.60
0.05
0.020
0.022
0.024
0.002
0.15
0.25
2.00
1.60
2.00
0.90
0.50
0.006
0.010
0.079
0.063
0.079
0.035
0.020
0.18
1.85
1.45
1.85
0.75
0.30
2.15
1.70
2.15
1.00
0.007
0.073
0.057
0.073
0.030
0.012
0.085
0.067
0.085
0.039
D
D2
E
E2
e
L
0.50
0.08
0.020
0.003
ddd
20/27
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TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Package information
Figure 32. DFN8 2 x 2 0.6, 8 pitch, 0.5 mm footprint recommendation
Doc ID 022743 Rev 1
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Package information
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Figure 33. MiniSO8 package outline
-INI3/ꢃ,
Table 9.
Symbol
MiniSO8 package mechanical data
Dimensions
Millimeters
Typ.
Inches
Typ.
Min.
Max.
Min.
Max.
A
A1
A2
b
1.10
0.15
0.95
0.40
0.23
3.20
5.15
3.10
0.043
0.006
0.037
0.016
0.009
0.126
0.203
0.122
0
0
0.75
0.22
0.08
2.80
4.65
2.80
0.85
0.030
0.009
0.003
0.11
0.033
c
D
3.00
4.90
3.00
0.65
0.60
0.95
0.25
0.118
0.193
0.118
0.026
0.024
0.037
0.010
E
0.183
0.11
E1
e
L
0.40
0°
0.80
0.016
0°
0.031
L1
L2
k
8°
8°
ccc
0.10
0.004
22/27
Doc ID 022743 Rev 1
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Figure 34. QFN16 - 3 x 3 x 0.9 mm, pad 1.7 - package outline
Package information
6&10.ꢁꢄ,
Doc ID 022743 Rev 1
23/27
Package information
Table 10.
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
QFN16 - 3 x 3 x 0.9 mm, pad 1.7 - package mechanical data
Dimensions
Symbol
Millimeters
Min.
Inches
Min.
Nom.
Max.
Nom.
Max.
A
A1
A3
b
0.90
0.80
0.00
1.00
0.05
0.035
0.032
0.000
0.039
0.002
0.20
3.00
3.00
0.50
0.008
0.118
0.118
0.020
0.18
2.90
1.50
2.90
1.50
0.30
3.10
1.80
3.10
1.80
0.007
0.114
0.061
0.114
0.061
0.012
0.122
0.071
0.122
0.071
D
D2
E
E2
e
L
0.30
0.50
0.012
0.020
Figure 35. QFN16 - 3 x 3 x 0.9 mm, pad 1.7 - footprint recommendation
1&.ꢁꢄꢀ&0
24/27
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TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
Package information
Figure 36. TSSOP14 body 4.40 mm, lead pitch 0.65 mm - package outline
433/0ꢁꢅ
Table 11.
Symbol
TSSOP14 body 4.40 mm, lead pitch 0.65 mm - package mechanical data
Dimensions
Millimeters
Typ.
Inches
Typ.
Min.
Max.
Min.
Max.
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
5.10
6.60
4.50
0.047
0.006
0.041
0.012
0.0089
0.201
0.260
0.176
0.05
0.80
0.19
0.09
4.90
6.20
4.30
0.002
0.031
0.007
0.004
0.193
0.244
0.169
0.004
0.039
1.00
c
D
5.00
6.40
4.40
0.65
0.60
1.00
0.197
0.252
E
E1
e
0.173
0.0256 BSC
L
0.45
0°
0.75
L1
k
8°
0°
8°
aaa
0.10
0.018
0.024
0.030
Doc ID 022743 Rev 1
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Ordering information
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
6
Ordering information
Table 12.
Order codes
Order code
TSV521ICT
Temperature range
Package
Packing
Marking
SC70-5
DFN8 2 x 2
MiniSO8
K1G
K1G
TSV522IQ2T
TSV522IST
-40 to 125 °C
Tape and reel
K1G
QFN16 3 x 3
TSSOP14
MiniSO8
K1G
TSV524IQ4T
TSV524IPT
TSV524
K1H
TSV522IYST
TSV524IYPT
TSV521AICT
TSV522AIQ2T
TSV522AIST
TSV524AIQ4T
TSV524AIPT
TSV522AIYST
TSV524AIYPT
-40 to 125 °C
Automotive grade
Tape and reel
Tape and reel
Tape and reel
(1)
TSSOP14
SC70-5
TSV524Y
K1K
DFN8 2 x 2
MiniSO8
K1K
-40 to 125 °C
K1K
QFN16 3 x 3
TSSOP14
MiniSO8
K1K
TSV524A
K1L
-40 to 125 °C
Automotive grade
(1)
TSSOP14
TSV524AY
1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC
Q001 and Q 002 or equivalent are ongoing.
7
Revision history
Table 13.
Document revision history
Revision
Date
19-Jun-2012
Changes
1
Initial release.
26/27
Doc ID 022743 Rev 1
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
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