TDA7705_10_技术文档

TDA7705

Highly integrated tuner for AM/FM car radio

Features

■ Fully integrated VCO for world tuning

■ High performance PLL for fast RDS system

■ AM/FM mixers with high image rejection

■ Integrated AM-LNA and AM-PINDIODE

■ Automatic self alignment for preselection and

image rejection

■ Digital IF signal processing, high performance

LQFP64

and drift-free

■ Integrated IF-filters with high selectivity, high

dynamic range and adaptive bandwidth control

■ RDS demodulation with group and block

synchronization

It contains mixers and IF amplifiers for AM and

FM, fully integrated VCO and PLL synthesizer,

IF-processing including adaptive bandwidth

control, stereo decoder and RDS decoder on a

single chip.

■ High performance stereodecoder with

noiseblanker

2

■ I C/SPI bus controlled

■ Single 5 V supply

■ LQFP64 package

The utilization of digital signal processing results

in numerous advantages against today's tuners:

very low number of external components, very

small space occupation and easy application,

very high selectivity due to digital filters, high

flexibility by software control and automatic

alignment.

Description

The TDA7705 highly integrated tuner (HIT) is a

new generation of high performance tuners for

carradio applications.

Table 1.

Device summary

Order code

Package

Packing

TDA7705

LQFP64 (10x10x1.4mm)

Tray

TDA7705TR

Tape and reel

March 2010

Doc ID 15938 Rev 8

1/42

www.st.com

1

Contents

TDA7705

Contents

1

Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1

1.2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2

Function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

FM - mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

FM - AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

AM - LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

AM - AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

AM - mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

IF A/D converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Audio D/A converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.10 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.11 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.12 IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.13 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.13.1 Serial interface choice / boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2

2.13.2 I C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.13.3 SPI bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1

3.2

3.3

3.4

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4.1

3.4.2

3.4.3

3.4.4

3.4.5

FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Tuning DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2/42

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TDA7705

Contents

3.4.6

3.4.7

3.4.8

3.4.9

IF ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2

I C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4.10 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4.11 Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.5

Overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.5.1

3.5.2

3.5.3

3.5.4

3.5.5

FM overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

AM MW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

AM LW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

AM SW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

WX overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4

5

Front-end processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Weak signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.1

FM IF-processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

Dynamic channel selection filter (DISS) . . . . . . . . . . . . . . . . . . . . . . . . 33

Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Adjacent channel mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Stereo blend- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

High cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Stereo decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.2

AM IF-processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.2.1

5.2.2

5.2.3

Channel selection filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

High cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6

Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.1

6.2

Basic application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Application schematic example with SPI-bus and tuned preselection . . . 39

7

8

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Doc ID 15938 Rev 8

3/42

List of tables

TDA7705

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Boot mode pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Tuning DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

IF ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

2

I C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

FM overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

AM MW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

AM LW overall system performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

AM SW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

WX overall system performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Register 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Register 0x01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Register 0x02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Register 0x05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Dynamic channel selection filter (DISS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Adjacent channel mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Stereo blend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

High cut control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

De-emphasis filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Stereo decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Channel selection filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

High cut control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2

I C "write" sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2

I C "read" sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SPI "write" sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SPI "read" sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2

I C bus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

SPI bus timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 10. FM input set-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 11. AM MW input set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 12. AM LW input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 13. AM SW input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 14. WX input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2

Figure 15. FM wide-band application / I C control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 16. Example of FM tuned (narrow-band) application / SPI control . . . . . . . . . . . . . . . . . . . . . . 39

Figure 17. LQFP64 (10x10x1.4mm) mechanical data and package dimensions. . . . . . . . . . . . . . . . . 40

Doc ID 15938 Rev 8

5/42

Block diagram and pins description

TDA7705

1

Block diagram and pins description

1.1

Block diagram

Figure 1.

Functional block diagram

SUM

6/42

Doc ID 15938 Rev 8

TDA7705

Block diagram and pins description

1.2

Pin description

Figure 2.

Pin connection (top view)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

2

3

4

5

6

7

8

9

LFI

PLLTEST

DAC

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

GND-1V2

VDD-1V2

TEST

TCAGCFM

FMMIX1dec

FMMIX1in

FMMIX2in

GND-RF

FMPINDRV

VCC-RF

RSTN

MODE

GPIO0

GPIO1

GPIO2

GPIO3

RDSINT

VDD-1V2

SCL/CLK

SDA/MOSI

SPI_MISO

SPI_CS

GND-3V3

10

11

12

13

14

TCAM

AMPINDRV

PINDdec

PINDin

GND-LNA

LNAin

15

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

AC00418

Table 2.

Pin #

Pin description

Pin name

Function

1

2

LF1

PLL loopfilter output

PLLTEST

DAC

PLL test output / GPO

FM tuning DAC output

FM AGC time constant

FM mixer decoupling

3

4

TCAGCFM

FMMIX1dec

FMIX1in

FMIX2in

GND-RF

FMPINDRV

VCC-RF

TCAM

5

6

FM mixer input 1

7

FM mixer input 2

8

RF Ground

9

FM AGC PIN diode driver

5V supply for RF section

AM AGC time constant

AM AGC external PIN diode driver

AM AGC internal PIN diode decoupling

AM AGC internal PIN diode input

AM LNA and internal PIN diode GND

AM LNA input

10

11

12

13

14

15

16

AMPINDRV

PINDdec

PINDin

GND-LNA

LNAin

Doc ID 15938 Rev 8

7/42

Block diagram and pins description

TDA7705

Table 2.

Pin #

Pin description (continued)

Pin name

LNAdec

Function

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

AM LNA decoupling

AM LNA output first stage

AM LNA input 2^ndstage

AM LNA output

LNAout

LNAin2

LNAout2

LNAdec2

AMMIXin2

AMMIXin1

AMMIXdec

GND-IF

AM LNA decoupling 2^ndstage

AM mixer input 2

AM mixer input 1

AM mixer decoupling

IF and Vref GND

VREF165

VREFdec

GND-DIG

VCC-DIG

VCCreg1V2

REG1V2

VDD-3V3

GND-3V3

SPI_CS

1.65V reference voltage decoupling

3.3V reference voltage decoupling

Digital GND

5V supply for digital logic

VCC of 1.2V regulator

1.2V regulator output

3.3V VDD output / decoupling

3.3V VDD GND

SPI chip select

SPI_MISO

SPI Data output

SDA / SPI_MOSI I²C bus data / SPI data input

SCL / SPI_CLK I²C bus Clock / SPI clock

VDD-1V2

RDSINT

GPIO3

1.2V DSP supply

RDS interrupt

Reserved

GPIO2

Reserved

GPIO 1

GPIO 0

MODE

Reserved

For debug purpose only, connected to GND

Reset pin (active low)

Test input

RSTN

TEST

VDD-1V2

GND-1V2

VCC-DAC

OSCout

OSCin

1.2V DSP supply

Digital GND for 1.2V VDD

5V supply of audio DAC

Xtal osc output

Xtal osc input

8/42

Doc ID 15938 Rev 8

TDA7705

Block diagram and pins description

Function

Table 2.

Pin #

Pin description (continued)

Pin name

52

53

54

55

56

57

58

59

60

61

62

63

64

GND-DAC

DACoutL

DACoutR

GND-IFADC

LIFrefL

Audio DAC GND

Audio output left

Audio output right

IF ADC GND

IF ADC reference low

IF ADC reference high

5V supply of IF ADC

5V supply of PLL

PLL GND

LIFrefH

VCC-IFADC

VCC-PLL

GND-PLL

VCO-dec

LFref

VCO decoupling

Loopfilter reference

5V supply of VCO

VCO GND

VCC-VCO

GND-VCO

Doc ID 15938 Rev 8

9/42

Function description

TDA7705

2

Function description

2.1

FM - mixers

The image-rejection mixer has two FM inputs, selectable through software. These inputs

feed stages with different gains, noise figures, and IIP3. They are optimized for best

performance in case of a passive tuned prestage and for a passive fixed bandpass without

tuning for low-cost application respectively.

The second input offers also the possibility of an easy addition of a weather-band

preselection filter.

The input frequency is downconverted to low IF with high image rejection.

The tuned application is supported by an 8-bit tuning DAC. The alignment of the DAC is

performed automatically.

2.2

FM - AGC

The programmable RFAGC senses the mixer input whereas the IFAGC senses the IFADC

input to avoid overload.

The PIN diode driver is able to drive external PIN diodes with a current value as high as

15mA.

The time constant of the FM-AGC is defined by an external capacitor.

2.3

2.4

AM - LNA

The AM-LNA is integrated with low noise and high IIP2 and IIP3. The gain of the LNA is

controlled by the AGC. The maximum gain is set with an external resistor, typically 26 dB

with 1 kΩ.

AM - AGC

The programmable AM-RF-AGC senses the mixer inputs and controls the internal PIN diode

and LNA gain.

First the LNA gain is reduced by about 10dB, then the PIN diodes are activated to attenuate

the signal.

The time constant of the AM-AGC is defined with an external capacitor and programmable

internal currents.

2.5

AM - mixers

The image-rejection mixer has two AM inputs selectable via software. It easily supports low-

cost applications for extended frequency bands like SW, DRM.

The input frequency is converted to low IF with high image rejection.

10/42

Doc ID 15938 Rev 8

TDA7705

Function description

2.6

IF A/D converters

A high performance IQ-IFADC converts the IF-signal to digital IF for subsequent digital

signal processing.

2.7

2.8

Audio D/A converters

A stereo DAC provides the left / right audio signals after IF-processing and stereodecoding

by the DSP.

VCO

The VCO is fully integrated without any external tuning component. It covers all FM

frequency bands including EU, US , Japan, EastEU, Weatherband and AM-bands including

LW, MW, SW.

2.9

PLL

The high speed tuning PLL is able to settle within about 300 µs for fast RDS applications.

The frequency step can be as low as 5 kHz in FM and 500 Hz in AM.

2.10

2.11

Crystal oscillator

The device works with a 37.05 MHz fundamental tone crystal, and can be used also with a

rd

3

overtone 37.05 MHz crystal.

DSP

The DSP and its hardware accelerators perform all the digital signal processing. The main

program is fixed in ROM. Control parameters are copied in RAM and are accessible and

modifiable there, thus allowing parametric performance optimization.

It performs:

●

digital down-conversion of IF

bandwidth selection with variable controlled bandwidth

FM and AM noiseblanking

FM/AM demodulation with softmute, high-cut, weak signal processing and quality

detection

●

FM stereo decoding with stereo blend

RDS demodulation including error correction and block synchronization with generation

of an RDS interrupt for the main µP

●

Autonomous control of RDS-AF tests

Self alignment of preselection tuning

Doc ID 15938 Rev 8

11/42

Function description

TDA7705

2.12

IO interface pins

The TDA7705 has the following IO pins:

PLLTEST

SPI_CS

pin 2

general purpose output

pin 34

serial communication with µP

reset pin driven by µP

SPI_MISO pin 35

SDA/MOSI pin 36

SCL/CLK

RDSINT

RSTN

pin 37

pin 39

pin 45

The pins labeled GPIO0, 1, 2 and 3 (pins 43 to 40) are reserved.

The pin PLLTEST output voltage can be freely programmed via software and be used to

drive switches if needed by the application.

All the inputs are voltage-tolerant up to 3.5 V . The outputs can drive currents up to 0.5 mA

from the internal 3.3 V supply line.

2.13

Serial interface

2

The device is controlled with a standard I C bus or SPI interface.

Through the serial bus the processing parameters can be modifed and the signal quality

parameters and the RDS information can be read out.

The operation of the device is handled through high level commands sent by the main car-

radio µP through the serial interface, which allow to simplify the operations carried out in the

main µP. The high level commands include among others:

●

set frequency (which allows to avoid computing the PLL divider factors);

●

start seek (the seek operation can be carried out by the TDA7705 in a completely

autonomous fashion);

●

RDS seek/search (jumps to AF and quality measurements are automatically

sequenced).

2.13.1

Serial interface choice / boot mode

The device can communicate with the main µP with two different standard serial protocols:

2

SPI and I C. The configuration is chosen by setting the proper value (0V or 3.3V) at pins 35

and 39 and it is latched (e.g. made effective) when the RSTN line transitions from low to

high (when RSTN is low, the IC is in reset mode).

The voltage level forced to pins 35 and 39 must be released to start the system operation a

suitable time after the RSTN line has gone high.

The list of configurations is shown in the following table:

12/42

Doc ID 15938 Rev 8

TDA7705

Table 3.

Function description

SPI

Boot mode pin configuration

I²C (addr. 0 x C2)

Configuration:

I²C (addr. 0 x C8)

RDSINT

at reset

operation

at reset

operation

at reset

operation

0

RDS interrupt

out

0

RDS interrupt

out

1

RDS interrupt

out

39

37

36

35

34

in

I²C SCL

in

I²C SCL

in

SPI CLK

in

SCL

SDA

x

I²C SDA

in/out

I²C SDA

in/out

SPI MOSI

in

0

1

SPI MISO

out

(SPI_MISO)

-

in

SPI SS

in

(SPI_CS)

2

x

If I C serial bus is chosen as means of communication with the controlling device, two chip

addresses are possible: 0xC2/C3 or 0xC8/C9, depending on the initial configuration of pins

35 and 39.

The status of pins 35 and 39 during the reset phase can be set to:

high, through external <10 kΩ resistors tied to 3.3V (pin 32), or

low, by not forcing any voltage on them from outside, as 50 kohm internal pull-down

resistors are present on said pins.

To make sure the boot mode is correctly latched up at start-up, it is advisable to keep the

RSTN line low until the IC supply pins have reached their steady state, and then for an

additional time T

(see Section 3.4.8).

reset

2

2.13.2

I C bus protocol

2

I C requires two signals: clock (SCL) and data (SDA - bidirectional). The protocol requires

an acknowledge after any 8-bit transmission.

A "write" communication example is shown in the figure below, for an unspecified number of

data bytes (see the relevant technical documentation for frame structure description):

2

Figure 3.

I C "write" sequence

SDA

SCL

a7

a6

…

a0

d7

d6

…

d0

clk1

clk2

…

clk8

clk9

clk1

clk2

…

clk8

clk9

START

address

ACK

data

ACK

STOP

Doc ID 15938 Rev 8

13/42

Function description

The sequence consists of the following phases:

TDA7705

●

START: SDA line transitioning from H to L with SCL fixed H. This signifies a new

transmission is starting;

data latching: on the rising SCL edge. The SDA line can transition only when SCL is

low (otherwise its transitions are interpreted as either a START or a STOP transition);

th

ACKnowledge: on the 9 SCL pulse the µP keeps the SDA line H, and the TDA7705

pulls it down if communication has been successful. Lack of the acknowledge pulse

generation from the TDA7705 means that the communication has failed;

●

a chip address byte must be sent at the beginning of the transmission. The value can

be C2 or C8 (according to the mode chosen at start-up during boot) for "write";

as many data bytes as needed can follow the address before the communication is

terminated. See the next section for details on the frame format;

STOP: SDA line transitioning from L to H with SCL H. This signifies the end of the

transmission.

Red lines represent transmissions from the TDA7705 to the µP.

A "read" communication example is shown in the figure below, for an unspecified number of

data bytes (see later on for frame structure decription):

2

Figure 4.

I C "read" sequence

SDA

SCL

a7

a6

…

a0

d7

d6

…

d0

clk1

clk2

…

clk8

clk9

clk1

clk2

…

clk8

clk9

START

address

ACK

data

ACK

STOP

The sequence is very similar to the "write" one and has the same constraints for start, stop,

data latching. The differences follow:

●

a chip address must always be sent by the µP to the TDA7705; the address must be C3

(if C2 had been selected at boot) or C9 (if C8 had been selected at boot);

●

a header is transmitted after the chip address (the same happens for "write") before

data are transferred from the TDA7705 to the µP. See the relevant technical

documentation for details on the frame format;

●

when data are transmitted from the TDA7705 to the µP, the µP keeps the SDA line H;

the ACKnowledge pulse is generated by the µP for those data bytes that are sent by the

TDA7705 to the µP. Failure of the µP to generate an ACK pulse on the 9 CLK pulse

th

has the same effect on the TDA7705 as a STOP.

The max. clock speed is 500 kbit/s.

2.13.3

SPI bus protocol

SPI requires four signals: clock (CLK), master output/slave input (MOSI - for communication

from the µP to the TDA7705), master input/slave output (MISO - for communication from the

TDA7705 to the µP), chip select (CS). CLK is generated by the master device and is used

for synchronization. MOSI and MISO are the data lines. The CS line is unique for each

device in an SPI bus. The µP pulls low the TDA7705 CS line to select it for communication.

The protocol does not foresee any transmission acknowledgement.

The SPI protocol has four possible modes of operation as far as data latching is concerned:

14/42

Doc ID 15938 Rev 8

TDA7705

Function description

Figure 5.

SPI modes

In the case of the TDA7705, the data are latched on the clock's rising edge, with CPOL = 1

and CPHA = 1 (mode 3 in the figure above). According to the specification of this mode, the

polarity of the CLK line when no communication is taking place is high.

A "write" communication example is shown in the figure below, for an unspecified number of

bits (see the relevant technical documentation for frame structure description):

Figure 6.

SPI "write" sequence

CS

CLK

MOSI

MSB

...

LSB

The start condition is signaled by the CS line going low, and the stop condition by the CS

line going high. It is not allowed to toggle the CS line while the communication is going on.

A "read" communication example is shown in the figure below, for an unspecified number of

bits (see the relevant technical documentation for frame structure description ):

Figure 7.

SPI "read" sequence

CS

CLK

MOSI

MISO

MSB

...

LSB

MSB

...

LSB

The red line is controlled by the TDA7705, whereas the black lines are controlled by the µP.

Doc ID 15938 Rev 8

15/42

Electrical specifications

TDA7705

3

Electrical specifications

3.1

Absolute maximum ratings

Table 4.

Symbol

Absolute maximum ratings

Parameter

Supply voltage

Test condition

Min

Typ

Max

Units

V_CC

T_stg

-

5.5

V

Storage temperature

-

-55

-

150

°C

Human body model

Charged device model

Charged device model, corner pins

Machine model

≥ 2000

≥ 450

≥ 750

≥ 150

V_ESD

ESD withstand voltage

V

3.2

Thermal data

Table 5.

Symbol

Thermal data

Parameter

Test condition

LQFP64 10x10, double-layer JEDEC PCB

Value

Units

Thermal resistance

junction-to-ambient

R_{Th j-amb}

55

°C/W

3.3

General key parameters

Table 6.

Symbol

General key parameters

Parameter

Test condition

Min

Typ

Max

Units

V_CC

I_CC

5 V supply voltage

-

4.7

-

5

5.25

295

85

V

mA

°C

V

Supply current @ 5 V

Ambient temperature range

220

T_amb

-40

2

-

V_VCCREG12VCCREG12 supply voltage

see note⁽¹⁾

-

when supplied externally

see note ⁽²⁾

Digital core 1.2V supply

voltage

V_1V2

1.08

1.2

-

1.32

120

135

150

V

V_1V2= 1.08 V

see note ⁽²⁾

-

mA

Digital core 1.2 V supply

current

V_1V2= 1.2 V

see note ⁽²⁾

I_1V2

80

-

V_1V2= 1.32 V

see note ⁽²⁾

1. In the typical application supplied from 5V with a series resistor.

2. When the 1.2 V supply is applied externally, and not using the internal 1.2 V regulator.

16/42

Doc ID 15938 Rev 8

TDA7705

Electrical specifications

3.4

Electrical characteristics

V

= 4.7 V to 5.25 V; T

= -40 °C to +85 °C; unless otherwise specified.

CC

amb

3.4.1

FM - section

Table 7.

Symbol

FM - section

Parameter

Test condition

Min

Typ

Max

Units

FM IMR mixer

R_in

Input resistance

-

90

-

130

2.5

170

3.1

kΩ

Mix 1, R_source= 1.5 kΩ,

noiseless

V_noise

Input noise voltage

nV/√Hz

Mix 2, R_source= 800 Ω,

noiseless

-

2

2.5

-

Mix 1

122

118

125

121

dBµV

up to V_in/tone= 90 dBµV

Mix 2

IIP3

3

^rdorder intercept point

up to V_in/tone= 85 dBµV

FM AGC

Mix 1, min setting

Mix 1, max setting

Mix 2, min setting

Mix 2, max setting

-

87

93

85

91

2

-

RFAGC threshold, referred to

mixer input;

-

dBµV

-

RF level

RFAGC-Thr

-

Threshold steps

-

dB

Threshold error

@ T_amb= 27 °C

-1.5

1.5

Threshold temperature drift

-

0.016

81

-

dB/K

Mix 1, min setting

-

IFAGC threshold, referred to

mixer input; at tuned

frequency

Mix 1, max setting

-

85

-

dBµV

Mix 2, min setting

-

77

RF level

IFAGC-Thr

Mix 2, max setting

-

81

-

Threshold steps

-

2

-

dB

Threshold error

@ T_amb= 27 °C

-1.5

1.5

-

Threshold temperature drift

Pin diode source current

Pin diode sink current

-

0.016

dB/K

mA

µA

-

@ T_amb= 27 °C; see note⁽¹⁾

12

3

-

20

Pin diode source current in

constant current mode

-

@ T_amb= 27 °C; see note⁽¹⁾

0.4

-

mA

1. The current is generated by a PTAT (Proportional To Absolute Temperature) source, and has therefore a temperature

dependency described by: ΔI/Io = ΔT/To, with Io being the current at ambient temperature (25 °C) and To the ambient

temperature (25°C) expressed in Kelvin, that is 298 K.

Doc ID 15938 Rev 8

17/42

Electrical specifications

TDA7705

Units

3.4.2

AM - section

Table 8.

Symbol

AM - section

Parameter

Test condition

Min

Typ

Max

AM IMR Mixer

R_in

Input resistance

-

20

-

30

45

-

kΩ

V_{out_max}

Max. output voltage

Input noise voltage

without clipping

126

dBµV

Mix 1, R_source= 1 kΩ,

noiseless

-

8.5

129

12

-

V_N,in

nV/√Hz

Mix 2, R_source= 1 kΩ,

noiseless

Mix 1,2

IIP3

IIP2

3

^rdorder intercept point

126

dBµV

dB

up to V_in/tone= 90 dBµV

Mix1 1,2

2^ndorder intercept point

-

158

-

up to V_in/tone= 90 dBµV

N=2,3,4,5,6

N=7,9

-

100

85

-

LO hsupp LO harmonic suppression

AM LNA

Max Gain, R_ext= 1 kΩ

21

-

25

12

28

-

Gain

Voltage gain

dB

Min Gain (AGC controlled)

R_in

C_in

Input resistance

Input capacitance

Input noise voltage

-

1000

20

kΩ

pF

-

V_N,in

IIP3

IIP2

-

1.0

1.4

nV/√Hz

dBµV

3

2

^rdorder intercept point

^ndorder intercept point

@ maximum LNA gain

-

125

143

-

AM PIN diode

Full attenuation,

C_source= 80 pF, f=1 MHz

IIP2

2^ndorder intercept point

-

140

-

dBµV

R_min

C_in

Minimum resistance

Input capacitance

-

50

12

80

-

Ω

High ohmic

pF

AM AGC

Mix 1,2 min setting

-

87

93

1

-

Referred to mixer input

RF level

AGC-Thr

dBµV

dB

Mix 1,2 max setting

Threshold steps

-

Thr-steps Threshold error

Threshold temperature drift

@ T_amb= 27 °C

-2.5

-3

2

-

2.5

3

-

Pin diode source current

Pin diode sink current

@ T_amb= 27 °C; see note⁽¹⁾

-

10

50

mA

µA

-

15

35

Pin diode source current in

constant current mode

-

@ T_amb= 27 °C; see note⁽¹⁾

1.5

2.5

3.5

mA

1. The current is generated by a PTAT (Proportional To Absolute Temperature) source, and has therefore a temperature

dependency described by: ΔI/Io = ΔT/To, with Io being the current at ambient temperature (25 °C) and To the ambient

temperature (25 °C) expressed in Kelvin, that is 298 K.

18/42

Doc ID 15938 Rev 8

TDA7705

Electrical specifications

3.4.3

VCO

Table 9.

Symbol

VCO

Parameter

Test condition

Min

Typ

Max

Units

F_VCO

Frequency range VCO

-

1100

1550

MHz

Locked VCO;

values referred @ 100MHz

@ 100 Hz

PN

Phase noise of LO

-

-100

-115

-

dBc/Hz

Hz

@ 1 kHz

@ 10 kHz

FM reception, deemphasis

50µs, f_audio= 20 Hz...20 kHz

dev

Deviation error (rms)

5

3.4.4

Phase locked loop

Table 10. Phase locked loop

Symbol

Parameter

Settling time FM

Test condition

Min

Typ

Max

Units

T_settle

Δf < 10 kHz

-

300

5

-

µs

kHz

Hz

FM step

AM step

FM frequency step

AM frequency step

-

500

3.4.5

Tuning DAC

Table 11. Tuning DAC

Symbol

Parameter

Test condition

Min

Typ

Max

Units

Res

V_outmin

V_outmax

R_out

Resolution

8 bit

-

18

-

0.7

-

mV

V

Min output voltage

Max ouput voltage

Output impdedance

Diff. Non linearity

Conversion time

0.6

-

VCC-0.2 VCC-0.1

V

1.5

2.5

-

3.5

0.5

-

kΩ

LSB

µs

DNL

-

T_conv

20

3.4.6

IF ADC

Table 12. IF ADC

Symbol

Parameter

Test condition

BW = 200 kHz

Min

Typ

Max

Units

DR_FM

Dynamic range in FM

-

90

-

dB

mixer 1

mixer 2

1.1

0.7

1.9

1.2

V_{N,in FM}

Input noise referred to mixer input

-

nV/√Hz

DR_AM

Dynamic range in AM

BW = 4 kHz

-

103

6.9

-

dB

V_{N,in AM}

Input noise referred to mixer input

12

nV/√Hz

Doc ID 15938 Rev 8

19/42

Electrical specifications

TDA7705

Units

3.4.7

Audio DAC

Table 13. Audio DAC

Symbol

Parameter

Test condition

Full scale

Min

Typ

Max

V_out

BW

Max. output voltage

Bandwidth

-

1

-

Vrms

KHz

Ω

1dB attenuation

-

15

R_out

Output resistance

Output noise

Distortion

-

600

750

60

900

95

V_{N, out}

THD

-

µVrms

%

-6 dBFS

0.03

0.04

3.4.8

IO interface pins

Table 14. IO interface pins

Symbol

Parameter

Test condition

_out= 500 µA

Min

Typ

Max

Units

High level output voltage (all

IOs except GPO pin 2)

-

I

2.9

3.2

-

V

GPIOs source current (all IOs Total sourced current by all

in source mode except pin 2) GPIOs

-

1.25

0.3

mA

V

Low level output voltage (all

I_out= -1 mA

0.1

IOs except GPO pin 2)

-

Input voltage range

-

0

2.0

-

3.5

-

V

High level input voltage

Low level input voltage

0.8

Minimum time during which

pin RSTN must be low so as

to reset the device

T

Reset time

10

-

µs

reset

Minimum time during which

the voltage applied at pins 25

and 39 must be kept in order

to latch the correct boot mode

(serial bus configuration)

Boot mode configuration latch

time

T_latch

10

-

µs

GPO PLLTEST (pin 2) max

source current

-

1

mA

GPO PLLTEST (pin 2) max

sink current

-1

GPO PLLTEST (pin 2)

minimum high level output

voltage

-

I_out= 1 mA

2.8

-

3.1

0.1

-

V

GPO PLLTEST (pin 2)

maximum high level output

voltage

I

_out= 1 mA

0.3

20/42

Doc ID 15938 Rev 8

TDA7705

Electrical specifications

2

3.4.9

I C interface

2

The following parameters apply to the serial bus communication when I C protocol has

been selected at start-up. For the other electrical characteristics of the pins, Section 3.4.8

applies. The parameters of the following table are defined as in Figure 8.

2

Table 15. I C interface

Symbol

Parameter

SCL Clock frequency

Min

Max

Units

f_SCL

t_AA

-

500

-

kHz

µs

SCL low to SDA data valid

0.3

time the bus must be kept free before a new

transmisison

t_buf

1.3

-

µs

t_HD-STA

t_LOW

START condition hold time

Clock low period

0.6

1.3

0.6

0.1

0

-

µs

t_HIGH

t_SU-SDA

t_HD-DAT

t_SU-DAT

t_R

Clock high period

-

START condition setup time

Data input hold time

Data input setup time

SDA & SCL rise time

SDA & SCL fall time

Stop condition setup time

Data out time

-

0.9

-

0.1

-

0.3

-

t_F

-

t_SU-STOP

t_DH

0.6

-

0.3

2

Figure 8.

I C bus timing diagram

t

F

HIGH

R

LOW

SCL

t

SU-STA

HD-DAT

t

SU-STOP

t

SU-DAT

t

HD-SDA

SDA IN

t

buf

AA

DH

SDA OUT

D95AU378A

Doc ID 15938 Rev 8

21/42

Electrical specifications

TDA7705

3.4.10

SPI interface

The following parameters apply to the serial bus communication when SPI protocol has

been selected at start-up. For the other electrical characteristics of the pins, Section 3.4.8

applies.

Table 16. SPI interface

Symbol

Parameter

Min

Max

Unit

f_SCK

t_SU

t_H

Clock frequency

Data setup time

Data hold time

SCK high time

SCK low time

Input rise time

Input fall time

-

4.0

-

MHz

ns

µs

ns

25

50

-

t_WH

t_WL

t_RI

-

2

50

-

t_FI

-

t_V

Output valid from clock low

Output hold time

Output disable time

CS high time

-

t_HO

t_DIS

t_CS

t_CSS

t_CSH

25

-

25

CS setup time

-

CS hold time

-

Figure 9.

SPI bus timing diagram

t

CS

V

IH

SPI_SS

V

IL

t

CSH

CSS

V

IH

t

WL

SPI_CLK

WH

t

IL

t

H

SU

V

IH

VALID IN

SPI_MOSI

V

IL

t

RI

FI

t

V

t

HO

DIS

V

OH

HI-Z

SPI_MISO

V

OL

3.4.11

Warning

When the TDA7705 is not powered on, the internal ESD protection diodes pull-down keep

2

the I C/SPI lines connected to ground. This implies that the I C/SPI bus connected to the

TDA7705 may not be used to drive other devices when the TDA7705 is powered off.

22/42

Doc ID 15938 Rev 8

TDA7705

Electrical specifications

3.5

Overall system performance

All measurements obtained with application of Figure 16 (FM tuned application / SPI

control) unless otherwise specified.

3.5.1

FM overall system performance

Antenna level equivalence: 0 dBµV = 1 µV

(Antenna terminal voltage with 50 Ω source).

rms

Figure 10. FM input set-up

A

50Ω

PCB

UNDER

TEST

50Ω

V_rf

+ 6dB

Input level referred to signal generator loaded with 50 Ω (V , node 'A'); no antenna dummy;

rf

AM input not connected. F = 98.1 MHz, V = 60 dBµV, mono modulation, f = 40 kHz,

rf

dev

f

= 1 kHz. De-emphasis = 50 µs. Unless otherwise specified

audio

Table 17. FM overall system performance

Parameter

Test condition

Min

Typ

Max

Units

(can be modified by the user)

Tuning range FM Eu

Tuning step FM Eu

Tuning range FM US

Tuning step FM US

Tuning range FM Jp

Tuning step FM Jp

Tuning range FM EEu

87.5

-

100

-

108

MHz

kHz

(automatic FE alignment

available)

(can be modified by the user)

-

87.5

-

107.9

-

(can be modified by the user)

MHz

kHz

(automatic FE alignment

available)

(can be modified by the user)

200

-

76

-

90

-

MHz

kHz

(automatic FE alignment

available)

(can be modified by the user)

100

-

65

74

MHz

(automatic FE alignment not

available)

Tuning step FM EEu

Sensitivity

(can be modified by the user)

S/N =26dB

-

100

-7

-

kHz

-4

dBµV

@ 10 dBµV, no highcut, DISS

BW = #3

S/N

-

55

75

81

73

-

dB

@ 60 dBµV, mono

72

78

70

@ 60 dBµV,

Deviation = 75 kHz, mono

Ultimate S/N

@ 60 dBµV, stereo

Doc ID 15938 Rev 8

23/42

Electrical specifications

Table 17. FM overall system performance (continued)

TDA7705

Units

Parameter

Test condition

Deviation= 75 kHz

Min

Typ

Max

Distortion

-

0.05

140

-

%

Max deviation

THD=3%

kHz

ΔF=100kHz, SINAD=30dB

desired 40 dBµV, dev=40kHz,

400Hz

undesired. dev=40kHz, 1KHz

Adjacent channel selectivity

Alternate channel selectivity

-

25

63

94

88

-

dB

ΔF=200 kHz, SINAD=30 dB

desired 40 dB µV,

dev=40kHz, 400 Hz

undesired. dev=40kHz, 1kHz

Desired = 10 dBµV

SINAD = 30 dB

Max. strong signal interferer

dBµV

Undesired ΔF = 5 MHz

dev = 40 kHz, 1 kHz

Desired = 10 dBµV

SINAD = 30 dB

no preselection (“wide-band”)

application

Undesired ΔF = 5 MHz

dev = 40 kHz, 1 kHz

Desired = 40 dBµV,

dev = 40 kHz, 400 Hz,

SINAD = 30 dB

Undesired1 = 400 kHz,

dev = 40 kHz, 1 kHz

-

103

106

103

-

dBµV

Undesired2 = 800 kHz, no

mod

3 signal performance⁽¹⁾

Desired = 40 dBµV,

dev = 40 kHz, 400 Hz,

SINAD = 30 dB

Undesired1 = 1 MHz,

dev=40kHz, 1 kHz

Undesired2= 2MHz, no mod

Desired = 40 dBµV,

dev = 40 kHz, 400 Hz,

SINAD = 30 dB

Undesired1 = 400 kHz,

dev = 40 kHz, 1 kHz

3 signal performance⁽¹⁾

Undesired2 = 800 kHz, no

mod

no preselection (“wide-band”)

application

Desired = 40 dBµV,

dev=40kHz, 400 Hz,

SINAD=30 dB

-

104

70

-

dBµV

dB

Undesired1 = 1 MHz,

dev=40kHz, 1 kHz

Undesired2= 2MHz, no mod

AM suppression

m =30 %

24/42

Doc ID 15938 Rev 8

TDA7705

Electrical specifications

Table 17. FM overall system performance (continued)

Parameter

Image rejection

Test condition

Min

Typ

Max

Units

-

80

-

dB

-0.33

-0.27

@40 dBµV

Logarithmic field strength

indicator

(equiv.

to 37

(equiv.

to 43

-0.3

--

read “FM_Smeter_log”

dBµV)

1. Signal levels referred to combiner output.

3.5.2

AM MW overall system performance

Antenna level equivalence: 0 dBµV = 1 µV

.

rms

Figure 11. AM MW input set up

15pF

A

50Ω

30Ω

PCB

UNDER

TEST

50Ω

68pF

V_rf

+ 6dB

Level referred to SG output before antenna dummy (V , node 'A'); capacitive dummy

rf

15pF+68pF, FM input not connected. F = 999 kHz (1000 kHz for US), V =74 dBµV,

rf

mod = 30%, f

=400 Hz, unless otherwise specified.

audio

Table 18. AM MW overall system performance

Parameter

Test condition

Min

Typ

Max

Units

Tuning range MW Eu/Jp

Tuning step MW Eu/Jp

Tuning range MW US

Tuning step MW US

Sensitivity

(can be modified by the user)

S/N = 20 dB

531

-

1629

kHz

dBµV

dB

-

530

-

9

-

1710

10

27

66

-

30

-

Ultimate S/N

@ 80 dBµV

63

Ref.=74 dBµV

AGC F.O.M.

50

-

62

0.1

42

65

-

dB

%

-10dB drop point

Distortion

m = 80 %

ΔF=9 kHz, SINAD = 26 dB

undesired. m=30%, 1 kHz

Adjacent channel selectivity

-

dB

ΔF=18 kHz, SINAD=26 dB

undesired. m=30%, 1kHz

Alternate channel selectivity

-

50

-

dB

Doc ID 15938 Rev 8

25/42

Electrical specifications

Table 18. AM MW overall system performance (continued)

TDA7705

Parameter

Test condition

Min

Typ

Max

Units

ΔF= 40 kHz

desired = 40 dBµV

-

15

-

dB

undesired = 100 dBµV,

m= 30%, 1 kHz

Strong signal interferer

SNR

ΔF= 400kHz

desired=40 dBµV

17

-

4

-

dB

undesired=100 dBµV,

m=30%, 1kHz

ΔF= 40 kHz

desired=40 dBµV

undesired=110 dBµV,

m=30%, 1 kHz

Strong signal interferer

suppression

ΔF= 400kHz

desired=40 dBµV

-

undesired=110 dBµV,

m=30%, 1kHz

ΔF= 40kHz

desired=80 dBµV

-

10

undesired=100 dBµV,

m=30%, 1kHz

Strong signal interferer

cross-modulation

ΔF= 400kHz

desired=80 dBµV

-

dB

-

undesired=100 dBµV,

m=30%, 1kHz

Image rejection

-

80

-

0.50

0.43

@60 dBµV

Logarithmic field strength

indicator

(equiv.

to 57

(equiv.

to 63

0.47

read “AM_Smeter_log”

dBµV)

26/42

Doc ID 15938 Rev 8

TDA7705

Electrical specifications

3.5.3

AM LW overall system performance

Antenna level equivalence: 0 dBµV = 1 µV

rms

Figure 12. AM LW input set-up

15pF

A

50Ω

30Ω

PCB

UNDER

TEST

50Ω

68pF

V_rf

+ 6dB

Level referred to SG output before antenna dummy (V , node 'A'); capacitive dummy

rf

15pF+68pF; FM input not connected. F = 216 kHz, V =74 dBµV, mod = 30 %,

rf

f

= 400 Hz, unless otherwise specified.

audio

Table 19. AM LW overall system performance

Parameter Test condition

Tuning range LW

Min

Typ

Max

Units

(can be modified by the user)

S/N =20 dB

144

-

288

kHz

dBµV

dB

Tuning step LW

Sensitivity

-

1

-

33

-

30

66

Ultimate S/N

@ 80 dBµV

63

Ref.=74 dBµV

AGC F.O.M.

50

62

65

dB

-10dB drop point

Distortion

m = 80 %

-

0.1

80

-

%

Image rejection

dB

Doc ID 15938 Rev 8

27/42

Electrical specifications

TDA7705

3.5.4

AM SW overall system performance

Antenna level equivalence: 0dBµV = 1µV

rms

Figure 13. AM SW input set-up

15pF

A

50Ω

30Ω

PCB

UNDER

TEST

50Ω

68pF

V_rf

+ 6dB

Level referred to SG output before antenna dummy (V , node 'A'); capacitive dummy

rf

15pF+68pF; FM input not connected. F = 6000 kHz, V =74 dBµV, mod = 30 %,

rf

f

= 400 Hz, unless otherwise specified.

audio

Table 20. AM SW overall system performance

Parameter Test condition

Tuning range LW

Min

Typ

Max

Units

(can be modified by the user)

S/N =20dB

2300

-

30000

kHz

dBµV

dB

Tuning step LW

Sensitivity

-

1

-

32

-

29

66

62

0.3

80

Ultimate S/N

AGC F.O.M.

Distortion

@ 80 dBµV

63

50

-

Ref.=74 dBµV -10dB drop point

m = 80 %

65

-

dB

%

Image rejection

-

dB

28/42

Doc ID 15938 Rev 8

TDA7705

Electrical specifications

3.5.5

WX overall system performance

Antenna level equivalence: 0 dBµV = 1 µV

(Antenna terminal voltage with 50Ω source).

rms

Figure 14. WX input set-up

A

50Ω

PCB

UNDER

TEST

50Ω

V_rf

+ 6dB

Input level referred to signal generator loaded with 50 Ω (V , node 'A'); no antenna dummy;

rf

AM input not connected. F =162.475 MHz, V = 60 dBµV, mono modulation, f = 3 kHz,

rf

dev

f

=400 Hz. De-emphasis = 75 µs. Application: WX using mixer input 2, in conjunction

audio

with FM narrow-band. Unless otherwise specified.

Table 21. WX overall system performance

Parameter

Sensitivity

Test condition

S/N = 26 dB

Min

Typ

Max

Units

-

-7

81

-

dBµV

dB

Ultimate S/N

Distortion

@ 60 dBµV

Deviation= 4.5 kHz

THD = 3 %

0.8

%

Max deviation

> 5 kHz

kHz

ΔF= 25 kHz, SINAD = 30 dB

desired 40 dBµV,

dev =2.0 kHz, 400 Hz

undesired. dev= 3 kHz, 1 kHz

Adjacent channel Selectivity

Alternate Channel Selectivity

-

70

-

dB

ΔF=50kHz, SINAD=30dB

desired 40 dBµV,

dev=2.0kHz, 400Hz

undesired. dev=2.0kHz, 1kHz

Doc ID 15938 Rev 8

29/42

Front-end processing

TDA7705

4

Front-end processing

All the parameters in this section refer to the programmability of the FE part of the device

(registers). The part of the registers that are not described here have either fixed values or

values written by the tuner drivers, and are described in the proper technical documentation.

Table 22. Register 0x00

Register number

Register definition

MSB

LSB

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

AM mixer input selector

0

1

1 input #1

0 input #2

AM PIN diode

0

1

internal

external

AM AGC mode

LNA and PIN diode

PIN diode only

AM AGC time constant

slow (125 ms with 1 µF)

medium (25 ms with 1 µF)

fast (5 ms with 1 µF)

AM AGC threshold @ mixin

90 dBµV

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

91 dBµV

92 dBµV

93 dBµV

90 dBµV

89 dBµV

88 dBµV

87 dBµV

AM AGC attack time constant

normal

0

1

fast

30/42

Doc ID 15938 Rev 8

TDA7705

Front-end processing

Register definition

Table 23. Register 0x01

Register number

MSB

LSB

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

FM mixer input selector

input #1

0

1

0

1

0

1

input #2

FM mixer gain

high

0

1

low

FM AGC time constant

normal

0

1

fast

FM AGC output mode

normal

0

1

0

1

0

constant 15 mA

constant 1 mA

Table 24. Register 0x02

Register number

Register definition

MSB

LSB

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

FM RF AGC threshold @

mixin

0

1

0 87 dBµV

1 89 dBµV

0 91 dBµV

1 93 dBµV

FM iF AGC threshold @

IFADC in

0

1

0

1

0

120 dBµV

122 dBµV

124 dBµV

Tuning DAC enable

0

1

off

on

(1)

Tuning DAC programming

0

1

0

1

… … … … … … … …

…

510

511

1

0

1

1. Normally handled by tuner drivers.

Doc ID 15938 Rev 8

31/42

Front-end processing

TDA7705

Table 25. Register 0x05

Register number

Register definition

MSB

LSB

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

PLLTEST output status

0 low

1 high

32/42

Doc ID 15938 Rev 8

TDA7705

Weak signal processing

5

Weak signal processing

All the parameters in this section refer to the programmability of the DSP part of the device.

The typical values are those set by default parameters (start-up without parametric change

from main µP); the max and the min values refer to the programmability range. The values

are referred to the typical application (Figure 16: Example of FM tuned (narrow-band)

application / SPI control). Wherever the possible values are a discrete set, all the possible

programmable values are displayed.

5.1

FM IF-processing

5.1.1

Dynamic channel selection filter (DISS)

Table 26. Dynamic channel selection filter (DISS)

(discrete set)

Symbol

Parameter

IF filter #6

Test condition

Min

Typ

Max

Units

-

150

110

80

-

kHz

IF filter #5

IF filter #4

DISS BW IF filter #3

IF filter #2

response: - 3dB

60

45

IF filter #1

35

IF filter #0

25

5.1.2

Soft mute

Table 27. Soft mute

(continuous set)

Symbol

Parameter

Test condition

audio atten = 1 dB

Min

Typ

Max

Units

SMsp

Start point vs. field strength

End point vs. field strength

read “FM_softmute”

0

6

20

dBµV

no adjacent channel present

audio atten = SMd + 1 dB

read “FM_softmute”

SMep

SMd

-6

10

dBµV

no adjacent channel present

Depth

-

-30

0.1

-15

0

dB

Hz

Field strength LPF cut-off

SMtauatt frequency for soft mute

activation

-

100

4000

Field strength LPF cut-off

SMtaurel frequency for soft mute

release

-

0.1

1

4000

Hz

Doc ID 15938 Rev 8

33/42

Weak signal processing

TDA7705

5.1.3

Adjacent channel mute

Table 28. Adjacent channel mute

(continuous set)

Symbol

Parameter

Test condition

Min

Typ

Max

Units

ACMd

Depth

SMd

0

dB

5.1.4

Stereo blend-

Table 29. Stereo blend

(continuous set)

Symbol

Parameter

Test condition

Min

Typ

Max

Units

field strength = 80 dBµV, pilot

deviation = 6.75 kHz

MaxSep

Maximum stereo separation

Start point vs. field strength

0

40

50

dB

separation = MaxSep - 1 dB

no multipath present

SBFSsp

SBFSep

20

50

30

60

dBµV

separation = 1 dB

End point vs. field strength

Field strength-related

no multipath present

V_rfstep-like variation from

20 dBµV to 80 dBµV

SBFStM2S transition time from mono to

stereo

0.001

3

20

s

Field strength-related

SBFStS2M transition time from stereo to

mono

V_rfstep-like variation from

80 dBµV to 20 dBµV

0.5

separation = MaxSep - 1 dB

equivalent 19 kHz AM

modulation depth;

SBMPsp Start point vs. multipath

SBMPep End point vs. multipath

5

10

30

80

%

field strength = 80 dBµV

separation = 1 dB

equivalent 19 kHz AM

modulation depth;

field strength = 80 dBµV

Multipath -related transition

SBMPtM2S

V_rfstep-like variation from

20 dBµV to 80 dBµV

0.001

1

20

s

time from mono to stereo

Multipath -related transition

SBMPtS2M

V_rfstep-like variation from

80 dBµV to 20 dBµV

0.001

time from stereo to mono

Threshold on pilot tone

Pil ThrM2S Pilot detector stereo threshold deviation for mono-stereo

transition

0.8

-

2.74

0.01

7

-

kHz

Difference in pil. det.

Pilot detector threshold

hysteresis

deviation threshold for stereo

to mono transition compared

to PilThrM2S

Pil ThrHyst

34/42

Doc ID 15938 Rev 8

TDA7705

Weak signal processing

5.1.5

High cut control

Table 30. High cut control

(continuous set)

Symbol

Parameter

Test condition

Min

Typ

Max

Units

minimum RF level for widest

HC filter (filter # 7)

HCFSsp

Start point vs. field strength

0

50

dBµV

no multipath present

maximum RF level for

narrowest HC filter (filter # 0)

HCFSep

End point vs. field strength

Field strength-related

0

30

40

dBµV

no multipath present

V_rfstep-like variation from

60 dBµV to 10 dBµV

(1)

HCFStW2N transition time from wide to

narrow band

-

Field strength-related

HCFStN2W transition time from narrow to

wide band

V_rfstep-like variation from

0 dBµV to 60 dBµV

(1)

14

10

100

s

minimum RF level for widest

HC filter (filter # 7)

HCMPsp Start point vs. multipath

HCMPep End point vs. multipath

equivalent 19 kHz AM

modulation depth;

5

150 ⁽²⁾

%

field strength = 80 dBµV

maximum RF level for

narrowest HC filter (filter # 0)

equivalent 19 kHz AM

modulation depth;

5

30

150 ⁽²⁾

field strength = 80 dBµV

Multipath -related transition

HCMPtN2W time from narrow to wide

band

V_rfstep-like variation from

20 dBµV to 80 dBµV

0.001

14

20

18

s

Multipath -related transition

HCMPtW2N

V_rfstep-like variation from

80 dBµV to 20 dBµV

time from wide to narrow

Filter #7, -3 dB response

frequency, input signal with

pre-emphasis

Maximum cut-off frequency of

HCmaxBW

HCmin

BW

kHz

high cut filter bank

Filter #0, -3 dB response

frequency, input signal with

pre-emphasis

Minimum cut-off frequency of

HCminBW

HCma

xBW

0.1

-

3

kHz

-

high cut filter bank

HCnumFilt Number of discrete HC filters

-

8 ⁽³⁾

-

1. Depends only on field strength filter time constant.

2. Means that 100% equivalent 19 kHz AM modulation depth will not achieve full band narrowing.

3. Intermediate filters (#6 - #1) cut-off frequencies exponentially spaced between HCmaxBW and HCminBW.

Doc ID 15938 Rev 8

35/42

Weak signal processing

TDA7705

Table 31. De-emphasis filter

(continuous set)

Symbol

Parameter

Test condition

Min

Typ

Max

Units

De-emphasis time constant 1

De-emphasis time constant 2

-

50

75

-

DEtc

µs

5.1.6

Stereo decoder

Table 32. Stereo decoder

Symbol

Parameter

Test condition

Min

Typ

Max

Units

PilSup

Pilot signal suppression

Pilot 9%, 19 kHz, ref=40 kHz

f = 38 kHz

-

60

70

80

-

dB

SubcSup Subcarrier suppression

f = 57 kHz

f = 76 kHz

5.2

AM IF-processing

5.2.1

Channel selection filter

Table 33. Channel selection filter

Symbol Parameter

CSF BW Channel selection filter BW

Test condition

Min

Typ

Max

Units

response: - 3dB

-

3.7

-

kHz

5.2.2

Soft mute

Table 34. Soft mute

(continuous set)

Symbol

Parameter

Test condition

Min

Typ

Max

Units

audio atten = 1 dB

SMsp

Start point vs. field strength

End point vs. field strength

read “FM_softmute”

0

25

40

dBµV

no adjacent channel present

audio atten = SMd + 1 dB

read “FM_softmute”

SMep

SMd

0

30

dBµV

no adjacent channel present

Depth

-

-40

-24

0.1

0

dB

s

Transition time for field

SMtauatt strength-dependent soft mute

activation

-

0.001

10

Transition time for field

SMtaurel strength-dependent soft mute

release

-

0.001

3

10

s

36/42

Doc ID 15938 Rev 8

TDA7705

Weak signal processing

5.2.3

High cut control

Table 35. High cut control

(continuous set)

Symbol

Parameter

Test condition

Min

Typ

Max

Units

minimum RF level for widest

HC filter (filter # 7)

HCFSsp

Start point vs. field strength

0

40

50

dBµV

no multipath present

maximum RF level for

narrowest HC filter (filter # 0)

HCFSep

End point vs. field strength

Field strength-related

0

30

0.2

10

14

50

20

18

dBµV

s

no multipath present

V_rfstep-like variation from

60 dBµV to 10 dBµV

HCFStW2N transition time from wide to

narrow band

0.001

Field strength-related

HCFStN2W transition time from narrow to

wide band

V_rfstep-like variation from

0 dBµV to 60 dBµV

s

Filter #7, -3 dB response

frequency, input signal with

pre-emphasis

Maximum cut-off frequency of

HCmaxBW

HCmin

BW

kHz

high cut filter bank

Filter #0, -3 dB response

frequency, input signal with

pre-emphasis

Minimum cut-off frequency of

HCminBW

HCma

xBW

1

-

3

8

kHz

-

high cut filter bank

HCnumFilt Number of discrete HC filters

-

Doc ID 15938 Rev 8

37/42

Application schematics

TDA7705

6

Application schematics

6.1

Basic application schematic

2

Figure 15. FM wide-band application / I C control

1 u F

1 0 n F

2 7 1 / 2 W

V C C - D A C

4 9

V D D - 3 V 3

3 2

O S C o u t

R E G - 1 V 2

3 1

5 0

4 7 0 n F

O S C i n

5 1

V C C R E G 1 2

3 0

G N D - D A C

V C C - D I G

1 0 0 n F

2 9

5 2

D A C o u t L

G N D - D I G

2 8

D A C O U T _ L

5 3

1 u F

D A C o u t R

V R E F d e c

D A C O U T _ R

5 4

2 7

G N D - I F A D C

V R E F 1 6 5

2 6

5 5

L I F r e f L

5 6

G N D - I F

2 5

6 8 p F

L I F r e f H

A M M I X d e c

2 4

1 0 0 n F

5 7

V C C - I F A D C

A M M I X i n 1

1 K

2 3

5 8

V C C - P L L

5 9

A M M I X i n 2

2 2

6 8 u H

G N D - P L L

L N A d e c 2

1 0 0 n F

2 1

6 0

V C O d e c

6 1

L N A o u t 2

2 0

L F r e f

L N A i n 2

1 9

6 2

V C C - V C O

6 3

L N A o u t

1 8

G N D - V C O

L N A d e c

1 7

6 4

T O K O

2 - 1 F 0 R 2 2 Q 2 L L

1. Note: components marked with a * are being considered for replacement with resistors, pending

optimization test results.

38/42

Doc ID 15938 Rev 8

TDA7705

Application schematics

6.2

Application schematic example with SPI-bus and tuned

preselection

Figure 16. Example of FM tuned (narrow-band) application / SPI control

1 u F

1 0 n F

2 7 1 / 2 W

V C C - D A C

O S C o u t

V D D - 3 V 3

3 2

R E G - 1 V 2

3 1

V C C R E G 1 2

3 0

V C C - D I G

2 9

4 9

5 0

5 1

5 2

5 3

5 4

5 5

5 6

5 7

5 8

5 9

6 0

6 1

6 2

6 3

6 4

4 7 0 n F

O S C i n

G N D - D A C

1 0 0 n F

D A C o u t L

D A C o u t R

G N D - D I G

2 8

V R E F d e c

2 7

V R E F 1 6 5

2 6

G N D - I F

2 5

D A C O U T _ L

D A C O U T _ R

1 u F

G N D - I F A D C

L I F r e f L

L I F r e f H

V C C - I F A D C

V C C - P L L

A M M I X d e c

2 4

1 0 0 n F

6 8 p F

A M M I X i n 1

1

1 K

2 3

A M M I X i n 2

2 2

L N A d e c 2

2 1

L N A o u t 2

2 0

L N A i n 2

1 9

L N A o u t

1 8

L N A d e c

1 7

6 8 u H

G N D - P L L

V C O d e c

1 0 0 n F

L F r e f

V C C - V C O

G N D - V C O

1 0 n F

C 2 8

6 8 6 K R

2

K V 1 7 7 0

D 3

1

- 1 0 0 0 1 0 1 E 5 5 8 C N

T O K L O 6

1 2 p F

C 2 3

1 5 p F C 3 1

1 K 5

2

1

E 1

K P 2 3 1

K P 2 3 1 1 E

1

2

2 2 0

1. Note: components marked with a * are being considered for replacement with resistors, pending

optimization test results.

Doc ID 15938 Rev 8

39/42

Package information

TDA7705

7

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

Figure 17. LQFP64 (10x10x1.4mm) mechanical data and package dimensions

mm

inch

DIM.

OUTLINE AND

MECHANICAL DATA

MIN. TYP. MAX. MIN.

TYP. MAX.

0.063

A

A1

A2

B

1.60

0.05

1.35

0.17

0.09

0.15 0.002

0.006

1.40

0.22

1.45 0.053 0.055 0.057

0.27 0.0066 0.0086 0.0106

C

0.20 0.0035

0.0079

D

11.80 12.00 12.20 0.464 0.472 0.480

9.80 10.00 10.20 0.386 0.394 0.401

D1

D3

e

7.50

0.50

0.295

0.0197

E

11.80 12.00 12.20 0.464 0.472 0.480

9.80 10.00 10.20 0.386 0.394 0.401

E1

E3

L

7.50

0.60

1.00

0.295

0.75 0.0177 0.0236 0.0295

0.0393

0.45

L1

K

LQFP64 (10 x 10 x 1.4mm)

0˚ (min.), 3.5˚ (min.), 7˚(max.)

0.080

ccc

0.0031

D

D1

D3

A

A2

A1

48

33

32

49

0.08mm ccc

Seating Plane

17

16

64

1

C

e

K

TQFP64

0051434 F

40/42

Doc ID 15938 Rev 8

TDA7705

Revision history

8

Revision history

Table 36. Document revision history

Date

Revision

Changes

31-Jul-2007

01-Aug-2008

1

2

Initial release.

Full update datasheet.

Document status promoted from preliminary data to datasheet.

Updated Table 1: Device summary on page 1.

Updated Section 3: Electrical specifications on page 16.

Updated Section 4: Front-end processing on page 30.

Updated Section 5: Weak signal processing on page 33.

Updated Section 6: Application schematics on page 38.

08-May-2009

3

Updated Table 5: Thermal data on page 16.

09-Jun-2009

01-Jul-2009

4

5

Updated the value of “Adjacent channel selectivity” parameter in the

Table 17: FM overall system performance.

Updated Figure 17: LQFP64 (10x10x1.4mm) mechanical data and

package dimensions on page 40.

Modified Table 1: Device summary on page 1

Modified Table 5: Thermal data on page 16.

13-Jan-2010

6

Modified Section 3.5.5: WX overall system performance on page 29.

Modified Section 7: Package information on page 40.

Minor text changes in Section 2.13.

Modified min. value of “t_HD-DAT” parameter in Table 15: I²C interface

on page 21.

29-Jan-2010

22-Mar-2010

7

8

Added Section 3.4.11: Warning on page 22.

Doc ID 15938 Rev 8

41/42

TDA7705

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

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42/42

Doc ID 15938 Rev 8


型号：	TDA7705_10
厂家：	ST
描述：	Highly integrated tuner for AM/FM car radio 高度集成的调谐器AM / FM汽车收音机
文件：	总42页 (文件大小：402K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TDA7705_10 [STMICROELECTRONICS]

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