STW4141_06 [STMICROELECTRONICS]
Single-coil dual-output step-down DC/DC converter for digital base band and multimedia processor supply; 单线圈双输出降压型DC / DC转换器对数字基带和多媒体处理器供应
| 型号： | STW4141_06 |
| 厂家： | 
ST |
| 描述： | Single-coil dual-output step-down DC/DC converter for digital base band and multimedia processor supply |
| 文件： | 总30页 (文件大小：866K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STw4141
Single-coil dual-output step-down DC/DC converter
for digital base band and multimedia processor supply
Features
Solution size
7 x 8 mm
■ Single coil dual output switching converter for
digital core supply & digital I/Os supply
– Digital I/O supply:VOUT1 @ 200 mA
– CPU CORE supply:VOUT2 @ 400 mA
TFBGA 3x3mm
16 bumps 0.5 mm pitch
■ Wide range of fixed output voltage
configurations available
Applications
■ High efficiency synchronous step down
converter with up to 92 % for the entire device
■ Mobile phones
■ Size and cost optimized application board
(7x8 mm, height 1.2mm) three capacitors and
only one inductor necessary for both outputs
■ PDAs and hand held terminals
■ Portable media players
■ Digital still camera
■ 2.7 V to 5.5 V battery input range
■ WLAN and Bluetooth applications
■ ±100mV output voltage accuracy full range in
PWM (Including Line and Load Transients)
Description
■ 900 kHz fixed frequency PWM operation
■ PFM mode operation at light load current
The STw4141 is a single coil dual output
synchronous step down DC/DC converter that
requires only four standard external components.
It operates at a fixed 900 kHz switching frequency
in PWM mode. The device can operate in PFM
mode to maintain high efficiency over the full
range of output currents.
■ PWM/PFM switch can be done automatically or
forced by setting external pins (AUTO and
MODE/SYNC)
■ MODE/SYNC input pin for external clock
synchronization from 600 kHz to 1.5 MHz
The STw4141 application requires a very small
PCB area and offers a very efficient, accurate,
space and cost saving solution to fulfill the
requirements of digital baseband or multimedia
processor supply (CORE & I/O).
■ VSEL input pin for VOUT2/VOUT2(red.) selection
■ Ultra low shutdown current (Iq<1 µA)
■ Short circuit and thermal shutdown protections
Application test circuit
L
4.7 µH
VLX1
VLX2
A3
VIN=2.7V to 5.5V
VOUT1=1.8V
PVDD
VDD
VOUT1
FB1
A2
B1
A4
CIN
10 µF
6.3 V
COUT1
22 µF
6.3 V
D1
D3
D4
C2
C3
EN
VOUT2=1.0V/1.2V
AUTO
VOUT2
FB2
STw4141
B4
VSEL
COUT2
22 µF
6.3 V
D2
B2
MODE/SYNC
STATE
C1
A1
C4
B3
T_MODE
PGND GND
June 2006
Rev 2
1/30
www.st.com
1
Contents
STw4141
Contents
1
2
STw4141 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Settling time of VOUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Line transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Load transients in AUTO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Load transients in PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.10 Switching between PFM and PWM in FORCED mode . . . . . . . . . . . . . . 14
2.11 Efficiency in PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.12 Efficiency in AUTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.13 Output voltages versus output currents in PWM and PFM . . . . . . . . . . . . 17
3
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PWM and PFM mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal shutdown protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1
4.2
4.3
4.4
4.5
4.6
User mode details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Automatic PWM/PFM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
User selected PWM/PFM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
External clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Checking transient response versus external components . . . . . . . . . . . 21
Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.6.1
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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STw4141
Contents
4.6.2
4.6.3
4.6.4
Input capacitor (CIN selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output capacitors (COUT selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.7
PCB layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.7.1
4.7.2
PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TFBGA16 internal bumps access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
6
7
Package outline and mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/30
List of tables
STw4141
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
STw4141 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Dynamic electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
STw4141 available user modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operating mode information (STATE pin - digital output). . . . . . . . . . . . . . . . . . . . . . . . . . 19
Bill of material: inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bill of Material: capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TFBGA 3x3x1.20 16 F4x4 0.50. Package code: L0 - JEDEC/EAIJ . . . . . . . . . . . . . . . . . . 26
STw4141 order codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4/30
STw4141
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Pin assignment in TFBGA 3x3 mm - 16 bumps 0.5 mm pitch . . . . . . . . . . . . . . . . . . . . . . . 6
Smooth start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Settling time of VOUT2, IOUT1 = 200mA, IOUT2 = 400mA. . . . . . . . . . . . . . . . . . . . . . . . 11
Line transient, VOUT1 = 1.8V @ 100mA, VOUT2 = 1.2V @ 100mA . . . . . . . . . . . . . . . . . 12
Load transient in AUTO mode VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V. . . . . . . . . . . . 12
Load transient in PWM mode, IOUT1 = 1mA to 200mA, IOUT2 = 1mA to 400mA. . . . . . . 13
Switching between PFM to PWM - VIN = 3.6V, IOUT1 = 10mA, IOUT2 = 10mA. . . . . . . . 14
Switching between PWM to PFM - VIN = 3.6V, IOUT1 = 10mA, IOUT2 = 10mA. . . . . . . . 14
Switching regulator efficiency in PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Switching regulator efficiency in auto mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Output voltages versus output currents in PWM and PFM. . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Automatic PWM/PFM switch schematic example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. PWM/PFM forced mode schematic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. Application using external clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. Board layout track length and width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16. Demoboard top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. Demoboard assembled with 22 µF output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18. TFBGA16 ball pad spacing and track parameters to internal pads . . . . . . . . . . . . . . . . . . 24
Figure 19. PCB routing example using TFBGA16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. TFBGA 3x3x1.20 16 F4x4 0.50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5/30
STw4141 pinout
STw4141
1
STw4141 pinout
Figure 1.
Pin assignment in TFBGA 3x3 mm - 16 bumps 0.5 mm pitch
1
1
22
3
4
4
3
2
2
1
1
4
3
3
4
AA
BB
VOUT1
VOUT2
GND
VLX2
T_MODE
VSEL
VLX1
STATE
AUTO
FB2
PGND
PVDD
PGND
PVDD
VLX1
STATE
AUTO
FB2
VLX2
T_MODE
VSEL
VOUT1
VOUT2
GND
A
B
CC
C
MODE/
SYNC
MODE/
SYNC
FB1
VDD
EN
D
D
EN
VDD
FB1
D
Bottom view
Top view
Table 1.
Pin
STw4141 pin description
Symbol
Description
A1
B1
PGND
PVDD
Power ground
Power supply voltage
MODE/SYNC = High to forced PWM mode
MODE/SYNC = Low to forced PFM mode
C1
MODE/SYNC
MODE/SYNC = 600 kHz - 1.5 MHz external clock synchronization in PWM
D1
A2
FB1
Feedback 1
VLX1
External inductor connection pin 1
Output STATE pin allow the user to monitor operation mode of the product
STATE = High - PFM mode
STATE = Low - PWM mode
B2
C2
STATE
AUTO
If not used must be left unconnected.
PWM/PFM automatic switch control pin
AUTO = High - PWM/PFM mode automatic switch ENABLED
AUTO = Low - PWM/PFM mode automatic switch DISABLED
PWM/PFM mode controlled by MODE/SYNC pin)
D2
A3
B3
FB2
Feedback 2
VLX2
External inductor connection pin 2
T_MODE
Input signal for test mode selection. This pin must be connected to GND.
Voltage selection input
VSEL = High - VOUT1 = 1.8V, VOUT2 = 1.2V (valid for STA1)
VSEL = Low - VOUT1 = 1.8V, VOUT2 = 1.0V (valid for STA1)
(For other voltage options see Table 1: STw4141 ordering information)
C3
VSEL
D3
A4
VDD
Signal supply voltage
Output voltage 1
VOUT1
6/30
STw4141
STw4141 pinout
Table 1.
Pin
STw4141 pin description (continued)
Symbol
Description
B4
C4
VOUT2
GND
Output voltage 2
Signal ground
Enable Input:
EN = Low - Device in shutdown mode,
EN = High - Enable device
D4
EN
This pin must be connected either to VDD or GND.
This is the ground pin related to power signal. This pin should be connected to the board ground
plane by short and wide track or multiply vias to reduce impedance and EMI.
PGND pin
GND pins
PVDD pin
This is the ground pin related to analog signal.
This pin is designed to provide power to the device. This path leads high currents. It should be
wide and short to minimize track impedance to reduce losses and EMI.
This pin is designed to provide signal supply voltage to the device. There is no specific
requirement for its related track design.
VDD pin
External coil is connected on those pins. It should be placed as closed as possible to the device
in order minimize resistances which cause looses. These paths lead high currents.
VLX1/VLX2 pins
VOUT1 pin3
VOUT2 pin
It is the first output voltage of this device. This path leads high currents. It should be wide and
short to minimize track impedance to reduce losses and EMI.
It is the second output voltage of this device. This path leads high currents. It should be wide and
short to minimize track impedance to reduce losses and EMI.
FB1 pin
Intended to measure VOUT1 voltage in order to ensure the regulation of this output.
Intended to measure VOUT2 voltage in order to ensure the regulation of this output.
FB2 pin
This is the enable pin of the device. Pulling this pin to ground, forces the device into shutdown
mode. Pulling this pin to VDD enables the device. This pin must be terminated.
ENABLE pin
The MODE/SYNC pin is a multipurpose pin which provides mode selection and frequency
synchronization.
MODE/SYNC pin
The device can also be synchronized to an external clock signal from 600 kHz to 1.5 MHz by the
MODE/SYNC pin. During synchronization, the mode is forced to PWM mode and the top switch
turn-on is synchronized to the rising edge of the external clock.
This pin allows the device to automatically switch from PWM to PFM mode following load on both
2 outputs.
AUTO pin
STATE pin
VSEL pin
This output pin informs user in which state the device is working: PWM or PFM mode.
This pin is used to reduce VOUT2 (CORE) output voltage in order to reduce the processor power
consumption when entering into sleep mode.
7/30
Electrical characteristics
STw4141
2
Electrical characteristics
2.1
Absolute maximum ratings
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. All voltages are referenced to
GND.
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
V
PVDD
Power supply voltage
-0.3 to 6
-0.3 to 6
VDD
Signal supply voltage
V
VEN
-0.3 to VDD
-0.3 to VDD
-0.3 to VDD
-0.3 to VDD
-0.3 to VDD
-0.3 to VOUT1
Enable input
V
VSEL
Voltage selection
V
VMODE/SYNC
VAUTO
VT_MODE
VSTATE
Operating mode selection/synchronization input
PWM/PFM automatic switch selection
Test mode selection
V
V
V
Operating mode information
Output voltage 1, feedback 1
Output voltage 2, feedback 2
External inductor connection pin 1
External inductor connection pin 2
Operating temperature range
Maximum operating junction temperature
Storage temperature range
V
VOUT1,FB1
-0.3 to 3.3
-0.3 to 3.3
-0.3 to VDD
V
VOUT2, FB2
VLX1
VLX2
TA
V
V
-0.3 to 3.3
-40 to 85
150
V
°C
°C
°C
TJ
TSTG
-65 to 150
2.2
Thermal data
Table 3.
Symbol
Thermal data
Parameter
Value
Unit
Thermal Resistance Junction-Ambient
TFBGA 3x3 mm – 16 bumps - 0.5 mm pitch
RthJA
150
°C/W
8/30
STw4141
Electrical characteristics
2.3
DC electrical characteristics
Characteristics measured over recommended operating conditions unless otherwise is
noted.
All typical values are referred to TA = 25°C, PVDD = 3.6V, VDD = 3.6V.
Table 4.
Symbol
DC electrical characteristics
Parameter
Power supply voltage
Peak current limit
Test Conditions
Min.
Typ
Max.
Unit
V
PVDD
ILIM
2.7
5.5
1.6
A
(1)
Output voltage 1(2)
Output voltage 2(2)
-3
-3
+3
+3
%
%
VOUT1
VSEL = VDD,
MODE/SYNC = VDD
VOUT2
VSEL = GND,
MODE/SYNC = VDD
Output voltage 2(2)
-3
+3
%
IOUT1
IOUT2
Output current 1
Output current 2
200
400
mA
mA
IOUT1 = 0 mA, IOUT2 = 0 mA
Quiescent current
(PWM)
EN = VDD, VSEL = VDD
MODE/SYNC = VDD,
AUTO = GND
600
90
1
µA
µA
µA
I
OUT1 = 0 mA, IOUT2 = 0 mA
Quiescent current
(PFM)
EN = VDD, VSEL = VDD
MODE/SYNC = GND,
AUTO = GND
Iq
EN = GND,
VSEL = GND
MODE/SYNC = GND,
AUTO = GND
Shutdown current
5
Enable functions
VEN
H
L
Enable threshold high
Enable threshold low
0.9
0.9
V
V
VEN
0.4
0.4
Mode/sync functions
MODE/SYNC
threshold high
VM/SH
V
V
MODE/SYNC
threshold low
VM/S
L
VSEL functions
Voltage selection
threshold high
VSEL
H
0.9
V
V
Voltage selection
threshold low
VSELL
0.4
9/30
Electrical characteristics
STw4141
Unit
Table 4.
Symbol
DC electrical characteristics (continued)
Parameter
Test Conditions
Min.
Typ
Max.
Auto functions
Voltage selection
threshold high
VAUTO
VAUTO
H
L
0.9
V
V
Voltage selection
threshold low
0.4
State functions
Voltage selection
threshold high
VSTATE
H
L
RLmax = 100k, CLmax = 10pF
RLmax = 100k, CLmax = 10pF
0.7VOUT1
V
Voltage selection
threshold low
VSTATE
0.3 VOUT1
V
1. VOUT1 ≥ VOUT2 . This condition must always be valid.
2. Output voltage accuracy excludes line and load transients
2.4
Dynamic electrical characteristics
Characteristics measured over recommended operating conditions unless otherwise is
noted.
All typical values are referred to TA = 25°C, PVDD = 3.6V, VDD = 3.6V.
Table 5.
Symbol
Dynamic electrical characteristics
Parameter
Test Conditions
Min.
Typ
Max.
Unit
fSW
Switching frequency
900
kHz
kHz
µs
fSYNC
Ts
Sync mode frequency
Settling time (soft start)
Settling time
600
1500
400
80
TS2
VSEL change from GND to VDD
µs
VOUT2 (reduced)/VOUT2
10/30
STw4141
Electrical characteristics
2.5
Soft start
To avoid spikes on battery during STw4141 start-up sequence, a smooth start-up is
implemented. Reference voltage grows up less than 600 µs until it achieves is final target.
Therefore, STw4141 start up is smooth and secure for the overall mobile phone.
Figure 2 illustrates a smooth start up sequence where VIN = 3.6V, VOUT1 = 1.8V@ 200mA,
VOUT2 =1.2V@400mA.
Figure 2. Smooth start-up sequence
2.6
Settling time of V
OUT2
Figure 3.
Settling time of VOUT2, IOUT1 = 200mA, IOUT2 = 400mA
11/30
Electrical characteristics
STw4141
2.7
Line transients
Figure 4.
Line transient, VOUT1 = 1.8V @ 100mA, VOUT2 = 1.2V @ 100mA
2.8
Load transients in AUTO mode
Figure 5.
Load transient in AUTO mode VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V
12/30
STw4141
Electrical characteristics
2.9
Load transients in PWM mode
Figure 6.
Load transient in PWM mode, IOUT1 = 1mA to 200mA, IOUT2 = 1mA to 400mA
Load transient output 1 leading output 2
VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V
Load transient related to in-phase switching
VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V
Load transient related to anti-phase switching
VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V
Load transient output 2 leading output 1
VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V
13/30
Electrical characteristics
STw4141
2.10
Switching between PFM and PWM in FORCED mode
Figure 7.
Switching between PFM to PWM - VIN = 3.6V, IOUT1 = 10mA, IOUT2 = 10mA
Figure 8.
Switching between PWM to PFM - VIN = 3.6V, IOUT1 = 10mA, IOUT2 = 10mA
14/30
STw4141
Electrical characteristics
2.11
Efficiency in PWM
The efficiency of a switching regulator is equal to the total output power divided by the input.
STw4141 has high efficiency up to 92% (for the 2 outputs). Efficiency curve is flat over the
output current range.
Figure 9.
Switching regulator efficiency in PWM mode
Efficiency in PWM mode @ VIN=2.7V, TA= 25°C
Efficiency in PWM mode @ VIN=3.6V, TA= 25°C
100
100
90
90
80
80
70
70
60
60
50 Efficiency (%)
50 Efficiency (%)
40
30
20
10
0
90-100
80-90
70-80
60-70
50-60
40-50
30-40
20-30
10-20
0-10
40
90-100
80-90
70-80
60-70
50-60
40-50
30-40
20-30
10-20
0-10
30
20
10
0
200
180
160
140
200
180
160
140
120
100
120
100
80
60
IOUT1 (mA)
80
40
60
IOUT1 (mA)
20
IOUT2 (mA)
40
1
20
I
OUT2 (mA)
1
Efficiency vs IOUT1@IOUT2 PWM mode, TA=25°C
Efficiency vs IOUT1@IOUT2 PWM mode, TA=25°C
100
100
VIN = 3.6V
VIN = 2.7V
IOUT2 = 0 mA
IOUT2 = 0 mA
90
90
IOUT2 = 200 mA
IOUT2 = 200 mA
80
80
IOUT2 = 400 mA
IOUT2 = 400 mA
VOUT1 = 1.8V
VOUT1 = 1.8V
70
VOUT2 = 1.2V
70
VOUT2 = 1.2V
60
50
40
30
20
10
0
60
50
40
30
20
10
0
1
10
100
1000
1
10
100
1000
IOUT1 (mA)
IOUT1 (mA)
Efficiency vs IOUT2@IOUT1, PWM mode, TA=25°C
Efficiency vs IOUT2@IOUT1, PWM mode, TA=25°C
100
VIN = 3.6V
100
VIN = 2.7V
IOUT1 = 0 mA
90
IOUT1 = 0 mA
90
80
70
60
50
40
30
20
10
0
80
IOUT1 = 100 mA
IOUT1 = 100 mA
IOUT1 = 200 mA
70
IOUT1 = 200 mA
VOUT1 = 1.8V
VOUT2 = 1.2V
60
50
40
30
20
10
0
VOUT1 = 1.8V
VOUT2 = 1.2V
1
10
100
1000
1
10
100
1000
IOUT2 (mA)
IOUT2 (mA)
15/30
Electrical characteristics
STw4141
2.12
Efficiency in AUTO
The efficiency of a switching regulator is equal to the total output power divided by the input.
STw4141 has high efficiency up to 92% (both outputs) and always higher than 70% for
output currents higher than 1mA.
Figure 10. Switching regulator efficiency in auto mode
Efficiency VS output currents IOUT1 and IOUT2, VIN = 2.7V, AUTO mode
Efficiency VS output currents IOUT1 and IOUT2, VIN = 3.6V, AUTO mode
100
100
90
80
90
80
70
60
70
60
50
Efficiency (%)
50 Efficiency (%)
40
30
20
10
0
90-100
80-90
70-80
60-70
50-60
40-50
30-40
20-30
10-20
0-10
40
90-100
80-90
70-80
60-70
50-60
40-50
30-40
20-30
10-20
0-10
30
20
200
10
180
160
150
0
120
120
90
80
60
I
OUT1 (mA)
IOUT1 (mA)
40
30
IOUT2 (mA)
IOUT2 (mA)
1
1
Efficiency VS IOUT1@IOUT2, AUTO mode, TA = 25°C
Efficiency VS IOUT1@IOUT2, AUTO mode, TA = 25°C
100
100
VIN = 2.7V
VIN = 3.6V
IOUT2 = 0 mA
IOUT2 = 0 mA
90
90
IOUT2 = 200 mA
IOUT2 = 200 mA
80
80
IOUT2 = 400 mA
IOUT2 = 400 mA
VOUT1 = 1.8V
70
70
VOUT2 = 1.2V
VOUT1 = 1.8V
VOUT2 = 1.2V
60
50
40
30
20
10
0
60
50
40
30
20
10
0
1
10
100
1000
1
10
100
1000
IOUT1 (mA)
IOUT1 (mA)
Efficiency VS IOUT2@IOUT1, AUTO mode, TA = 25°C
Efficiency VS IOUT2@IOUT1, AUTO mode, TA = 25°C
100
100
VIN = 2.7V
VIN = 3.6V
IOUT1 = 0 mA
IOUT1 = 0 mA
90
90
80
80
IOUT1 = 100 mA
IOUT1 = 100 mA
70
70
IOUT1 = 200 mA
IOUT1 = 200 mA
60
60
VOUT1 = 1.8V
VOUT1 = 1.8V
VOUT2 = 1.2V
50
50
40
30
20
10
0
VOUT2 = 1.2V
40
30
20
10
0
1
10
100
1000
1
10
100
1000
IOUT2 (mA)
IOUT2 (mA)
16/30
STw4141
Electrical characteristics
2.13
Output voltages versus output currents in PWM and PFM
Figure 11. Output voltages versus output currents in PWM and PFM
VOUT1 VS IOUT1 @ IOUT1 - PWM mode
VOUT2 VS IOUT2 @ IOUT1 - PWM mode
1.830
1.820
1.810
1.800
1.790
1.780
1.770
1.230
1.220
1.210
1.200
1.190
1.180
1.170
VIN = 3.6V
VIN = 3.6V
IOUT1 = 0 mA
IOUT2 = 0 mA
IOUT2 = 200 mA
IOUT1 = 100 mA
IOUT1 = 200 mA
IOUT2 = 400 mA
1
10
100
1000
1
10
100
1000
IOUT1 (mA)
IOUT2 (mA)
VOUT1 VS IOUT1 @ IOUT2 - PFM mode
VOUT2 VS IOUT2 @ IOUT1 - PFM mode
1.230
1.220
1.210
1.200
1.190
1.180
1.170
1.830
1.820
1.810
1.800
1.790
1.780
1.770
VIN = 3.6V
VIN = 3.6V
IOUT1 = 0 mA
IOUT2 = 0 mA
IOUT2 = 20 mA
IOUT2 = 40 mA
IOUT1 = 10 mA
IOUT1 = 20 mA
1
10
100
1
10
100
IOUT2 (mA)
IOUT1 (mA)
17/30
Functional description
STw4141
3
Functional description
Introduction
The STw4141 is an easy to use, single coil dual outputs step down DC/DC converter
optimized to supply low-voltage to CPUs or DSPs in cell phones and other miniature devices
powered by single cell lithium-ion or 3 cell NiMH/NiCd batteries. It provides two different
output voltages with high efficiency operation in a wide range of output currents. The device
offers high DC voltage regulation accuracy and load transient response to satisfy
demanding processor core supply. The converter is based on voltage mode buck
architecture using PWM and PFM operation modes.
At light load currents, the device can operate in PFM mode to maintain high efficiency over
the entire load current range. Switching between PWM and PFM modes can be done
automatically or can be forced by external pins (AUTO and MODE/SYNC). Externally
synchronized or fixed frequency (internal oscillator) PWM mode offers full output current
capability while minimizing interference to sensitive RF and data acquisition circuits.
PWM and PFM mode operation
PWM (Pulse Width Modulation) mode is intended for normal load to high load currents.
Energy is delivered to the load with an accurate and defined frequency of 900 kHz.
PFM (Pulse Frequency Modulation) mode is intended for low load currents to maintain high
efficiency conversion.
Forced mode: When AUTO pin is LOW, the operating mode is selectable by the user itself.
It means that system controls the behavior of the STw4141 according to processor needs.
STw4141 is switched from PWM to PFM mode using MODE/SYNC pin (refer to Section 4.1).
Automatic PWM / PFM switch: When AUTO pin is HIGH, the operating mode is directly
controlled by internal digital circuit according to processor needs. The device switches from
PWM to PFM by itself if sum of output currents is lower than approximately 100 mA during at
least 16 clock cycles. The device can be forced to PWM mode connecting MODE/SYNC to
HIGH level. (see Section 2.8 and Section 2.9).
Current limiter
This protection limits the current flowing through coil. As soon as ILIM is detected, the duty
cycle is terminated and prevents the coil current against rising above peak current limit.
There is no reset of device.
Short circuit protection
It protects the device against short-circuit at output terminals. When one or both output
voltages are decreased by 0.7 V below their nominal output values the device enters into
reset followed by soft start sequence.
Thermal shutdown protection
Thermal shutdown protects the device against damage due to overheating when maximum
operating junction temperature is exceeded. The device is kept in reset until junction
temperature decreases by 25°C approximately.
18/30
STw4141
Application information
4
Application information
4.1
User mode details
The following table describes the different user modes available. Depending on the
application constraints (processor I/O pins available) and expected efficiency, PWM or PFM
mode are forced or automatically controlled by STw4141 internal digital gates.
Table 6.
Mode
STw4141 available user modes
User mode/pins
EN
AUTO
MODE/SYNC
OFF
Shutdown
L
H
H
X
L
L
X
L
Forced PFM
Forced PWM
H
FORCED
Forced PWM and synchronized external
clock
H
L
CLK
Auto mode
H
H
H
H
L
Forced PWM
H
AUTO
Forced PWM and synchronized external
clock
H
H
CLK
Table 7.
Operating mode information (STATE pin - digital output)
Operation mode
State pin voltage level
PFM
VOUT1
GND
PWM
19/30
Application information
STw4141
4.2
Automatic PWM/PFM mode
This user mode is designed to allow STw4141 to switch automatically between PWM and
PFM modes. This feature improves the application efficiency because STw4141 enters in
PFM mode according to application processor current consumption.
Figure 12. Automatic PWM/PFM switch schematic example
L 4.7 µH
VLX1
VLX2
VIN=2.7V to 5.5V
PVDD
VOUT1
FB1
A2
A3
B1
A4
D1
APE I/O
VDD
EN
CIN
10 µF
6.3 V
COUT1
22 µF
6.3 V
C1
100 nF
D3
D4
C2
C3
VOUT2
AUTO
STw4141
B4
APE CORE
FB2
COUT2
22 µF
6.3 V
C2
100 nF
VSEL
APPLICATION
PROCESSOR
D2
B2
MODE/SYNC
STATE
C1
A1
C4
B3
T_MODE
PGND GND
MODE_INFO
SLEEP
GND
4.3
User selected PWM/PFM mode
STw4141 PWM/PFM mode can also be controlled by the application processor. This feature
is accessible through MODE/SYNC pin state. It is useful to users who want to use STw4141
with the modem digital processor. Therefore, MODE/SYNC pin is connected to SLEEP
mobile phone signal.
Figure 13. PWM/PFM forced mode schematic example
L 4.7 µH
VLX1
VLX2
VIN=2.7V to 5.5V
PVDD
VOUT1
FB1
A2
A3
B1
A4
D1
APE I/O
VDD
EN
CIN
10 µF
6.3 V
COUT1
22 µF
6.3 V
C1
100 nF
D3
D4
C2
C3
VOUT2
AUTO
STw4141
B4
APE CORE
FB2
COUT2
22 µF
6.3 V
C2
100 nF
VSEL
APPLICATION
PROCESSOR
D2
B2
MODE/SYNC
STATE
C1
A1
C4
B3
T_MODE
PGND GND
MODE_INFO
PWR_EN
SLEEP
GND
20/30
STw4141
Application information
4.4
External clock synchronization
Figure 14. Application using external clock synchronization
L
4.7 µH
VLX1
VLX2
VIN=2.7V to 5.5V
PVDD
VOUT1
FB1
A2
A3
B1
A4
D1
APE I/O
VDD
EN
CIN
10 µF
6.3 V
COUT1
22 µF
6.3 V
C1
100 nF
D3
D4
C2
C3
VOUT2
AUTO
STw4141
B4
APE CORE
FB2
COUT2
22 µF
6.3 V
C2
100 nF
VSEL
APPLICATION
PROCESSOR
D2
B2
MODE/SYNC
STATE
C1
A1
C4
B3
T_MODE
PGND GND
MODE_INFO
CLK
SLEEP
GND
4.5
Checking transient response versus external components
The regulator loop response can be checked by looking at the load transient response.
Switching regulators take several cycles to respond to a step in load current. When a load
step occurs, VOUT is immediately shifted by an amount equal to ILOAD x ESR, where ESR is
the equivalent series resistance of COUT. ILOAD also begins to charge or discharge COUT
generating a feedback error signal used by the regulator to return VOUT to its steady-state
value. In order to improve the transient response, it is better to use two 10 µF ceramic
capacitors on each output to reduce ESR.
4.6
Bill of Material
4.6.1
Inductor selection
The choice of which inductor to use depends on the price and size versus performance
required with the STw4141 application. Table 7 shows some typical surface mount inductors
that work well in STw4141 applications.
Table 8.
Bill of material: inductor selection
Value
Max DC
current
(mA)
RDC
(Ω)
Size (mm)
W x L x H
Part number
Supplier
(µH)
VFL4012A-4R7M1R1
VFL3012A-4R7MR74
744031004
TDK
TDK
4.7
4.7
4.7
0.14
0.16
1100
740
3.5 x 3.7 x 1.2
2.6 x 2.8 x 1.2
3.8 x 3.8 x 1.8
WUERTH
0.085
900
21/30
Application information
STw4141
4.6.2
Input capacitor (CIN selection)
Input capacitor of 10 µF ceramic low ESR capacitor should be used to reduce switching
losses. It should be placed as close as possible to supply pins VDD and PVDD. The
connection traces should be wide and short to minimize impedance.
4.6.3
Output capacitors (COUT selection)
The selection of COUT is driven by the required ESR to minimize voltage ripple and load
step transients. There are two possibilities for output capacitors: either a 22 µF is connected
to ground or two 10 µF ceramic are used to reduce ESR and switching losses. The capacitor
should be placed as close as possible to VOUTx pins. The connection traces should be wide
and short to minimize impedance.
4.6.4
Capacitors selection
Table 9.
Bill of Material: capacitor selection
Component
Supplier
Part number
Value
Case size
GRM188R60J106ME47D
GRM21BR60J106ME15L
10 µF, 6.3V
10 µF, 6.3V
0603
0805
MURATA
CIN
TAIYO YUDEN JMK212BJ106MG-T
10 µF, 6.3V
0805
C1608X5R0J106MT
10 µF, 6.3V
0603
TDK
C2012X5R0J106MT
10 µF, 6.3V
0805
GRM188R60J106ME47D
2 x 10 µF, 6.3V
2 x 10 µF, 6.3V
22 µF, 6.3V
2 x 0603
2 x 0805
0805
MURATA
GRM21BR60J106ME15L
GRM21BR60J226ME15L
JMK212BJ106MG-T
JMK212BJ226MG-T
C1608X5R0J106MT
C2012X5R0J106MT
C2012X5R0J226MT
2 x 10 µF, 6.3V
22 µF, 6.3V
2 x 0805
0805
COUT1, COUT2 TAYIO YUDEN
2 x 10 µF, 6.3V
2 x 10 µF, 6.3V
22 µF, 6.3V
2 x 0603
2 x 0805
0805
TDK
22/30
STw4141
Application information
4.7
PCB layout considerations
The Printed Circuit Board layout must include the following consideration:
Current paths carrying high currents (bold lines in Figure 15) must be wide and short to
minimize impedance in order to reduce looses and EMI.
Small currents flow through voltage paths. No specific care is requested about voltage paths
but it is recommended to follow the general rules for PCB routing to reduce influence of
external and internal interferences.
Figure 15. Board layout track length and width
L 4.7 µH
HIGH CURRENT PATH
VLX1
VLX2
VIN=2.7V to 5.5V
VOUT1=1.8V
PVDD
VDD
VOUT1
FB1
A2
A3
B1
A4
CIN
10 µF
6.3 V
COUT1
22 µF
6.3 V
D1
D3
D4
C2
C3
EN
VOUT2=1.0V/1.2V
AUTO
VOUT2
STw4141
B4
VSEL
FB2
COUT2
22 µF
6.3 V
D2
B2
MODE/SYNC
STATE
C1
A1
C4
B3
T_MODE
PGND GND
23/30
Application information
STw4141
4.7.1
PCB layout
Figure 16 and Figure 17 show the PCB layout. All components are on the top side of the
board.
Figure 16. Demoboard top layer
Figure 17. Demoboard assembled with 22 µF
output capacitor
4.7.2
TFBGA16 internal bumps access
Pad centers are at 500 µm distance. Pad diameter is 275 µm. The distance between two
adjacent pad edges is only 225 µm. We recommend a distance for lead-out signals from the
center of pad matrix by 75 µm wide trace. Isolation distance in this case is 75 µm (see
Figure 18 and Figure 19).
Figure 18. TFBGA16 ball pad spacing and track parameters to internal pads
Grid dot distance :
with
A = 500µm
B = 275µm
C = 75µm
24/30
STw4141
Application information
Figure 19. PCB routing example using TFBGA16
25/30
Package outline and mechanical data
STw4141
5
Package outline and mechanical data
Table 10. TFBGA 3x3x1.20 16 F4x4 0.50. Package code: L0 - JEDEC/EAIJ
Ref
Min.
Typ.
Max.
A
1.01
0.15
1.20 (Note 1)
A1
A2
b
0.82
0.30
3.00
1.50
3.00
1.50
0.50
0.25
2.85
0.35
3.15
D
D1
E
2.85
0.85
3.15
E1
e
ddd
eee
fff
0.08
0.15
0.05
Note:
1
2
Max mounted height is 1.12 mm. Based on a 0.28 mm ball pad diameter.
Solder paste is 0.15 mm thickness and 0.28 mm diameter.
TFBGA stands for Thin Profile Fine Pitch Ball Grid Array.
Thin profile: The total profile height (DIm A) is measured from the seating plane to the top of
the component.
A = 1.01 to 1.20 mm
Fine pitch < 1.00 mm pitch.
3
4
The tolerance of position that controls the location of the pattern of balls with respect to
datums A and B.
For each ball there is a cylindral tolerance zone eee perpendicular to datum C and located
on true position with respect to datums A and B as defined by e. The axis perpendicular to
datum C of each ball must lie within this tolerance zone.
The tolerance of position that controls the location of the balls within the matrix with respect
to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C
and located on true position as defined by e. The axis perpendicular to datum C of each ball
must lie within the tolerance zone.
Each tolerance zone fff in the array is contained entirely in the respective above eee zone
above.
The axis of each ball must be simultaneously in both tolerance zones.
5
Leadfree package according to JEDEC JESD-020-C
26/30
STw4141
Package outline and mechanical data
Figure 20. TFBGA 3x3x1.20 16 F4x4 0.50
27/30
Ordering information
STw4141
6
Ordering information
Table 11. STw4141 order codes
Output voltage options(1)
Package
marking
Part number
Package
Packing
(2)
VOUT1
(I/O)
VOUT2
VOUT2reduced
(CORE)
(CORE)
STw41411
STw41411/T
STw41412
STw41412/T
STw41413
STw41413/T
STw41414
STw41414/T
STw41415
STw41415/T
STw41416
STw41416/T
STw41417
STw41417/T
STA1
STA1
STA2
STA2
STA3
STA3
STA4
STA4
STA5
STA5
STA6
STA6
STA7
STA7
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
1.2 V
1.2 V
1.3 V
1.3 V
1.4 V
1.4 V
1.5 V
1.5 V
1.25 V
1.25 V
1.35 V
1.35 V
1.3 V
1.3 V
1.0 V
1.0 V
1.0 V
1.0 V
1.2 V
1.2 V
1.3 V
1.3 V
1.0 V
1.0 V
1.0 V
1.0 V
1.0 V
1.0 V
Tray
Tape and reel
Tray
Tape and reel
Tray
Tape and reel
Tray
TFBGA
3x3x1.2
16 balls
Tape and reel
Tray
Tape and reel
Tray
Tape and reel
Tray
Tape and reel
1. The output configuration which will be introduced in production will be only those related to customer design-in.
2. VOUT1 ≥ VOUT2 THIS CONDITION MUST BE ALWAYS VALID.
28/30
STw4141
Revision history
7
Revision history
Table 12. Document revision history
Date
Revision
Changes
24-Jan-2006
1
Initial release.
Updates in Table 8: Bill of material: inductor selection
Updates in Table 9: Bill of Material: capacitor selection
9-Jun-2006
2
Moved Ordering information to the end of the document and updated
the order codes..
29/30
STw4141
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30/30
相关型号：
STW4141_0606
Single-coil dual-output step-down DC/DC converter for digital base band and multimedia processor supply
STMICROELECTR
STW42N65M5
N-channel 650 V, 0.070 Ω, 33 A MDmesh⢠V Power MOSFET in I2PAK, TO-220, TO-220FP, D2PAK and TO-247
STMICROELECTR
STW43NM60ND
N-channel 600 V, 0.075 Ω, 35 A TO-247 FDmesh™ Power MOSFET (with fast diode
STMICROELECTR
STW43NM60NDD
35A, 600V, 0.095ohm, N-CHANNEL, Si, POWER, MOSFET, TO-247AC, ROHS COMPLIANT, TO-247, 3 PIN
STMICROELECTR
STW4510AE
7-CHANNEL POWER SUPPLY SUPPORT CKT, PBGA84, 6 X 6 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, TFBGA-84
STMICROELECTR
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