STV82X8 [STMICROELECTRONICS]
Digital Audio Decoder / Processor for BTSC Television/Video Recorders; 数字音频解码器/处理器的BTSC电视/录像机
| 型号： | STV82X8 |
| 厂家： | 
ST |
| 描述： | Digital Audio Decoder / Processor for BTSC Television/Video Recorders |
| 文件： | 总157页 (文件大小：2311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
STV82x8
Digital Audio Decoder/Processor
for BTSC Television/Video Recorders
PRELIMINARY DATA
Virtual or true multi-channel capabilities and easy digital
links make them ideal for digital audio low cost consumer
applications. Starting from enhanced stereo up to
independent control of 5 loudspeakers and a subwoofer
(5.1 channels), the STV82x8 family offers standard and
advanced features plus sound enhancements, spatial
and virtual effects to enhance television viewer comfort
and entertainment.
Key Features
■ Fully Automatic Multi-Standard Demodulation
● M/N standards
● FM mono
● BTSC (US MTS) stereo and SAP standards
■ Multi-Channel Capability
● 3 I²S digital inputs, S/PDIF (in/out)
● 5.1 analog outputs
● Dolby® Pro Logic®
Typical Applications
● Dolby® Pro Logic II®
● 2 I²S digital outputs (TQFP100 only)
● 2 asynchronous I²S digital inputs (TQFP100 only)
● Analog and digital TV with virtual surround sound
● Analog and digital TV with multi-channel surround
sound
● DVD and HDD recorders
● “Palm size” portable TV
■ Sound Processing
● ST royalty-free processing: ST WideSurround, ST
OmniSurround, ST Dynamic Bass, ST Bass
Enhancer, SRS® WOW™ , SRS® TruSurround
XT™ which is Virtual Dolby® Surround and Virtual
Dolby® Digital compliant
8
x
2
8
V
®
T
S
● Independent Volume / Balance for Loudspeakers
and Headphone
● Loudspeakers: Smart Volume Control (SVC),
5-band equalizer and loudness
TQFP80 Package
TQFP100 Package
● Headphone: Smart Volume Control (SVC), bass-
treble, loudness, ST Dynamic Bass and SRS®
TruBass™
● 3 different bip tones
■ Analog Audio Matrix
● 4 stereo inputs or 5 stereo inputs (TQFP100 only)
● 3 stereo outputs
● Pass-thru mode
■ Audio Delay for Audio Video Synchronization
● Embedded stereo delay up to 120 ms for lip-sync
function
© 2004 SRS Labs, Inc. All rights reserved, SRS and
the SRS logo are registered trademarks of SRS Labs, Inc.
● Independent delay on headphone and loudspeaker
channels
● External additional audio delay support (TQFP100
only)
The STV82x8 family, based on audio digital signal
processors (DSP), performs high quality and advanced
dedicated digital audio processing.These devices
provide all of the necessary resources for automatic
detection and demodulation of analog audio
transmissions for USA, Taiwanese, Brazilian etc.
terrestrial analog TV broadcasts.
“Dolby”, “Pro Logic”, and the double-D symbol are trademarks of
Dolby Laboratories.
Rev. 1
February 2005
1/157
STV82x8
Figure 1: STV82x8 Block Diagram (TQFP80)
Audio
DAC
T U O L A X T
Audio Matrix
N
A L X I T
S _ E L C L K
Back-end Processing and Pre-scaler
DATA_0
DATA_1
DATA_2
LR_CLK
S_CLK
2/157
STV82x8
Figure 2: STV82x8 Block Diagram (TQFP100)
Audio
DAC
T
N
L
O L U A X T
A L X I T
Audio Matrix
K _ S C E L
Back-end Processing and Pre-scaler
DATA_0
DATA_1
DATA_2
LR_CLK
SCLK
A_DATA
A_LR_CLK
A_S_CLK
D_DATA
3/157
STV82x8
Table of Contents
Chapter 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.1
STV82x8 Overview ............................................................................................................13
1.1.1 Core Features ..........................................................................................................................................13
1.1.2 Software Information ...............................................................................................................................14
1.1.3 Electrical Features ...................................................................................................................................14
1.2
Typical Applications ...........................................................................................................15
Chapter 2
System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Chapter 3
Digital Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Sound IF Signal ..................................................................................................................19
Demodulation .....................................................................................................................19
3.1
3.2
Chapter 4
Dedicated Digital Signal Processor (DSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Back-end Processing .........................................................................................................21
Audio Processing ...............................................................................................................22
ST WideSurround ...............................................................................................................24
ST OmniSurround ..............................................................................................................25
Dolby Pro Logic II Decoder ................................................................................................25
4.1
4.2
4.3
4.4
4.5
4.6
Bass Management .............................................................................................................25
4.6.1 Bass Management Configuration 0 .........................................................................................................26
4.6.2 Bass Management Configuration 1 .........................................................................................................26
4.6.3 Bass Management Configuration 2 .........................................................................................................27
4.6.4 Bass Management Configuration 3 .........................................................................................................28
4.6.5 Bass Management Configuration 4 .........................................................................................................29
4.7
SRS WOW and TruSurround XT ......................................................................................29
4.7.1 SRS TruSurround ....................................................................................................................................29
4.7.2 SRS WOW ...............................................................................................................................................30
4.8
Smart Volume Control (SVC) .............................................................................................30
ST Dynamic Bass/ST Bass Enhancer ...............................................................................31
5-Band Audio Equalizer .....................................................................................................31
Bass/Treble Control ...........................................................................................................31
Automatic Loudness Control ..............................................................................................32
Volume/Balance Control ....................................................................................................32
Soft Mute Control ...............................................................................................................33
Beeper ................................................................................................................................33
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4/157
STV82x8
Chapter 5
Analog Audio Matrix (Input / Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
I²S Interface (In / Out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Chapter 6
6.1
I²S Inputs ............................................................................................................................36
6.1.1 I²S Inputs in TQFP 80 Package ...............................................................................................................36
6.1.2 I²S Inputs in TQFP 100 Package .............................................................................................................37
6.2
I²S Outputs .........................................................................................................................37
6.2.1 I²S Outputs in TQFP 80 Package ............................................................................................................37
6.2.2 I²S Outputs in TQFP 100 Package ..........................................................................................................38
Chapter 7
S/PDIF Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Chapter 8
Power Supply Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
8.1
Standby Mode (Loop-through mode) .................................................................................41
Chapter 9
Additional Controls and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Headphone Detection ........................................................................................................42
IRQ Generation ..................................................................................................................42
I²C Bus Expander ...............................................................................................................42
9.1
9.2
9.3
Chapter 10 STV82x8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Chapter 11 I²C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
11.1
11.2
I²C Address and Protocol ...................................................................................................44
Start-up and Configuration Change Procedure ..................................................................45
Chapter 12 Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
I²C Register Map ................................................................................................................47
Software Registers .............................................................................................................49
STV82x8 General Control Registers ..................................................................................53
Clocking 1 ..........................................................................................................................56
Demodulator .......................................................................................................................58
Demodulator Channel 1 .....................................................................................................61
I2S and Analog Control ......................................................................................................69
Clocking 2 ..........................................................................................................................72
DSP Control .......................................................................................................................73
12.10 Automatic Standard Recognition ........................................................................................78
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STV82x8
12.11 Demodulator .......................................................................................................................81
12.12 Audio PreProcessing & Selection ......................................................................................84
12.13 Matrixing .............................................................................................................................89
12.14 Audio Processing ...............................................................................................................96
12.15 Mute .................................................................................................................................123
12.16 Beeper ..............................................................................................................................124
12.17 SPDIF Output Configuration ............................................................................................126
12.18 Headphone Configuration ................................................................................................126
12.19 DAC Control .....................................................................................................................127
12.20 AutoStandard Coefficients Settings .................................................................................129
Chapter 13 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
13.1
13.2
TQFP 80-pin Package ......................................................................................................131
TQFP 100-pin Package ....................................................................................................134
Chapter 14 Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Chapter 15 Input/Output Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Chapter 16 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
Absolute Maximum Ratings ............................................................................................145
Thermal Data ..................................................................................................................145
Power Supply Data ..........................................................................................................145
Crystal Oscillator .............................................................................................................146
Analog Sound IF Signal ..................................................................................................146
SIF to I²S Output Path Characteristics .............................................................................146
SCART to SCART Analog Path Characteristics ..............................................................147
SCART and MONO IN to I²S Path Characteristics ..........................................................148
I2S to LS/HP/SUB/C Path Characteristics .......................................................................148
16.10 I²S to SCART Path Characteristics ..................................................................................148
16.11 MUTE Characteristics ......................................................................................................149
16.12 Digital I/Os Characteristics ...............................................................................................149
16.13 I²C Bus Characteristics ..................................................................................................150
16.14 I²S Bus Interface ..............................................................................................................151
Chapter 17 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
6/157
STV82x8
17.1
17.2
TQFP80 Package ............................................................................................................153
TQFP100 Package ..........................................................................................................154
Chapter 18 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
7/157
General Description
STV82x8
1
General Description
This chip performs BTSC stereo and SAP analog TV stereo sound identification and
demodulation (no specific I²C programming is required). It offers various audio processing
functions such as equalization, loudness, beeper, volume, balance, and surround effects. It provides
a cost-effective solution for analog and digital TV designs.
The STV82x8 is an audio processor which integrates SRS® WOW™, SRS® TruSurround XT™,
Dolby® Pro Logic®, Dolby® Pro Logic II®, Virtual Dolby® Surround (VDS) and Virtual
Dolby® Digital (VDD) capabilities.
Advanced ST royalty-free algorithms such as ST OmniSurround, ST WideSurround, ST Dynamic
Bass, ST Bass Enhancer are also available in this audio sound processor. ST OmniSurround is a
certified Dolby® algorithm for the Virtual Dolby® Digital (VDD) and the Virtual Dolby® Surround
(VDS). When using VDD or VDS, either an external Dolby® Digital or an internal Pro Logic® (or
Pro Logic II®) decoder must be used respectively.
The STV82x8 is perfectly suited to current and future digital TV platforms, based on audio/video
digital chips (STD2000 - DTV100 platform) which include an internal digital decoder (MPEG,
Dolby® Digital...). In the case where a Dolby® Digital decoder is embedded in the audio/video
digital chip, Virtual Dolby® Digital certification could be obtained.
8/157
STV82x8
General Description
Table 1: STV82x8 Version List (TQFP 80)
STV8248
S
STV8258
STV8268
S
STV8278
S
STV8288
S
S
S
T
V
8
2
1
8
S
T
V
8
2
3
8
S
T
T
V
V
8
S
T
V
8
T
V
8
S
T
V
8
T
V
8
S
T
V
8
T
V
8
S
T
V
8
T
V
8
8
2
5
8
2
2
5
8
2
2
2
2
4
2
6
2
7
2
8
4
8
6
8
7
8
8
8
8
D
D
S
X
D
D
S
8
D
D
S
X
8
D
D
S
X
8
D
D
S
X
X
Multi-Channel Capabilities
I²S data input number
1
1
1
1
3
3
1
1
3
3
3
3
Analog loudspeakers output number
2.1
2.1
2.1
2.1
2.1
2.1
5.1
5.1
5.1
5.1
5.1
5.1
Embedded SRS® and Dolby® algorithms
Dolby
Dolby
®
®
Pro Logic
Pro Logic II
®
(DPLI) or
(DPLII)
DPLI
DPLI
XT
DPLI
DPLI
XT
DPLI
DPLI
XT
DPLI
DPLI DPLII DPLII
®
SRS
®
WOW
TruSurround XT (XT)
™
(WOW) or
WOW
XT
XT
SRS®
™
General Capabilities
S/PDIF Pass-thru
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BTSC & SAP / Mono FM
Demodulation
ST OmniSurround1,
ST WideSurround
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ST Voice, ST Dynamic Bass,
ST Bass Enhancer
Dolby® Pro Logic ® (DPLI) or
Dolby® Pro Logic II® (DPLII)
5.1 output
DPLI
DPLI
DPLI
DPLI DPLII DPLII
Dolby® Digital Bypass 5.1 output2
Virtual Dolby® Surround
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Virtual Dolby® Digital capability2
1. When using Virtual Dolby® Digital or Virtual Dolby® Surround with ST OmniSurround or SRS®
TruSurround XT™ a Dolby® Digital or a Pro Logic ® (or Pro Logic II®) decoder is mandatory respectively
2. Dolby® Digital Bypass capability or Virtual Dolby® Digital are obtained with the use of an external Dolby®
Digital decoder (for example STD2000).
9/157
General Description
STV82x8
Figure 3: Package Ordering Information
Order Code:
STV82x8 (Tray)
®
STV82x8/T (Tape & Reel)
For Example: STV8258DSX/T will be delivered in Tape & Reel conditioning
10/157
STV82x8
General Description
Table 2: STV82x8 Version List (TQFP 100)
STV8248
S
STV8258
STV8268
S
STV8278
S
STV8288
S
S
S
T
V
8
2
1
8
F
S
T
V
8
2
3
8
F
S
T
T
V
V
8
S
T
V
8
T
V
8
S
T
V
8
T
V
8
S
T
V
8
T
V
8
S
T
V
8
T
V
8
8
2
5
8
2
2
5
8
2
2
2
2
4
2
6
2
7
2
8
4
8
6
8
7
8
8
8
8
F
D
F
D
S
X
F
F
D
D
S
8
F
D
F
D
S
X
8
F
D
F
D
S
X
8
F
D
F
D
S
X
X
Multi-Channel Capabilities
I²S data input number
1
1
1
1
3
3
1
1
3
3
3
3
Analog loudspeakers output number
2.1
2.1
2.1
2.1
2.1
2.1
5.1
5.1
5.1
5.1
5.1
5.1
Embedded SRS® and Dolby® algorithms
Dolby® Pro Logic ® (DPLI) or
Dolby® Pro Logic II® (DPLII)
DPLI
DPLI
XT
DPLI
DPLI
XT
DPLI
DPLI
XT
DPLI
DPLI DPLII DPLII
SRS® WOW™ (WOW) or
SRS® TruSurround XT™ (XT)
WOW
XT
XT
General Capabilities
S/PDIF Pass-thru
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Second SIF input
I²S Output (always available)
BTSC & SAP / Mono FM
Demodulation
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ST OmniSurround1,
ST WideSurround
ST Voice, ST Dynamic Bass,
ST Bass Enhancer
Dolby® Pro Logic ® (DPLI) or
Dolby® Pro Logic II® (DPLII)
5.1 output
DPLI
DPLI
DPLI
DPLI DPLII DPLII
Dolby® Digital Bypass 5.1 output2
Virtual Dolby® Surround
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Virtual Dolby® Digital capability2
1. When using Virtual Dolby® Digital or Virtual Dolby® Surround with ST OmniSurround or SRS®
TruSurround XT™ a Dolby® Digital or a Pro Logic ® (or Pro Logic II®) decoder is mandatory respectively
2. Dolby® Digital Bypass capability or Virtual Dolby® Digital are obtained with the use of an external Dolby®
Digital decoder (for example STD2000).
11/157
General Description
STV82x8
Figure 4: Package Ordering Information
Order Code:
STV82x8F (Tray)
®
STV82x8F/T (Tape & Reel)
For Example: STV8258FDSX/T will be delivered in Tape & Reel conditioning
12/157
STV82x8
General Description
1.1
STV82x8 Overview
1.1.1 Core Features
●
Single audio source processing:
— IF source and/or analog stereo input (SCART)
— one digital source with a maximum of 6 synchronous channels (5.1 is obtained across three
I²S)
●
●
●
SIF input signal with Automatic Gain Control (AGC)
BTSC and SAP demodulator, FM Mono
Audio processor working at 48 kHz with specific features:
— For loudspeakers (L, R, L , R , SubW, C):
S
S
Dolby® Pro Logic II ® decoder with bass management
SRS® WOW™ or TruSurround XT™ including Virtual Dolby® Surround and Virtual Dolby®
Digital
ST WideSurround
ST OmniSurround
ST Dynamic Bass / ST Bass Enhancer
5-band equalizer or bass / treble controls
Loudness
Smart Volume Control
Volume/balance/soft-mute
Three different types of bips
Video processing delay compensation
— For headphones:
SRS® TruBass™
ST Dynamic Bass
Smart Volume Control
Bass / treble controls
Loudness
Volume/balance/soft-mute
Three different types of bips
Video processing delay compensation
●
●
Shared outputs for headphone and certain loudspeakers (surround channels);
Analog matrix with:
— Five external inputs:
Four SCART inputs (2 V
capable)
RMS
One analog mono input (0.5 V
)
RMS
— One internal input from a digital matrix via a DAC
— Three external outputs (2 V capable)
RMS
— One internal output for the digital matrix (using an internal ADC)
Digital matrix with:
●
— Three input modes (demodulator/SCART, SCART only and I²S)
— Three stereo outputs (loudspeakers, headphone and SCART)
High-end audio DAC
●
●
●
S/PDIF output for connection with an external amplifier/decoder
Internal multiplexer for the S/PDIF output (to share the internal S/PDIF output and the S/PDIF
output generated by the external decoder of the digital broadcast)
13/157
General Description
STV82x8
●
●
●
Specific stand-by mode (loop-through)
Control by I²C bus (two I²C addresses)
System PLL and clock generation using either a single crystal oscillator or a differential clock
input
1.1.2 Software Information
The different software combinations are listed in Table 3.
Table 3: Input/Output Software Configurations
Output (Number of Channels)
Input (Number of Channels)
1 (Mono)
2 (+1)
4 (+1)
5.1
ST WideSurround or
SRS® WOW™
ST WideSurround or
ST OmniSurround or
SRS® TruSurround XT™ or
SRS® WOW™ or
2 (LO & RO)
Dolby® Pro Logic® II
Dolby® Pro Logic® II
Dolby® Pro Logic® II
Dolby® Pro Logic® II
ST WideSurround or
ST OmniSurround or
SRS® TruSurround XT™ or
SRS® WOW™ or
2 (LT & RT)
Dolby® Pro Logic® I or II
Dolby® Pro Logic® I or II
ST OmniSurround or
SRS® TruSurround XT™
4 (+1)
5.1
No processing
Downmix
ST OmniSurround or
SRS® TruSurround XT™
No processing
Note: In addition to the above sound processing, it is always possible to add ST Voice and also ST
Dynamic Bass or ST Bass Enhancer algorithms.
Note: The SRS® TruSurround® and ST OmniSurround are approved by Dolby Labs as Virtual Dolby
Surround (VDS) and Virtual Dolby Digital (VDD).
The SRS® TruSurround XT™ system is composed of:
●
SRS® TruSurround™
SRS® WOW™
●
The SRS® WOW™ system also includes:
●
●
●
SRS® Dialog Clarity™
SRS® TruBass™
SRS® 3D mono / stereo
1.1.3 Electrical Features
Multi Power Supplies: 1.8 V, 3.3 V and 8 V.
Power Consumption:
●
lower than 800mW in functional mode (full features)
●
200 mW in loop-through mode corresponding to the switch-off of all digital blocks
14/157
STV82x8
General Description
1.2
Typical Applications
The STV82x8 is specified to enable flexible, analog and digital TV chassis design (refer to Figure 5,
Figure 6, Figure 7 and Figure 8).
The main considerations are:
●
●
●
all necessary connections between devices can be provided through the TV set,
pseudo stand-by mode used to copy to VCR or the DVD sources when the TV set is OFF,
pin compatibility with previous STV82x7 (TQFP80 package) TV design.
The STV82x8 can be used to process dual audio sources (one analog and one digital in parallel).
Note: Headphone and loudspeakers can be used simultaneously for dual-language purpose. In this case,
certain restrictions occur (see Section 4.2: Audio Processing).
For more connections, the SCART-to-SCART path can be used. The use of these full analog paths
implies that the sound is not digitally processed.
Figure 5: STV8238 Typical Application (Enhanced Stereo)
I²S In and Out (TQFP100)
I²S In or Out (TQFP80)
R
Tuner
S/PDIF
Output & Pass-thru
STV8238
Demodulation
- BTSC stereo & SAP
Sound Processing
- Volume, Balance, 5-Band Equalizer
- ST OmniSurround
SubW
L
or
- SRS® WOW™
4 x SCART
(TQFP100)
Left Right
15/157
General Description
STV82x8
Figure 6: STV8248 Typical Application (Analog Virtual Sound)
I²S In and Out (TQFP100)
I²S In or Out (TQFP80)
S/PDIF
Output & Pass-thru
R
Tuner
STV8248
Demodulation
- BTSC stereo & SAP
SubW
or
Sound Processing
- Volume, Balance, 5-Band Equalizer
- SRS® TruSurround XT™
- ST OmniSurround
L
1
- Virtual Dolby® Surround
4 x SCART
(TQFP100)
Left Right
1. When using VDS with ST OmniSurround or SRS TruSurround XTTM, an optional internal Pro Logic® decoder is mandatory.
Figure 7: STV8258 Typical Application (Digital: Virtual Sound)
Multi-Channel Digital Decoder
(Dolby® Digital)
R
S/PDIF
Output & Pass-thru
I²S
SubW
STV8258
Tuner
Demodulation
- BTSC stereo & SAP
or
L
Audio Processing
- Volume, Balance, 5-Band Equalizer
- SRS® TruSurround XT™
- ST OmniSurround
- Virtual Dolby® Surround
- Virtual Dolby® Digital
1
2
4 x SCART
(TQFP100)
Left Right
1. When using VDS with ST OmniSurround or SRS TruSurround XTTM, an optional internal Pro Logic® decoder is mandatory.
2. When using VDD with ST OmniSurround or SRS TruSurround XTTM, an external Dolby® Digital decoder is mandatory.
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STV82x8
General Description
Figure 8: STV8288 Typical Application (Digital TV: Multi-Channel and Virtual Sound)
Multi-Channel Digital Decoder
(Dolby® Digital)
R
C
S/PDIF
Output & Pass-thru
R
S
I²S
SubW
STV8288
Tuner
Demodulation
- BTSC stereo & SAP
or
L
S
Audio Processing
L
- Volume, Balance, 5-Band Equalizer
- Dolby® Pro Logic II®
- ST OmniSurround
- 5.1 Analog Outputs
- SRS® TruSurround XT™
1
- Virtual Dolby® Surround
- Virtual Dolby® Digital
2
4 x SCART
(TQFP100)
Left Right
Shared with surround L /R
S
S
1. When using VDS with ST OmniSurround or SRS TruSurround XTTM, an optional internal Pro Logic® decoder is mandatory.
2. When using VDD with ST OmniSurround or SRS TruSurround XTTM, an external Dolby® Digital decoder is mandatory.
Figure 9: STV8218 Typical Application (DVD & HDD Recorders)
A/V Codec
(Digital Recorder)
I²S
Tuner
or
STV8218
Demodulation
- BTSC stereo & SAP
- Volume, Balance, 5-Band Equalizer
- ST OmniSurround
4 x SCART
(TQFP100)
Left Right
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System Clock
STV82x8
2
System Clock
The System Clock integrates 2 independent frequency synthesizers.
The first frequency synthesizer is used by the demodulator at a frequency of 24.576 MHz.
The second frequency synthesizer is used by the DSP core and can be adjusted between 100 and
150 MHz depending on the application.
The default values are designed for a standard 27-MHz reference frequency provided by a stable
single crystal oscillator or an external differential clock signal (for example, from the STV35x0)
depending on the CLK_SEL pin configuration (CLK_SEL = 1 means a single crystal oscillator, 0
means an external differential clock).
The 27-MHz value is the recommended frequency for minimizing potential RF interference in the
application. The sinusoidal clock frequency, and any harmonic products, remain outside the TV
picture and sound IFs (PIF/SIF) and Band-I RF.
Note: A change in the reference frequency is compatible with other default I²C programming values,
including those of the built-in Automatic Standard Recognition System.
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STV82x8
Digital Demodulator
3
Digital Demodulator
The Digital Demodulator (see Figure 10) consists of a channel demodulator and a stereo/SAP
decoder.
All channel parameters are programmed automatically by the built-in Automatic Standard
Recognition System (Autostandard) in order to find the STEREO or the SAP modes. Channel
parameters can also be programmed manually via the I²C interface for very specific standards not
included among the known standards.
Figure 10: Demodulator Block Diagram
DSP Processing
DEMOD_STAT(0Dh)
STEREO_SAP_STATUS(4Ch)
AUTOSTD
DETECTION
ACOEFF1(1Dh)
BCOEFF1(1Eh)
SAP_CONF(47h)
CARFQ1 (12-14h) FIR1C (15-1Ch)
Deemphasis,
DBX decoding
and dematrixing
(L+R)* or mono*
Channel
Stereo/SAP
Demodulator
FM
Demodulator
AGC
Amp
DCO1+
Filter
A/D
SIF
(L-R)dbx or SAPdbx
Mixer
FIR1
AGC
Control
*: Pre-emphasis signal
dbx: DBX -encoded signal
3.1
3.2
Sound IF Signal
The Analog Sound Carrier IF is connected to the STV82x8 via the SIF pin. Before Analog-to-Digital
Conversion (ADC), an Automatic Gain Control (AGC) is performed to adjust the incoming IF signal
to the full scale of the ADC. A preliminary video rejection is recommended to optimize conversion
and demodulation performances. The AGC system provides a gain value allowing for a wide range
of SIF input levels.
The TQFP100 package provides a second SIF input.
Demodulation
The demodulation system operates by default in Automatic mode. In this mode, the STV82x8 is able
to identify and demodulate the BTSC TV sound standard including stereo and SAP modes
without any external control via the I²C interface.
The built-in Automatic Standard Recognition System (Autostandard) automatically programs
the appropriate bits in the I²C registers which are forced to Read-only mode for users.
STEREO and SAP modes can be removed (or added) from the List of modes to be recognized by
programming registers AUTOSTD_CTRL. The identified standard is displayed in register
AUTOSTD_STATUS and any change to standard is flagged to the host system via pin IRQ. This flag
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Digital Demodulator
STV82x8
must be reset by re-programming the LSB of register IRQ_STATUS while checking the detected
standard status by reading registers AUTOSTD_STATUS.
ITo recover out-of standard FM deviations or the Sound Carrier Frequency Offset, additional I²C
controls are provided without interfering with the Automatic Standard Recognition System
(Autostandard).
Table 4: BTSC Standard
Aural
Carrier
(4.5 MHz)
Peak
Frequency Audio Pre-
Modulation Sub-Carrier
Source
Modulation
Sub-Carrier
Range
processing
Type
Deviation
Deviation
75 µs Pre-
emphasis
Monophonic
Pilot
L+R
0.05 -15 kHz
25 kHz (1)
5 kHz
0Fh
2Fh
DBX
Compression
Stereophonic
L-R
0.05 -15 kHz
0.05 -15 kHz
AM DSB SC
FM
50 kHz(1)
DBX
Compression
SAP
2nd Channel
5Fh
10 kHz
15 kHz
(1) L+R and L-R must not exceed 50 kHz
Sound Carrier Frequency Offset Recovery:IF Carrier frequency can be adjusted with register
CAROFFSET1 within a large range (up to 120 kHz ) while the Automatic Standard Recognition
System remains active. The frequency offset estimation is written in registers DEMOD_DC_LEVEL
2
and can be used to implement the Automatic Frequency Control (AFC) via an external I² C control.
Manual Mode: If required, the Automatic Standard Recognition System system can be disabled
(Manual mode) and the user can control all registers including those only controlled by the
Automatic Standard Recognition System function when active. Manual mode is selected in register
AUTOSTD_CTRL by setting to 0 bits SAP_CHECK, STEREO_CHECK and MONO_CHECK.
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STV82x8
Dedicated Digital Signal Processor (DSP)
4
Dedicated Digital Signal Processor (DSP)
A dedicated Digital Signal Processor (DSP) takes charge of all audio processing features and the
low frequency signal processing features of the demodulator. The internal 24-bit architecture will
ensure a high quality signal treatment and an excellent dynamic.
4.1
Back-end Processing
The “back-end” processing corresponds to the low frequency signal processing (32 kHz or higher
frequencies) of the demodulator and other inputs (I²S, ADC).
Figure 11 shows a flowchart of the back-end processing tasks. However, the figure shows that the
processing is only a SINGLE SOURCE PROCESSING flow (no processing is possible with
“Demod + SCART” and I²S inputs simultaneously) and that the selection of a headphone output
restricts the loudspeakers configuration to 2.1 instead of 5.1.
Figure 11: Back-end Audio Processing
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Dedicated Digital Signal Processor (DSP)
STV82x8
The main features depend on the path:
●
FM Channel
— DC Removal
— Prescaling
— De-emphasis (50 or 75 us)
— Stereo Dematrix
Input SCART Channel
— DC Removal
●
— Prescaling
●
●
Input I²S Channel
— I²S Prescaling
Digital Audio Matrix
— Audio Channel Multiplexer between the different sources (IF, I²S, SCART) towards all
outputs (S/PDIF, LS, HP or SCART).
●
Autostandard management
— device configuration depending on the standard to be detected
— freeze the device when a standard is detected
— once a standard detected, check that there is no change in the detection status
— set the correct action depending on any change in the detection status (mono backup or
mute setup and new standard detection)
●
SCART
— Downmixing: L / R or L / R (see AC-3 specification)
T
T
0
0
— Soft Mute
4.2
Audio Processing
The following software is provided for main loudspeakers (L, R, C, L , R , SubW):
S
S
●
Downmix
Dolby® Pro Logic II® Decoder (L , R →L, R, C, Ls, Rs, SubW) with Bass Management
●
T
T
●
ST WideSurround, ST OmniSurround, SRS® WOW™ or SRS® TruSurround XT® (certified
Virtual Dolby® Surround and Virtual Dolby® Digital)
●
●
●
●
●
●
●
●
●
●
●
●
ST Dynamic Bass and ST Bass Enhancer
Smart Volume Control (SVC)
5-band Equalizer or Bass-Treble
Loudness
Volume with independent channels (Smooth Volume Control)
Master Volume Control
Mute/soft-mute
Balance
Beeper
Pink Noise Generator (used to position the loudspeakers)
Programmable Delay for each loudspeaker
Adjustable Delay for “lip sync” up to 120 ms (to compensate for audio/video latency)
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STV82x8
Dedicated Digital Signal Processor (DSP)
The following software is provided for the headphone or auxiliary output:
●
Downmix
●
●
●
●
●
●
●
●
●
●
SRS® TruBass™
ST Dynamic Bass
Smart Volume Control (SVC)
Bass/Treble
Loudness
Independent Volume for each channel (Smooth Volume Control)
Soft Mute
Balance
Beeper
Adjustable Delay for “lip sync” feature up to 120 ms (to compensate for audio/video latency)
The following software is provided for SCART or S/PDIF outputs:
●
Downmix
Soft Mute
●
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Dedicated Digital Signal Processor (DSP)
STV82x8
Figure 12: Audio Processing for Loudspeakers, Headphone, SCART and S/PDIF outputs
4.3
ST WideSurround
STV82x8 offers three preset ST WideSurround Sound effects on the Loudspeakers path:
●
●
●
Music, a concert hall effect
Movie, for films on TV
Simulated Stereo, which generates a pseudo-stereo effect from mono source
“ST WideSurround Sound” is an extension of the conventional stereo concept which improves the
spatial characteristics of the sound. This could be done simply by adding more speakers and coding
more channels into the source signal as is done in the cinema, but this approach is too costly for
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STV82x8
Dedicated Digital Signal Processor (DSP)
normal home use. The ST WideSurround system exploits a method of phase shifting to achieve a
similar result using only two speakers. It restores spatiality by adding artificial phase differences.
The Surround/Pseudo-stereo mode is automatically selected by the Automatic Standard
Recognition System (Autostandard) depending on the detected stereo or mono source. By default,
“Movie” is selected for Surround mode. This value may be changed to “Music” by the
WIDESRND_MODE bit in the WIDESRND_CONTROL register.
Additional user controls are provided to better adapt the spatial effect to the source. The ST
WideSurround Gain (WIDESRND_LEVEL) and ST WideSurround Frequency (WIDESRND_FREQ)
registers can be used to enhance Music Predominancy in Music mode and Theater effect and Voice
Predominancy in Movie mode.
4.4
ST OmniSurround
STV82x8 offers a spatial virtualizer to output any multi-channel input in stereo on the Loudspeakers
path.
“ST OmniSurround” will recreate a multi-channel spatial sound environment using only the Left and
Right front speakers. It can be adapted to any input configuration (OMNISRND_INPUT_MODE).
ST Voice will allow you to enhance the voice content of your program to increase the intellegibility
and the presence of the sound.
4.5
Dolby Pro Logic II Decoder
Dolby® Pro Logic II® is a matrix decoder that decodes the five channels of surround sound that
have been encoded onto the stereo sound tracks of Dolby® Surround program material such as
DVD movies and TV shows.
It is even possible to decode standard stereo signals like music or non encoded movies.
Furthermore, it is an active process designed to enhance sound localization through the use of very
high-separation decoding techniques.
The Dolby® Pro Logic II® decoder is also able to emulate the former Dolby® Pro Logic® decoder
in a specific mode.
4.6
Bass Management
This processing will generate the subwoofer signal and adjust all loudspeakers channels gain and
bandwidth.
Speakers capable of reproducing the entire frequency range will be referred to as “full range
speakers”, then signals sent to full range speaker will be full bandwidth (no filtering).
Speakers that have limited bass handling capabilities will be referred to as “satellite speakers”, then
signals sent to satellite speaker will be high-pass filtered to remove bass information below 100 Hz.
In the STV82x8, five output configuration modes have been implemented according to “Dolby
Digital Consumer Decoder” specifications. They are described below.
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Dedicated Digital Signal Processor (DSP)
4.6.1 Bass Management Configuration 0
STV82x8
In some cases, the bass management filters are available in the decoder itself, so there is no need
to reproduce these filters. The output configuration shown in Figure 13 offers this possibility.
Figure 13: Bass Management Configuration 0 (with Pro Logic switch indicating its reset state)
L
L
R
C
R
C
Ls
Ls
Rs
Rs
-15 dB
+
LFE
SubW
-5 dB
4.6.2 Bass Management Configuration 1
Configuration 1, shown in Figure 14, assumes that all five speakers are not full range and that all of
the bass information will be redirected to and reproduced by a single subwoofer. This configuration
is intended for use with 5 satellite speakers.
To prevent signal overload, the five main channels are attenuated by 15 dB, while the LFE channel
is attenuated by 5dB to maintain the proper mixing ratio.
Figure 14: Bass Management Configuration 1 (with Pro Logic switch indicating its reset state)
L
L
R
C
R
C
Ls
Ls
Rs
Rs
-15 dB
+
LFE
SubW
-5 dB
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STV82x8
Dedicated Digital Signal Processor (DSP)
4.6.3 Bass Management Configuration 2
Configuration 2 assumes that the left and right speakers, are full range while the center and
surround speakers are smaller speakers. Also, all bass data is redirected to the left and right
speakers.
This configuration include output level adjustment that allows 12 dB attenuation for the 3 smaller
speakers (C, Ls, Rs). When the level adjustment will be disabled the decoder boosts by 12 dB the
full range speakers (Left, Right).
Figure 15: Bass Management Configuration 2 (all switches indicate their reset state)
Level Adjustment
OFF Switch
L
+
+
-12 dB
L
+12 dB
-12 dB
-1.5 dB
C
C
R
R
-12 dB
+12 dB
-12 dB
Subwoofer
ON Switch
-1.5 dB
Ls
Ls
+
-12 dB
Rs
Rs
-15 dB
+
SubW
-5 dB
LFE
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Dedicated Digital Signal Processor (DSP)
4.6.4 Bass Management Configuration 3
STV82x8
The third configuration, shown in Figure 16, assumes that all speakers except the center are full
range, then all bass information will be directed to and reproduced by the front left and front right
and both surround speakers. In order to provide more flexibility to this configuration, a switch will
offer an option which will produce a subwoofer channel by the LFE channel.
When the Subwoofer Switch is OFF, the input channels will be attenuated by 8 dB. Configuration 3
is required in certain high-end products.
Figure 16: Bass Management Configuration 3 (all switches indicate their reset state)
Level Adjustment
OFF Switch
L
+
+8dB
+4dB
+
-8dB
-4dB
L
C
+8dB
+4dB
-8dB
-4dB
C
-4.5dB
R
+
+8dB
+
-8dB
-4dB
R
+4dB
+8dB
Ls
+
-8dB
-4dB
Ls
+4dB
+8dB
Rs
+
-8dB
-4dB
Rs
+4dB
-8dB
-4dB
LFE
+10dB
SubW
Subwoofer
ON Switch
Subwoofer
ON Switch
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STV82x8
Dedicated Digital Signal Processor (DSP)
4.6.5 Bass Management Configuration 4
This configuration implements the Simplified Dolby configuration. The center, left surround and right
surround channels are summed and then filtered by the LPF. The composite bass information is
either summed back into the left and right channels or summed with the LFE channel and sent to
the subwoofer output, see Figure 17.
Figure 17: Implementation of the Bass Management Configuration 4 (Simplified Configuration)
L
+
L
C
C
R
R
+
Ls
Rs
Ls
Rs
Subwoofer
ON Switch
-4.5dB
+
-10.5dB
-5dB
LFE
+
SubW
4.7
SRS WOW and TruSurround XT
The SRS® TruSurround XT™ is a processing system that can accept from 1 to 6 channels on input
and that will generate a 2-channel output signal.
This processing system includes the latest SRS® algorithms:
●
SRS® WOW™
●
SRS® TruSurround® (Multi-channel signal virtualizer)
4.7.1 SRS TruSurround
The SRS® TruSurround® is a processing that can accept from 2 to 5 channels on input and that will
generate a 2-channel output signal.
SRS® TruSurround® uses Head-Related Transfer Function (HRTF) -based frequency tailoring of
(L/R) difference signals to extend the sound image out past the physical boundaries of the speaker
placements to surround channel information. These rear channel HRTF curves have much greater
peak to valley differences at center frequencies. These were chosen to cause rear channel
difference signals to virtualize farther behind the listener and directed to a different virtual position
as compared to front channel signals. Information that is equal (L+R) in the rear surround channels
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Dedicated Digital Signal Processor (DSP)
STV82x8
is processed by an identical HRTF curve but mixed in at a much lower amount. This HRTF
processing of equal (L/R) signals was again used to virtualize information to the rear of the listener.
The SRS® TruSurround® is certified by Dolby Laboratories to be a Virtual Dolby® Digital and
Virtual Dolby® Surround.
4.7.2 SRS WOW
The SRS® WOW™ is an a sound processing system including:
●
●
●
SRS® 3D Mono/Stereo™
SRS® Dialog Clarity™
SRS® TruBass™
4.7.2.1 SRS 3D Mono/Stereo
This system is used to create a pseudo-stereo signal for mono inputs or a three-dimensional spatial
signal for stereo inputs.
4.7.2.2 SRS Dialog Clarity
This system is used to enhance dialog perception.
4.7.2.3 SRS TruBass
The SRS® TruBass™ audio enhancement technology provides deep, rich bass to small speaker
systems without the need for a subwoofer or additional extra physical components. For systems
with a subwoofer, TruBass™ complements and enhances bass performance. Psycho-acoustically,
when the human ear is presented with a low frequency sound signal that is missing the fundamental
harmonic, it will fill in the fundamental frequency based on the higher harmonics that are present.
By accentuating the second and higher frequency harmonics of the bass portion of a signal,
TruBass™ gives the perception of greatly improved bass response.
SRS® TruBass™ is implemented on loudspeakers path, headphone path or on both in parallel.
4.8
Smart Volume Control (SVC)
The Smart Volume Control regulates the audio signal level before audio processing. This regulation
is necessary in order for the signal level to be independent from the source (terrestrial channels, I2S
or SCART), its modulation (FM) and annoying volume changes (advertising, etc.). The Smart
Volume Control works as an audio compressor/expander; i.e. when the input signal exceeds the
threshold level, a very rapid attenuation (-2 dB/ms) is applied to rescale the signal down to the
threshold value. When the input signal is below the threshold level, the previous attenuation is
reduced slowly in order to retrieve the original input level (0dB gain). If the input signal is too low, an
addition gain of 6 dB can be provided.
To personalize the action of the SVC, five parameters are available:
1. Threshold: Maximum quasi-peak level that can be expected on output
2. Peak measurement mode: Select the channel on which the peak measurement must be
performed (Left, Right, Center...)
3. Release time: Gain slope applied to the amplification phase
4. Expander switch: To allow a +6dB amplification of small signals in order to reduce the output
dynamic range
5. Make up gain: Allows compensation of the signal amplitude limitation thanks to a 0 to 24 dB
adjustable gain.
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STV82x8
Dedicated Digital Signal Processor (DSP)
The SVC is implemented on the loudspeakers path, headphone path or on both in parallel
(independent settings). Also, the SVC can be applied in six-channel mode (L, R, L , R , C and
S
S
SubW).
4.9
ST Dynamic Bass/ST Bass Enhancer
STV82x8 offers dynamic bass boost processing on the Loudspeakers path:
ST Dynamic Bass is a bass boost process that can dramatically increase the bass content of any
program without any output level saturation.
3 cutoff frequencies (BASS_FREQ) can be chosen, 100 Hz, 150 Hz and 200 Hz to adapt the effect
to your loudspeakers. The amount of bass (BASS_LEVEL) can also be fine tuned in order to adapt
the effect loudness.
4.10 5-Band Audio Equalizer
The loudspeakers audio spectrum is split into 5 frequency bands and the gain of each of band can
be adjusted within a range from -12 dB to +12 dB in steps of 0.25 dB. The Audio Equalizer may be
used to pre-define frequency band enhancement features dedicated to various kinds of music or to
attenuate frequency resonances of loudspeakers or the listening environment. The Equalizer is
enabled by the LS_EQ_ON bit in the EQ_BT_CTRL register. The gain value for Band X is
programmed in register LS_EQ_BANDX.
The 5-Band Audio Equalizer is exclusive with Bass-Treble control. Bit LS_EQ_BT_SW in register
EQ_BT_CTRL is used to select either the 5-Band Audio Equalizer or the Bass-Treble control for the
Loudspeakers path.
Depending on the LS Equalizer or LS Bass-Treble value, the volume level can be clamped to the LS
output to prevent any possible signal clipping from occuring using the ANTICLIP_LS_VOL_CLAMP
bit in the VOLUME_MODES (D7h) register.
Figure 18: Equalizer
f1 = 100 Hz, f2 = 316 Hz, f3 = 1 kHz, f4 = 3.16 kHz and f5 = 10 kHz
4.11 Bass/Treble Control
The gain of bass and treble frequency bands for Headphone can be also tuned within a range from
-12 dB to +12 dB in steps of 0.25 dB. It may be used to pre-define frequency band enhancement
features dedicated to various kinds of music. The Headphone Bass/Treble feature is enabled by
setting the HP_BT_ON bit in the EQ_BT_CTRL register. The Bass and Treble gain values are
adjusted in registers HP_BASS_GAIN and HP_TREBLE_GAIN, respectively.
Depending on the HP Bass-Treble value, the volume level can be clamped to the HP output to
prevent any possible signal clipping from occuring using the ANTICLIP_HP_VOL_CLAMP bit in the
VOLUME_MODES (D7h) register.
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Dedicated Digital Signal Processor (DSP)
STV82x8
4.12 Automatic Loudness Control
As the human ear does not hear the audio frequency range the same way depending on the power
of the audio source, the Loudness Control corrects this effect by sensing the volume level and then
boosting bass and treble frequencies proportionally to middle frequencies at lower volume.
While maintaining the amplitude of the 1 kHz components at an approximately constant value, the
gain values of lower and higher frequencies are automatically progressively amplified up to +18 dB
when the audio volume level decreases.The maximum treble amplification can be adjusted from
0 dB (first order loudness) to +18 dB (second order loudness) in steps of 0.125 dB. As the volume is
proportional to the external audio amplification power, the loudness amplification threshold is
programmable in order to tune the absolute level. The Loudspeakers Loudness function is enabled
by setting the LS_LOUD_ON bit in register LS_LOUDNESS. The Loudspeakers Loudness
Threshold and Maximum Treble Gain values are also programmed in this register. The Headphone
Loudness function is enabled by setting the HP_LOUD_ON bit in register HP_LOUDNESS. The
Headphone Loudness Threshold and Maximum Treble Gain values are also programmed in this
register.
The loudness cut-off frequency is 100 Hz.
4.13 Volume/Balance Control
The STV82x8 provides a Volume/Balance Control for all output channels configuration (except for
S/PDIF) with different volume level per channel (L, R, C, L , R , SubW, SCART). Its wide range
S
S
(from +11.875 to -116 dB, in a dB linear scale with a 0.125 dB step) largely covers typical home
applications (approx. 60 dB) while maintaining a good S/N ratio.
Figure 19: Volume Control
+11.875 dB
-116 dB
Mute
00h
3FFh
I²C Control
An extra Master Volume Control can apply an extra gain/attenuation on L, R, C, L , R and SubW
S
S
channels.
The Volume/Balance Control can operate in one of two different modes:
●
In Differential mode (default value), the volume control is a common volume value for both the
Left and Right Loudspeakers or Headphone channels (see Figure 19) and complimentary
balance control is used (see Figure 20).
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STV82x8
Dedicated Digital Signal Processor (DSP)
●
In Independent mode, the volume for the Left and Right channels for Loudspeakers or
Headphone is controlled independently.
Figure 20: Differential Balance
100%
Mute
000h
200h
1FFh
I²C Control (10 bits)
4.14 Soft Mute Control
The Digital Soft Mute is applied smoothly (20 ms for 120 dB range) to avoid any switch noise on
output. It is available on all output channels pairs:
●
●
●
●
●
●
S/PDIF channel (Left/Right)
SCART channels (Left/Right)
Loudspeakers channels (Left/Right)
Center
Subwoofer
Headphone/Surround channels (Left/Right)
Another soft mute (analog) is also available on each DAC output.
4.15 Beeper
The beeper is used to generate a tone on the Loudspeakers or/and Headphone outputs. The
beeper sound (square wave) is added to the audio signal which is attenuated by 20 dB. The beep
sound amplitude includes a smooth attack and decay to avoid any parasitic noise when starting and
stopping.
It can be used for various applications such as beep sounds for remote control, alarm clock or other
features.
The Beeper operates in one of two modes:
● Pulse mode (beep applications): A tone with a programmable short duration (0.1, 0.25, 0.5
and 1.0 s) is generated. Afterwards, the beeper is automatically disabled and the output is
switched back to the audio signal, see Figure 21.
● Continuous mode (alarm application): A tone with a programmable long duration is
generated. Its start and stop controls must be programmed by I²C, see Figure 22.
The Beeper function is enabled by setting the BEEPER_ON bit in register BEEPER_ON.
Beeper parameters are controlled in register BEEPER_MODE.
The beeper tone level and frequency are programmed in register BEEPER_FREQ_VOL. The level
(or volume) ranges between 0 dB and -93 dB in steps of 3 dB and the tone frequency ranges
between 62.2 Hz and 8 kHz in steps of 1 octave.
33/157
Dedicated Digital Signal Processor (DSP)
STV82x8
A beep generator is shared only by the Loudspeakers or Headphone outputs. Therefore, in the
event of simultaneous beeps when in Pulse mode, only the first beep will define the effective
duration that will be the same for both outputs.
Figure 21: Pulse Mode
BEEP_ON = 1
BEEP_ON = 0
0.1, 0.25, 0.5 and 1.0 s
T predefined
62.5 Hz < f < 8 kHz
Figure 22: Continuous Mode
BEEP_ON = 1
T defined by I²C write
BEEP_ON = 0
62.5 Hz < F < 8 kHz
34/157
STV82x8
Analog Audio Matrix (Input / Output)
5
Analog Audio Matrix (Input / Output)
The analog part of the audio matrix can be divided into two parts: the SCART input matrix and the
SCART output matrix.
Figure 23: SCART Input Matrix
S1in
S2in
Digital
Matrix
S3in
S4in
S5in*
Audio ADC
2
*TQFP100 package only
MONO_in
Select
The SCART input matrix is an input for the digital matrix (after the ADC) which select which source
will be sent to the DSP.
Figure 24: SCART1/2/3 Output Matrix
S1in
S2in
2
S3in
S1out
Soft
S4in
mute
S5in*
Stereo DAC
MONO_in
Select or Mute
*TQFP100 only
The SCART output matrix selects the sound to output, which can be directly a SCART input or the
output of the DSP. A mute function is provided to switch off the outputs.
A soft-mute function is provided to avoid all spurious sounds when switching from one position to
another position.
The SCART 2 and 3 output matrices have the same functions as the SCART 1 output matrix.
The particularity of the matrix is to accept input signal of 2 V
such level. In this case, the power supply must be 8 V.
and to have the capability to output
RMS
The Mono audio input is able to accept signals with a 0.5 V
amplitude.
RMS
35/157
I²S Interface (In / Out)
STV82x8
6
I²S Interface (In / Out)
6.1
I²S Inputs
6.1.1 I²S Inputs in TQFP 80 Package
The STV82x8 can interface with a digital sound decoder. In this case, the digital data can be input
at a speed of 0.384 Mbytes/s (3.072 MHz for a 48 kHz sampling frequency with 32 bits of data).
A Sample Rate Conversion (SRC) is necessary if input frequency is not 48 kHz (STV82x8 slave) in
order to obtain a fixed frequency output from this block (48 kHz).
Note: The SRC function is only available in single I²S input mode.
The interface with one I²S connection (I2S_DATA0) enables the input of stereo or stereo-coded
Dolby® Pro Logic®.
One interface with three I²S connections connected to the DSP enables the processing of a multi-
channel signal (maximum of 6 channels).
Figure 25: TQFP 80 I²S Input Block Diagram
I2S_DATA0
fS Input = 32 to 48 kHz
I2S_DATA1
fS Input = 48 kHz only
Audio Processing
I2S_DATA2
fS Input = 48 kHz only
48 kHz DSP
Processing
I2S_SCLK
fS Input * 64
I2S_LR_CLK
fS Input = 32 to 48 kHz
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STV82x8
I²S Interface (In / Out)
6.1.2 I²S Inputs in TQFP 100 Package
An additional (auxiliary) asynchronous input is available in the TQFP100 package. An I2SD_DATA
input for external delay is also available, but it must be in phase with the I²S output clocks.
Figure 26: TQFP100 I²S Input Block Diagram
I2S_DATA0
fS Input = 32 to 48 kHz
I2S_DATA1
fS Input = 48 kHz only
I2S_DATA2
fS Input = 48 kHz only
I2S_SCLK
fS Input * 64
Audio Processing
I2S_LR_CLK
fS Input = 32 to 48 kHz
48 kHz DSP
Processing
I2SA_DATA
fS Input = 32 to 48 kHz
I2SA_SCLK
fS Input * 64
I2SA_LR_CLK
fS Input = 32 to 48 kHz
I2SD_DATA
fS Input = 48 kHz in phase with I2SO_LR_CLK and I2SO_SCLK
6.2
I²S Outputs
6.2.1 I²S Outputs in TQFP 80 Package
A digital stereo output (I²S compatible) is also available for routing the demodulated signal or a
converted input audio signal to an external device. In this case, the I2S_DATA0 signal and all clock
signals are set as outputs by setting bit D5 in register RESET to 1 (and bit D6 for the clocking). The
STV82x8 drives the serial bus (I2S_SCLK, I2S_LR_CLK, and I²2S_DATA0) in master mode in 64.fs
format with a sampling frequency (f ) of 48 kHz. The I2S_PCM_CLK signal can be used as a master
s
clock for the slave interface, if required. Both standard and non-standard modes are available.
37/157
I²S Interface (In / Out)
STV82x8
.
Figure 27: TQFP 80 I²S Output Block Diagram
I2S_DATA0
fS Output = 48 kHz
Audio Processing
I2S_SCLK
48 kHz DSP
Processing
fS Output * 64
I2S_LR_CLK
fS Output = 48 kHz
I2S_PCM_CLK
6.2.2 I²S Outputs in TQFP 100 Package
Two digital stereo outputs (I²S compatible) are available for routing the demodulated signal or a
converted input audio signal to an external device or perform an external delay. In this case, the
I2SO_DATA0 and I2SO_DATA1 signals are available with all I²S inputs active. The STV82x8 drives
the serial bus (I2SO_SCLK,I2SO_LR_CLK, I2SO_DATA0, and I2SO_DATA1) in master mode in
64.fs format with a sampling frequency (fs) of 48 kHz. The I2S_PCM_CLK signal can be used as a
master clock if required for the slave interface. Both standard and non-standard modes are
available. .
Figure 28: TQFP100 I²S Output Block Diagram
I2SO_DATA0
fS Output = 48 kHz
I2SO_DATA1
fS Output = 48 kHz
Audio Processing
I2SO_SCLK
fS Output * 64
48 kHz DSP
Processing
I2SO_LR_CLK
fS Output = 48 kHz
I2S_PCM_CLK
38/157
STV82x8
I²S Interface (In / Out)
Note: The Input and Output modes for I²S are exclusive in the TQFP80 package.
Figure 29: I²S Data Format: Lch = LOW, Rch = HIGH (I²S Input or Output mode)
1/fs
Lch
Rch
I2S_LR_CLK
I2S_SCLK
(= 64fs)
1
2
1
2
1
2
2
3
3
22 23 24
3
22 23 24
I2S_DATAx
(standard mode)
MSB
3
MSB
3
LSB
LSB
1
2
1
2
1
22 23 24
22 23 24
I2S_DATAx
(non-standard mode)
MSB
MSB
LSB
LSB
39/157
S/PDIF Input/Output
STV82x8
7
S/PDIF Input/Output
An S/PDIF output is available for connection with an external decoder/amplifier. An internal
multiplexer allows selection of either the internal signal or the external signal connected on the S/
PDIF input (for example, the signal provided by the external MPEG audio / Dolby Digital decoder).
The outputted internal signal can be selected from:
●
●
●
●
L/R
C/Sub
HP or Surround
SCART
A Mute facility is also provided on the S/PDIF output.
40/157
STV82x8
Power Supply Management
8
Power Supply Management
A mixed supply voltage environment requires the following voltages:
●
●
●
3.3V capable inputs/outputs for digital pins;
1.8V digital core;
8V capable inputs/outputs for analog audio interfaces (capability to output 2 V
requirements);
for SCART
RMS
●
●
●
3.3V for stereo ADC and DAC (analog part);
1.8V for stereo ADC and DAC (digital part);
1.8V for IF ADC and AGC.
These voltages will be delivered by the application with an accuracy of 5%. For more information,
refer to Section 16.3: Power Supply Data.
Other specific DC voltages or features are provided:
●
Voltage Reference and Biasing Generation (AGC, ADCs, DACs),
Bandgap reference.
●
8.1
Standby Mode (Loop-through mode)
The STV82x8 provides a Loop-through mode configuration that bypasses IC functions via a SCART
I/O pin (Full Analog Path only). In this case, only a minimum power of 200 mW is required.
In Standby mode, the digital and analog power supplies are switched off, except for pins VCC_H,
VCC33_LS, VCC33_SC, and VCC_NISO which are used to maintain the SCART path with the last
configuration programmed by analog matrixing (register SCART1_2_OUTPUT_CTRL and
SCART3_OUTPUT_CTRL). When switching back to normal Full Power mode, all I²C registers are
reset except for those used in Standby mode to maintain the original configuration.
In Standby mode, the I²C bus does not operate. However, the bus can still be used by other ICs
since the I²C I/O pins (SDA and SCL) of the STV82x8 are forced into a high-impedance
configuration.
41/157
Additional Controls and Flags
STV82x8
9
Additional Controls and Flags
This logic contains:
●
●
●
the headphone detection,
the IRQ generation, signal to be output to the MCU,
the I²C bus expander output pin.
9.1
9.2
Headphone Detection
For headphone, the HP_DET input can be used to automatically mute the Loudspeakers and
Subwoofer outputs when the HP_LS_MUTE bit is set in register HEADPHONE_CONFIG (active
low). When a headphone is detected (the HP_DET pin is set to 0) and the Mute function is enabled.
Each change on the HP_DET pin generates an IRQ request to the microprocessor on the IRQ pin.
IRQ Generation
Four IRQs are generated by the STV82x8. On each IRQ generation, the IRQ pin is set to 1. The
pending IRQ status must be read at the I²S address 81h and the acknowledge is done by writing 0
to this register.
The four availables IRQs are:
IRQ0: The identified TV sound standard is displayed in register AUTOSTD_STATUS. Each change
in the detected standard is flagged to the host system via hardware pin IRQ. The flag must be reset
by re-programming the IRQ bit in register AUTOSTD_CTRL and then checking the detected
standard status by reading registers AUTOSTD_DEM_STATUS and AUTOSTD_TIME.
IRQ1: This IRQ is enabled only in digital input mode. In case of I²S synchronisation loss, this IRQ is
set to 1.
IRQ2: This IRQ is set to 1 when the device detects any change on the HP Detection pin
(Headphone connection or deconnection).
IRQ3: On the STV82x8, same pins are used for both Headphone and Surround loudspeaker signal
output. A change in the Headphone configuration (HP active or not active) will lead to a signal
switch on those hardware pins. In order to ensure a smooth audio transition, the output is soft muted
before the signal is switched. The IRQ3 is then set to 1 to advise the master processor that the
signal has been switched and to request a HP/Srnd Ouput Un-Mute.
9.3
I²C Bus Expander
Pin BUS_EXP can be used to control external switchable IF SAW filters or audio switches. This pin
can be directly programmed by register RESET.
42/157
STV82x8
STV82x8 Reset
10 STV82x8 Reset
All STV82x8 features are controlled via the I²C bus.
The STV82x8 can be "reset" in 2 ways:
1. By Software via the I²C bus: This clears all synchronous logic, except for the I²C bus registers.
2. By Hardware via the RESET pin: In addition to clearing all synchronous logic, the RESET input
(active on the low level) resets all the I²C bus registers to the default values listed below.
Table 5: RESET Default Values
Function
Default Mode
Demodulation
Auto-standard
OFF
Scanned Standards
Audio Outputs
M/N BTSC
Automatic Mute Mode
Loudspeaker Source
Loudspeaker Volume
ON
Demodulated Sound
-40 dB, Differential Mode, Muted
L/R = 100%
Loudspeaker L/R Balance
Subwoofer
-40 dB / OFF
Headphone Source
Headphone Automatic Detection
Headphone Volume
Headphone L/R Balance
SCART1 Output
Demodulated Sound
ON
-40 dB, Differential Mode, Muted
L/R = 100%
Demodulated Sound
SCART1 Source
SCART2 Source
Mute
SCART2 Output
SCART3 Output
I²S Output (TQFP 100)
43/157
I²C Interface
STV82x8
11 I²C Interface
11.1 I²C Address and Protocol
The STV82x8 I²C interface works in Slave mode and is fully compliant with I²C standards in Fast
mode (maximum frequency of 400 kHz). Two pairs of I²C chip addresses are used to connect two
STV82x8 chips to the same I²C serial bus. The device address pairs are defined by the polarity of
the ADR_SEL pin and are listed in the following table:
Table 6: I²C Read/Write Addresses
ADR
Write Address (W)
Read Address (R)
LOW (connected to GND1)
HIGH (connected to VDD1)
80h
84h
81h
85h
Protocol Description
●
Write Protocol
Start
W
A
Sub-address
A
A
Data
A
....
A
Data
A
Stop
A
●
Read Protocol
Start
W
A
Sub-address
Stop
Start
R
A
Data
....
A
Data
N
●
●
●
●
●
W = Write address,
R = Read address,
A = Acknowledge,
N = No acknowledge.
Sub-address is the register address pointer; this value auto-increments for both write and read.
44/157
STV82x8
I²C Interface
11.2 Start-up and Configuration Change Procedure
Figure 30: Flowchart
Power ON
NOTE: This HW reset after Power ON is
mandatory to prevent incorrect device
configuration.
Hardware Reset (by pin 43)
Clock PLLs progammation
(for oscillator values other than 27 MHz)
(Registers FS1 and FS2)
(By I²C transfer)
Load Patch File
HW_RESET bit = 1
(bit 2 in HOST_CMD register)
(DSP RUN)
INIT_MEM bit ?
(bit 0 in DSP_STATUS
(DSP inititialization)
=0
register)
=1
(Analog or Digital)
Device Configuration Set-up
HOST_RUN bit = 1
(bit 0 in DSP_RUN register)
(Start DSP processing)
(Change configuration)
INIT_MEM bit = 0
HOST_NO_INIT bit = 1
(Registers 85h to FFh are not reset)
(bit 1 in DSP_RUN register)
(OPTIONAL)
(Stop DSP processing)
HOST_RUN bit = 0
45/157
Register List
STV82x8
12 Register List
Note: The unused bits (defined as ‘Reserved’) in the I²C registers must be kept to zero.
The system clock registers (from address 08h to 0Bh and from address 5Ah to 5Dh) do not need to
be modified if a standard 27 MHz crystal oscillator is used.
The default values of the demodulator registers (from address 0Ch to 55h) are for optimum
performances and any change is not recommended, except for:
●
CAROFFSET1 (22h) to compensate IF carrier frequency with an out-of-standard offset.
●
Soundlevel Prescaling PRESCALE_DEMOD_MONO (94h), PRESCALE_DEMOD_STEREO
(95h), PRESCALE_DEMOD_SAP (96h), PRESCALE_SCART (97h), PRESCALE_I2S0 (98H),
PRESCALE_I2S1 (99H), PRESCALE_I2S2 (9AH) to equalize demodulated or external audio
signal before audio processing.
●
Peak detector registers PEAK_DETECTOR (9Bh), PEAK_L (9Ch), PEAK_R (9Dh),
PEAK_L_R (9Eh) can be used to measure internal sound level.
Sound source selection for each audio output channel to be done using AUDIO_MATRIX1 (A2h),
AUDIO_MATRIX2 (A3h) and AUDIO_MATRIX3 (A4h).
Register AUTOSTD_CTRL (8Ah) is used to select the list of mono, stereo and SAP signals to be
recognized automatically.
Note: () used in reset value column means that the bit or the byte is read-only.
(S) symbol indicates that the field value is represented in signed binary format.
46/157
STV82x8
Register List
12.1 I²C Register Map
By default, all I²C registers controlled by Automatic Standard Recognition System (Autostandard)
are forced to Read-only mode for the user. These registers and bits are shaded in Table 1.
Table 7: List of I²C Registers (Sheet 1 of 2)
Name
Ad.
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IC General Control
CUT_ID
00h
01h
(0000 0001)
0000 0000
0
0
CUT_NUMBER[5:0]
CLOCK_
0
SOFT_
LRST1
RESET
BUS_EXP I2S_CO_EN I2S_DO_EN EN_STBY
SOFT_RST
DOWN
SYNC_
LOCK_
MODE
I2S_CTRL
04h
0000 0001
I2S_PLL
0
I2S_SRC
0
LOCK_TH[1:0]
SYNC_CST[1:0]
SIGN
0
LOCK_
FLAG
I2S_STAT
05h
06h
(0000 0000)
(0000 0000)
0
0
0
LR_OFF
I2S_SFO[7:0]
I2S_SYNC_OFFSET
Clocking 1
SYS_CONFIG
FS1_DIV
07h
08h
09h
0Ah
0Bh
0000 1010
0001 0011
0001 0001
0011 0110
0000 0000
SYNC_PLL OPEN_PLL
INPUT_FREQ[3:0]
BIT[1:0]
SDIV1[2:0]
EN_PROG
0
0
0
NDIV1[1:0]
0
FS1_MD
0
MD1[4:0]
FS1_PE_H
FS1_PE_L
PE_H1[7:0]
PE_L1[7:0]
Demodulator
DEMOD_CTRL
DEMOD_STAT
AGC_CTRL
0Ch
0Dh
0Eh
0000 0001
(0000 0000)
0001 0001
0
0
0
0
0
0
0
0
0
DEMOD_MODE[2:0]
FM1_CAR FM1_SQ
AGC_CST[1:0]
0
0
0
0
IF_SELECT
AGC_REF[2:0]
SIG_
UNDER
AGC_GAIN
DC_ERR_IF
0Fh
10h
(0000 0000)
(0000 0000)
0
AGC_ERR[4:0]
DC_ERR[7:0]
SIG_OVER
Demodulator Channel 1
CARFQ1H
CARFQ1M
CARFQ1L
FIR1C0
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
0010 1110
1110 0000
0000 0000
0000 0001
0000 0000
1111 1110
1111 1100
0000 0000
0000 1011
0001 1001
0010 0100
0010 0010
0000 1001
(0000 0000)
0010 0000
0011 1100
0000 0000
0000 0010
CARFQ1[23:16]
CARFQ1[15:8]
CARFQ1[7:0]
FIR1C0[7:0] (S)
FIR1C1[7:0] (S)
FIR1C2[7:0] (S)
FIR1C3[7:0] (S)
FIR1C4[7:0] (S)
FIR1C5[7:0] (S)
FIR1C6[7:0]6 (S)
FIR1C7[7:0] (S)
ACOEFF1[7:0]
BCOEFF1[7:0]
CRF1[7:0] (S)
FIR1C1
FIR1C2
FIR1C3
FIR1C4
FIR1C5
FIR1C6
FIR1C7
ACOEFF1
BCOEFF1
CRF1
CETH1
CETH1[7:0]
SQTH1
SQTH1[7:0]
CAROFFSET1
CHANNEL_GAIN
CAROFFSET1[7:0] (S)
0
0
0
0
0
0
CH_GAIN[1:0]
47/157
Register List
STV82x8
Table 7: List of I²C Registers (Sheet 2 of 2)
Name
Ad.
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BTSC Stereo and SAP
STEREO_CONF
STEREO_FSM_CONF
STEREO_LEVEL_H
STEREO_LEVEL_L
SAP_CONF
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
00111000
00001110
00100000
00010000
00000000
00100000
00010000
(00000000)
(00000000)
(00000000)
01101100
0000011
LOCK_TH_STE[7:4]
LOOP_GAIN[1:0]
GAIN_INI[2:0]
FREQ_PIL
RESET
0
0
0
0
BYPASS
FSM_OFF
STE_DEM
STE_LEV_H[7:0]
STE_LEV_L[7:0]
0
0
0
0
0
SAP_SEL
SAP_LEVEL_H
SAP_LEV_H[7:0]
SAP_LEV_L[7:0]
SAP_LEVEL_L
STE_CAR_LEVEL
STE_PLL_STATUS
STEREO_SAP_STATUS
PLL_P_GAIN
STE_CAR_LEV[7:0]
0
0
0
LOOP_GAIN[3:0]
LOCK_DET STE_DET
OVER
0
LOCK_DET STE_DET
SQ_DET SAP_DET
OVER
0
PLL_P_GAIN[7:0]
0
PLL_I_GAIN
0
0
0
PLL_I_GAIN[3:0]
SAP_SQ_TH
00110000
SAP_SQ_TH[7:0]
Analog and I2S Out Control
ADC_
I2S_ADC_CTRL
56h
0000 1000
I2S_DATA0_CTRL
0
ADC_INPUT_SEL[2:0]
POWER_UP
SC2_MUTE
SCART1_2_OUTPUT_CTRL
SCART3_OUTPUT_CTRL
I2SO_DATA_CTRL
57h
58h
59h
1010 1000
0000 1011
0000 0000
SC2_OUTPUT_SEL[2:0]
SC1_MUTE
SC1_OUTPUT_SEL[2:0]
SC3_OUTPUT_SEL[2:0]
I2SO_DATA0_CTRL
0
0
0
0
0
SC3_MUTE
0
I2SO_DATA1_CTRL
Clocking 2
FS2_DIV
5Ah
5Bh
5Ch
5Dh
0001 0001
0001 0001
0101 1100
0010 1001
0
0
NDIV2[1:0]
0
0
SDIV2[2:0]
FS2_MD
0
MD2[4:0]
FS2_PE_H
FS2_PE_L
PE_H2[7:0]
PE_L2[7:0]
48/157
STV82x8
Register List
12.2 Software Registers
Table 8: List of I²C Registers (Sheet 1 of 5)
Name
Addr.
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DSP Control
PATCH_WR
HW_RESET ITE_ENABL EMUL_SW
E
HOST_CMD
IRQ_STATUS
80h
81h
0000 0000
0000 0000
IT_IN_DSP
IRQ7
0
0
0
0
IRQ5
(HP/Srnd
unmute
ready)
IRQ3
IRQ4
(HP
detected)
IRQ2
(I2S sync
found)
IRQ1
IRQ0
(I2S SRC
input freq
change)
IRQ6
(I2S sync (AutoStanda
lost)
rd)
FW_VERSION
ONCHIP_ALGO
DSP_STATUS
DSP_RUN
82h
83h
84h
85h
(0000 0001)
(0000 0000)
0000 0000
0000 0000
SOFT_VERSION[7:0]
PROLOGIC MULTI_I2S_
TRUSURR
OUND
MULTICHA
NNEL_OUT
0
0
0
0
0
TRUBASS
0
PROLOGIC
0
_TYPE
IN
0
0
0
INIT_MEM
TEST_MOD
E_INPUT
REGISTER
S_RESET
TEST_MODE
INPUT_CONFIG
HOST_RUN
LOCK_
MODE_EN
LRCLK_STA LRCLK_PO SCLK_POL
RT LARITY ARITY
I2S_IN_CONFIG
86h
1000 1110
RESET_I2S
0
DATA_CFG I2S_MODE
I2S_IN_SHIFT_RIGHT
I2S_IN_MASK
87h
88h
0000 1000
0001 1111
0
0
0
0
0
SHIFT_RIGHT_RANGE
WORD_MASK
0
ENABLE_IR
AUTO_SRC Q_SRC_FR
ENABLE_IR ENABLE_IR
Q_SYNC_F Q_SYNC_L
I2S_IN_STATUS
89h
1000 0(000)
0
I2S_INPUT_FREQ
_SYNC
EQ_CHANG
E
OUND
OST
Automatic Standard Detection
MONO_SA
P_MATRIX_
CTRL
SIHGLESH
OT
FORCE_SQ FORCE_SQ AUTO_MUT SAP_CHEC STEREO_C MONO_CH
AUTOSTD_CTRL
8Ah
0000 0000
_SAP
_MONO
E
K
HECK
ECK
AUTOSTD_TIME
8Bh
8Ch
0000 1010
0
0
0
0
0
0
STEREO_TIME
SAP_OK
FM_TIME
STEREO_
OK
AUTOSTD_
ON
AUTOSTD_STATUS
(0000 0000)
0
MONO_OK
AUTOSTD_DEM_STATU
S
OVERFLO
W
8Dh
8Eh
8Fh
(0000 0000)
0000 0000
0000 0111
0
0
0
LCK_DET
0
ST_DET
SAP_SQ
SAP_DET
FM1_CAR
FM1_SQ
DMA_FORCE_OFF
0
0
ADC
I2S2
I2S1
I2S0
DEMOD
LRCLK_STA LRCLK_PO SCLK_POL
RT LARITY ARITY
I2S_IN_DELAY_CONFIG
SYNC
DATA_CFG I2S_MODE
Demodulator
BTSC_FINE_PRESCALE
_ST
90h
91h
0000 0000
0000 0000
BTSC_FINE_PRESCALE_ST[7:0] (S)
BTSC_FINE_PRESCALE_SAP[7:0] (S)
BTSC_FINE_PRESCALE
_SAP
FINE_PRES
CAL_SELE
CT_SAP
BTSC_CONTROL
DCREMOVAL
92h
93h
0010 0000
0011 0111
DBX_DEMATRIX
DBX_ON
DEEMPHASIS_CH1
DC_DEMO
DEEMPHASIS_CH0
DEEMPHAS
IS_FILTER_
SELECT
DBX_FILTE
R_SELECT
DC_DEMO DC_SCART
0
0
0
D_POST_O
N
D_PRE_ON
_ON
Audio Preprocessing & Selection
PRESCALE
_DEMOD_S
ELECT_SA
P
PRESCALE_DEMOD_M
ONO
94h
95h
0000 0000
PRESCALE_DEMOD_MONO[6:0] (S)
PRESCALE_DEMOD_STEREO[6:0] (S)
PRESCALE_DEMOD_ST
EREO
0000 0000
0
PRESCALE_DEMOD_SA
P
96h
97h
0000 0000
0000 0000
0
0
PRESCALE_DEMOD_SAP[6:0] (S)
PRESCALE_SCART[6:0] (S)
PRESCALE_SCART
49/157
Register List
STV82x8
Table 8: List of I²C Registers (Sheet 2 of 5)
Name
Addr.
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRESCALE_I2S0
PRESCALE_I2S1
PRESCALE_I2S2
98h
99h
9Ah
0000 0000
0000 0000
0000 0000
0
0
0
PRESCALE_I2S0[6:0] (S)
PRESCALE_I2S1[6:0] (S)
PRESCALE_I2S2[6:0] (S)
PEAK_DET
ECTOR_ON
PEAK_DETECTOR
PEAK_L
9Bh
9Ch
9Dh
9Eh
0000 0000
0(000 0000)
0(000 0000)
0(000 0000)
0
PEAK_L_R_RANGE[2:0]
PEAK_DET_INPUT[2:0]
OVERLOAD
_L
PEAK_L[6:0]
PEAK_R[6:0]
PEAK_L_R[6:0
OVERLOAD
_R
PEAK_R
OVERLOAD
_L_R
PEAK_L_R
Matrixing
LTRT_OUT_
MODE
DOWNMIX_MODE
9Fh
A0h
A1h
0111 1111
0000 0000
0000 0001
MIX_OUT_MODE[2:0]
LFE_IN
MIX_IN_MODE[2:0]
DOWNMIX_DUAL_MOD
E
LTRT_DUAL_SELECT
[1:0]
0
0
0
0
0
DUAL_ON
LS_DUAL_SELECT[1:0]
NORMALIZ
DOWNMIX_CONFIG
SRND_FACTOR[1:0]
CENTER_FACTOR[1:0] LR_UPMIX
E
AUDIO_MATRIX1
AUDIO_MATRIX2
AUDIO_MATRIX3
A2h
A3h
A4h
0001 0010
0000 0010
0001 0000
0
0
0
0
0
0
HP_OUT[2:0]
SCART2_OUT[2:0]
SPDIF_OUT[2:0]
LS_OUT[2:0]
SCART1_OUT[2:0]
DELAY_OUT[2:0]
AUTOSTD_ AUTOSTD_
CONTROL_ CONTROL_
CHANNEL_MATRIX_LS
CHANNEL_MATRIX_HP
A5h
A6h
A7h
0000 0010
0000 0000
0000 0000
0
0
0
CM_MATRIX_LS[2:0]
CM_MATRIX_HP[2:0]
LS
SPDIF
AUTOSTD_
CONTROL_ CM_SOURCE_HP[2:0]
HP
CM_POSTION_HP[2:0]
AUTOSTD_
CONTROL_
SCART1
CHANNEL_MATRIX_SC
ART1
CM_SOURCE_SCART1[ CM_POSTION_SCART1[
2:0] 2:0]
CM_MATRIX_SCART1[2:0]
AUTOSTD_
CONTROL_
SCART2
CHANNEL_MATRIX_SC
ART2
CM_SOURCE_SCART2[ CM_POSTION_SCART2[
A8h
A9h
0000 0000
0000 0000
CM_MATRIX_SCART2[2:0]
CM_MATRIX_SPDIF[2:0]
2:0]
2:0]
CHANNEL_MATRIX_SP
DIF
CM_POSTION_SPDIF[
2:0]
CM_SOURCE_SPDIF[3:0]
DEMOD_DC_LEVEL
AAh
ABh
ACh
(0000 0000)
0000 0000
0000 0000
DEMOD_DC_LEVEL[7:0] (S)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Audio Processing
DOLBY_DE AV_DELAY_
AV_DELAY_CONFIG
ADh
0000 0000
0
0
0
0
0
0
LAY_ON
ON
AV_DELAY_TIME_LS
AV_DELAY_TIME_HP
AEh
AFh
0000 0000
0000 0000
AV_DELAY_TIME_LS[7:0]
AV_DELAY_TIME_HP[7:0]
PL2_ACTIV
E
PROLOGIC2_CONTROL
PROLOGIC2_CONFIG
B0h
B1h
0111 0110
0000 0000
PL2_LFE
PL2_OUTPUT_DOWNMIX[2:0]
PL2_MODES[2:0]
PL2_RS_P PL2_PANO PL2_AUTO
OLARITY RAMA BALANCE
0
0
0
0
PL2_SRND_FILTER[1:0]
PROLOGIC2_DIMENSIO
N
B2h
B3h
B4h
0000 0000
0000 0011
0000 0000
PL2_C_WIDTH[2:0]
0
PL2_DIMENSION[2:0]
PROLOGIC2_LEVEL
NOISE_GENERATOR
PL2_LEVEL[7:0]
10_DB_ATT SRIGHT_
ENUATE
SLEFT_
NOISE
SUB_
NOISE
CENTER_
NOISE
RIGHT_
NOISE
LEFT_
NOISE
NOISE_ON
NOISE
PCM_SRND_DELAY
B5h
B6h
0000 0000
0000 0000
0
0
0
0
0
0
DOLBY_DELAY_SRND[4:0]
PCM_CENTER_DELAY
0
DOLBY_DELAY_CENTER[3:0]
50/157
STV82x8
Register List
Table 8: List of I²C Registers (Sheet 3 of 5)
Name
Addr.
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DIALOG_CL HEADPHO
TRUSRND_ TRUSRND_
TRUSRND_CONTROL
B7h
0000 1000
TRUSRND_INPUT_MODE[3:0]
ARITY_ON
NE_ON
BYPASS
ON
TRUSRND_DC_ELEVATI
ON
B8h
B9h
BAh
BBh
BCh
BDh
BEh
0000 1100
0000 0000
0000 0110
00001 1001
0000 0110
0000 1001
0000 0010
TRUSRND_DC_ELEVATION[7:0]
TRUSRND_INPUT_GAIN[7:0]
TRUSRND_INPUT_GAIN
TRUBASS_LS_CONTRO
L
TRUBASS_
LS_ON
0
0
0
0
0
0
0
0
TRUBASS_LS_SIZE[2:0]
TRUBASS_LS_LEVEL
TRUBASS_LS_LEVEL[7:0]
TRUBASS_HP_CONTRO
L
SRS_TSXT
_GAIN_ON
TRUBASS_
HP_ON
0
TRUBASS_HP_SIZE[2:0]
TRUBASS_HP_LEVEL
SVC_LS_CONTROL
TRUBASS_HP_LEVEL[7:0]
SVC_
LS_AMP
SVC_
LS_ON
0
0
0
0
SVC_LS_INPUT[1:0]
SVC_LS_TIME_TH
SVC_LS_GAIN
BFh
C0h
0000 0000
0000 1111
SVC_LS_TIME[2:0]
0
SVC_LS_THRESHOLD[4:0]
SVC_LS_MAKE_UP_GAIN[5:0]
0
0
SVC_
LHP_AMP
SVC_
HP_ON
SVC_HP_CONTROL
C1h
0000 0010
0
0
0
0
0
SVC_HP_TIME_TH
SVC_HP_GAIN
C2h
C3h
0000 0000
0000 1111
SVC_HP_TIME[2:0]
0
SVC_HP_THRESHOLD[4:0]
0
0
SVC_HP_MAKE_UP_GAIN[5:0]
WIDESRND WIDESRND WIDESRND
_STEREO _MODE _ON
WIDESRND_CONTROL
C4h
0000 0100
0
0
WIDESRND_MEDIUM[
1:0]
WIDESRND_TREBLE[
1:0]
WIDESRND_FREQ
WIDESRND_LEVEL
OMNISRND_CONTROL
C5h
C6h
C7h
0001 0101
1000 0000
0000 1100
0
0
WIDESRND_BASS[1:0]
WIDESRND_GAIN[7:0]
SRND_PHA
SE_INV
OMNISRND
_ON
ST_VOICE[1:0]
OMNISRND_INPUT_MODE[3:0]
LS_DYN_B
ASS_ON
DYNAMIC_BASS_LS
DYNAMIC_BASS_HP
C8h
C9h
0110 0010
0110 0010
LS_BASS_LEVEL[4:0]
LS_BASS_FREQ[1:0]
HP_DYN_B
ASS_ON
HP_BASS_LEVEL[4:0]
LS_BASS_
HP_BASS_FREQ[1:0]
LS_BASS_ LS_BASS_
ENHANCE_ ENHANCE_
BASS_ENHANCE_LS
CAh
0000 0000
0
0
ENHANCE_
HP_FILTER
LS_BASS_ENHANCE_SCALE[2:0]
CUTOFF
ON
CBh
CCh
0000 0000
0000 0000
0
0
0
0
0
0
0
0
0
0
0
0
0
LS_EQ_BT
_SW
EQ_BT_CONTROL
HP_BT_ON
LS_EQ_ON
LS_EQ_BAND1
LS_EQ_BAND2
LS_EQ_BAND3
LS_EQ_BAND4
LS_EQ_BAND5
LS_BASS_GAIN
LS_TREBLE_GAIN
HP_BASS_GAIN
HP_TREBLE_GAIN
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
EQ_BAND1[7:0] (S)
EQ_BAND2[7:0] (S)
EQ_BAND3[7:0] (S)
EQ_BAND4[7:0] (S)
EQ_BAND5[7:0] (S)
LS_BASS[7:0] (S)
LS_TREBLE[7:0] (S)
HP_BASS[7:0] (S)
HP_TREBLE[7:0] (S)
BASS_MAN ST_LFE_AD DOLBY_PR
SUB_
ACTIVE
GAIN_
SWITCH
OUTPUT_BASS_MNGT
LS_LOUDNESS
D6h
D7h
D8h
1000 0000
0000 0100
0000 0100
OCFG_NUM[2:0]
AGE_ON
D
OLOGIC
LS_
LOUD_ON
0
LS_LOUD_THRESHOLD[2:0]
HP_LOUD_THRESHOLD[2:0]
LS_LOUD_GAIN_HR[2:0]
HP_
LOUD_ON
HP_LOUDNESS
0
HP_LOUD_GAIN_HR[2:0]
Volume
51/157
Register List
STV82x8
Table 8: List of I²C Registers (Sheet 4 of 5)
Name
Addr.
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANTCLIP_H ANTICLIP_L
P_VOL_CL S_VOL_CL
SCART2_
SCART1_
HP_
SRND_
LS_
VOLUME_MODES
D9h
1101 1111
0
VOLUME_ VOLUME_ VOLUME_ VOLUME_ VOLUME_
MODE
AMP
AMP
MODE
MODE
MODE
MODE
LS_L_VOLUME_MSB
LS_L_VOLUME_LSB
LS_R_VOLUME_MSB
LS_R_VOLUME_LSB
LS_C_VOLUME_MSB
LS_C_VOLUME_LSB
LS_SUB_VOLUME_MSB
DAh
DBh
DCh
DDh
DEh
DFh
E0h
1001 1000
0000 0000
0000 0000
0000 0000
1001 1000
0000 0000
1001 1000
LS_L_VOLUME_MSB[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LS_L_VOLUME_LSB[1:0]
LS_R_VOLUME_LSB[1:0]
LS_C_VOLUME_LSB[1:0]
LS_R_VOLUME_MSB[7:0]
0
0
LS_C_VOLUME_MSB[7:0]
0
0
LS_SUB_VOLUME_MSB[7:0]
LS_SUB_VOLUME_LSB[
1:0]
LS_SUB_VOLUME_LSB
LS_SL_VOLUME_MSB
LS_SL_VOLUME_LSB
LS_SR_VOLUME_MSB
LS_SR_VOLUME_LSB
E1h
E2h
E3h
E4h
E5h
0000 0000
1001 1000
0000 0000
0000 0000
0000 0000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LS_SL_VOLUME_MSB[7:0]
LS_SL_VOLUME_LSB[
1:0]
0
0
LS_SR_VOLUME_MSB[7:0]
LS_SR_VOLUME_LSB[
1:0]
0
0
LS_MASTER_VOLUME_
MSB
E6h
E7h
1110 1000
0000 0000
LS_MASTER_VOLUME_MSB[7:0]
LS_MASTER_VOLUME_
LSB
LS_MASTER_VOLUME_
LSB[1:0]
0
0
0
0
0
0
0
0
0
0
HP_L_VOLUME_MSB
HP_L_VOLUME_LSB
HP_R_VOLUME_MSB
E8h
E9h
EAh
1001 1000
0000 0000
0000 0000
HP_L_VOLUME_MSB[7:0]
0
0
HP_L_VOLUME_LSB[1:0]
HP_R_VOLUME_MSB[7:0]
HP_R_VOLUME_LSB
[1:0]
HP_R_VOLUME_LSB
EBh
0000 0000
0
0
0
0
0
0
0
0
0
0
0
0
AUX_VOLUME_SELECT
[1:0]
AUX_VOLUME_INDEX
AUX_L_VOLUME_MSB
AUX_L_VOLUME_LSB
AUX_R_VOLUME_MSB
AUX_R_VOLUME_LSB
ECh
EDh
EEh
EFh
F0h
0000 0001
1101 1101
0000 0000
0000 0000
0000 0000
AUX_L_VOLUME_MSB[7:0]
AUX_L_VOLUME_LSB[
1:0]
0
0
0
0
0
0
0
0
0
0
AUX_R_VOLUME_MSB[7:0]
AUX_R_VOLUME_LSB[
1:0]
0
0
Mute
HP
D_MUTE
SPDIF_D_M SCART2_ SCART1_D SRND_D_M
SUB_
D_MUTE
C_
D_MUTE
LS_
D_MUTE
MUTE_SOFTWARE
Beeper
F1h
F2h
1111 1111
0000 0000
UTE
D_MUTE
_MUTE
UTE
BEEPER_SOUND_SELE BEEPER_
BEEPER_ON
0
0
0
0
0
CT[1:0]
ON
BEEPER_
BEEPER_DURATION[1:0] CONTINUO
US
BEEPER_MODE
F3h
F4h
0100 0011
0111 0110
BEEPER_DECAY[1:0]
BEEPER_FREQ[2:0]
BEEPER_PATH[1:0]
BEEPER_FREQ_VOL
BEEPER_VOLUME[4:0]
SPDIF Out Configuration
SPDIF_CO
NSUMER_P
RO
SPDIF_OUT_CHANNEL_
STATUS
SPDIF_CO SPDIF_NO_
F5h
0000 0010
0000 0010
0
0
0
0
0
0
PYRIGHT
PCM
Headphone Configuration
KARAOKE_
HP_LS_
MUTE
HP_DET_
ACTIVE
HP_
DETECTED
HP_SCART2_CONFIG
F6h
SCART2_OUT_SELECT HP_FORCE
MIX
52/157
STV82x8
Register List
Table 8: List of I²C Registers (Sheet 5 of 5)
Name
DAC Control
DAC_CONTROL
Addr.
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPDIF_
MUX
DAC_SCAR DAC_SHP_ DAC_CSUB DAC_LSLR POWER_
T_MUTE MUTE _MUTE _MUTE UP
F7h
0001 1111
0
0
0
DAC_SW_CHANNELS
SPDIF_SW_CHANNELS
F8h
F9h
0000 0000
0000 0000
C_SUB_SW[1:0]
SUR_HP_SW[1:0]
SCART_SW[1:0]
DELAY_SW[1:0]
SPDIF_SW[1:0]
L_R_SW[1:0]
0
0
0
AutoStandard Coefficients Settings
AUTOSTD_FSM
FAh
0000 0000
0
0
0
0
0
0
0
0
FSM_STATE
AUTOSTD_COEFF_CTR
L
AUTOSTD_COEFF_
CTRL[1:0]
FBh
0000 0001
0
0
0
0
AUTOSTD_
COEFF_IN
DEX_MSB
AUTOSTD_COEFF_IND
EX_MSB
FCh
FDh
0000 0000
0000 0000
0
0
0
0
0
AUTOSTD_COEFF_IND
EX_LSB
AUTOSTD_COEFF_INDEX_LSB[7:0]
AUTOSTD_COEFF_VAL
UE
FEh
FFh
0000 0000
0000 0000
AUTOSTD_COEFF_VALUE[7:0]
PATCH_VERSION[7:0]
PATCH_VERSION
12.3 STV82x8 General Control Registers
CUT_ID
Version Identification
Address: 00h
Type: R
Bit 7
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
CUT_NUMBER[5:0]
Bit Name
Reset
Function
Bits[7:6]
00
Reserved
CUT_NUMBER[5:0] 000001 Dice Version Identification
RESET
Software Reset Register
Address: 01h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
Bit 1
Bit 0
CLOCK_DOW
N
BUS_EXP
I2S_CO_EN
I2S_DO_EN
EN_STBY
SOFT_LRST1 SOFT_RST
Description
The built-in Automatic Standard Recognition System (Autostandard) can be disabled. In this case,
the Software Reset function (bits SOFT_LRST1 and SOFT_LRST2) can be used to implement the
53/157
Register List
STV82x8
Automatic Standard Recognition by I²C Software. This is not required if the built-in Automatic
Standard Recognition System function is used (default).
Bit Name
Reset
Function
BUS_EXP
0
0
Static control by I2C of hardware pin BUS_EXP
I²2S_CO_EN
0 = I²2S Input (I2S_SCK , I2S_LR_CLK, I2S_PCM_CLK in input mode)
1 = I²2S Output (I2S_SCK , I2S_LR_CLK, I2S_PCM_CLK in output mode)
I²2S_DO_EN
EN_STBY
0
0
0 = I²2S Input (I2S_DATA0 in input mode)
1 = I²2S Output (I2S_DATA0 in output mode)
Standby mode enabling
0: Normal mode
1: To lock the digital signals before to settle the device in standby mode
CLOCK_DOWN
Bit [2]
0
0
0
0
clock down of the dsp, decoder.
Reserved
SOFT_LRST1
SOFTR_RST
Softreset (active high) of Decoder..
General softreset (active high) to reset all hardware registers except for I²2C data.
I2S_CTRL
I²S Synchronization Control Register
Address: 04h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2S_PLL
SYNC_SIGN
I2S_SRC
LOCK_TH[1:0]
LOCK_MODE
SYNC_CST[1:0]
54/157
STV82x8
Register List
Bit Name
Reset
Function
I2S_PLL
0
Selects the i2s source for the synchronization with the synthesizer (at 48KHz only)
0: I2S_LR_CLK selected
1: I2SA_LR_CLK selected
SYNC_SIGN
I2S_SRC
0
0
Reverse the sign of the loop - To be used in case of gain inversion of the Frequency Synthesizer
Selects the i2s source for the src
0: I2S_LR_CLK selected
1: I2SA_LR_CLK selected
LOCK_TH[1:0]
00
Lock Detector Threshold Programming
00: 1 CLK period error of accumulation
01: 2 CLK period error of accumulation
10: 4 CLK period error of accumulation
11: 8 CLK period error of accumulation
LOCK_MODE
0
Lock Detector Mode
0: Lock when accumulation error within lock threshold and LR detected (period counter not satu-
rated)
1: Lock when only accumulation error within lock threshold. Don’t care of the LR detection
SYNC_CST[1:0]
00
Synchronization Time Constant
Defines the measurement period of LR
00: Half period measured (lowest accuracy)
01: One full period measured
10: Two full periods measured
11: Four full periods measured (highest accuracy)
I2S_STAT
I²S Synchronization Status Register
Address: 05h
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
0
LR_OFF
LOCK_FLAG
Bit Name
Reset
Function
Bits[7:2]
LR_OFF
0
0
Reserved.
LR Signal Detection
0: LR signal detected and correct
1: Missing LR pulses detected
LOCK_FLAG
0
Lock Flag allowing unmute of Audio Output
55/157
Register List
STV82x8
I2S_SYNC_OFFSET
I²S Synchronization Offset Frequency Register
Address: 06h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2S_SFO[7:0]
Bit Name
Reset
Function
I2S_SFO[7:0]
0000 I²S synchronization frequency offset ( 450 ppm full scale)
0000
12.4 Clocking 1
A low-jitter PLL Clock is integrated and can be fully reprogrammed using the registers described
below. By default, the programming is defined for a 27-MHz crystal oscillator, which is the frequency
recommended for reducing potential RF interference in the application. However, if necessary, the
PLL Clock can be re-programmed for other crystal oscillator frequencies within a range from 23 to
30 MHz. Other crystal frequencies can be programmed on your demand.
Note: A Crystal Frequency change is compatible with other default I²C programming including the built-in
Automatic Standard Recognition System.
SYS_CONFIG
System Configuration Control Register
Address: 07h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SYNC_PLL
OPEN_PLL
INPUT_FREQ[3:0]
BIT[1:0]
Bit Name
Reset
Function
SYNC_PLL
0
Status of the loop wyth the synthesizer
0: Open
1: Closed
OPEN_PLL
0
Force the loop with the synthesizer to be open
0: No Action
1: Loop Open
INPUT_FREQ[3:0]
BIT[1:0]
0010
10
I2S Input frequency
0010: 48 kHz
Reserved
56/157
STV82x8
Register List
FS1_DIV
FS1 I/O Divider Programming Register
Address: 08h
Type: R/W
Bit 7
Bit 6
0
Bit 5
Bit 4
Bit 3
0
Bit 2
Bit 1
Bit 0
EN_PROG
NDIV1[1:0]
SDIV1[2:0]
Bit Name
Reset
Function
EN_PROG
0
FS1 programmation enable
0: FS1 I2C registers programmation ignored by system - FS1 pre-programmed automatically by
SYS-CONFIG register (normal use with standard oscillator of 27 MHz)
1: FS1 I2C registers programmation used by system - FS1 pre-programmation by SYS-CONFIG
desactivated (to be used in case of no standard oscillator, other than 27 MHz)
Bit 6
0
01
0
Reserved.
NDIV1[1:0]
Bit 3
FS1 Input clock divider selection
Reserved.
SDIV1[2:0]
011
FS1 Output clock divider selection
FS1_MD
FS1 Coarse Selection Register
Address: 09h
Type: R/W
Bit 7
Bit 6
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
MD1[4:0]
Bit Name
Reset
Function
Bits[7:5]
000
Reserved.
MD1[4:0]
10001 FS1 Coarse Selection
FS1_PE_H
FS1 Fine Selection Register (MSBs)
Address: 0Ah
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PE_H1[7:0]
Bit Name
Reset
Function
PE_H1[7:0]
0011 FS1 Fine Selection (MSBs)
0110
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Register List
STV82x8
FS1_PE_L
FS1 Fine Selection Register (LSBs)
Address: 0Bh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PE_L1[7:0]
Bit Name
PE_L1[7:0]
Reset
Function
0000 FS1 Fine Selection (LSBs)
0000
12.5 Demodulator
DEMOD_CTRL
Demodulator Control Register
Address: 0Ch
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
Bit 1
DEMOD_MODE[2:0]
Bit 0
Bit Name
Reset
Function
Bits [7:3]
00000 Reserved
DEMOD_MODE[
2:0]
001
Demodulator Mode Select
Demod FM
000:
001:
Normal
Wide
other configuration: Reserved
DEMOD_STAT
Demodulator Detection Status Register
Address: 0Dh
Type: R
Bit 7
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
FM1_CAR
FM1_SQ
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STV82x8
Register List
Bit Name
Reset
Function
Bits [7:2]
000
0
Reserved.
FM1_CAR
Channel 1 FM Carrier Detector Flag
0: Not detected
1: Detected
FM1_SQ
0
Channel 1 FM Squelch Detector Flag
0: Not detected
1: Detected
Note: These registers allow direct access to the demodulator signal detectors.
AGC_CTRL IF AGC Control Register
Address: 0Eh
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IF_SELECT
AGC_REF[2:0]
AGC_CST[1:0]
Bit Name
Reset
Function
Bits[7:5]
00
0
Reserved.
IF_SELECT
Selection of the IF input.
0: IF input SIF 1
1: IF input SIF 2
AGC_REF[2:0]
100
This bitfield is used to defines the clipping level which adjusts the allowable proportion of samples
at the input of the ADC which will be clipped. The AGC tries to maximize the use of the full scale
range of the ADC. The default setting gives a ratio of 1/256.
Clipping Ratio
Clipping Ratio
000:
001:
010:
011:
1/16 (Single carrier)
100:
101:
110:
111:
1/256 (Default)
1/512
1/1024
1/32
1/64
1/128
1/2048 (Multiple carriers)
AGC_CST[1:0]
01
AGC Time Constant
This is the time constant between each step of 1.5 dB by the AGC.
Step Duration (ms)
00
01
10
11
1.33
2.66
5.33
10.66
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Register List
STV82x8
AGC_GAIN
IF AGC Control and Status Register
Address: 0Fh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
AGC_ERR[4:0]
SIG_OVER
SIG_UNDER
Bit Name
Reset
Function
Bit 7
0
Reserved.
AGC_ERR[4:0]
00000 Amplifier Gain Control
This is the Gain Control value of AGC. There are 20 steps of +1.5 dB (see Note below).
00000: Gain-min
10100: Gain-min + 30 dB
11111: Gain-min + 30 dB
SIG_OVER
0
0
AGC Input SIgnal Upper Threshold
0: Normal signal
1: Signal too large and AGC is overloaded
SIG_UNDER
AGC Input SIgnal Lower Threshold
0: Normal signal
1: Signal too small and AGC is underloaded
When the AGC is in Automatic mode (AGC_CMD = 0), bits SIG_OVER and SIG_UNDER indicate
if the input signal is too small/large and the AGC is under/overloaded. This is useful when setting
the STV82x7 SIF input level.
Note: When AGC_CMD = 0, AGC_ERR[4:0] can be read -- indicating the input level. It can also be written
to -- presetting the AGC level which will then adjust itself to the final value.
When AGC_CMD = 1, the AGC is off and writing to AGC_ERR[4:0] directly controls the AGC
amplifier gain. Reading AGC_ERR just confirms the fixed value.
DC_ERR_IF
DC Offset Status for IF ADC
Address: 10h
Type: R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DC_ERR[7:0]
Bit Name
Reset
00000000 DC offset error of IF ADC output
Function
DC_ERR[7:0]
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STV82x8
Register List
12.6 Demodulator Channel 1
CARFQ1H, CARFQ1M, CARFQ1L Channel 1 Carrier DCO Frequency
Address: 12h to 14h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CARFQ1[23:16], CARFQ1[15:8], CARFQ1[7:0]
Bit Name
Reset
Function
CARFQ1[23:16]
CARFQ1[15:8]
CARFQ1[7:0]
00101110 Channel 1 DCO Carrier Frequency (8 MSBs)
11100000 Channel 1 DCO Carrier Frequency
00000000 Channel 1 DCO Carrier Frequency (8 LSBs), see Table 2.
Table 9: Mono Carrier Frequencies by System
System
M/N
Mono Carrier Freq. (MHz)
CARFQ1[23:0] (dec)
CARFQ1[23:0]
4.5
3072000
2EE000h
24
Note: Carrier Freq: CARFQ1(dec).f / 2 with f = 24.576 MHz (crystal oscillator frequency
S
S
independent)
FIR1C[0:7]
Channel 1 FIR Coefficients
Address: 15h to 1Ch
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FIR1C0[7:0] to FIR1C7[7:0]
Description
Bitfield
(reset state)
BTSC
01h
FM 27 kHz
FM 50 kHz
00h
FM 200 kHz
00h
FM 350 kHz
02h
FM 500 kHz
01h
FIR1C0[7:0]
FIR1C1[7:0]
FIR1C2[7:0]
FIR1C3[7:0]
FIR1C4[7:0]
FIR1C5[7:0]
FIR1C6[7:0]
FFh
FEh
FEh
00h
06h
0Eh
16h
FEh
01h
01h
00h
00h
FCh
01h
FCh
04h
FEh
FDh
FCh
03h
FAh
FCh
02h
08h
04h
05h
00h
0Dh
F6h
F2h
00h
0Bh
18h
F8h
06h
F2h
19h
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Register List
STV82x8
Description
Bitfield
(reset state)
BTSC
FM 27 kHz
FM 50 kHz
FM 200 kHz
4Ah
FM 350 kHz
FM 500 kHz
FIR1C7[7:0]
1Bh
1Fh
43h
4Dh
24h
ACOEFF1
Channel 1 Baseband PLL Loop Filter Proportional
Coefficient
Address: 1Dh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ACOEFF1[7:0]
Bit Name
Reset
00100010
Function
Used to program the Proportional Coefficient of the baseband PLL loop filter (Channel 1)
Defines the damping factor of the loop. For values, refer to Table 3.
ACOEFF1[7:0]
BCOEFF1
Channel 1 Baseband PLL Loop Filter Integral
Coefficient & DCO Gain
Address: 1Eh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BCOEFF1[7:0]
Bit Name
Reset
Function
Used to program the Integral Coefficient of the baseband PLL loop filter and DCO gain
Defines the bandwidth of the loop. For values, refer to Table 3.
BCOEFF1[7:0]
00001001
Table 10: Baseband PLL Loop Filter Adjustment (FM Mode)
FM Mode
ACOEFF
Small
Standard
Medium
Wide*
BTSC
10h
1Ah
62.5
96
22h
12h
125
192
2Ch
0Ah
250
384
2Ch
0Ah
500
768
22h
09h
500
768
BCOEFF
FM_DEV max (kHz)
DCO Range (kHz)
(*) Refer to DEMOD_CTRL (DEMOD_MODE[2:0])
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STV82x8
Register List
CRF1
Channel 1 Baseband PLL Demodulator Offset
Address: 1Fh
Type: R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CRF1[7:0]
Bit Name
Reset
(00000000) Channel 1 Carrier Recovery Frequency
Function
CRF1[7:0]
Displays the instantaneous frequency offset of the Channel 1 Baseband PLL Demodulator.
CETH1
Channel 1 FM Carrier Level Threshold
Address: 20h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CETH1[7:0]
Bit Name
Reset
Function
CETH1[7:0]
00100000 This register is used to compare the carrier level in the channel and the threshold value. This
level is measured after the channel filter and is relative to the full scale reference level (0 dB).
This is used as part of the validation of an FM signal, if the carrier level is below the threshold,
the signal is considered to be non-valid. Recommended value is 10h.
CETH
FFh
80h
Threshold (dB)
-6
-12
CETH
10h
08h
Threshold (dB)
-32 (Recommended Value)
-38
40h
-18
00h
OFF (all carrier levels are accepted)
20h
-24 (Default)
SQTH1
Channel 1 FM Squelch Threshold Register
Address: 21h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SQTH1[7:0]
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Register List
STV82x8
Bit Name
Reset
Function
SQTH1[7:0]
00111100 The squelch detector measures the level of high frequency noise (> 40 kHz) and compares it to
the threshold level (SQTH). If the level is below this value, the S/N of the FM signal is
considered to be acceptable. Values are given for FM with standard deviation.
SQTH
S/N (dB)
FAh
77h
3Ch
23h
19h
0
10
15 (Default)
20
25
CAROFFSET1
Channel 1 DCO Carrier Offset Compensation
Address: 22h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CAROFFSET1[7:0] (S)
Bit Name
Reset
Function
CAROFFSET1[7:0]
00000000 This value is used to correct the carrier frequency offset of the incoming IF signal. Automatic
frequency control in FM mode can be implemented by registers DC_REMOVAL_L and
DC_REMOVAL_R.
A DCO frequency offset (in two’s complement format) is added to the pre-programming value
by AUTOTSD in the CARFQ1 registers (corresponding to the standard IF carrier frequency).
The programmable carrier offset ranges from -192 kHz to +190.5 kHz with a resolution of
1.5 kHz.
For standard FM deviation, the value displays by DC_REMOVAL_L and DC_REMOVAL_R can
be directly loaded in CAROFFSET1 to exactly compensate the carrier offset on Channel 1
CHANNEL_GAIN
Demodulator channel gain
Address:45h
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
0
CH_GAIN[1:0]
Bit Name
Reset
Function
Bits[7:2]
000000
Reserved.
Channel 1 Gain after the FM Demodulation
CH_GAIN[1:0]
10
00: Gain
10: Gain*4 (Default)
01: Gain * 2
11: Gain *8
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STV82x8
Register List
STEREO_CONF
BTSC Stereo Configuration
Address:43h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LOCK_TH_STE[7:4]
LOOP_GAIN[1:0]
FREQ_PIL
RESET
Bit Name
Reset
Function
LOCK_TH_STE[
7:4]
0011
BTSC Lock Stereo Threshold
Gain of Stereo PLL
10
LOOP_GAIN[1:0]
00: Gain * 4
10: Gain (Default)
01: Gain * 2
11: Gain / 2
0
0
Pilot Frequency Selection
FREQ_PIL
RESET
0: 15.625-15.734 kHz
1: Reserved
Stereo Reset
1: Reset Active
STEREO_FSM_CONF
BTSC Finite State Machine Configuration
Address:44h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BYPASS
FSM_OFF
GAIN_INI[2:0]
STE_DEM
Bit Name
Reset
Function
BIT[7:6]
00
0
Reserved.
Bypass of the Stereo Block
BYPASS
0: Stereo Block is On
1: Stereo Block is Bypassed
1: FSM is Off. Gain set by I²C
0
FSM Switch Off
FSM_OFF
0: FSM is On
GAIN_INI[2:0]
STE_DEM
111
0
Initial loop gain for FSM
Stereo dematrix inside the stereo block (before DBX)
1: reset active
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Register List
STV82x8
STEREO_LEVEL_H
BTSC Threshold High for Stereo Detection
Address:45h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STE_LEV_H[7:0]
Bit Name
STE_LEV_H[7:0]
Reset
00100011 Threshold High for Stereo Detection
If carrier level is > STE_LEV_H, stereo is detected
Function
STEREO_LEVEL_L
BTSC Threshold Low for Stereo Detection
Address:46h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STE_LEV_L[7:0]
Bit Name
STE_LEV_L[7:0]
Reset
00001100 Threshold Low for Stereo Detection
Function
If carrier level is <STE_LEV_L, stereo is not longer detected
SAP_CONF
BTSC SAP Selection
Address:47h
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SAP_SEL
Bit Name
Reset
0000000 Reserved.
Selection of the SAP
0: Stereo selected
Function
bit[7:1]
0
SAP_SEL
1: SAP is selected on second channel
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STV82x8
Register List
SAP_LEVEL_H
BTSC Threshold High for SAP Detection
Address:48h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SAP_LEV_H[7:0]
Bit Name
SAP_LEV_H[7:0]
Reset
01010000
Function
Threshold high for SAP detection
If SAP signal level is > SAP_LEV_H, SAP is detected
SAP_LEVEL_L
BTSC Threshold Low for SAP Detection
Address:49h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SAP_LEV_L[7:0]
Bit Name
SAP_LEV_L[7:0]
Reset
00110000 Threshold low for SAP detection
Function
If sap signal level is <STE_LEV_L, SAP is not longer detected
STE_CAR_LEV
BTSC Stereo Carrier Level
Address:4Ah
Type: R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STE_CAR_LEV[7:0]
Bit Name
Reset
Function
STE_CAR_LEV[7:0] 00000000 Stereo carrier level
STE_PLL_STAT
BTSC Stereo PLL Status
Address:4Bh
Type: R
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LOOP_GAIN[3:0]
OVER
LOCK_DET
STE_DET
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Register List
STV82x8
Bit Name
Reset
Function
Bits[7:6]
00
000
0
Reserved.
LOOP_GAIN[3:0]
Final FSM gain at the end of the stereo search process
Overflow append in stereo search process
OVER
1: overflow
0
0
Stereo PLL lock status
LOCK_DET
STE_DET
0: no lock on pilot
1: lock on pilot or no pilot detected (no stereo)
Stereo Detection
0: no stereo dectected
1: stereo detected
STE_SAP_STAT
BTSC Stereo SAP Status
Address:4Ch
Type: R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
Bit 2
0
Bit 1
Bit 0
0
OVER
LOCK_DET
STE_DET
SQ_DET
SAP_DET
Bit Name
Reset
Function
Bit 7
0
0
Reserved.
Overflow append in stereo search process
OVER
1: overflow
0
0
Stereo PLL lock status
LOCK_DET
0: no lock on pilot
1: lock on pilot or no pilot detected (no stereo)
1: stereo detected
Stereo detection
STE_DET
bit[3:2]
0: no stereo dectected
00
0
Reserved.
Squelch detection of SAP
SQ_DET
0: problem of noise
1: level of noise is good
1: SAP detected
0
Signal detection of SAP
SAP_DET
0: SAP not detected
PLL_P_G
BTSC PLL Proportionnal Gain
Address:4Dh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLL_P_G[7:0]
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STV82x8
Register List
Bit Name
PLL_P_G[7:0]
Reset
Function
01101100 PLL Proportional Gain
PLL_I_G
BTSC PLL Integral Gain
Address:4Eh
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
0
PLL_I_G[3:0]
Bit Name
Reset
Function
Bits [7:4]
0000
0011
Reserved.
PLL_I_G[3:0]
PLL integral Gain
SAP_SQ_TH
SAP Squelch Threshold
Address:4Fh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SAP_SQ_TH[7:0]
Bit Name
SAP_SQ_TH[7:0]
Reset
00110000 SAP squelch threshold
Function
12.7 I2S and Analog Control
I2S_ADC_CTRL
I2S_DATA0 and ADC Input Selection and Power-up
Address: 56h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
ADC_
I2S_DATA0_CTRL[2:0]
ADC_INPUT_SEL[2:0]
POWER_UP
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Register List
STV82x8
Bit Name
Reset
Function
Source selection for output I2S_DATA0
000: LR
001: HP_LSS
010: LS_C and LS_SUB
011: SCART DAC
100: S/PDIF_OUT
101: DELAY
110: reserved
111: reserved
I2S_DATA0_CTRL[
2:0]
000
Bit[4]
0
1
Reserved.
Control of the power up of the Audio ADC
ADC_POWER_UP
0: ADC in power down mode
1: Wake up of the ADC
Selection of the ADC input signal
000: Input SCART 1 (Default) (B SDIP64)100: Input Mono
ADC_INPUT_SEL
[2:0]
000
001: Input SCART 2 (res. SDIP 64)
010: Input SCART 3 (res. SDIP 64)
011: Input SCART 4 (res. SDIP 64)
101: Input SCART (res. TQFP) (A SDIP64) (1_BIS)
110: Input SCART (5 TQFP100) (C SDIP64) (3_BIS)
111: reserved (mute)
SCART1_2_OUTPUT_CTRL
SCART 1_2 Input Selection and Mute
Address: 57h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SC2_MUTE
SC2_OUTPUT_SEL[2:0]
SC1_MUTE
SC1_OUTPUT_SEL[2:0]
Bit Name
Reset
Function
SC2_MUTE
Mute command for the output SCART 2
1
0: output not muted
1: output muted
Selection of the output SCART 2 configuration:
000: DSP
001: Input Mono
100: Input SCART 3 (res. SDIP 64)
101: Input SCART 4 (res. SDIP 64)
SC2_OUTPUT_
SEL[2:0]
010
1
010: Input SCART 1 (Def) (B SDIP 64) 110: Input SCART (res. TQFP) (A SDIP 64) (1_BIS)
011: Input SCART 2 (res. SDIP 64)
111: Input SCART (5 TQFP 100) (C SDIP 64) (3_BIS)
Mute command for the output SCART 1
SC1_MUTE
0: output not muted
1: output muted
SC1_OUTPUT_
SEL[2:0]
Selection of the output SCART 1 configuration:
000: DSP (Default)
001: Input Mono
100: Input SCART 3 (res. SDIP 64)
101: Input SCART 4 (res. SDIP 64)
000
010: Input SCART 1 (B SDIP 64) 110: Input SCART (res. TQFP) (A SDIP 64) (1_BIS)
011: Input SCART 2 (res SDIP 64) 111: Input SCART (5 TQFP100) (C SDIP64) (3_BIS)
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STV82x8
Register List
SCART3_OUTPUT_CTRL
SCART 3 Input Selection and Mute
Address: 58h
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
SC3_OUTPUT_SEL[2:0]
Bit 0
0
SC3_MUTE
Bit Name
Reset
Function
Bits[7:4]
0000 Reserved.
Mute command for the output SCART 3
SC3_MUTE
1
0: output not muted
1: output muted
SC3_OUTPUT_SE
L[2:0]
Selection of the output SCART 3 configuration:
000: DSP
100: Input SCART 3 (res. SDIP 64)
011
001: Input Mono
101: Input SCART 4 (res. SDIP 64)
010: Input SCART 1 (B SDIP)
110: Input SCART (res. TQFP) (A SDIP64) (1_BIS)
011: Input SCART 2 (Default) (res. SDIP 64)111: Input SCART (5 TQFP 100) (C SDIP 64) (3_BIS)
I2SO_DATA_CTRL
I2S Data Source Control
Address: 59h
Type: R/W
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
0
Bit 2
Bit 1
Bit 0
I2SO_DATA1_CTRL[2:0]
I2SO_DATA0_CTRL[2:0]
Bit Name
Reset
Function
Bit [7]
0
Reserved.
000
Source Selection for I2SO_DATA1 Output
000: Mute
001: LR
010: HP_LSS
011: LS_C and LS_SUB
100: SCART DAC
101: S/PDIF_OUT
110: Delay
I2SO_DATA1_CTRL
[2:0]
111: Mute
Bit [3]
0
Reserved.
000
Source Selection for I2SO_DATA0 Output
000: Mute
001: LR
010: HP_LSS
011: LS_C and LS_SUB
100: SCART DAC
101: S/PDIF_OUT
110: Delay
I2SO_DATA0_CTRL
[2:0]
111: Mute
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Register List
STV82x8
12.8 Clocking 2
FS2_DIV
FS2 I/O Divider Programming Register
Address: 5Ah
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NDIV2[1:0]
SDIV2[2:0]
Bit Name
Reset
Function
Bit [7:6]
0
01
0
Reserved.
NDIV2[1:0]
Bit 4
FS2 Input clock divider selection
Reserved.
SDIV2[2:0]
001
FS2 Output clock divider selection
FS2_MD
FS2 Coarse Selection Register
Address: 5Bh
Type: R/W
Bit 7
Bit 6
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
MD2[4:0]
Bit Name
Reset
Function
Bits[7:5]
000
Reserved.
MD2[4:0]
10001 FS2 Coarse Selection
FS2_PE_H
FS2 Fine Selection Register (MSBs)
Address: 5Ch
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PE_H2[7:0]
Bit Name
Reset
Function
0101
1100
PE_H2[7:0]
FS2 Fine Selection (MSBs)
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STV82x8
Register List
FS2_PE_L
FS2 Fine Selection Register (LSBs)
Address: 5Dh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PE_L2[7:0]
Bit Name
Reset
Function
0010
1001
PE_L2[7:0]
FS2 Fine Selection (LSBs)
12.9 DSP Control
HOST_CMD
DSP Hardware Control
Address: 80h
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
Bit 1
Bit 0
PATCH_WRIT
E_ENABLE
IT_IN_DSP
HW_RESET
EMUL_SW
Bit Name
Reset
Function
IT_IN_DSP
Bits[6:3]
0
Valid I2C table.
0000 Reserved.
HW_RESET
Bits[1:0]
0
DSP Hardware reset when set.
Reserved.
00
IRQ_STATUS
IRQ Status
Address: 81h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
IRQ4
Bit 3
Bit 2
Bit 1
Bit 0
IRQ7
IRQ6
IRQ5
IRQ3
IRQ2
IRQ1
IRQ0
Bit Name
Reset
Function
Bits[7:6]
IRQ5
00
0
Reserved.
Hp/Srnd DAC unmute ready
HP detected
IRQ4
0
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Register List
STV82x8
Bit Name
Reset
Function
IRQ3
IRQ2
IRQ1
IRQ0
0
0
0
0
I2S SRC freq change detected
I2S sync found IRQ
I2S sync lost IRQ
Auto-Standard IRQ
FW_VERSION
Embedded Firmware Version
Address: 82h
Type: R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FW_VERSION[7:0]
Bit Name
Reset
Function
SOFT_VERSION
[7:0]
0000
0011
Version of the Embedded software.
ONCHIP_ALGOS
Display Algorithms available on the chip
Address: 83h
Type: R
Bit 7
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PROLOGIC_T
YPE
TRU
SURROUND
MULTICHANN
EL_OUT
0
MULTI_I2S_IN
TRUBASS
PROLOGIC
Bit Name
Reset
Function
Bits[7:6]
00
Reserved.
PROLOGIC_TYPE
0: ProLogic 1
1: ProLogic 2
0
0
MULTI_I2S_IN
0: 1 I2S input
1: 3 I2S inputs
TRUBASS
0
0
0
SRS TruBass algorithm is present when set.
TRUSURROUND
PROLOGIC
SRS TruSurround algorithm is present when set.
Dolby Pro Logic algorithm is present when set.
Multi-Channel output is present when set.
MULTICHANNEL_O
UT
0
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STV82x8
Register List
DSP_STATUS
DSP Status
Address: 84h
Type: R
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
INIT_MEM
Bit Name
Reset
Function
Bits[7:1]
0000000 Reserved.
DSP Initialization
0: DSP is not initialized.
INIT_MEM
0
1: DSP is initialized.
DSP_RUN
DSP Configuration and Run
Address: 85h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TEST_MODE_
INPUT
REGISTERS_
RESET
0
TEST_MODE
INPUT_CONFIG
HOST_RUN
Bit Name
Reset
Function
Bits[7]
0
Reserved.
active in TEST_MODE = 1 (bypass processing)
0: I2S_0 input -> L/R output
I2S_1 input -> C/LFE output
I2S_2 input -> Ls/Rs output
TEST_MODE_INP
UT
0
I2S_0 input -> SCART output (-6dB)
1: I2S_0 input -> L/R output
I2S_0 input -> C/LFE output
I2S_0 input -> Ls/Rs output
I2S_0 input -> SCART output (-6dB)
00: standard configuration
01: bypass processing configuration
10: Clock Loop test
TEST_MODE[5:4]
INPUT_CONFIG
00
00
11: Not Used
00: BTSC + I2S SRC + I2S DELAY + ADC
01: BTSC + I2S 48K + I2S DELAY + ADC
10: Not Used
11: BTSC + MULTI I2S 48K + ADC
RESGISTERS_RE
SET
0: I2C register table is not initialized when we soft reset
1: I2C register table is initialized when we soft reset
0
0
0: Soft Reset DSP
1: Start DSP
HOST_RUN
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Register List
STV82x8
I2S_IN_CONFIG
I2S Configuration
Address: 86h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LOCK_MODE
_EN
LRCLK_POLA SCLK_POLAR
RESET_I2S
SYNC
LRCLK_START
DATA_CFG
I2S_MODE
RITY
ITY
Bit Name
Reset
Function
0: Disable Lock Mode for external I2S input
1: Enable Lock Mode for external I2S input
LOCK_MODE_EN
RESET_I2S
1
0
Reset I2S input sync when set
I2S Synchronisation:
SYNC
0
0
0: Direct Capture
1: Wait for Sync signal
according to LRCLK POLARITY, first data take:
LRCLK_START
0: Left
1: Right
LRCLK_POLARITY
SCLK_POLARITY
0
1
Polarity of the left data
0: Falling Edge
1: Rising Edge
0: LSB First
1: MSB First
DATA_CFG
I2S_MODE
1
1
0: Not Standard Mode
1: Standard Mode
Note: This register must be set before the Start of the Software (85h: HOST_RUN = 1).
I2S_IN_SHIFT_RIGHT I2S Shift Right
Address: 87h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SHIFT_RIGHT_RANGE[4:0]
Bit Name
Reset
Function
Bits [7:5]
000
Reserved
SHIFT_RIGHT_RA
NGE[4:0]
Define the shift right to apply to 32-bit input samples. Range: 0 to 31
01000
Note: This register has to be set before the Start of the Software (0x85 : HOST_RUN = 1).
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STV82x8
Register List
I2S_IN_MASK
I2S Mask
Address: 88h
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
WORD_MASK[4:0]
Bit Name
Reset
Function
Bits [7:5]
000
Reserved
WORD_MASK[4:0]
11111 Define the mask to apply to 32-bit input samples. Range: 0 to 31
Note: This register has to be set before the Start of the Software (0x85 : HOST_RUN = 1).
I2S_IN_STATUS SRC I2S Input Behaviour
Address: 89h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ENABLE_IRQ ENABLE_IRQ
_SRC_FREQ_ _SYNC_FOUN
AUTO_SRC_S
YNC
ENABLE_IRQ
_SYNC_LOST
I2S_INPUT_FREQ
CHANGE
D
Bit Name
Reset
Function
AUTO_SRC_SYNC
0
Allow the DSP to reset the SRC input DMA when an input freq change is detected. (Working in
SRC mode only)
0: no reset on input frequency change
1: reset on input frequency change
ENABLE_IRQ_SRC
_FREQ_CHANGE
0
Generate an IRQ3 when a frequency change is detected on SRC input. (Working in SRC mode
only)
0: IRQ3 generation not active
1: IRQ3 generation active
ENABLE_IRQ_SYN
C_FOUND
0
0
0
Generate an IRQ2 when a signal is synchronized on SRC input. (Working in SRC mode only)
0: IRQ2 generation not active
1: IRQ2 generation active
ENABLE_IRQ_SYN
C_LOST
Generate an IRQ1 when a signal is lost on SRC input. (Working in SRC mode only)
0: IRQ1 generation not active
1: IRQ1 generation active
Bits [3]
Reserved
I2S_INPUT_FREQ
(000) Display the frequency detected on SRC input
000:
001:
010:
011:
no signal locked on SRC input
100: signal locked but frequency unknown
101: not used
110: not used
32 kHz
44.1 kHz
48 kHz
111: not used
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Register List
STV82x8
12.10 Automatic Standard Recognition
AUTOSTD_CTRL
Automatic Standard Recognition Control
Address: 8Ah
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MONO_SAP_C FORCE_SQ_S FORCE_SQ_M
STEREO_CHE MONO_CHEC
SINGLE_SHOT
AUTO_MUTE SAP_CHECK
TRL_MATRIX
AP
ONO
CK
K
Bit Name
Reset
Function
SINGLE_SHOT
Single-shot mode (To be selected whith any of the Mono/Stereo or Sap check bits):
0
0: Single Shot mode is not selected
1: Single Shot mode is selected1
MON_SAP_CONTR
OL_MATRIX
Change the behaviour of the automatic matrix control for SAP language
0: When SAP signal is detected, SAP signal is outputed on both Left and Right channels
1: When SAP signal is detected, Mono signal is outputed on the Left channel and SAP signal is
outputed on the Right channe
0
FORCE_SQ_SAP
Force the squelch status during SAP detection by autostandard.
0
0
0: SAP squelch from demod status
1: SAP squelch forced to 1
FORCE_SQ_MON
O
Force the squelch status during MONO detection by autostandard.
0: MONO squelch from demod status
1: MONO squelch forced to 1
AUTO_MUTE
0: Output channels are never mutted
1: Output channels are automaticly muted when no signal is detected
0
0
0
0
SAP_CHECK
0: No SAP standard research
1: SAP standard research
STEREO_CHECK
MONO_CHECK
0: No STEREO standard research
1: STEREO standard research (priority is given to SAP if selected)
0: No MONO standard research (AutoStandard OFF)
1: MONO standard research (mandatory to activate Autostandard)
1. Single_Shot mode will pre-program demodulator registers in a choosen standard (bits b2, b1, b0).
Autostandard will be switched OFF (Mono_check = 0) after the programation of the registers.
AUTOSTD_TIME
Detection Time Out
Address: 8Bh
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STEREO_TIME[2:0]
FM_TIME[1:0]
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STV82x8
Register List
Bit Name
Reset
Function
Bits [7:5]
000
Reserved
STEREO_TIME[2:0]
Stereo Detection Time-out
000:
001:
010:
011:
20 ms (Default) 100: 400 ms
000
10
40 ms
100 ms
200 ms
101: 800 ms
110: 1200 ms
111: 1600 ms
FM_TIME[1:0]
FM Detection Time-out
00: 16 ms
01: 32 ms
10: 48 ms (Default)
11: 64 ms
Note: The time-out default value is optimum and does not normally need to be changed.
AUTOSTD_STATUS Detection Standard Status
Address: 8Ch
Type: R
Bit 7
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
0
SAP_OK
STEREO_OK
MONO_OK AUTOSTD_ON
Bit Name
Reset
Function
Bits[7:4]
0000 Reserved.
SAP_OK
SAP Standard Recognition Status
0
0
0
0
0: SAP Standard not detected
1: SAP Standard detected
STEREO_OK
MONO_OK
AUTOSTD_ON
Stereo Standard Recognition Status
0: Stereo Standard not detected
1: Stereo Standard detected
Mono Standard Recognition Status
0: Mono Standard not detected
1: Mono Standard detected
Automatic Standard Recognition System Status
0: Automatic Standard Recognition System is OFF
1: Automatic Standard Recognition System is ON
AUTOSTD_DEM_STATUS
Demodulator Status
Address: 8Dh
Type: R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
OVERFLOW
LCK_DET
ST_DET
SAP_SQ
SAP_DET
FM1_CAR
FM1_SQ
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Register List
STV82x8
Bit Name
Reset
Function
Bits[7]
0
Reserved.
0: Stereo Lock Not Detected
1: Stereo Lock Detected
LCK_DET
ST_DET
0
0
0
0
0
0
0: Stereo Not Detected
1: Stereo Detected
0: SAP Squelch Not Detected
1: SAP Squelch Detected
SAP_SQ
SAP_DET
FM1_CAR
FM1_SQ
0: SAP Not Detected
1: SAP Detected
0: FM1 Carrier Not Detected
1: FM1 Carrier Detected
0: FM1 Squelch Not Detected
1: FM1 Squelch Detected
DMA_FORCE_OFF
Input DMA disable
Address: 8Eh
Type: R
Bit 7
Bit 6
0
Bit 5
0
Bit 4
ADC
Bit 3
I2S2
Bit 2
I2S1
Bit 1
I2S0
Bit 0
0
DEMOD
Bit Name
Reset
Function
Bits[7:5]
000
Reserved.
ADC
0: ADC input DMA active
1: ADC input DMA not active
0
0
0
0
0
I2S2
0: I2S2 input DMA active
1: I2S2 input DMA not active
I2S1
0: I2S1 input DMA active
1: I2S1 input DMA not active
I2S0
0: I2S0 input DMA active
1: I2S0 input DMA not active
DEMOD
0: Demod input DMA active
1: Demod input DMA not active
Note: This register must be set before the Start of the Software (85h: HOST_RUN = 1).
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STV82x8
Register List
I2S_IN_DELAY_CONFIG
I2S Configuration for Delay Input
Address: 8Fh
Type: R/W
Bit 7
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LRCLK_POLA SCLK_POLAR
0
SYNC
LRCLK_START
DATA_CFG
I2S_MODE
RITY
ITY
Bit Name
Reset
Function
Bits[7:6]
00
Reserved.
I²S Synchronisation:
SYNC
0
0
0: Direct Capture
1: Wait for Sync signal
LRCLK_START
according to LRCLK POLARITY, first data take:
0: Left
1: Right
LRCLK_POLARITY
SCLK_POLARITY
0
1
polarity of the left data
0: Falling Edge
1: Rising Edge
DATA_CFG
I2S_MODE
0: LSB First
1: MSB First
1
1
0: Not Standard Mode
1: Standard Mode
Note: For this input, the SHIFT_RIGHT and MASK of the I2S input are set.
SHIFT_RIGHT = 0x08
MASK = 0x1F
12.11 Demodulator
BTSC_FINE_PRESCALE_ST
BTSC input prescale for Stereo Mode
Address: 90h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BTSC_FINE_PRESCALE_ST[7:0] (S)
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Register List
STV82x8
Bit Name
Reset
Function
Set the prescale of the signal coming from the demodulator when STEREO is demodulated in
order to optimize the signal level at DBX block input (steps of 0.02 dB):
1000 0000:
...
0000 0000:
0000 0001:
...
-2.56 dB
BTSC_FINE_PRES
CALE_ST[7:0]
0000
0000
0 dB
0.02 dB
0111 1111:
2.54 dB
BTSC_FINE_PRESCALE_SAP
BTSC Input Prescale for SAP Mode
Address: 91h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BTSC_FINE_PRESCALE_SAP[7:0] (S)
Bit Name
Reset
Function
Set the prescale of the signal coming from the demodulator when SAP is demodulated in order to
optimize the signal level at DBX block input (steps of 0.02 dB):
1000 0000:
...
0000 0000:
0000 0001:
...
-2.56 dB
BTSC_FINE_PRES
CALE_SAP[7:0]
0000
0000
0 dB
0.02 dB
0111 1111:
2.54 dB
BTSC_CONTROL
BTSC Back-end Decoder Control
Address: 92h
Type: R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FINE_PRESC
ALE_SELECT
_SAP
DBX_DEMATRIX[1:0]
DBX_ON
DEEMPHASIS_CH1[1:0]
DEEMPHASIS_CH0[1:0]
Bit Name
Reset
Function
FINE_PRESCALE_
SELECT_SAP
Select the prescale value to apply on second channel before DBX
0
0: STEREO prescale (register 90h)
1: SAP prescale (register 91h)
DBX_DEMATRIX[
1:0]
Select L/R Dematrix for STEREO standard
00
0
00: No dematrixing (Mono or SAP)
01: L/R Dematrix (STEREO): L=Ch0+(Ch1)/2, R=Ch0-(Ch1)/2
10: Reserved
11: Reserved
DBX_ON
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0: DBX noise reductor not active
1: DBX noise reductor active on second channel (STEREO or SAP)
STV82x8
Register List
Bit Name
Reset
Function
DEEMPHASIS_CH
1[1:0]
Select the demmphasis for demodulator second channel :
00
00: No De-emphasis
10: 50 µs De-emphasis
11: 75 µs De-emphasis
01: 25 µs De-emphasis
DEEMPHASIS_CH
0[1:0]
Select the demmphasis for demodulator first channel :
00
00: No De-emphasis
10: 50 µs De-emphasis
11: 75 µs De-emphasis
01: 25 µs De-emphasis
DC_REMOVAL
DC Removal
Address: 93h
Type: R
Bit 7
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DEEMPHASIS
_FILTER_SEL
ECT
DBX_FILTER_
SELECT
DC_DEMOD_ DC_DEMOD_ DC_SCART_O
POST_ON PRE_ON
0
0
N
Bit Name
Reset
Function
Bits[7:6]
00
Reserved.
DBX_FILTER_SEL
ECT
Select the type of filter used in the DBX block
1
0: 1st Order Filter De-emphasis
1: 2nd Order Filter De-emphasis
DEMPHASIS_FILT
ER_SELECT
Select the type of filter used in the De-emphasis block
1
0
0
0: 1st Order Filter De-emphasis
1: 2nd Order Filter De-emphasis
Bit[3]
Reserved
DC_DEMOD_POST
_ON
Control the DC removal placed on the demod path, AFTER the DBX block:
0: DC removal OFF
1: DC Removal ON
DC_DEMOD_PRE_
ON
Control the DC removal placed on the demod path, BEFORE the DBX block:
0
0
0: DC removal OFF
1: DC Removal ON
DC_SCART_ON
Control the DC removal placed on the SCART path:
0: DC removal OFF
1: DC Removal ON
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Register List
STV82x8
12.12 Audio PreProcessing & Selection
PRESCALE_DEMOD_MONO
Prescale for Demod MONO
Address: 94h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRESCALE_D
EMOD_SELEC
T_SAP
PRESCALE_DEMOD_MONO[6:0] (S)
Bit Name
Reset
Function
PRESCALE_DEMO
D_SELECT_SAP
Select the prescale value to apply on channel 0 (Mono/Stereo):
0: Apply STEREO Prescale (95h) to the demodulated signal. To be used in case of STEREO
demodulation.
0
1: Apply MONO Prescale (94h) on left channel and SAP Prescale (96h) on right channel to
the demodulated signal. To be used in case of MONO or SAP demodulation.
PRESCALE_DEMO
D_MONO[6:0]
Set the prescale of the signal coming from the demodulator when MONO (Channel 0):
101 0000:
...
-12 dB
000 0000
000 0000:
000 0001:
...
0 dB
0.5 dB
011 0000:
24 dB
PRESCALE_DEMOD_STEREO
Prescale for Stereo Demodulation
Address: 95h
Type: R/W
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRESCALE_DEMOD_STEREO[6:0] (S)
Bit Name
Reset
Function
Bits[7]
0
Reserved.
PRESCALE_DEMO
D_STEREO[6:0]
Sets the prescale value of the Stereo signal coming from the demodulator (Channels 0 and 1):
101 0000:
...
-12 dB
000 0000
000 0000:
000 0001:
...
0 dB
0.5 dB
011 0000:
24 dB
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STV82x8
Register List
PRESCALE_DEMOD_SAP
Prescale for SAP Demodulation l
Address: 96h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
PRESCALE_DEMOD_SAP[6:0] (S)
Bit Name
Reset
Function
Bits[7]
0
Reserved.
PRESCALE_DEMO
D_SAP[6:0]
Set the prescale of the signal coming from the demodulator when SAP (channel 0):
101 0000:
...
-12dB
000 0000
000 0000:
000 0001:
...
0dB
0.5dB
011 0000:
24dB
PRESCALE_SCART
Prescale for SCART
Address: 97h
Type: R/W
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRESCALE_SCART[6:0] (S)
Bit Name
Reset
Function
Bits[7]
0
Reserved.
PRESCALE_SCAR
T[6:0]
Set the prescale of the signal coming from the SCART ADC:
101 0000:
...
-12dB
000 0000
000 0000:
000 0001:
...
0dB
0.5dB
011 0000:
24dB
PRESCALE_I2S0
Prescale for I2S0
Address: 98h
Type: R/W
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRESCALE_I2S0[6:0] (S)
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Register List
STV82x8
Bit Name
Reset
Function
Bits[7]
0
Reserved.
PRESCALE_I2S0[
6:0]
Set the prescale of the signal coming from the I2S0 (SRC input or I2S0 in multichannel input
mode):
101 0000:
...
000 0000:
000 0001:
...
-12dB
000 0000
0dB
0.5dB
011 0000:
24dB
PRESCALE_I2S1
Prescale for I2S1
Address: 99h
Type: R/W
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRESCALE_I2S1[6:0] (S)
Bit Name
Reset
Function
Bits[7]
0
Reserved.
PRESCALE_I2S1[
6:0]
Set the prescale of the signal coming from the I2S1 (I2S1 in multichannel input mode):
101 0000:
...
-12dB
000 0000
000 0000:
000 0001:
...
0dB
0.5dB
011 0000:
24dB
PRESCALE_I2S2
Prescale for I2S2
Address: 9Ah
Type: R/W
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRESCALE_I2S2[6:0] (S)
Bit Name
Reset
Function
Bits[7]
0
Reserved.
PRESCALE_I2S2[
6:0]
Set the prescale of the signal coming from the I2S2 (delay input or I2S2 in multichannel input
mode):
101 0000:
...
000 0000:
000 0001:
...
-12dB
000 0000
0dB
0.5dB
011 0000:
24dB
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STV82x8
Register List
PEAK_DETECTOR
Peak Detector
Address: 9Bh
Type: R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PEAK_DETEC
TOR_ON
0
PEAK_L_R_RANGE[2:0]
PEAK_DET_INPUT[2:0]
Bit Name
Reset
Function
Bits[7]
0
Reserved.
Control the sensitivity of the “Left - Right” peak measurement (register 0x9E).
The difference between Left and Right signal is sometime very small (in case of mono input for
example), so we can multiply the “Left - Right” peak measurement in order to add precision:
PEAK_L_R_RANG
E[2:0]
000
000:
001:
010:
011:
Left - Right
100: (Left - Right) x 16
101: (Left - Right) x 32
110: (Left - Right) x 64
111: (Left - Right) x 128
(Left - Right) x 2
(Left - Right) x 4
(Left - Right) x 8
PEAK_DETECTOR
_INPUT[2:0]
Select the input on which the peak detector makes the measurement:
000:
001:
010:
011:
demod signal
I2S0 signal
I2S1 signal
I2S2 signal
100: SCART signal
101: reserved
110: reserved
111: reserved
000
0
PEAK_DETECTOR
_ON
Control the Peak detector:
0: Peak detector OFF
1: Peak detector ON
PEAK_L
Peak Detector Left Channel
Address: 9Ch
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OVERLOAD_L
PEAK_L[6:0] (S)
Bit Name
Reset
Function
OVERLOAD_L
This bit is set to 1 by the DSP when the Left peak detector reaches its maximum value (0x7F).
It can be reset to 0.
0
PEAK_L[6:0]
Displays the Absolute Peak Level of the Left channel of the audio source selected. The measured
value is updated continuously every 64 ms. The range varies linearly from the full scale (0 dB)
down to 1/256 of the full scale (-48 dB).
000 0000:<-36dBFS
000 1111:-18dBFS
...
...
000 0000
000 0001:-36dBFS
001 1111:-12dBFS
...
...
000 0011:-30dBFS
...
011 1111:-6dBFS
...
000 0111:-24dBFS
...
111 1111:0dBFS
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PEAK_R
Peak Detector Right Channel
Address: 9Dh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OVERLOAD_R
PEAK_R[6:0] (S)
Bit Name
Reset
Function
OVERLOAD_R
This bit is set to 1 by the DSP when the Right peak detector reaches its maximum value (0x7F).
It can be reset to 0.
0
PEAK_R[6:0]
Displays the Absolute Peak Level of the Right channel of the audio source selected. The measured
value is updated continuously every 64 ms. The range varies linearly from the full scale (0 dB)
down to 1/256 of the full scale (-48 dB).
000 0000:<-36dBFS
000 1111:-18dBFS
...
...
000 0000
000 0001:-36dBFS
001 1111:-12dBFS
...
...
000 0011:-30dBFS
...
011 1111:-6dBFS
...
000 0111:-24dBFS
...
111 1111:0dBFS
PEAK_L_R
Peak Detector Left Minus Right Channel
Address: 9Eh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OVERLOAD_L
_R
PEAK_L_R[6:0] (S)
Bit Name
Reset
Function
OVERLOAD_L_R
This bit is set to 1 by the DSP when the “Left-Right” peak detector reaches its maximum value
0
(0x7F).
It can be reset to 0.
PEAK_L_R[6:0]
Displays the Difference between L and R (L - R) channels for the audio source selected:
000 0000:<-36dBFS
000 1111:-18dBFS
...
...
000 0001:-36dBFS
...
001 1111:-12dBFS
...
000 0000
000 0011:-30dBFS
...
011 1111:-6dBFS
...
000 0111:-24dBFS
...
111 1111:0dBFS
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Register List
12.13 Matrixing
DOWNMIX_MODE
Downmix Mode Configuration
Address: 9Fh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
MIX_IN_MODE[2:0]
Bit 0
LT_RT_OUT_M
ODE
MIX_OUT_MODE[2:0]
LFE_IN
Bit Name
Reset
Function
LT_RT_OUT_MOD
E
Define to format for downmix Lt/Rt output:
0
0: Lt/Rt Prologic compatible mode
1: L/R stereo mode
MIX_OUT_MODE[
2:0]
Select output channels configuration for downmix:
see table 3.
111
1
LFE_IN
To select if LFE is inputed on I2S1 in multichannel input mode:
0: No LFE on I2S1 input
1: LFE on I2S1 input
MIX_IN_MODE[2:0]
Select input channels configuration for downmix:
see table 2.
111
Table 11: DownMix IN modes
Parameter
Coding (bin)
Parameter
Field Lebel
Function
000
001
010
011
100
101
110
111
MODE11
MODE10
MODE20
MODE30
MODE21
MODE31
MODE22
MODE32
not used
1/0 (C)
2/0 (L,R)
3/0 (L,R,C)
2/1 (L,R,S)
3/1 (L,R,C,S)
2/2 (L,R,Ls,Rs)
3/2 (L,R,C,Ls,Rs)
Table 12: DownMix OUT modes
Parameter
Coding (bin)
Parameter
Field Lebel
Function
000
001
010
MODE20t
MODE10
MODE20
2/0 Dolby Surround (Lt,Rt)
1/0 (C)
2/0 (L,R)
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Table 12: DownMix OUT modes (Continued)
Parameter
Coding (bin)
Parameter
Field Lebel
Function
011
100
101
110
111
MODE30
MODE21
MODE31
MODE22
MODE32
3/0 (L,R,C)
2/1 (L,R,S)
3/1 (L,R,C,S)
2/2 (L,R,Ls,Rs)
3/2 (L,R,C,Ls,Rs)
DOWNMIX_DUAL_MODE
Downmix Dual Mode Configuration
Address: A0h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DUAL_ON
LS_DUAL_SELECT[1:0]
LTRT_DUAL_SELECT[1:0]
Bit Name
Reset
Function
Bits[7:5]
000
Reserved.
DUAL_ON
Select dual mode for DownMix bloc in case of dual language (in dual mode, Input and output mode
are forced to 2_0):
0
0: Standard DownMix
1: DownMix in Dual Mode
LS_DUAL_SELECT
[1:0]
Select the language for LS output in case of Dual mode:
00
00
00: Stereo
10: Right mono
01: Left mono
11: Left + Right mix
LTRT_DUAL_SELE
CT[1:0]
Select the language for LtRt output in case of Dual mode:
00: Stereo
10: Right mono
01: Left mono
11: Left + Right mix
DOWNMIX_CONFIG
Downmix Configuration
Address: A1h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRND_FACTOR[1:0]
CENTER_FACTOR[1:0]
LR_UPMIX
NORMALIZE
Bit Name
Reset
Function
Bits[7:6]
00
00
Reserved
SRND_FACTOR
[1:0]
00: -3 dB
01: -4.5 dB
10: -6 dB
10: -6 dB
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Register List
Bit Name
Reset
Function
CENTER_FACTOR 00
[1:0]
00: -3 dB
01: -4.5 dB
10: -6 dB
11: -4.5 dB
LR_UPMIX
0
0: Upmixing disabled
1: Upmixing enabled (DTS specified)
NORMALIZE
1
0: Normalization disabled
1: Nnormalization enabled
AUDIO_MATRIX1
AudioMatrix Configuration Register
Address: A2h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HP_OUT
LS_OUT
Bit Name
Reset
Function
Bits[7:6]
00
Reserved
HP_OUT[1:0]
LS_OUT[1:0]
010
010
Select the source to output on HP. See table 4.
Select the source to output on LS. See table 4.
AUDIO_MATRIX2
AudioMatrix part configurationr
Address: A3h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCART2_OUT
SCART1_OUT
Bit Name
Reset
Function
Bits[7:6]
00
Reserved
SCART2_OUT
[1:0]
010
Select the source to output on SCART2:
see table 4.
SCART1_OUT
[1:0]
010
Select the source to output on SCART1:
see table 4.
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AUDIO_MATRIX3
AudioMatrix part configuration
Address: A4h
Type: R/W
Bit 7
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
SPDIF_OUT
DELAY_OUT
Bit Name
Reset
Function
Bits[7:6]
00
Reserved.
SPDIF_OUT[1:0]
DELAY_OUT[1:0]
010
010
Select the source to output on SPDIF. See table 4.
Select the source to output on DELAY. See table 4.
Table 13: AudioMatrix Input Sources
Parameter
Coding (bin)
Parameter
Field Lebel
Function
000
001
010
011
100
101
110
111
MUTE
DELAY
DEMOD
LtRt
Mute Output
Delay Input
BTSC Demod Input
Downmix LtRt Input
I2S Input
I2S
SCART
-
SCART Input
Reserved
-
Reserved
CHANNEL_MATRIX_LS
Channel Matrix Configuration
Address: A5h
Type: R/W
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
Bit 1
Bit 0
AUTOSTD_CT AUTOSTD_CT
CM_MATRIX_LS[2:0]
RL_LS
RL_SPDIF
Bit Name
Reset
Function
AUTOSTD_CTRL_L 0
S
If this bit is activated, Autostandard algorithm will select automaticaly the appropriate matrixing
(Bits[2:0]) for LS output channels depending on the detected standard (see table 6).
0: Manual Matrix Selection
1: Automatic Matrix Selection if AutoStandard is ON
Note: Automatic Matrix Selection must be used only when DEMOD signal is directed to the Matrix.
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Register List
Bit Name
Reset
Function
AUTOSTD_CTRL_
SPDIF
0
If this bit is activated, Autostandard algorithm will select automaticaly the appropriate matrixing
(bits[2:0]) for SPDIF output channels depending on the detected standard (see table 6).
0: Manual Matrix Selection
1: Automatic Matrix Selection if AutoStandard is ON
Note: Automatic Matrix Selection must be used only when DEMOD signal is directed to the Matrix.
Bits[5:3]
000
Reserved
CM_MATRIX_LS[
2:0]
0000
Select the matrixing for the LS channels. See table 5.
CHANNEL_MATRIX_HP
Channel Matrix Configuration
Address: A6h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AUTOSTD_CT
RL_HP
CM_SOURCE_HP[1:0]
CM_POSITION_HP[1:0]
CM_MATRIX_HP[2:0]
Bit Name
Reset
Function
AUTOSTD_CTRL_
HP
0
If this bit is activated, Autostandard algorithm will select automaticaly the appropriate matrixing
(bits[2:0]) for HP output channels depending on the detected standard (see table 6).
0: Manual Matrix Selection
1: Automatic Matrix Selection if AutoStandard is ON
Note: Automatic Matrix Selection must be used only when DEMOD signal is directed to the Matrix.
CM_SOURCE_HP[ 00
2:0]
Select the source to copy on HP channel. See table 7.
CM_POSITION_HP 00
[1:0]
Select the position for the HP matrix. See block diagram
Select the matrixing for the HP channels. See table 5.
CM_MATRIX_HP[ 0000
2:0]
CHANNEL_MATRIX_SCART1 Channel Matrix configuration
Address: A7h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AUTOSTD_CT
RL_SCART1
CM_SOURCE_SCART1[1:0] CM_POSITION_SCART1[1:0]
CM_MATRIX_SCART1[2:0]
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STV82x8
Bit Name
Reset
Function
AUTOSTD_CTRL_
SCART1
0
If this bit is activated, Autostandard algorithm will select automaticaly the appropriate matrixing
(Bits[2:0]) for SCART1 output channels depending on the detected standard (see table 6).
0: Manual Matrix Selection
1: Automatic Matrix Selection if AutoStandard is ON
Note: Automatic Matrix Selection must be used only when DEMOD signal is directed to the Matrix.
CM_SOURCE_SCA 00
RT1[2:0]
Select the source to copy on SCART1 channel. See table 7.
CM_POSITION_SC 00
ART1[1:0]
Select the position for the SCART1 matrix. See block diagram
Select the matrixing for the SCART1 channels. See table 5.
CM_MATRIX_SCA 0000
RT1[2:0]
CHANNEL_MATRIX_SCART2 Channel Matrix configuration
Address: A8h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AUTOSTD_CT
RL_SCART2
CM_SOURCE_SCART2[1:0] CM_POSITION_SCART2[1:0]
CM_MATRIX_SCART2[2:0]
Bit Name
Reset
Function
If this bit is activated, Autostandard algorithm will select automaticaly the appropriate matrixing
(Bits[2:0]) for SCART2 output channels depending on the detected standard (see table 6).
AUTOSTD_CTRL_
SCART2
0
0: Manual Matrix Selection
1: Automatic Matrix Selection if AutoStandard is ON
Note: Automatic Matrix Selection must be used only when DEMOD signal is directed to the Matrix.
CM_SOURCE_SCA
RT2[2:0]
00
00
Select the source to copy on SCART2 channel. See table 7.
CM_POSITION_SC
ART2[1:0]
Select the position for the SCART2 matrix. See block diagram
CM_MATRIX_SCA
RT2[2:0]
0000 Select the matrixing for the SCART2 channels. See table 5.
CHANNEL_MATRIX_SPDIF
Channel Matrix Configuration
Address: A9h
Type: R/W
Bit 7
Bit 6
CM_SOURCE_SPDIF[2:0]
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CM_POSITION_SPDIF[1:0]
CM_MATRIX_SPDIF[2:0]
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Register List
Bit Name
Reset
Function
CM_SOURCE_SPD
IF[2:0]
000
Select the source to copy on SPDIF channel. See table 7.
CM_POSITION_SP
DIF[1:0]
00
Select the position for the SPDIF matrix. See block diagram.
CM_MATRIX_SPDI
F[2:0]
0000 Select the matrixing for the SPDIF channels. See table 5.
Table 14: Channel Matrix Modes
Parameter
Coding (Bin)
Parameter Field Lebel
Function
Bypass Stereo Signal
000
001
010
011
100
101
110
111
BYPASS
LEFT ONLY
Copy Left Signal On Both Channels
Copy Right Signal On Both Channels
Copy (Left + Right)/2 On Both Channels
Swap Channel (Left = Right, Right = Left)
Reserved
RIGHT ONLY
LEFT + RIGHT MIX
SWAP
-
-
-
Reserved
Reserved
Table 15: Automatic Channel Matrix Modes
Standard
Detected by
Autostandard
MONO_SAP_CTRL_MATRIX
reg 0x8A, bit[6] value = 0
MONO_SAP_CTRL_MATRIX
reg 0x8A, bit[6] value = 1
Left Output
Mono Signal
Left Signal
SAP Signal
Right Output
Mono Signal
Right Signal
SAP Signal
Left Output
Right Output
Mono
Stereo
SAP
Mono Signal
Left Signal
Mono Signal
Right Signal
SAP Signal
Mono Signal
Table 16: Channel Matrix Source Selection
Parameter
Coding (Bin)
Parameter Field Lebel
Function
bypass stereo signal coming from Audiomatrix
000
001
010
BYPASS
LS Channels
HP Channels
copy signal from LS channels
copy signal from HP channels
copy signal from C/Sub channels (ONLY
AVAILABLE ON SPDIF CHANNEL MATRIX)
011
C/Sub Channels
copy signal from Ls/Rs channels (ONLY
AVAILABLE ON SPDIF CHANNEL MATRIX)
100
101
Ls/Rs Channels
-
Reserved
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STV82x8
Table 16: Channel Matrix Source Selection (Continued)
Parameter
Coding (Bin)
Parameter Field Lebel
Function
110
111
-
-
Reserved
Reserved
DEMOD_DC_LEVEL
DC Level on Demod FM Mono Input
Address: AAh
Type: R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DEMOD_DC_LEVEL[7:0] (S)
Bit Name
Reset
Function
DEMOD_DC_LEVE (0000 Display the amount of the DC component in the signal comming from the FM mono channel. This
L[7:0] 0000) DC Level can be used to implement a Carrier Offset compensation.
12.14 Audio Processing
AV_DELAY_CONFIG
AV Delay Configuration
Address: ADh
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
DOLBY_DELA AV_DELAY_O
Y_ON
N
Bit Name
Reset
Function
Bits[7:2]
0000 00 Reserved
Must be set to 1 to use the Center, Left Srnd and Right Srnd delays for ProLogic decoder multi-
channel output.
DOLBY_DELAY_O
N
0
0
Note: This value must be updated when AV_DELAY_ON = 0..
AV_DELAY_ON
0: No AV delay
1: AV delay is active
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Register List
AV_DELAY_TIME_LS
AV Delay LS Configuration
Address: AEh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AV_DELAY_TIME_LS[7:0]
Bit Name
Reset
Function
Set the delay time for LS channel.
0000 0000:
0 ms
AV_DELAY_TIME_
LS[7:0]
0000 0000 0001:
0000 ...
0.66 ms
1011 0001:
116.82 ms (max)
Note: this value must be updated when AV_DELAY_ON = 0..
AV_DELAY_TIME_HP
AV Delay HP Configuration
Address: AFh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AV_DELAY_TIME_HP[7:0]
Bit Name
Reset
Function
AV_DELAY_TIME_
HP[7:0]
Set the delay time for HP channel.
0000 0000:
0 ms
0000 0000 0001:
0000 ...
0.66 ms
1011 0001:
116.82 ms (max)
Note: this value must be updated when AV_DELAY_ON = 0..
Note: The sum of AV_DELAY_TIME_LS and AV_DELAY_TIME_HP must not exceed:
• 177 (116.82 ms) if DOLBY_DELAY_ON = 0
• 100 (66.66 ms) if DOLBY_DELAY_ON = 1
PRO_LOGIC2_CONTROL
Dolby ProLogic 2 Mode Configuration
Address: B0h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PL2_LFE
PL2_OUTPUT_DOWNMIX[2:0]
PL2_MODES[2:0]
PL2_ACTIVE
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Bit Name
Reset
Function
0: Reset the LFE channel
1: Bypass the LFE channel
PL2_LFE
0
000:
001:
010:
011:
not applicable
not applicable
not applicable
3/0 output mode (L,R,C)
100: 2/1 output mode (L,R,Ls - phantom)
101: 3/1 output mode (L,R,C,Ls)
110: 2/2 output mode (L,R,Ls,Rs - phantom)
111: 3/2 output mode (L,R,C,Ls,Rs)
PL2_OUTPUT_DO
WNMIX[2:0]
000
000:
001:
010:
011:
Pro Logic 1 Emulation
Virtual
Music
100: Matrix
101: Custom
110: not applicable
111: not applicable
PL2_MODES[2:0]
PL2_ACTIVE
000
0
Movie (standard)
0: Dolby Prologic 2 is not active
1: Dolby Prologic 2 is active
PRO_LOGIC2_CONFIG
Dolby ProLogic 2 Configuration
Address: B1h
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PL2_RS_POL PL2_PANORA PL2_AUTOBA
0
PL2_SRND_FILTER[1:0]
ARITY
MA
LANCE
Bit Name
Reset
Function
Bits[7:6]
00
Reserved.
00: Off
PL2_SRND_FILTE
R[1:0]
01: Shelf
10: 7-kHz LP
11: not applicable
00
PL2_RS_POLARIT
Y
0: Rs polarity normal
1: Rs polarity inverted
0
0
0
0: Panorama Off
1: Panorama On
PL2_PANORAMA
PL2_AUTOBALAN
CE
0: Autobalance Off
1: Autobalance On
PRO_LOGIC2_DIMENSION
Dolby ProLogic 2 Dimension
Address: B2h
Type: R/W
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
0
Bit 2
Bit 1
Bit 0
PL2_C_WIDTH
PL2_DIMENSION
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Register List
Bit Name
Reset
Function
Bit 7
0
Reserved.
ProLogic 2 center width:
000:
001:
010:
011:
0, no spread
100: 54
101: 62
110: 69
PL2_C_WIDTH[2:0] 000
20
28
36
111: 90, phantom
Bit 3
0
Reserved.
ProLogic 2 dimension:
000:
001:
010:
011:
-3, most surround
-2
-1
100:
101:
1
2
PL2_DIMENSION [
2:0]
000
110: 3, most center
111: not used
0, neutral
PRO_LOGIC2_LEVEL
Dolby ProLogic 2 Input Level
Address: B3h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PL2_LEVEL
Bit Name
Reset
Function
Input Gain attenuation:
0000 0000:
0000 0001:
...
0 dB
-0.5 dB
0000000
0
PL2_LEVEL[7:0]
1111 1111:
-127.5 dB
NOISE_GENERATOR
Pink Noise Generator
Address: B4h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10_DB_ATTEN SRIGHT_NOIS
CENTER_NOI
SE
SLEFT_NOISE SUB_NOISE
RIGHT_NOISE LEFT_NOISE
NOISE_ON
UATE
E
Bit Name
Reset
Function
10_DB_ATTENUAT
E
0: noise is output with full range
1: noise is output with a 10dB attenuation
0
SRIGHT_NOISE
SLEFT_NOISE
SUB_NOISE
0
0
0
1: Generates noise on LS right surround output
1: Generates noise on LS left surround output
1: Generates noise on LS subwoofer output
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Register List
STV82x8
Bit Name
Reset
Function
CENTER_NOISE
RIGHT_NOISE
LEFT_NOISE
0
0
0
1: Generates noise on LS center output
1: Generates noise on LS right output
1: Generates noise on LS left output
0: Noise Generation not active
1: Noise Generation active
NOISE_ON
0
PCM_SRND_DELAY
Dolby Surround Delay
Address: B5h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DOLBY_DELAY_SRND[4:0]
Bit Name
Bits[7:5]
Reset
Function
000
Reserved.
DOLBY_DELAY_S 00000
RND[4:0]
Surround Channel Delay
Range: 0 to 30 (in ms)
Note: To use this feature, set the DOLBY_DELAY_ON bit to 1 in register AV_DELAY_CONFIG (ADh).
PCM_CENTER_DELAY Dolby Center Delay Register
Address: B6h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
DOLBY_DELAY_CENTER[3:0]
Bit Name
Bits[7:4]
Reset
Function
0000
Reserved.
DOLBY_DELAY_C 0000
ENTER[3:0]
Center Channel Delay
Range: 0 to 10 (in ms)
Note: To use this feature, set the DOLBY_DELAY_ON bit to 1 in register AV_DELAY_CONFIG (ADh).
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Register List
TRUSRND_CONTROL
SRS TruSurround Control
Address: B7h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DIALOG_CLA HEADPHONE
TRUSRND_INPUT_ MODE[3:0]
TRUSRND_BY TRUSRND_O
PASS
RITY_ON
_ON
N
Bit Name
Reset
Function
0: Dialog Clarity OFF
1: Dialog Clarity ON
DIALOG_CLARITY
_ON
0
Note: The Dialog Clarity Level is set in register 0xB8: TRUSRND_DC_ELEVATION
Process the sound espacialy for Headphone. This option must be selected only if the TruSurround
sound is redirected to the headphone output thanks to the HP channel matrix.
HEADPHONE_ON
0
0: Standard mode for Loudspeaker output
1: Headphone mode for Headphone output only
0000: Mono on Center channel
0001: Mono on Left channel
0010: L/R stereo (SRS mode)
0011: L/R/S (SRS mode, Prologic 1 Process)
0100: L/R/Ls/Rs (SRS mode)
TRUSRND_INPUT_
MODE[3:0]
0000 0101: L/R/C (TruSurround mode)
0110: L/R/C/S (TruSurround mode, Prologic 1 Process)
0111: L/R/C/Ls/Rs (TruSurround mode)
1000: Lt/Rt (TruSurround mode)
1001: L/R/C/Ls/Rs (SRS mode, BS Digital Broadcast)
1010: L/R/C/Ls/Rs (TruSurround, Prologic 2 Music mode)
Bypass the TruSurround effect by applying a simple donwmix on input channels.
TRUSRND_BYPAS
S
0
0
0: TruSurround mode
1: Bypass mode (downmix to 2 channels)
0: TruSurround OFF
1: TruSurround ON
TRUSRND_ON
TRUSRND_DC_ELEVATION
Set Dialog Clarity Level
Address: B8h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRUSRND_DC_ELEVATION[7:0]
Bit Name
Reset
Function
TRUSRND_DC_EL 0000
EVATION[7:0] 1100
Dialog Clarity Elevation:
0000 0000:
0000 0001:
...
0 dB
-0.5 dB
1111 1111:
-127.5 dB
101/157
Register List
STV82x8
TRUSRND_INPUT_GAIN
Input Gain for TruSurround
Address: B9h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRUSRND_INPUT_GAIN[7:0]
Bit Name
Reset
Function
TRUSRND_INPUT_ 0000
GAIN[7:0] 0000
Input Gain attenuation:
0000 0000:
0000 0001:
...
0 dB
-0.5 dB
1111 1111:
-127.5 dB
TRUBASS_LS_CONTROL
SRS TruBass for LS Configuration
Address: BAh
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
TRUBASS_LS
_ON
0
TRUBASS_LS_SIZE[2:0]
Bit Name
Reset
Function
Bits[7:3]
0000
Reserved.
TRUBASS_LS_SIZ
E[2:0]
000:
001:
010:
011:
LF response at 40 Hz
LF response at 60 Hz
LF response at 100 Hz
LF response at 150 Hz
100: LF response at 200 Hz
101: LF response at 250 Hz
110: LF response at 300 Hz
111: LF response at 400 Hz
011
0
TRUBASS_LS_ON
0: LS TruBass OFF
1: LS TruBass ON
TRUBASS_LS_LEVEL
SRS TruBass for LS Level
Address: BBh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRUBASS_LS_LEVEL[7:0]
102/157
STV82x8
Register List
Bit Name
Reset
Function
TRUBASS_LS_LEV 0000
Define the amount of SRS TruBass effect for LS outputs:
EL[7:0] 1001
0000 0000:
0000 0001:
...
0dB
-0.5dB
1111 1111:
-127.5dB
TRUBASS_HP_CONTROL
SRS TruBass for HP Configuration
Address: BCh
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRS_TSXT_G
AIN_ON
TRUBASS_HP
_ON
0
TRUBASS_HP_SIZE[2:0]
Bit Name
Reset
Function
SRS_TSXT_GAIN_ 0
ON
Apply the TruSurround Gain (register 0xB9) to the TruBass input block. This gain must be applied
only if the TruSurround signal have been redirected to the TruBass HP thanks to the HP Channel
Matrix.
0: TSXT input gain is not applied
1: TSXT input gain is applied. (this configuration must be used if the LS signal processed with
TSXT is redirected to the HP channel)
Bits[6:3]
000
Reserved.
TRUBASS_HP_SIZ
E[2:0]
000:
001:
010:
011:
LF response at 40 Hz
LF response at 60 Hz
LF response at 100 Hz
LF response at 150 Hz
100: LF response at 200 Hz
101: LF response at 250 Hz
110: LF response at 300 Hz
111: LF response at 400 Hz
011
0
TRUBASS_HP_ON
0: HP TruBass OFF
1: HP TruBass ON
TRUBASS_HP_LEVEL
SRS TruBass for HP Level
Address: BDh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRUBASS_HP_LEVEL[7:0]
Bit Name
Reset
Function
Define the amount of SRS TruBass effect for HP outputs:
TRUBASS_HP_LE 0000
VEL[7:0] 1001
0000 0000:
0000 0001:
...
0dB
-0.5dB
1111 1111:
-127.5dB
103/157
Register List
STV82x8
SVC_LS_CONTROL
Smart Volume Control for LS
Address: BEh
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
SVC_LS_INPUT[1:0]
SVC_LS_AMP SVC_LS_ON
Bit Name
Reset
Function
Bits[7:4]
0000
Reserved.
SVC_LS_INPUT[
1:0]
Select input for peak detection in multichannel mode:
00: Left/Right
01: Center
00
10: Left/Right/Center
11: Not Used
SVC_LS_AMP
SVC_LS_ON
1
0
0: 0 dB amplification in auto-mode
1: +6 dB amplification in auto-mode
0: Manual mode(simple prescaler)
1: Automatic mode
SVC_LS_TIME_TH
Smart Volume Control Parameters for LS
Address: BFh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SVC_LS_TIME[2:0]
SVC_LS_THRESHOLD[4:0]
Bit Name
Reset
Function
Time Constant for Amplification (6-dB gain step) in Automatic mode:
000:
001:
010:
011:
30 ms
200 ms
500 ms
1 s
100: 16 s
101: 32 s
110: 64 s
111: 128 s
SVC_LS_TIME[2:0] 100
SVC_LS_THRESH
OLD[4:0]
11000
See tables 8 and 9
Table 17: Gain (Threshold Field) Values in Manual mode
Manual Mode
Gain (dB)
00101
00100
00011
00010
+15.5
+12
+9.5
+6
104/157
STV82x8
Register List
Table 17: Gain (Threshold Field) Values in Manual mode (Continued)
Manual Mode
Gain (dB)
00001
00000
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
+3.5
0
-2.5
-6
-8.5
-12
-14.5
-18
-20.5
-24
-26.5
-30
Table 18: Threshold values in Automatic mode
Automatic Mode
Threshold (dB)
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
-2.5
-6
-8.5
-12
-14.5
-18
-20.5
-24
-26.5
-30
SVC_LS_GAIN
Make-up Gain for SVC LS
Address: C0h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SVC_LS_GAIN[5:0]
Bit Name
Reset
Function
Bits[7:6]
00
Reserved.
105/157
Register List
STV82x8
Bit Name
Reset
Function
Set “make-up” gain applied at SVC LS output:
000000:
000001:
+0 dB
+0.5 dB
SVC_LS_GAIN[5:0] 000000 ...
101110:
+23 dB
+23.5 dB
+24 dB
101111:
110000:
SVC_HP_CONTROL
Smart Volume Control for HP
Address: C1h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
SVC_HP_AMP SVC_HP_ON
Bit Name
Reset
Function
Bits[7:2]
0000 00 Reserved.
SVC_HP_AMP
1
0: 0 dB amplification in auto-mode
1: +6 dB amplification in auto-mode
SVC_HP_ON
0
0: Manual mode (simple prescaler)
1: Automatic mode
SVC_HP_TIME_TH
Smart Volume Control Parameters for HP
Address: C2h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SVC_HP_TIME[2:0]
SVC_HP_THRESHOLD[4:0]
Bit Name
Reset
Function
SVC_HP_TIME[2:0]
Time Constant for Amplification (6-dB gain step) in Automatic mode:
000:
001:
010:
011:
30 ms
200 ms
500 ms
1 s
100: 16 s
101: 32 s
110: 64 s
111: 128 s
100
SVC_HP_THRESH
OLD[4:0]
11000
See tables 8 and 9
106/157
STV82x8
Register List
SVC_HP_GAIN
Make-up Gain for SVC HP
Address: C3h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SVC_HP_GAIN[5:0]
Bit Name
Reset
Function
Bits[7:6]
00
Reserved.
Set “make-up” gain applied at SVC HP output:
000000:
000001:
+0 dB
+0.5 dB
SVC_HP_GAIN[5:0] 000000 ...
101110:
+23 dB
+23.5 dB
+24 dB
101111:
110000:
WIDESRND_CONTROL
ST Wide Surround Control
Address: C4h
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
Bit 1
Bit 0
WIDESRND_S WIDESRND_ WIDESRND_O
0
TEREO
MODE
N
Bit Name
Reset
Function
Bits[7:3]
00000
0
Reserved.
WIDESRND_STER
EO
ST Wide Surround Sound Stereo Mode
0: ST Wide Surround Sound in Mono mode (Default)
1: ST Wide Surround Sound in Stereo mode
WIDESRND_MODE 0
ST Wide Surround Sound Stereo Mode
0: Movie Mode
1: Music Lode
WIDESRND_ON
0
ST Wide Surround Sound Enable
0: ST Wide Surround Sound is disabled
1: ST Wide Surround Sound is enabled
WIDESRND_FREQ
ST Wide Surround Sound Frequency
Address: C5h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WIDESRND_BASS[1:0]
WIDESRND_MEDIUM[1:0]
WIDESRND_TREBLE[1:0]
107/157
Register List
STV82x8
Bit Name
Reset
00
Function
Bits[7:6]
Reserved.
WIDESRND_BASS[ 01
1:0]
Defines the bass frequency effect for ST Wide Surround Sound. Programmable values are listed in
Table 10.
WIDESRND_MEDI 01
UM[1:0]
Defines the medium frequency effect for ST Wide Surround Sound in Movie or Mono mode (no
effect in Music mode). Programmable values are listed in Table 10.
WIDESRND_TREB 01
LE[1:0]
Defines the treble frequency effect for ST Wide Surround Sound in Movie or Mono mode (no effect
in Music mode). Programmable values are listed in Table 10.
Table 19: Phase Shifter Center Frequencies
Phase Shifter Center Frequency
BASS_FREQ[1:0]
MEDIUM_FREQ[1:0] TREBLE_FREQ[1:0]
00
40 Hz
90 Hz
202 Hz
416 Hz
500 Hz
588 Hz
2 kHz
4 kHz
5 kHz
6 kHz
01 (Default)
10
11
120 Hz
160 Hz
WIDESRND_LEVEL
ST Wide Surround Gain
Address: C6h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WIDESRND_GAIN[7:0]
Bit Name
Reset
Function
WIDESRND_GAIN[ 10000000
7:0]
Defines the ST Wide Surround Sound component gain in linear scale.
Level (%)
Level (%)
1000 0000 (Default)
0111 1111
0111 1110
0111 1101
........
100%
99.2%
98.4%
97.6%
0000 0100
0000 0011
0000 0010
0000 0001
0000 0000
3.1%
2.3%
1.6%
0.8%
0%
OMNISURROUND_CONTROL
ST Omnisurround Configuration
Address: C7h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRND_PHASE
_INV
OMNISRND_O
N
ST_VOICE[1:0]
OMNISRND_INPUT_MODE[3:0]
108/157
STV82x8
Register List
Bit Name
Reset
Function
00: OFF
01: Low
10: Mid
11: High
ST_VOICE[1:0]
00
SRND_PHASE_INV
Invert Right Surround phase in 2_2 or 3_2 input mode:
0
0: Right Surround phase not inverted
1: Right Surround phase invertedl
OMNISRND_INPUT
_ MODE[3:0]
0000: Mono on center channel
0001: Mono on left channel
0101: L/R/C
0110: L/R/C/S
0000 0010: L/R stereo
0011: L/R/S
0111: L/R/C/Ls/Rs
1000: Lt/Rt (Passive matrix)
0100: L/R/Ls/Rs
0: OmniSurround OFF
1: OmniSurround ON
OMNISRND_ON
0
DYNAMIC_BASS_LS
ST Dynamic Bass for LS
Address: C8h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_DYN_BAS
S_ON
LS_BASS_LEVEL[4:0]
LS_BASS_FREQ[1:0]
Bit Name
Reset
Function
LS_BASS_LEVEL [
4:0]
ST Dynamic Bass output gain:
00000:
00001:
+0dB
+0.5dB
00000 ...
11101:
+14.5dB
+15dB
+15.5dB
11110:
11111:
LS_BASS_FREQ [
1:0]
00: 100-Hz Cut-Off frequency
01: 150-Hz Cut-Off frequency
10: 200-Hz Cut-Off frequency
11: 250-Hz Cut-Off frequency
00
0
LS_DYN_BASS_O
N
0: ST Dynamic Bass OFF
1: ST Dynamic Bass ON
DYNAMIC_BASS_HP
ST Dynamic Bass for HP
Address: C9h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HP_DYN_BAS
S_ON
HP_BASS_LEVEL[4:0]
HP_BASS_FREQ[1:0]
109/157
Register List
STV82x8
Bit Name
Reset
Function
HP_BASS_LEVEL[
4:0]
ST Dynamic Bass output gain:
00000:
00001:
...
+0dB
+0.5dB
00000
11101:
11110:
11111:
+14.5dB
+15dB
+15.5dB
HP_BASS_FREQ[
1:0]
00: 100-Hz Cut-Off frequency
01: 150-Hz Cut-Off frequency
10: 200-Hz Cut-Off frequency
11: 250-Hz Cut-Off frequency
00
0
HP_DYN_BASS_O
N
0: ST Dynamic Bass OFF
1: ST Dynamic Bass ON
BASS_ENHANCE_LS
ST Bass Enhancer for LS
Address: CAh
Type: R/W
Bit 7
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_BASS_EN
HANCE_HP_F
ILTER
LS_BASS_EN
HANCE_CUT
OFF
LS_BASS_EN
HANCE_ON
0
LS_BASS_ENHANCE_SCALE[2:0]
Bit Name
Reset
Function
Bits[7:6]
00
Reserved.
LS_BASS_ENHAN
CE_HP_FILTER
Add an High Pass Filter in order to reduce the lower bass content in the signal in order to reduce
the constraint on small speakers.
0
0: No High Pass Filter. To be used on wide band speakers
1: High Pass Filter. To be used on narrow band speakers.
LS_BASS_ENHAN
CE_SCALE[2:0]
Set the amount of bass generated by the processing:
000:
...
Light Bass Content
000
111:
Stong Bass Content
Define the corner frequency for the bass generation:
LS_BASS_ENHAN
CE_CUTOFF
0
0
0: Cuttoff Frequency = 80 Hz
1: Cutoff Frequency = 120 Hz
LS_DYN_BASS_O
N
0: ST Bass Enhancer OFF
1: ST Bass Enhancer ON
EQ_BT_CTRL
Loudspeakers Equalizer Control
Address: CCh
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
Bit 1
Bit 0
LS_EQ_BT_S
W
0
HP_BT_ON
LS_EQ_ON
110/157
STV82x8
Register List
Bit Name
Reset
Function
Bits[7:3]
00000
0
Reserved.
HP_BT_ON
Bass-Treble for HP Enable
0: Bass-Treble is disabled
1: Bass-Treble is enabled
LS_EQ_BT_SW
LS_EQ_ON
0
1
5-Band Equalizer or Bass-Teble for LS selection
0: 5-Band Equalizer is selected for Loudspeakers.
1: Bass-Treble is selected for Loudspeakers.
5-Band Equalizer/Bass-Treble for LS Enable
0: 5-Band Equalizer/Bass-Treble is disabled
1: 5-Band Equalizer/Bass-Treble is enabled
LS_EQ_BANDX
Loudspeakers Equalizer Gain for BandX
Address: CDh to D1h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EQ_BANDX[7:0]
Bit Name
EQ_BANDX[7:0]
Reset
Function
0000 BandX gain adjustment within a range from -12 dB to +12 dB in steps of 0.25 dB.
0000
Band1: 100 Hz, Band2: 330 Hz, Band3: 1 kHz, Band4: 3.3 kHz, Band5: 10 kHz.
Table 20: Loudspeakers Equalizer/Bass-Treble Gain Values (and Headphone Bass-Treble Gain Values)
Value
Gain G (dB)
00110000
00101111
+12
+11.75
+11.50
.....
00101110
................
00000000 (Default)
................
0
.....
10101110
-11.50
-11.75
-12
10101111
10110000
111/157
Register List
STV82x8
LS_BASS_GAIN
Loudspeakers Bass Gain Register
Address: D2h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_BASS[7:0]
Bit Name
Reset
Function
LS_BASS[7:0]
0000 Gain Tuning of Loudspeakers Bass Frequency
0000
Gain may be programmed within a range between +12 dB and -12 dB in steps of 0.25 dB.
Programmable values are listed in Table 11.
LS_TREBLE_GAIN
Loudspeakers Treble Gain Register
Address: D3h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_TREBLE
Bit Name
Reset
Function
LS_TREBLE[7:0]
0000 Gain Tuning of Loudspeakers Treble Frequency
0000
Gain may be programmed within a range between +12 dB and -12 dB in steps of 0.25 dB.
Programmable values are listed in Table 11.
HP_BASS_GAIN
Headphone Bass Gain
Address: D4h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HP_BASS[7:0]
Bit Name
Reset
Function
HP_BASS[7:0]
0000000 Gain Tuning of Headphone Bass Frequency
0
Gain may be programmed within a range between +12 dB and -12 dB in steps of 0.25 dB.
Programmable values are listed in Table 11.
112/157
STV82x8
Register List
HP_TREBLE_GAIN
Headphone Treble Gain
Address: D5h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HP_TREBLE
Bit Name
Reset
Function
HP_TREBLE[7:0]
0000 Gain Tuning of Headphone Treble Frequency
0000
Gain may be programmed within a range between +12 dB and -12 dB in steps of 0.25 dB.
Programmable values are listed in Table 11.
OUTPUT_BASS_MNGT
Bass Redirection
Address: D4h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BASS_MANA
GE_ON
DOLBY_PROL
OGIC
GAIN_SWITC
H
ST_LFE_ADD
SUB_ACTIVE
OCFG_NUM[2:0]
Bit Name
Reset
Function
BASS_MANAGE_O
N
0
0: BassManagement disabled
1: BassManagement enabled
ST_LFE_ADD
0
Add the signal comming from the LFE input (MULTI_I2S mode only) to the calculated Subwoofer
signal:
0: No LFE channel to add
1: Add LFE signal to the Subwoofer computed signal
DOLBY_PROLOGI
C
0
If the BassManagement is used with Dolby Prologic decoder, the surround channels must not be
added to generate the Subwoofer channel:
0: Standard configuration (Dolby Digital compliant), surround channels are used to generate the
Subwoofer channel.
1: Dolby Prologic configuration, surround channels are not used to generate the Subwoofer
channel.
SUB_ACTIVE
0
0
In some configurations the Subwoofer signal can be redirected to L/R channels if there is no
Subwoofer output:.
0: No Subwoofer output, the Sub signal is added to L/R channels
1: Subwoofer signal is outputed on Subwoofer output.
GAIN_SWITCH
Gain Switch available in some configurations:
0: Level Adjustment ON
1: Level Adjustment OFF
113/157
Register List
STV82x8
Bit Name
Reset
Function
OCFG_NUM[2:0]
000
Select Bass Management configuration:
000:
001:
010:
011:
100:
101:
110:
111:
Output Configuration 0
Output Configuration 1
Output Configuration 2
Output Configuration 3
Output Configuration 4 (Simplified Configuration)
Output Configuration 5 (Stereo Full Bandwith Speakers)
Output Configuration 6 (Stereo Narrow Bandwith Speakers)
Not Used
LS_LOUDNESS
Loudness Configuration for LS
Address: D7h
Type: R/W
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_LOUD_THRESHOLD[2:0]
LS_LOUD_GAIN_HR[2:0]
LS_LOUD_ON
Bit Name
Reset
Function
Bit 7
0
Reserved.
Define the volume threshold level since which loudness effect is applied:
LS_LOUD_THRES
HOLD[2:0]
000
010
0
000:
001:
010:
011:
0 dB
100: -24 dB
101: -32 dB
110: -36 dB
111: -42 dB
-6 dB
-12 dB
-18 dB
LS_LOUD_GAIN_H
R[2:0]
Define the amount of Treble added by loudness effect:
000:
001:
010:
011:
0 dB
3 dB
6 dB
9 dB
100: 12 dB
101: 15 dB
110: 18 dB
111: Not Used
LS_LOUD_ON
0: Loudness is not active on LS output
1: Loudness is active on LS output
HP_LOUDNESS
Loudness Configuration for HP
Address: D8h
Type: R/W
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HP_LOUD_THRESHOLD[2:0]
HP_LOUD_GAIN_HR[2:0]
HP_LOUD_ON
Bit Name
Reset
Function
Bit 7
0
Reserved.
114/157
STV82x8
Register List
Bit Name
Reset
Function
HP_LOUD_THRES
HOLD[2:0]
000
Define the volume threshold level since which loudness effect is applied :
000:
001:
010:
011:
0 dB
100: -24 dB
101: -32 dB
110: -36 dB
111: -42 dB
-6 dB
-12 dB
-18 dB
HP_LOUD_GAIN_H
R[2:0]
010
Define the amount of Treble added by loudness effect:
000:
001:
010:
011:
0 dB
3 dB
6 dB
9 dB
100: 12 dB
101: 15 dB
110: 18 dB
111: not used
HP_LOUD_ON
0
0: Loudness is not active on HP output
1: Loudness is active on HP output
VOLUME_MODES
Set the Volume Modes
Address: D9h
Type: R/W
Bit 7
Bit 6
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCART2_
VOLUME_
MODE
SCART1_
VOLUME_
MODE
HP_
VOLUME_
MODE
SRND_
VOLUME_
MODE
LS_
VOLUME_
MODE
ANTICLIP_HP ANTICLIP_LS
_VOL_CLAMP _VOL_CLAMP
Bit Name
Reset
Function
ANTICLIP_HP_VOL
_CLAMP
1
The output level is clamped depending on the HP Bass-Treble value to avoid any possible signal
clipping on HP output.
0: Volume clamp on HP output is not active
1: Volume clamp on HP output is active
ANTICLIP_LS_VOL
_CLAMP
1
The output level is clamped depending on the LS Equalizer or LS Bass-Treble value to avoid any
possible signal clipping on LS output.
0: Volume clamp on LS output is not active
1: Volume clamp on LS output is active
Bits[5]
0
1
Reserved.
SCART2_VOLUME
_MODE
Volume mode for SCART2 output:
0: Independant
1: Differential
SCART1_VOLUME
_MODE
1
1
1
Volume mode for SCART1 output:
0: Independant
1: Differential
HP_VOLUME_
MODE
Volume mode for Headphone output:
0: Independant
1: Differential
SRND_VOLUME_
MODE
Volume mode for Surround output:
0: Independant
1: Differential
115/157
Register List
STV82x8
Bit Name
Reset
Function
1
Volume mode for LS output:
LS_VOLUME_
MODE
0: Independant
1: Differential
LS_L_VOLUME_MSB
Loudspeaker Left Volume MSB
Address: DAh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_L_VOLUME_MSB[7:0]
Bit Name
Reset
Function
8 MSBs of the 10-bit Left Loudspeaker Volume
LS_L_VOLUME_M
SB[7:0]
1001
1000
LS_L_VOLUME_LSB
Loudspeaker Left Volume LSB
Address: DBh
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
LS_L_VOLUME_LSB[1:0]
Bit Name
Reset
Function
Bits[7:2]
000000 Reserved.
00 2 LSBs of the 10-bit Left Loudspeaker Volume
LS_L_VOLUME_LS
B[1:0]
LS_R_VOLUME_MSB
Loudspeaker Right Volume MSB
Address: DCh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_R_VOLUME_MSB[7:0]
Bit Name
Reset
Function
8 MSBs of the 10-bit Right Loudspeaker Volume
LS_R_VOLUME_M
SB[7:0]
0000
0000
116/157
STV82x8
Register List
LS_R_VOLUME_LSB
Loudspeaker Right Volume LSB
Address: DDh
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
LS_R_VOLUME_LSB[1:0]
Bit Name
Reset
Function
Bits[7:2]
000000 Reserved.
00 2 LSBs of the 10-bit Right Loudspeaker Volume
LS_R_VOLUME_L
SB[1:0]
LS_C_VOLUME_MSB
Loudspeaker Center Volume MSB
Address: DEh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_C_VOLUME_MSB[7:0]
Bit Name
Reset
Function
8 MSBs of the 10-bit Center Loudspeaker Volume
LS_C_VOLUME_M
SB[7:0]
1001
1000
LS_C_VOLUME_LSB
Loudspeaker Center Volume LSB
Address: DFh
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
LS_C_VOLUME_LSB[1:0]
Bit Name
Reset
Function
Bits[7:2]
0000 00 Reserved.
00 2 LSBs of the 10-bit Center Loudspeaker Volume
LS_C_VOLUME_L
SB[1:0]
117/157
Register List
STV82x8
LS_SUB_VOLUME_MSB
Loudspeaker Subwoofer Volume MSB
Address: E0h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_SUB_VOLUME_MSB[7:0]
Bit Name
Reset
Function
8 MSBs of the 10-bit Subwoofer Loudspeaker Volume
LS_SUB_VOLUME
_MSB[7:0]
1001
1000
LS_SUB_VOLUME_LSB
Loudspeaker Subwoofer Volume LSB
Address: E1h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
LS_SUB_VOLUME_LSB[1:0]
Bit Name
Reset
Function
Bits[7:2]
000000 Reserved.
00
LS_SUB_VOLUME
_LSB[1:0]
2 LSBs of the 10-bit Subwoofer Loudspeaker Volume
LS_SL_VOLUME_MSB
Loudspeaker Left Surround Volume MSB
Address: E2h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_SL_VOLUME_MSB[7:0]
Bit Name
Reset
Function
8 MSBs of the 10-bit Left Surround Loudspeaker Volume
LS_SL_VOLUME_
MSB[7:0]
1001
1000
118/157
STV82x8
Register List
LS_SL_VOLUME_LSB
Loudspeaker Surround Left Volume LSB
Address: E3h
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
0
LS_SL_VOLUME_LSB[1:0]
Bit Name
Reset
Function
Bits[7:2]
000000 Reserved.
00 2 LSBs of the 10-bit Left Surround Loudspeaker Volume
LS_SL_VOLUME_L
SB[1:0]
LS_SR_VOLUME_MSB
Louspeaker Surround Right Volume MSB
Address: E4h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_SR_VOLUME_MSB[7:0]
Bit Name
Reset
Function
8 MSBs of the 10-bit Right Surround Loudspeaker Volume
LS_SR_VOLUME_
MSB[7:0]
0000
0000
LS_SR_VOLUME_LSB
Loudspeaker Surround Right Volume LSB
Address: E5h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
LS_SR_VOLUME_LSB[1:0]
Bit Name
Reset
Function
Bits[7:2]
000000 Reserved.
00
LS_SR_VOLUME_
LSB[1:0]
2 LSBs of the 10-bit Right Surround Loudspeaker Volume
119/157
Register List
STV82x8
LS_MASTER_VOLUME_MSB
Loudspeaker Master Volume MSB
Address: E6h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_MASTER_VOLUME_MSB[7:0]
Bit Name
Reset
Function
8 MSBs of the 10-bit Master Loudspeaker Volume
LS_MASTER_
VOLUME_MSB[7:0]
1110
1000
LS_MASTER_VOLUME_LSB
Loudspeaker Master Volume LSB
Address: E7h
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
LS_MASTER_VOLUME_LSB[
1:0]
0
Bit Name
Reset
Function
Bits[7:2]
000000 Reserved.
00
LS_MASTER_VOL
UME_LSB[1:0]
2 LSBs of the 10-bit Master Loudspeaker Volume
HP_L_VOLUME_MSB
Headphone Left Volume MSB
Address: E8h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HP_L_VOLUME_MSB[7:0]
Bit Name
Reset
Function
8 MSBs of the 10-bit Left Headphone Volume
HP_L_VOLUME_M
SB[7:0]
1001
1000
120/157
STV82x8
Register List
HP_L_VOLUME_LSB
Headphone Left Volume LSB
Address: E9h
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
0
HP_L_VOLUME_LSB[1:0]
Bit Name
Reset
Function
Bits[7:2]
000000 Reserved.
00 2 LSBs of the 10-bit Left Headphone Volume
HP_L_VOLUME_L
SB[1:0]
HP_R_VOLUME_MSB
Headphone Right Volume MSB
Address: EAh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HP_R_VOLUME_MSB[7:0]
Bit Name
Reset
Function
8 MSBs of the 10-bit Right Headphone Volume
HP_R_VOLUME_
MSB[7:0]
0000000
0
HP_R_VOLUME_LSB
Headphone Right Volume LSB
Address: EBh
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
HP_R_VOLUME_LSB[1:0]
Bit Name
Reset
Function
Bits[7:2]
000000 Reserved.
00
HP_R_VOLUME_L
SB[1:0]
2 LSBs of the 10-bit Right Headphone Volume
121/157
Register List
STV82x8
AUX_VOLUME_INDEX
Select the AUX to apply Volume
Address: ECh
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
AUX_VOLUME_SELECT[1:0]
Bit Name
Reset
Function
Bits[7:2]
000000 Reserved.
AUX_VOLUME_SE
LECT[1:0]
00
Select the output on which the AUX_VOLUME values will be applied:
00: No volume applied (mandatory step to change selection from 01 to 10)
01: Volume applied to SCART1 output
10: Volume applied to SCART2 output
11: Not used
AUX_L_VOLUME_MSB
Auxiliary Left Volume MSB
Address: EDh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AUX_L_VOLUME_MSB[7:0]
Bit Name
Reset
Function
AUX_L_VOLUME_
MSB[7:0]
1001
1000
8 MSBs of the 10-bit Left Auxiliary Volume
AUX_L_VOLUME_LSB
Auxiliary Left Volume LSB
Address: EEh
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
AUX_L_VOLUME_LSB[1:0]
Bit Name
Reset
Function
Bits[7:2]
000000 Reserved.
AUX_L_VOLUME_L
SB[1:0]
00
2 LSBs of the 10-bit Left Auxiliary Volume
122/157
STV82x8
Register List
AUX_R_VOLUME_MSB
Auxiliary Right Volume MSB
Address: EFh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AUX_R_VOLUME_MSB[7:0]
Bit Name
Reset
Function
8 MSBs of the 10-bit Right Auxiliary Volume
AUX_R_VOLUME_
MSB[7:0]
0000
0000
AUX_R_VOLUME_LSB
Auxiliary Right Volume LSB
Address: F0h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
AUX_R_VOLUME_LSB[1:0]
Bit Name
Reset
Function
Bits[7:2]
000000 Reserved.
00 2 LSBs of the 10-bit Right Auxiliary Volume
AUX_R_VOLUME_
LSB[1:0]
12.15 Mute
MUTE_SOFTWARE
Soft Mute Output by DSP
Address: F1h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPDIF_D_MUT SCART2_D_M SCART1_D_M SRND_D_MUT
HP_D_MUTE
SUB_D_MUTE C_D_MUTE
LS_D_MUTE
E
UTE
UTE
E
Bit Name
Reset
Function
1
Digital Soft Mute for HP output:
HP_D_MUTE
0: Soft Mute not active
1: Soft Mute active
1
Digital Soft Mute for SPDIF output:
SPDIF_D_MUTE
0: Soft Mute not active
1: Soft Mute active
123/157
Register List
STV82x8
Bit Name
Reset
Function
1
Digital Soft Mute for SCART2 output:
SCART2_D_MUTE
0: Soft Mute not active
1: Soft Mute active
1
1
1
1
1
Digital Soft Mute for SCART1 output:
SCART1_D_MUTE
SRND_D_MUTE
SUB_D_MUTE
C_D_MUTE
0: Soft Mute not active
1: Soft Mute active
Digital Soft Mute for SURROUND output:
0: Soft Mute not active
1: Soft Mute active
Digital Soft Mute for SUBWOOFER output:
0: Soft Mute not active
1: Soft Mute active
Digital Soft Mute for CENTER output:
0: Soft Mute not active
1: Soft Mute active
Digital Soft Mute for LOUDSPEAKER output:
LS_D_MUTE
0: Soft Mute not active
1: Soft Mute active
12.16 Beeper
BEEPER_ON
Set Beeper On
Address: F2h
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
Bit 1
Bit 0
BEEPER_SOUND_SELECT[
1:0]
0
BEEPER_ON
Bit Name
Reset
Function
Bits[7:3]
00000 Reserved.
00
Select the kind of sound generated by the beeper when BEEPER_ON is set to 1:
00: Square Wave Signal. Frequency and Decay can be set in Register 0xf4.
01: Wood Block Natural Sound
10: Clic Natural Sound
BEEPER_SOUND_
SELECT[1:0]
11: Bleep Natural Sound.
0
Control Beeper Sound Start/Stop:
BEEPER_ON
0: Start Beeper
1: Stop Beeper
Note: if BEEPER_SOUND_SELECT = 0 and BEEPER_CONTINUOUS(reg 0xF3) is set to 1, the
BEEPER_ON needs to be set to 0 to stop the beeper sound ; otherwise, the beeper is stopped
automaticaly.
124/157
STV82x8
Register List
On beeper STOP, the register 0xF2 is reset to 0. Take care to set bit[2:1] on each BEEPER_ON
action.
BEEPER_MODE
Beeper Control
Address: F3h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BEEPER_CO
NTINUOUS
BEEPER_DECAY[2:0]
BEEPER_DURATION[1:0]
BEEPER_PATH
Bit Name
Reset
Function
Control the decay of the envelope of the Beeper sound:
BEEPER_DECAY [
2:0]
000:
...
Short Decay (sounds dry)
000
111:
Very Long Decay (sounds wet)
BEEPER_DURATIO
N [1:0]
Define Beeper Duration when BEEPER_CONTINUOUS is set to 0:
00: 0.1 sec.
01: 0.25 sec.
10: 0.5 sec.
11: 1 sec.
00
0
BEEPER_CONTIN
UOUS
Set Beeper Pulse Mode
0: Pulse mode selected, the BEEPER_ON is automaticaly reset to 0.
1: Continuous mode selected, the BEEPER_ON must be set to 0 to stop the beeper sound.
BEEPER_PATH [
1:0]
Set the output channels when beeper is active
00: no channels.
01: Loudspeakers only.
11
10: Headphone only.
11: Loudspeakers and Headphone selected.
BEEPER_FREQ_VOL
Beeper Frequency and Volume Settings
Address: F4h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BEEP_FREQ[2:0]
BEEP_VOL[4:0]
Bit Name
Reset
011
Function
Defines the frequency of the beeper tone from 62.5 Hz to 8 kHz in octaves
BEEP_FREQ[2:0]
000:
001:
010:
011:
62.5 Hz
125 Hz
250 Hz
500 Hz (Default)
100: 1 kHz
101: 2 kHz
110: 4 kHz
111: 8 kHz
125/157
Register List
STV82x8
Bit Name
Reset
Function
BEEP_VOL[4:0]
10000
Defines the Beeper volume from 0 to -93 dB in steps of 3 dB.
11111: 0 dB (1 VRMS
)
...
11110: -3 dB
11101: -6 dB
...
00011: -84 dB
00010: -87 dB
00001: -90 dB
00000: -93 dB
10000: -48 dB (Default)
12.17 SPDIF Output Configuration
SPDIF_OUT_CHANNEL_STATUS
Address: F5h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
Bit 1
Bit 0
SPDIF_COPY SPDIF_NO_PC SPDIF_CONS
RIGHT
M
UMER_PRO
Bit Name
Reset
Function
Bits[7:3]
00000 Reserved.
SPDIF_COPYRIGH
T
0
0
0
0: Copyright
1: No Copyright
0: PCM Format
1: No PCM Format
SPDIF_NO_PCM
SPDIF_CONSUME
R_PRO
0: Consumer Format
1: Professional Format
12.18 Headphone Configuration
HEADPHONE_CONFIG
Headphone Configuration
Address: F6h
Type: R/W
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
KARAOKE_MI
X
HP_DET_ACTI HP_DETECTE
SCART2_OUT_SELECT[1:0]
HP_FORCE HP_LS_MUTE
VE
D
Bit Name
Reset
Function
Bits [7]
0
Reserved.
When set, mix the HP channel signal with the LS channel signal. The mixed signal is output on the
LS channel.
KARAOKE_MIX
126/157
0
STV82x8
Register List
Bit Name
Reset
Function
Select SCART2 output:
00: SCART2 not output
01: SCART2 signal output on C/Sub DAC
10: SCART2 signal output on Srnd/HP DAC
11: not used
SCART2_OUT_SE
LECT[1:0]
00
1: force to output the HP signal (bypass surround)
HP_FORCE
0
0
Note: when HP is forced, IRQ5 and HP/Srnd DAC automatic mute are not active.
0: when HP is detected and active, LS are not muted
1: when HP is detected and active, LS are muted
HP_LS_MUTE
0: HP detection is not active
HP_DET_ACTIVE
HP_DETECTED
1
0
1: HP detection is active, when HP detected, Surround signal is bypassed and HP signal is
outputed on HP
1: When a signal is detected on HP_DET pin
12.19 DAC Control
DAC_CONTROL
DAC Control Register
Address: F7h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DAC_SCART_ DAC_SHP_MU DAC_CSUB_M DAC_LSLR_M
SPDIF_MUX
POWER_UP
MUTE TE UTE UTE
Bit Name
Reset
Function
Bits [7:6]
00
Reserved.
Redirect external or internal source i2s to i2s output :
SPDIF_MUX
0
1
1
1
0: Internal I²S
1: External I²S
SCART Left/Right Analog Soft Mute
DAC_SCART_MUT
E
0: Soft Mute not active
1: Soft Mute active
Surround/HP Left/Right Analog Soft Mute
DAC_SHP_MUTE
DAC_CSUB_MUTE
0: Soft Mute not active
1: Soft Mute active
Center/Subwoofer Analog Soft Mute
0: Soft Mute not active
1: Soft Mute active
LS Left/Right Analog Soft Mute
DAC_LSLR_MUTE
POWER_UP
1
1
0: Soft Mute not active
1: Soft Mute active
0: DACs Power OFF
1: Power ON
127/157
Register List
STV82x8
DAC_SW_CHANNELS
DAC SW Channel Register
Address: F8h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C_SUB_SW
SUR_HP_SW
SCART_SW
SPDIF_SW
Bit Name
Reset
Function
Center/Sub DAC:
C_SUB_SW
00
00: Left/Right channels inverted
11: Left/Right channels non inverted
Surround/HP DAC:
SUR_HP_SW
SCART_SW
SPDIF_SW
00
00
00
00: Left/Right channels inverted
11: Left/Right channels non inverted
SCART DAC:
00: Left/Right channels inverted
11: Left/Right channels non inverted
SPDIF:
00: Left/Right channels inverted
11: Left/Right channels non inverted
SPDIF_SW_CHANNELS
SPDIF SW Channel Register
Address: F9h
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
DELAY_SW
LS_L_R_SW
Bit Name
Reset
Function
Bits [7:4]
0000
00
Reserved.
Delay output:
DELAY_SW
00: Left/Right channels inverted
11: Left/Right channels non inverted
00
Loudspeaker L/R output:
LS_L_R_SW
00: Left/Right channels inverted
11: Left/Right channels non inverted
128/157
STV82x8
Register List
12.20 AutoStandard Coefficients Settings
AUTOSTD_COEFF_CTRL
Autostd Control Register Coefficients
Address: FBh
Type: R/W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
AUTOSTD_COEFF_CTRL[1:0]
Bit Name
Reset
Function
Bits [7:2]
000000 Reserved.
AUTOSTD_COEFF 01
_CTRL[1:0]
Control the Demod filter coeff table settings
01: init Coeffs to ROM values
10: Update Coeffs with I2C value
AUTOSTD_COEFF_INDEX_MSB
Address: FCh
Type: R/W
Bit 7
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
AUTOSTD_CO
EFF_INDEX_
MSB
0
Bit Name
Reset
Function
Bits [7:2]
0000000 Reserved.
FIR Coefficients table index (MSB)
AUTOSTD_COEFF
_INDEX_MSB
0
AUTOSTD_COEFF_INDEX_LSB
Address: FDh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AUTOSTD_COEFF_INDEX_LSB[7:0]
Bit Name
Reset
Function
AUTOSTD_COEFF
_INDEX_LSB[7:0]
0000
0000
FIR Coefficients table index (LSB)
129/157
Register List
STV82x8
AUTOSTD_COEFF_VALUE
Address: FEh
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AUTOSTD_COEFF_VALUE[7:0]
Bit Name
Reset
Function
AUTOSTD_COEFF
_VALUE[7:0]
0000
0000
FIR Coefficients table value to update
130/157
STV82x8
Pin Descriptions
13 Pin Descriptions
13.1 TQFP 80-pin Package
●
●
●
●
●
●
●
AP
DP
I
= Analog Power
= Digital Power
= Input
O
= Output
OD
B
= Open-Drain
= Bi-Directional
= Analog
A
Table 21: TQFP80 Pin Description (Sheet 1 of 4)
Pin
No.
STV82x8
Pin Name
Type
(STV82x8)
Function for STV82x8
(Function for STV82x6 in italic characters)
STV82x6
Pin Name
1
2
3
4
5
6
7
8
9
SC1_OUT_L
A
A
SCART1 Audio Output Left
AO1L
SC1_OUT_R
VCC_H
SCART1 Audio Output Right
AO1R
AP
AP
A
8V Power for Audio I/O & ESD
High Current Ground for Audio Outputs
SCART3 Audio Output Left
Not connected
Connected to Ground
Not connected
Not connected
VDDC
GND_H
SC3_OUT_L
SC3_OUT_R
VCC33_SC
GND33_SC
SC1_IN_L
A
SCART3 Audio Output Right
AP
AP
A
3.3V Power for Audio Buffers & DAC / ADC
Ground for Audio Buffers & DAC / ADC
SCART1 Audio Input Left
GNDC
AI1L
10 SC1_IN_R
A
SCART1 Audio Input Right
AI1R
Audio Bias Voltage Decoupling 1.55V
(Switched VREF decoupling pin for Audio Converters
11 VREFA
A
VMC1
(VMCP))
NC (GND_SA in
STV82x7)
12
AP
A
Connected to Ground
Bandgap Voltage Reference Decoupling 1.2V
(VREF decoupling pin for Audio Converters (VMC))
13 VBG
VMC2
14 SC2_IN_L
15 SC2_IN_R
A
A
SCART 2 Audio Input Left
SCART 2 Audio Input Right
AI2L
AI2R
3.3V Power for Audio DACs
(3.3V Power Supply for Audio Buffers and SCART)
16 VCC33_LS
17 GND33_LS
AP
AP
VDDA
Ground for Audio DACs
(Ground for Audio Buffers and SCART)
GNDAH
18 SC2_OUT_L
19 SC2_OUT_R
A
A
SCART 2 Audio Output Left
SCART 2 Audio Output Right
AO2L
AO2R
GND_SA (VCC_NISO
in STV82x7)
20
AP
Ground for DACs
VDDH
131/157
Pin Descriptions
STV82x8
Table 21: TQFP80 Pin Description (Sheet 2 of 4)
Pin
No.
STV82x8
Pin Name
Type
(STV82x8)
Function for STV82x8
(Function for STV82x6 in italic characters)
STV82x6
Pin Name
21 VSS33_CONV
22 VDD33_CONV
AP
AP
Ground for DAC 1.8 to 3.3V Converters
Connected to Ground
3.3V Power for DAC 1.8 to 3.3V Converters
(Voltage Reference for Audio buffers)
VREFA
23 SC3_IN_L
24 SC3_IN_R
25 SCL_FLT
A
A
A
SCART 3 Audio Input Left
SCART 3 Audio Input Right
SCART Filtering Left
AI3L
AI3R
Not connected
SCART Filtering Right
(Bandgap Voltage Source Decoupling)
26 SCR_FLT
A
BGAP
27 LS_C
A
A
A
A
A
A
Center Output
Not connected
LSL
28 LS_L
Left Loudspeaker Output
29 LS_R
Right Loudspeaker Output
LSR
30 LS_SUB
31 HP_LSS_L
32 HP_LSS_R
Subwoofer Output
SW
Left Headphone Output or Left Surround Output
Right Headphone Output or Right Surround Output
HPL
HPR
Ground for Digital part of the DAC/ADC
(Substrate Analog/Digital Shield)
33 VSS18_CONV
DP
GNDSA
34 VDD18_CONV
35 HP_DET
36 ADR_SEL
37 VSS18
38 VDD18
39 SCL
DP
I
1.8V Power for Digital part of the DAC/ADC
Headphone Detection
Not connected
HPD
I
Hardware Address selection for I²C Bus
Ground for Digital part
ADR
DP
DP
OD
OD
DP
Connected to Ground
Not connected
SCL
1.8V Power for Digital part
I²C Clock Input
40 SDA
I²C Data I/O
SDA
41 VSS18
Ground for Digital part
Connected to Ground
1.8V Power for Digital part
(5V Power Regulator Control)
42 VDD18
43 RST_N
44 S/PDIF_IN
DP
REG
I
I
Main Reset Input
RESET
SYSCK
Serial Audio Data Input
(System Clock output)
Serial Audio Data Output
(I²S Master Clock output)
45 S/PDIF_OUT
O
MCK
46 VDD33_IO1
47 VSS33_IO1
48 CK_TST_CTRL
49 VSS18
DP
DP
D
3.3V power for Digital IO
Ground for Digital IO
VDD1
GND1
To be Grounded
Not connected
GNDSP
DP
DP
I
Ground for Digital part
1.8V Power for Digital part
Clock Input Format Selection
50 VDD18
Not connected
Not connected
51 CLK_SEL
132/157
STV82x8
Pin Descriptions
Table 21: TQFP80 Pin Description (Sheet 3 of 4)
Pin
No.
STV82x8
Pin Name
Type
(STV82x8)
Function for STV82x8
(Function for STV82x6 in italic characters)
STV82x6
Pin Name
Crystal Oscillator Input or Differential Input Positive
(Crystal Oscillator Input)
52 XTALIN_CLKXTP
53 XTALOUT_CLKXTM
54 VCC18_CLK1
I
XTI
Crystal Oscillator Output or Differential Input Negative
(Crystal Oscillator Output)
O
XTO
VDDP
1.8V Power for Clock PLL Analog & Crystal Oscillator 1/2
(3.3V Power supply for Analog PLL Clock)
AP
55 GND18_CLK1
56 GND18_CLK2
AP
AP
Ground for Clock PLL Analog & Crystal Oscillator 1/2
Ground for Clock PLL Digital 1/2
GNDP
GND2
1.8V Power for Clock PLL Digital 1/2
(3.3V Power supply for Digital core, DSPs & IO Cells)
57 VCC18_CLK2
DP
VDD2
58 VSS33_IO2
59 VDD33_IO2
60 I2S_PCM_CLK
DP
DP
I/O
Ground for Digital IO
Connected to Ground
Not connected
3.3V power for Digital IO
I²S Master Clock Input/Output Channel 0, 1 & 2
Not connected
I²S Serial Clock Input/Output Channel 0, 1& 2 (I²S bus
data output)
61 I2S_SCLK
62 I2S_LR_CLK
63 I2S_DATA0
64 I2S_DATA1
65 I2S_DATA2
I/O
I/O
I/O
I
SDO
ST/SDI
WS
I²S Word Select Input/Output Channel 0 , 1 & 2
(Stereo Detection output / I²S Bus Data input)
I²S Data Input/Output Stereo Channel 0
(I²S Bus Word Select output)
I²S Data Input Stereo Channel 1
(I²S Bus Clock output)
SCK
I²S Data Input Stereo Channel 2
(Bus Expander Output 1)
I
BUS1
66 VDD18
67 VSS18
DP
DP
1.8V Power for Digital Core & I/O Cells Pin
Ground for Digital Core & I/O Cells Pin
Not connected
Connected to Ground
Bus Expander Function
(Bus Expander Output 2)
68 BUS_EXP
O
BUS0
69 IRQ
O
AP
DP
DP
A
Interrupt Request to Microprocessor
Ground Substrate Connection
VDD 1.8V for ADC (Digital Part)
Ground to Complement 1.8V VDD for ADC
Sound IF input
IRQ
70 GND_PSUB
71 VDD18_ADC
72 VSS18_ADC
73 SIF_P
Connected to Ground
Not connected
Connected to Ground
SIF
ADC VTOP Decoupling pin
74 SIF_N
A
VTOP
Polarization for the IF block
(Voltage Reference for AGC Decoupling pin)
75 GNDPW_IF
AP
VREFIF
76 VCC18_IF
77 GND18_IF
78 MONO_IN
79 SC4_IN_L
AP
AP
A
1.8V Power for IF AGC & ADC
Ground for IF AGC & ADC
Mono Input (for AM Mono)
SCART4 Audio Input Left
VDDIF
GNDIF
MONOIN
Not connected
A
133/157
Pin Descriptions
STV82x8
Table 21: TQFP80 Pin Description (Sheet 4 of 4)
Pin
No.
STV82x8
Pin Name
Type
(STV82x8)
Function for STV82x8
(Function for STV82x6 in italic characters)
STV82x6
Pin Name
80 SC4_IN_R
A
SCART4 Audio Input Right
Not connected
13.2 TQFP 100-pin Package
●
●
●
●
●
●
●
AP
DP
I
= Analog Power
= Digital Power
= Input
O
= Output
OD
B
= Open-Drain
= Bi-Directional
= Analog
A
Table 22: TQFP100 Pin Description (Sheet 1 of 4)
Pin
No.
STV82x8
Pin Name
Type
(STV82x8)
Function for STV82x8
SCART1 Audio Output Left
1
2
3
4
5
6
7
8
9
SC1_OUT_L
A
A
SC1_OUT_R
VCC_H
SCART1 Audio Output Right
8V Power for Audio I/O & ESD
High Current Ground for Audio Outputs
SCART3 Audio Output Left
AP
AP
A
GND_H
SC3_OUT_L
SC3_OUT_R
VCC33_SC
GND33_SC
SC1_IN_L
A
SCART3 Audio Output Right
3.3V Power for Audio Buffers & DAC / ADC
Ground for Audio Buffers & DAC / ADC
SCART1 Audio Input Left
AP
AP
A
10 SC1_IN_R
11 VREFA
A
SCART1 Audio Input Right
A
Audio Bias Voltage Decoupling 1.55V
Bandgap Voltage Reference Decoupling 1.2V
SCART 2 Audio Input Left
12 VBG
A
13 SC2_IN_L
14 SC2_IN_R
15 VCC33_LS
16 GND33_LS
17 SC2_OUT_L
18 SC2_OUT_R
19 SC5_IN_L
20 SC5_IN_R
21 NC
A
A
SCART 2 Audio Input Right
AP
AP
A
3.3V Power for Audio DACs
Ground for Audio DACs
SCART 2 Audio Output Left
A
SCART 2 Audio Output Right
SCART 5 Audio Input Left
A
A
SCART 5 Audio Input Right
134/157
STV82x8
Pin Descriptions
Table 22: TQFP100 Pin Description (Sheet 2 of 4)
Pin
No.
STV82x8
Pin Name
Type
(STV82x8)
Function for STV82x8
22 NC
23 GND_SA
24 NC
AP
Ground for DACs
25 NC
26 VSS33_CONV
27 VDD33_CONV
28 SC3_IN_L
29 SC3_IN_R
30 SCL_FLT
31 SCR_FLT
32 LS_C
AP
AP
A
Ground for DAC 1.8 to 3.3V Converters
3.3V Power for DAC 1.8 to 3.3V Converters
SCART 3 Audio Input Left
SCART 3 Audio Input Right
SCART Filtering Left
A
A
A
SCART Filtering Right
A
Center Output
33 NC
34 LS_L
A
A
A
A
A
Left Loudspeaker Output
35 NC
36 LS_R
Right Loudspeaker Output
37 NC
38 LS_SUB
39 NC
Subwoofer Output
40 HP_LSS_L
41 NC
Left Headphone Output or Left Surround Output
42 HP_LSS_R
43 NC
Right Headphone Output or Right Surround Output
44 NC
45 VSS18_CONV
46 VDD18_CONV
47 HP_DET
48 ADR_SEL
49 VSS18
50 VDD18
51 SCL
DP
DP
I
Ground for Digital part of the DAC/ADC
1.8V Power for Digital part of the DAC/ADC
Headphone Detection
I
Hardware Address selection for I²C Bus
Ground for Digital part
DP
DP
OD
OD
I
1.8V Power for Digital part
I²C Clock Input
52 SDA
I²C Data I/O
53 RST_N
54 I2SD_DATA
55 I2SO_DATA1
Main Reset Input
I
I²S Data Delay Input Stereo Channel
I²S Data Output Stereo Channel O_1
O
135/157
Pin Descriptions
STV82x8
Table 22: TQFP100 Pin Description (Sheet 3 of 4)
Pin
No.
STV82x8
Pin Name
Type
(STV82x8)
Function for STV82x8
56 I2SO_LR_CLK
57 I2SO_SCLK
58 I2SO_DATAO
59 S/PDIF_IN
60 S/PDIF_OUT
61 VDD33_IO1
62 VSS33_IO1
63 CK_TST_CTRL
64 VSS18
O
O
I²S Word Select Output Channel O_0 & O_1
I²S Serial Clock Output Channel O_0 & O_1
I²S Data Output Stereo Channel O_0
Serial Audio Data Input
O
I
O
Serial Audio Data Output
DP
DP
D
3.3V power for Digital IO
Ground for Digital IO
To be Grounded
DP
DP
I
Ground for Digital part
65 VDD18
1.8V Power for Digital part
66 CLK_SEL
Clock Input Format Selection
67 XTALIN_CLKXTP
68 XTALOUT_CLKXTM
69 VCC18_CLK1
70 GND18_CLK1
71 GND18_CLK2
72 VCC18_CLK2
73 VSS33_IO2
74 VDD33_IO2
75 I2S_PCM_CLK
76 I2S_SCLK
77 I2S_LR_CLK
78 I2S_DATA0
79 I2S_DATA1
80 I2S_DATA2
81 NC
I
Crystal Oscillator Input or Differential Input Positive
Crystal Oscillator Output or Differential Input Negative
1.8V Power for Clock PLL Analog & Crystal Oscillator 1/2
Ground for Clock PLL Analog & Crystal Oscillator 1/2
Ground for Clock PLL Digital 1/2
1.8V Power for Clock PLL Digital 1/2
Ground for Digital IO
O
AP
AP
AP
DP
DP
DP
I/O
I/O
I/O
I/O
I
3.3V power for Digital IO
I²S Master Clock Input/Output Channel 0, 1 & 2
I²S Serial Clock Input/Output Channel 0, 1 & 2
I²S Word Select Input/Output Channel 0,1 & 2
I²S Data Input/Output Stereo Channel 0
I²S Data Input Stereo Channel 1
I²S Data Input Stereo Channel 2
I
82 I2SA_SCLK
83 I2SA_LR_CLK
84 I2SA_DATA
85 VDD18
I
I²S Serial Clock Input Channel Auxiliary
I²S Word Select Input Channel Auxiliary
I²S Data Input Stereo Channel Auxiliary
1.8V Power for Digital Core & I/O Cells Pin
Ground for Digital Core & I/O Cells Pin
Bus Expander Function
DP
DP
O
86 VSS18
87 BUS_EXP
88 IRQ
O
Interrupt Request to Microprocessor
Ground Substrate Connection
89 GND_PSUB
AP
136/157
STV82x8
Pin Descriptions
Table 22: TQFP100 Pin Description (Sheet 4 of 4)
Pin
No.
STV82x8
Pin Name
Type
(STV82x8)
Function for STV82x8
VDD 1.8V for ADC (Digital Part)
90 VDD18_ADC
91 VSS18_ADC
92 SIF_P
DP
DP
A
Ground to Complement 1.8V VDD for ADC
Sound IF input 1
ADC VTOP Decoupling pin
93 SIF_N
A
94 SIF2_P
A
Sound IF input 2
95 GNDPW_IF
96 VCC18_IF
97 GND18_IF
98 MONO_IN
99 SC4_IN_L
100 SC4_IN_R
AP
AP
AP
A
Polarization for the IF block
1.8V Power for IF AGC & ADC
Ground for IF AGC & ADC
Mono Input (for AM Mono)
SCART 4 Audio Input Left
SCART 4 Audio Input Right
A
A
137/157
Application Diagrams
STV82x8
14 Application Diagrams
Figure 31: STV82x8 TQFP80 Application Diagram
+
+
+
+
+
+
+
+
+
+
+
+
+
+
1 0 K
R 1
1
+
+
+
H
1 0 µ
L 1 1
5 6 0
R 3
V N
V S S 3 3 _ C O
N _ R S C 4 _ I
8 0
N _ L S C 4 _ I
7 9
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
V N O
3 3 D _ C V D
N _ L S C 3 _ I
N _ R S C 3 _ I
L _ F S L C T
N I _ O N M O
F
F
7 8
7 7
7 6
1 8 D _ N I
G
1 8 C _ I V C
S C R _ F L T
I F P W G N D _
F _ S N I
F _ S P I
7 5
L S _ C
L S _ L
L S _ R
7 4
7 3
V S S 1 8 _ A D C
7 2
V D D 1 8 _ A D C
7 1
L S _ S U B
H P _ L S S _ L
L _ H L S S _ R
V S S 1 8 _ C O
1 8 D _ C V D
H P _ D E T
A D R _ S E L
P S U B G N D _
7 0
6 9
I R Q
V N
V N O
B U S _ E X P
6 8
V S S 1 8
6 7
8
V D D 1
6 6
2 A D A S T _ I 2
1 A D A S T _ I 2
0 A D A S T _ I 2
L K _ C S 2 _ I L R
6 5
6 4
6 3
6 2
V S S 1 8
V D D 1
S C L
S D A
8
S 2 _ I S C L K
6 1
1
3
138/157
STV82x8
Application Diagrams
Figure 32: STV82x8 TQFP100 Application Diagram
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
1 0 K
R 1
0
+
+
+
H
1 0 µ
L 1 1
5 6 0
R 3
H
1 0 µ
L 1 9
5 6 0
R 1
2
V N O
V N O
L _ N 3 _ C I S
R _ N 3 _ C I S
L T L _ C
T L F
_ C L S
N C
_ L L S
N C
_ R L S
N C
B U _ S L S
N C
3 3 S
_
S
C
V
R _ N 4 _ C I S
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
4 9
5 0
1 0 0
9 9
3 3 D _ D C
V
L _ N 4 _ C I S
N I O _ M O N
9 8
9 7
9 6
F
F
_
1 8 D _ N I G
1 8 C _ C I V
F
S
S C R _
F I
G N D P W
9 5
2 _ F I P S
9 4
9 3
9 2
9 1
9 0
N
P
1 8 S _ S A V
1 8 D _ D A V
S I F _
S I F _
C D
C D
P S U B G N D _
8 9
I R Q
8 8
E X P B U S _
8 7
V S S 1
8 6
L
S L S _ H P _
N C
S L S _ H P _
8
8
V D D 1
8 5
8 4
8 3
8 2
8 1
8 0
7 9
7 8
7 7
7 6
R
D A T S A A I 2
L K _ C _ L A S 2 I
S C L S A I 2
_
N C
N C
V N O
V N O
R
K
_
1 8 S
_
S C
V
V
N C
D A S T _ A I 2 2
D A S T _ A I 2 1
D A S T _ A I 2 0
1 8 D _ D C
D E T H P _
S E L A D R _
V S S 1
8
8
L K _ C _ L S R 2 I
S C S L _ I 2
V D D 1
K
1
3
139/157
Application Diagrams
STV82x8
Figure 33: STV82x7/STV82x8 TQFP80 Compatiblity Application Diagram
+
+
+
+
+
+
+
+
+
+
+
+
+
+
1 0 K
R 1
1
+
+
+
H
1 0 µ
L 1 1
5 6 0
R 3
3
1
V S S 3 3 _ C O N V
V D D 3 3 _ C O N V
S C 3 _ I N _ L
S C 3 _ I N _ R
S C L _ F L T
S C R _ F L T
S C 4 _ I N _ R
8 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
S C 4 _ I N _ L
7 9
M O N O _ I N
7 8
G N D 1 8 _ I F
7 7
V C C 1 8 _ I F
7 6
G N D _ P W I F
7 5
L S _ C
L S _ L
L S _ R
S I F _ N
7 4
S I F _ P
7 3
V S S 1 8 _ A D C
7 2
L S _ S U B
H P _ L S S _ L
H L _ L S S _ R
V S S 1 8 _ C O N V
V D D 1 8 _ C O N V
H P _ D E T
A D R _ S E L
V S S 1 8
V D D 1 8
S C L
S D A
V D D 1 8 _ A D C
7 1
G N D _ P S U B
7 0
I R Q
6 9
B U S _ E X P
6 8
V S S 1 8
6 7
V D D 1 8
6 6
I 2 S _ D A T A 2
6 5
I 2 S _ D A T A 1
6 4
I 2 S _ D A T A 0
6 3
I 2 S _ L R _ C L K
6 2
I 2 S _ S C L K
6 1
1
3
140/157
STV82x8
Input/Output Groups
15 Input/Output Groups
Pin numbers apply to SDIP package only.
VCC18_IF
VCC33_LS
VCC18_IF
SIF_P73
MONO_IN 78
50K
50K
30K
VREFA
50K
GND_PSUB
GND 33_LS
VCC18_IF
VCC_H
SC1_OUTL
SC1_OUTR
SC2_OUTL
SC2_OUTR
SC3_OUTL 18
SC3_OUTR 19
1
2
5
6
VCC18_IF
REF
SIF_N
74
GND_PSUB
VCC33_LS
GNDIF
VCC_H
VREFA
SC1_IN_L
9
LS_L
SCR_FLT
LS_C
LS_L
LS_R
LS_SUB
HP_LSS_L 31
HP_LSS_R 32
25
26
27
28
29
30
SC1_IN_R 10
SC2_IN_L 14
SC2_IN_R 15
SC3_IN_L 23
SC3_IN_R 24
SC4_IN_L 79
SC4_IN_R 80
150
7K5
22K5
GND_PSUB
GND_PSUB
141/157
Input/Output Groups
STV82x8
VCC33_LS
VCC33_LS
VB G
(1.2V)
10K
VREFA 11
VB G 13
BAND-GAP=1.2V
5K4
16K8
GND33_LS
GND33_LS
VDD33_I01
VDD33_I02
59
VCC18_CLK2 57
VCC18_CLK1 54
HP_DET
ADR_SEL
RST_N
CLK_TST_CTRL 48
35
36
43
VDD33_I01
VDD18
46
38
42
50
66
VSS
VSS
37
41
47
49
58
67
VDD33_I01
VDD33_I01
GND18_CLK1 55
GND18_CLK2 56
S/PDIF_OUT 45
GND_PSUB 21
70
VSS
142/157
STV82x8
Input/Output Groups
VCC18_CLK1
VDD33_I02
VDD33_I02
XTALIN_CLKXTP
52
BUS_EXD
IRQ
68
69
GND18_CLK1
500K
VCC18_CLK1
VSS
XTALOUT_CLKXTM 53
VDD33_I01
GND18_CLK1
S/PDIF_IN 44
VDD18
CLK_SEL
51
VSS
VDD33_I02
VSS
I2S_PCM_CLK 60
I2S_LR_CLK
61
I2S_DATA0
I2S_DATA1
I2S_DATA2
62
63
64
SCL 35
SDA 40
VSS
VSS
143/157
Input/Output Groups
STV82x8
34
22
20
VDD18_CONV
VDD33_CONV
VCC_NISO
16
7
VCC33_LS
VCC33_SC
3
VCC_H
71
76
VDD18_ADC
VCC18_IF
77
75
GND18_IF
GNDPW_IF
72
VSS18_ADC
GND_PSUB
70
21
17
4
GND33_LS
GND_H
8
GND33_SC
12
33
GND_SA
VSS18_CONV
144/157
STV82x8
Electrical Characteristics
16 Electrical Characteristics
Test Conditions: T
= 25° C, V
= 8 V, V
= 1.8V, V = 3.3V, crystal oscillator at 27
XX_33
OPER
CC_H
XX_18
MHz, default register values for synthesizer, unless otherwise specified.
16.1 Absolute Maximum Ratings
Symbol
Parameter
Analog and Digital 1.8 V Supply Voltage
Value
Units
VXX_18
2.5
V
(VCC18_CLK1, VCC18_CLK2, VCC18_IF, VDD18, VDD18_CONV, VDD18_ADC
)
Analog and Digital 3.3 V Supply Voltage
VXX_33
4.0
V
(VCC33_SC, VCC33_LS, VDD33_IO1, VDD33_IO2, VDD33_CONV, VCC_NISO
Analog Supply High Voltage (VCC_H
)
HVCC
VESD
TOPER
TSTG
)
8.8
4
V
Capacitor 100 pF discharged via 1.5 kΩ serial resistor (Human Body Model)
Operating Ambient Temperature
kV
°C
°C
0, +70
-55 to +150
Storage Temperature
16.2 Thermal Data
Symbol
Parameter
Value
Units
RthJA
Junction-to-Ambient Thermal Resistance
42
°C/W
16.3 Power Supply Data
Symbol
Parameter
Min.
Typ. Max. Units
Analog and Digital 1.8 V Supply Voltage
VXX_18
1.70
1.80
1.90
V
(VCC18_CLK1, VCC18_CLK2, VCC18_IF, VDD18, VDD18_CONV, VDD18_ADC
)
Analog and Digital 3.3 V Supply Voltage
VXX_33
HVCC
3.13
7.6
3.30
8.0
3.47
8.4
V
V
(VCC33_SC, VCC33_LS, VDD33_IO1, VDD33_IO2, VDD33_CONV, VCC_NISO
Analog Supply High Voltage (VCC_H
)
)
Current Consumption for Digital 1.8 V Supply (VCC18_CLK2, VDD18, VDD18_CONV
,
IVDD18
TBD
mA
VDD18_ADC
)
IVDD33
IVCC18
Current Consumption for Digital 3.3 V Supply ( VDD33_IO1, VDD33_IO2
)
TBD
TBD
mA
mA
Current Consumption for Analog 1.8 V Supply (VCC18_CLK1, VCC18_IF
)
Current Consumption for Analog 3.3 V Supply (VCC33_SC, VCC33_LS, VDD33_CONV
,
IVCC33
TBD
mA
VCC_NISO
)
IVCC_H
Current Consumption for Analog Supply High Voltage (8 V)
Total Power Dissipation
TBD
TBD
mA
PDTOT
mW
145/157
Electrical Characteristics
STV82x8
16.4 Crystal Oscillator
Symbol
Parameter
Min.
Typ. Max. Units
fP
Crystal Series Resonance Frequency (at C21 = C22 = 27 pF load capacitor)
Frequency Tolerance at 25 °C
27
MHz
ppm
ppm
fF
DF/FP
DF/FT
-30
-30
+30
+30
15
Frequency Stability versus Temperature within a range from 0 to 70 °C
Motional Capacitor
C1
RS
Serial Resistance
30
Ω
CS
Shunt Capacitance
7
pF
16.5 Analog Sound IF Signal
Symbol
Parameter
SIF Frequency Flatness
Test Conditions
Min.
Typ. Max. Units
AGC_ERR at 0, frequency range
from 4 to 7MHz
BANDSIF
dB
RINSIF
DCINSIF
SIF Input Resistance
SIF Input DC Level
SIF Input Capacitance
60
72
0.9
3
85
kΩ
V
CINSIF
pF
FM Carrier
SNR 40 dB
RMS unweighted 20 Hz to
15 kHz
VSIFFM
µVPP
SIF Input Sensitivity
TBD
Standard M/N 27 kHz FM
Deviation 1 kHz
Standard (FM50k)
1
5
kHz
kHz
SIF Carrier Accuracy for
FM
Shifted Standard
(FM50k with DCO
compensation)
DFSIFFM
120
AGC
AGCstep
IF AGC Step
1.4
29
1.5
30
1.6
31
dB
dB
AGCdyn
Relative Maximum Gain to Step 0
Valid from Step 21 to Step 31
16.6 SIF to I²S Output Path Characteristics
Test Conditions: SIF amplitude = 100 mVpp, unless otherwise specified, I²S output.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Units
FM Demodulation
BANDFM
Frequency Response
20 Hz to 15 kHz
TBD
dB
146/157
STV82x8
Electrical Characteristics
Symbol
SNRFM
THDFM
Parameter
Signal to Noise
Test Conditions
Min.
Typ.
Max. Units
TBD
dB
RMS unweighted, 20 Hz to 15 kHz,
Standard M/N 27 kHz FM Deviation,1 kHz
Total Harmonic Distortion
Stereo Channel Separation
TBD
%
Standard M/N BTSC stereo,
FM deviation, 1 kHz
SEPFM
TBD
dB
16.7 SCART to SCART Analog Path Characteristics
Test Conditions: Rload
= 10 kΩ, Cload
= 330 pF, MONO_IN voltage = 0.5 V
MAX
MAX RMS
Symbol
Analog-to-Analog STEREO and MONO
RINSCART
Parameter
Test Conditions
Min.
Typ.
Max. Units
SCART Input Resistance
34
40
kΩ
Ω
V
ROUTSCART
Output Resistance for SCARTs
SCART Input DC Level
VDCINSCART
VDCOUTSCART
1.57
3.64
SCART Output DC Level
V
Clipping input level from
SCART input
VRMS
Clipping
SCART
CLIPSCART
At 1 kHz 1% THD
Clipping input level from
MONO_IN input
VRMS
%
1 VRMS, at 1 KHz
THD from SCART input
0.02
0.02
THDSCART
THD SCART
THD from MONO_IN
input
0.25 VRMS, at 1 KHz
%
1 VRMS, 20 Hz to 20 kHz Bandwidth,
RMS unweighted
SCART input
82
76
dB
dB
Signal to Noise
Ratio
SNRSCART
0.25 VRMS, 20 Hz to 20 kHz
Bandwidth, RMS unweighted
MONO_IN input
SCART input
20 Hz to 20 kHz
20 Hz to 20 kHz
dB
dB
Frequency
Flatness
BANDSCART
MONO_IN input
12
90
1 VRMS @ 1 kHz on ref signal, the
other one grounded
XTALKL/R
XTALKIN
Left/Right Crosstalk
dB
dB
1 VRMS @ 1 kHz on ref signal, all
other inputs grounded
Audio Crosstalk from Input Channel n to
Input Channel m
90
90
1 VRMS @ 1 kHz on reference
output, signal on a single input, all
other inputs grounded
Audio Crosstalk from Output Channel n
to Output Channel m
XTALKOUT
dB
147/157
Electrical Characteristics
STV82x8
16.8 SCART and MONO IN to I²S Path Characteristics
Test Conditions: Sampling Frequency = 32 kHz, Maximum MONO_IN voltage = 0.5 V
.
RMS
Symbol
Parameter
THD from
Test Conditions
IN = 2 VRMS at 1 KHz
Min.
Typ. Max. Units
V
V
0.006
0.006
%
%
SCART input
THDADC
THD ADC
THD from
MONO_IN input
IN = 0.5 VRMS at 1 KHz
20 to 15 kHz Bandwidth, RMS unweighted
IN = 200 mVRMS SCART input
SNRADC
Signal to Noise Ratio
dB
V
BANDADC
XTALKADC
Frequency Flatness
Left Right Crosstalk
20 Hz to 15 kHz
dB
dB
at 1 KHz, VIN = 1 VRMS
16.9 I2S to LS/HP/SUB/C Path Characteristics
Test Conditions: Sampling Frequency = 32KHz, L
= 100 µH, C
= 33nF, R
= 30KΩ.
LOAD
LOAD
LOAD
Symbol
Parameter
Test Conditions
Min.
Typ. Max. Units
Output Resistance for Main
Outputs
LS_L, LS_R, LS_SUB, LS_C, HP_LSS_R
and HP_LSS_L pins
ROUTDAC
90
Ω
VDCOUTDAC
THDDAC
MAIN Output DC Level
1.54
V
Total Harmonic Distortion
90% Full-scale Range at 1 kHz
%
20 to 15 kHz Bandwidth, RMS unweighted,
at -20dB full range
SNRDAC
Signal to Noise Ratio
dB
VOUTAMPDAC
XTALKDAC
mVRMS
dB
MAIN Output Amplitude
Left Right Crosstalk
100% Full-scale Range at 1 kHz
at 1 KHz, -20dBFS
900
16.10 I²S to SCART Path Characteristics
Test Conditions: Sampling Frequency = 32 kHz, C
= 33 nF on DAC SCART pins,
LOAD
DAC SCART prescale at -5.5 dB.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Units
THDDACSCART
Total Harmonic Distortion
90% Full-scale Range at 1 kHz
0.08
%
20 Hz to 15 kHz Bandwidth unweighted,
-20dB Full Range
SNRDACSCART
Signal to Noise Ratio
dB
VODACSCART
VRMS
dB
MAIN Output Amplitude
Left Right Crosstalk
100% Full-scale Range at 1 kHz
at 1 KHz, -20 dBFS
2
XTALKDACSCART
148/157
STV82x8
Electrical Characteristics
16.11 MUTE Characteristics
Symbol
Parameter
DAC Mute analog
SCART Mute
Test Conditions
I2S to DAC at 1 kHz
Min.
Typ.
Max. Units
MUTEDAC
dB
2 VRMS @ 1 kHz on ref signal, all other
inputs grounded
MUTESCART
dB
16.12 Digital I/Os Characteristics
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Units
except SDA, SCL and CLK_SEL,
3.3V power supply
VIL
Low Level Input Voltage
0.5
V
except SDA, SCL and CLK_SEL,
3.3V power supply
VIH
IIN
High Level Input Voltage
Input Current
2.0
V
µA
V
1
CLK_SEL Low Level Input
Voltage
VILCLK_SEL
1.8V power supply
1.8V power supply
0.3
CLK_SEL High Level Input
Voltage
VIHCLK_SEL
1.2
3.0
V
VOL
VOH
Low Level Output Voltage
High Level Output Voltage
S/PDIF_OUT, IRQ, BUS_EXP
S/PDIF_OUT, IRQ, BUS_EXP
0.3
V
V
149/157
Electrical Characteristics
STV82x8
16.13 I²C Bus Characteristics
Symbol
SCL
Parameter
Test Conditions
Min.
Typ
Max.
Unit
VIL
VIH
IIL
Low Level Input Voltage
High Level Input Voltage
-0.3
2.3
-10
1.5
5.5
10
V
V
V
IN = 0 to 5.0 V
Input Leakage Current
Clock Frequency
Input Rise Time
µA
kHz
ns
ns
pF
fSCL
tR
400
300
300
10
1 V to 2 V
2 V to 1 V
tF
Input Fall Time
CI
Input Capacitance
SDA
VIL
VIH
IIL
Low Level Input Voltage
High Level Input Voltage
-0.3
2.3
-10
1.5
5.5
10
V
V
V
IN = 0 to 5.0 V
Input Leakage Current
Input Rise Time
µA
ns
ns
V
tR
1 V to 2 V
2 V to 1 V
300
300
0.4
250
400
10
tF
Input Fall Time
VOL
tF
I
OL = 3 mA
Low Level Output Voltage
Output Fall Time
2 V to 1 V
ns
pF
pF
CL
CI
Load Capacitance
Input Capacitance
I²C Timing
tLOW
Clock Low period
Clock High period
Data Set-up Time
Data Hold Time
1.3
0.6
100
0
µs
µs
ns
ns
tHIGH
tSU,DAT
tHD,DAT
900
Set-up Time from Clock High
to Stop
tSU,STO
0.6
µs
Start Set-up Time following a
Stop
tBUF
1.3
0.6
0.6
µs
µs
µs
tHD,STA
tSU,STA
Start Hold Time
Start Set-up Time following
Clock Low to High Transition
150/157
STV82x8
Electrical Characteristics
Figure 34: I²C Bus Timing
SDA
SCL
t
BUF
t
t
SU,DAT
LOW
t
t
t
t
t
t
SU,STO
HD,STA
R
HD,DAT HIGH
F
t
SDA
SU,STA
16.14 I²S Bus Interface
I²S Bus Interface timing values shown in Figure 35.
Symbol
I²S Input
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VI2S_IL
VI2S_IH
ZI2S
Input I²S Low Level Voltage
Input I²S High Level Voltage
Input I²S Impedance
0.8
V
V
2
5
1
pF
µA
II2S_Leak
I²S Leakage Current
-1
I²S Input Setup Time before
Rising Edge of Clock
tI2S_Su
See Figure 35
30
ns
ns
I²S Input Hold Time after
Rising Edge of Clock
tI2S_Ho
See Figure 35
100
30
I²S Left Right Strobe Input
Frequency (I²S_DATA0 and
I²SA_DATA with SRC)
fI2S_LR0
49
kHz
I²S Serial Clock Input
fI2S_SCL0
Frequency (I²S_DATA0 and
I²SA_DATA with SRC)
1.092
32
3.136
MHz
I²S Left Right Strobe Input
Frequency (I²S_DATA0 and
I²SA_DATA with PLL,
I²S_DATA1,2)
fI2S_LR
Deviation = 250 ppm
48
kHz
I²S Serial Clock Input
Frequency (I²S_DATA0 and
I²SA_DATA with PLL,
I²S_DATA1,2)
fI2S_SCL
3.072
MHz
RI2S_SCL
I²S Serial Clock Input Ratio
0.9
2.4
1.1
0.4
I²S Output (I²S_DATA0 only)
VI2SOL
VI2SOH
IOL = 2 mA
OH = 2 mA
Output I²S Low Level Voltage
Output I²S High Level voltage
V
V
I
151/157
Electrical Characteristics
STV82x8
Symbol
fI2S_OLR
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I²S Left Right Strobe Output
Frequency (I²S_DATA0 and
I²SO_DATA0,1)
48
kHz
I²S Serial Clock Output
Frequency (I²S_DATA0 and
I²SO_DATA0,1)
fI2S_OSCL
3.072
MHz
ns
RI2S_SCL
tI2S_DEL
I²S Serial Clock Output Ratio
0.9
1.1
30
I²S Output Delay After Falling
Edge of Clock
See Figure 35, Cl = 30 pF
Figure 35: I²S Input Bus Timings
I²S_SCLK
tI2S_Su
tI2S_Ho
I²S_DATA
tI2S_Su
I²S_LR_CLK
152/157
STV82x8
Package Mechanical Data
17 Package Mechanical Data
17.1 TQFP80 Package
Figure 36: 80-Pin Thin Plastic Quad Flat Package
D
A
D1
A2
A1
b
e
E1
E
c
L1
L
h
Table 23: Package Mechanical Dimensions
mm
inches
Dim.
Min.
Typ.
Max.
Min.
Typ.
Max.
A
A1
A2
b
1.60
0.15
1.45
0.38
0.20
0.063
0.006
0.057
0.015
0.008
0.05
1.35
0.22
0.09
0.002
0.053
0.009
0.004
1.40
0.32
0.055
0.013
C
D
16.00
14.00
16.00
14.00
0.65
0.630
0.551
0.630
0.551
0.026
3.5°
D1
E
E1
e
K
0°
3.5°
0.75°
0.75
0°
0.75°
0.030
L
0.45
0.60
0.018
0.024
0.039
L1
1.00
153/157
Package Mechanical Data
STV82x8
17.2 TQFP100 Package
Figure 37: 100-Pin Thin Plastic Quad Flat Package
D
A
D1
A2
A1
b
e
E1
E
c
L
1
L
h
Table 24: Package Mechanical Dimensions
mm
inches
Typ.
Dim.
Min.
Typ.
Max.
Min.
Max.
A
A1
A2
b
1.60
0.15
1.45
0.27
0.20
0.063
0.006
0.057
0.011
0.008
0.05
1.35
0.17
0.09
0.002
0.053
0.007
0.004
1.40
0.22
0.055
0.009
C
D
16.00
14.00
16.00
14.00
0.50
0.630
0.551
0.630
0.551
0.020
3.5°
D1
E
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45
0.60
0.75
0.018
0.024
0.039
0.030
L1
1.00
Number of Pins
100
N
154/157
STV82x8
Revision History
18 Revision History
Revision
Date
Modification
0.1
15 Nov. 2004 Preliminary Datasheet - First Issue.
Major updates to Key Features on page 1, Typical Applications on page 1 and Chapter 1: General
Description on page 8.
0.2
0.3
19 Nov. 2004
7 Jan. 2005
Addition of TQFP100 information.
Updated Figure 1: STV82x8 Block Diagram (TQFP80) on page 2, Figure 2: STV82x8 Block
1.0
23 Feb. 2005 Diagram (TQFP100) on page 3, Section 16.5: Analog Sound IF Signal on page 146 and Section
16.6: SIF to I²S Output Path Characteristics on page 146.
155/157
Index
TQFP 80 .........................................................37
TQFP100 ........................................................38
I2C ....................................................................151
I2C Address ...........................................................44
IRQ Generation ......................................................42
A
Analog-to-Digital Conversion .....................................19
Audio Matrix
Analog ............................................................35
Automatic Frequency Control .....................................20
Automatic Gain Control ............................................19
Automatic Standard Recognition System ...........19-20, 47
L
Loudness Control
Automatic ........................................................32
B
P
Back-end Processing ...............................................21
Bass Management ..................................................25
Bass-Treble Control .................................................31
Beeper .................................................................33
Package Mechanical Data .......................................153
Power Supply Management .......................................41
R
C
Registers
Clock Generator .....................................................18
Clocking 1 .......................................................56
Clocking 2 .......................................................72
Demodulator ....................................................58
Demodulator Channel 1 ......................................61
General Control ................................................53
I²C Map ..........................................................47
Reset values ..........................................................43
D
Demodulation .........................................................19
Dolby Pro Logic II Decoder ........................................25
E
S
Electrical Characteristics ........................................145
Absolute Maximum Ratings ...............................145
Analog Sound IF Signal ....................................146
Crystal Oscillator .............................................146
Digital I/Os ....................................................149
I²C Bus .........................................................150
I2S to LS/HP/SW Path .....................................148
I2S to SCART Path .........................................148
MUTE Performance .........................................149
SCART to LS/HP/SW Path ................................148
SCART to SCART Analog Path ..........................147
SIF to LS/HP/SCART Path ................................146
Supply Data ...................................................145
Thermal Data .................................................145
Equalizer
SIF Signal
Analog ............................................................19
Signal Processor
Dedicated Digital ...............................................21
Signal to Noise .....................................................147
Smart Volume Control ..............................................30
Soft Mute Control ....................................................33
Software Information ................................................14
SRS
3D Mono/Stereo ...............................................30
Dialog Clarity ...................................................30
WOW .............................................................30
SRS‚
TruBass‰ .......................................................30
TruSurround ....................................................29
TruSurround XT‰ .............................................29
ST Bass Enhancer ..................................................31
ST Dynamic Bass ...................................................31
ST OmniSurround ...................................................25
ST WideSurround ...................................................24
5-Band Audio ...................................................31
H
Headphone Detection ..............................................42
T
I
Total Harmonic Distortion ........................................147
V
I²C Address ...........................................................44
I²C Bus Expander ...................................................42
I²C Protocol ...........................................................44
I²S Inputs
TQFP100 ........................................................37
TQFP80 ..........................................................36
I²S Outputs
Volume/Balance Control ...........................................32
156/157
STV82x8
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces
all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
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157/157
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