STR910FAM32X6_技术文档

STR91xFA

ARM966E-S™ 16/32-Bit Flash MCU with Ethernet, USB, CAN,

AC motor control, 4 timers, ADC, RTC, DMA

PRELIMINARY DATA

Features

■ 16/32-bit 96 MHz ARM9E based MCU

– ARM966E-S RISC core: Harvard archi-

tecture, 5-stage pipeline, Tightly-Coupled

Memories (SRAM and Flash)

LQFP80 12 x12mm

LQFP128 14 x 14mm

– STR91xFA implementation of core adds

high-speed burst Flash memory interface,

instruction prefetch queue, branch cache

LFBGA144 10 x 10 x 1.7

– Up to 96 MIPS directly from Flash memory

– Single-cycle DSP instructions are supported

– Binary compatible with 16/32-bit ARM7 code

■ Dual burst Flash memories, 32-bits wide

■ 10 Communication interfaces

– 10/100 Ethernet MAC with DMA and MII port

– USB Full-speed (12 Mbps) slave device

– CAN interface (2.0B Active)

– 3 16550-style UARTs with IrDA protocol

– 2 Fast I C™, 400 kHz

– 256KB/512KB Main Flash, 32KB 2nd Flash

– Sequential Burst operation up to 96 MHz

– 100K min erase cycles, 20 yr min retention

■ SRAM, 32-bits wide

2

– 2 channels for SPI™, SSI™, or Microwire™

– 64K or 96K bytes, optional battery backup

■ 9 programmable DMA channels

■ External Memory Interface (EMI)

– 8- or 16-bit data

– Up to 24-bit addressing

– Static Async modes for LQFP128 packages

– Additional Burst Synchronous modes for

LFBGA144 packages

– One for Ethernet, 8 programmable channels

■ Clock, reset, and supply management

– Two supplies required. Core: 1.8 V +/-10%,

I/O: 2.7 to 3.6 V

– Internal oscillator operating with external

4-25 MHz crystal

– Internal PLL up to 96MHz

– Real-time clock provides calendar functions,

tamper detection, and wake-up functions

■ Up to 80 I/O pins (muxed with interfaces)

– 5 V tolerant, 16 have high sink current

(8 mA)

– Bit-wise manipulation of pins within a port

■ 16-bit standard timers (TIM)

– Reset Supervisor monitors voltage supplies,

watchdog timer, wake-up unit, ext. reset

– 4 timers each with 2 input capture, 2 output

compare, PWM and pulse count modes

■ 3-Phase induction motor controller (IMC)

– Brown-out monitor for early warning interrupt

– Run, Idle, and Sleep Mode as low as 50 uA

■ Operating temperature -40 to +85°C

– 3 pairs of PWM outputs, adjustable centers

– Emergency stop, dead-time gen, tach input

■ JTAG interface with boundary scan

■ Vectored interrupt controller (VIC)

– 32 IRQ vectors, 30 intr pins, any can be FIQ

– Branch cache minimizes interrupt latency

■ 8-channel, 10-bit A/D converter (ADC)

– ARM EmbeddedICE® RT for debugging

– In-System Programming (ISP) of Flash

■ Embedded trace module (ARM ETM9)

– 0 to 3.6V range, 0.7 usec conversion

– DMA capability

– Hi-speed instruction tracing, 9-pin interface

May 2007

Rev 1

1/78

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without noticwew. w.st.com

78

STR91xFA

Contents

1

2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

2.2

2.3

2.4

System-in-a-Package (SiP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Package choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

ARM966E-S CPU core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Burst Flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4.1 Pre-Fetch Queue (PFQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4.2 Branch Cache (BC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4.3 Management of literals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.5

SRAM (64K or 96K Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.5.1 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.5.2 Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6

2.7

DMA data movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Non-volatile memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.7.1 Primary Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.7.2 Secondary Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.8

2.9

One-time-programmable (OTP) memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.8.1 Product ID and revision level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Vectored interrupt controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.9.1 FIQ handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.9.2 IRQ handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.9.3 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.10 Clock control unit (CCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.10.1 Master clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.10.2 Reference clock (RCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.10.3 AHB clock (HCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.10.4 APB clock (PCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.10.5 Flash memory interface clock (FMICLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.10.6 Baud rate clock (BRCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.10.7 External memory interface bus clock (BCLK) . . . . . . . . . . . . . . . . . . . . . . . . 16

2.10.8 USB interface clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.10.9 Ethernet MAC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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STR91xFA

2.10.10 External RTC calibration clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.10.11 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.11 Flexible power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.11.1 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.11.2 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.11.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.12 Voltage supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.12.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . . . . 18

2.12.2 Battery supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.13 System supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.13.1 Supply voltage brownout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.13.2 Supply voltage dropout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.13.3 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.13.4 External RESET_INn pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.13.5 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.13.6 JTAG debug command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.13.7 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.14 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.15 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.15.1 In-system-programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.15.2 Boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.15.3 CPU debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.15.4 JTAG security bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.16 Embedded trace module (ARM ETM9, v. r2p2) . . . . . . . . . . . . . . . . . . . . . . 23

2.17 Ethernet MAC interface with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.18 USB 2.0 slave device interface with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.18.1 Packet buffer interface (PBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.18.2 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.18.3 Suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.19 CAN 2.0B interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.20 UART interfaces with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.20.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.21 I2C interfaces with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.21.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.22 SSP interfaces (SPI, SSI, and Microwire) with DMA . . . . . . . . . . . . . . . . . . . 27

2.22.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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STR91xFA

2.23 General purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.24 A/D converter (ADC) with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.24.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.25 Standard timers (TIM) with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.25.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.26 Three-phase induction motor controller (IMC) . . . . . . . . . . . . . . . . . . . . . . . 30

2.27 External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3

4

4.1

4.2

LFBGA144 ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Default pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.1

5.2

5.3

5.4

Buffered and non-buffered writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

System (AHB) and peripheral (APB) buses . . . . . . . . . . . . . . . . . . . . . . . . . 44

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Two independent Flash memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.4.1 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.4.2 Optional configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.1

6.2

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.2.1 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . 49

LVD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.3.1 LVD delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.3

6.4

6.5

6.6

6.7

6.8

6.9

AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

RESET_INn and power-on-reset characteristics . . . . . . . . . . . . . . . . . . . . . 54

Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

RTC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.10 SRAM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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STR91xFA

6.11 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.12.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . 57

6.12.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.12.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . 58

6.12.4 Electro-Static Discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.12.5 Static and Dynamic Latch-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.12.6 Designing hardened software to avoid noise problems . . . . . . . . . . . . . . . . . 58

6.12.7 Electrical Sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.13 External memory bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.14 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.15 Communication interface electrical characteristics . . . . . . . . . . . . . . . . . . . . 65

6.15.1 10/100 Ethernet MAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 65

6.15.2 USB electrical interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.15.3 CAN interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.15.4 I2C electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.15.5 SPI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.1

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8

9

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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Description

STR91xFA

1

Description

STR91xFA is a series of ARM-powered microcontrollers which combines a 16/32-bit

ARM966E-S RISC processor core, dual-bank Flash memory, large SRAM for data or code, and

a rich peripheral set to form an ideal embedded controller for a wide variety of applications such

as point-of-sale terminals, industrial automation, security and surveillance, vending machines,

communication gateways, serial protocol conversion, and medical equipment. The ARM966E-S

core can perform single-cycle DSP instructions, good for speech processing, audio algorithms,

and low-end imaging.

This datasheet provides STR91xFA ordering information, functional overview, mechanical

information, and electrical device characteristics.

For complete information on STR91xFA memory, registers, and peripherals, please refer to the

STR91xFA Reference Manual.

For information on programming the STR91xFA Flash memory please refer to the STR9 Flash

Programming Reference Manual

For information on the ARM966E-S core, please refer to the ARM966E-S Rev. 2 Technical

Reference Manual.

Table 1.

Features

Device summary

STR910FA

STR911FA

STR912FA

M32X6 W32X6 Z32H6 M42X6 M44X6 W42X6 W44X6 W34X6 W42X6 W44X6 Z42H6 Z44H6

Flash

Kbytes

RAM -

Kbytes

Peripheral

functions

256

+32

256

+32

512

+32

256

+32

512

+32

512

+32

256

+32

512

+32

256

+32

512

+32

64

96

64

96

CAN,

40 I/Os

CAN, EMI,

80 I/Os

USB, CAN,

40 I/Os

USB, CAN,

EMI, 80 I/Os

Ethernet, USB, CAN,

EMI,80 I/Os

LQFP LQFP LFBGA

80 128 144

Packages

LQFP80

LQFP128

LFBGA144

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STR91xFA

Functional overview

2

Functional overview

2.1

System-in-a-Package (SiP)

The STR91xFA is a SiP device, comprised of two stacked die. One die is the ARM966E-S CPU

with peripheral interfaces and analog functions, and the other die is the burst Flash. The two die

are connected to each other by a custom high-speed 32-bit burst memory interface and a serial

JTAG test/programming interface.

2.2

2.3

Package choice

STR91xFA devices are available in 128-pin (14 x 14 mm) 80-pin (12 x 12 mm) LQFP and

LFBGA144 (10 x 10 mm) packages. Refer to the Table 1 on page 6 and to Table 35 on page 75

for a list of available peripherals for each of the package choices.

ARM966E-S CPU core

The ARM966E-S core inherently has separate instruction and data memory interfaces (Harvard

architecture), allowing the CPU to simultaneously fetch an instruction, and read or write a data

item through two Tightly-Coupled Memory (TCM) interfaces as shown in Figure 1. The result is

streamlined CPU Load and Store operations and a significant reduction in cycle count per

instruction. In addition to this, a 5-stage pipeline is used to increase the amount of operational

parallelism, giving the most performance out of each clock cycle.

Ten DSP-enhanced instruction extensions are supported by this core, including single-cycle

execution of 32x16 Multiply-Accumulate, saturating addition/subtraction, and count leading-

zeros.

®

The ARM966E-S core is binary compatible with 32-bit ARM7 code and 16-bit Thumb code.

2.4

Burst Flash memory interface

A Burst Flash memory interface (Figure 1) has been integrated into the Instruction TCM

(I-TCM) path of the ARM966E-S core. Also in this path is an 8-instruction Pre-Fetch Queue

(PFQ) and a 15-entry Branch Cache (BC), enabling the ARM966E-S core to perform up to 96

MIPS while executing code directly from Flash memory. This architecture provides high

performance levels without a costly instruction SRAM, instruction cache, or external SDRAM.

Eliminating the instruction cache also means interrupt latency is reduced and code execution

becomes more deterministic.

2.4.1 Pre-Fetch Queue (PFQ)

As the CPU core accesses sequential instructions through the I-TCM, the PFQ always looks

ahead and will pre-fetch instructions, taking advantage any idle bus cycles due to variable

length instructions. The PFQ will fetch 32-bits at a time from the Burst Flash memory at a rate

of up to 96 MHz.

7/78

Functional overview

STR91xFA

2.4.2 Branch Cache (BC)

When instruction addresses are not sequential, such as a program branch situation, the PFQ

would have to flush and reload which would cause the CPU to stall if no BC were present.

Before reloading, the PFQ checks the BC to see if it contains the desired target branch

address. The BC contains up to fifteen of the most recently taken branch addresses and the

first eight instructions associated with each of these branches. This check is extremely fast,

checking all fifteen BC entries simultaneously for a branch address match (cache hit). If there is

a hit, the BC rapidly supplies the instruction and reduces the CPU stall. This gives the PFQ time

to start pre-fetching again while the CPU consumes these eight instructions from the BC. The

advantage here is that program loops (very common with embedded control applications) run

very fast if the address of the loops are contained in the BC.

In addition, there is a 16th branch cache entry that is dedicated to the Vectored Interrupt

Controller (VIC) to further reduce interrupt latency by eliminating the stall latency typically

imposed by fetching the instruction that reads the interrupt vector address from the VIC.

2.4.3 Management of literals

Typical ARM architecture and compilers do not place literals (data constants) sequentially in

Flash memory with the instructions that use them, but instead the literals are placed at some

other address which looks like a program branch from the PFQ’s point of view. The STR91xFA

implementation of the ARM966E-S core has special circuitry to prevent flushing the PFQ when

literals are encountered in program flow to keep performance at a maximum.

8/78

STR91xFA

Functional overview

Figure 1. STR91xFA block diagram

Stacked Burst Flash Memory Die

JTAG ISP

STR91xA

STR91x

1.8V

GND

CORE SUPPLY, VDD

CORE GND, VSS

I/O SUPPLY, VDDQ

I/O GND, VSSQ

Main Flash 256K,

or 512K Bytes

2^ndFlash

32K Bytes

Burst Interface

3.0 or 3.3V

GND

BACKUP

SUPPLY

64K or 96K

Byte

SRAM

Burst Interface

VBATT

Pre-Fetch Que

and Branch

Cache

RTC

Arbiter

Instruction

TCM

Interface

JTAG

ARM966E-S

RISC CPU Core

Data TCM

Interface

JTAG

Debug

and

ETM

Control Logic / BIU and Write Buffer

AMBA / AHBAInterface

ETM

32.768 kHz

XTAL

Real Time Clock

Wake Up

Programmable Vectored

Interrupt Controllers

(4) 16-bit Timers,

CAPCOM, PWM

Interrupt Controller

Motor Control,

3-ph Induction

4 MHz to 25

MHz XTAL

PLL, Power Management,

and Supervisory Reset

AHB

to

APB

(3) UART w/ IrDA

(2) I2C

External Memory

Interface (EMI)***,

Muxed Address/Data

EMI Ctrl

16

32

48

(80) GPIO****

Programmable DMA

Controller (8 ch.)

Request

from

(2) SPI

UART,

I2C,

SPI,

CAN 2.0B

USB* Full Speed, 10

Endpoints with FIFOs

USB Bus

Timers,

Ext Req

ADC

8 Channel 10-bit

ADC

AVDD

To Ethernet

PHY (MII) **

Ethernet**

MAC, 10/100

Dedicated

DMA

Watchdog Tmr

AVREF*

AVSS

* USB not available on STR910

** Ethernet MAC not available on STR910 and STR911

*** EMI not available on LQFP80

**** Only 40 GPIOs on LQFP80

9/78

Functional overview

STR91xFA

2.5

SRAM (64K or 96K Bytes)

A 32-bit wide SRAM resides on the CPU’s Data TCM (D-TCM) interface, providing single-cycle

data accesses. As shown in Figure 1, the D-TCM shares SRAM access with the Advanced

High-performance Bus (AHB). Sharing is controlled by simple arbitration logic to allow the DMA

unit on the AHB to also access to the SRAM.

2.5.1 Arbitration

Zero-wait state access occurs for either the D-TCM or the AHB when only one of the two is

requesting SRAM. When both request SRAM simultaneously, access is granted on an

interleaved basis so neither requestor is starved, granting one 32-bit word transfer to each

requestor before relinquishing SRAM to the other. When neither the D-TCM or the AHB are

requesting SRAM, the arbiter leaves access granted to the most recent user (if D-TCM was last

to use SRAM then the D-TCM will not have to arbitrate to get access next time).

The CPU may execute code from SRAM through the AHB. There are no wait states as long as

the D-TCM is not contending for SRAM access and the AHB is not sharing bandwidth with

peripheral traffic. The ARM966E-S CPU core has a small pre-fetch queue built into this

instruction path through the AHB to look ahead and fetch instructions during idle bus cycles.

2.5.2 Battery backup

When a battery is connected to the designated battery backup pin (VBATT), SRAM contents

are automatically preserved when the normal operating voltage on VDD pins is lost or sags

below threshold. Automatic switchover to SRAM can be disabled by firmware if it is desired that

the battery will power only the RTC and not the SRAM during standby.

2.6

DMA data movement

DMA channels on the Advanced High-performance Bus (AHB) take full advantage of the

separate data path provided by the Harvard architecture, moving data rapidly and largely

independent of the instruction path. There are two DMA units, one is dedicated to move data

between the Ethernet interface and SRAM, the other DMA unit has eight programmable

channels with 16 request signals to service other peripherals and interfaces (USB, SSP, I2C,

ADC, UART, Timers, EMI, and external request pins). Both single word and burst DMA transfers

are supported. Memory-to-memory transfers are supported in addition to memory-peripheral

transfers. DMA access to SRAM is shared with D-TCM accesses, and arbitration is described

in Section 2.5.1. Efficient DMA transfers are managed by firmware using linked list descriptor

tables. Of the 16 DMA request signals, two are assigned to external inputs. The DMA unit can

move data between external devices and resources inside the STR91xFA through the EMI bus.

2.7

Non-volatile memories

There are two independent 32-bit wide Burst Flash memories enabling true read-while-write

operation. The Flash memories are single-voltage erase/program with 20 year minimum data

retention and 100K minimum erase cycles. The primary Flash memory is much larger than the

secondary Flash.

Both Flash memories are blank when devices are shipped from ST. The CPU can boot only

from Flash memory (configurable selection of which Flash bank).

10/78

STR91xFA

Functional overview

Flash memories are programmed half-word (16 bits) at a time, but are erased by sector or by

full array.

2.7.1 Primary Flash memory

Using the STR91xFA device configuration software tool and 3rd party Integrated Developer

Environments, it is possible to specify that the primary Flash memory is the default memory

from which the CPU boots at reset, or otherwise specify that the secondary Flash memory is

the default boot memory. This choice of boot memory is non-volatile and stored in a location

that can be programmed and changed only by JTAG In-System Programming. See Section 5:

Memory mapping, for more detail.

The primary Flash memory has equal length 64K byte sectors. Devices with 256 Kbytes of

primary Flash have four sectors and 512K devices have eight sectors.

2.7.2 Secondary Flash memory

The smaller of the two Flash memories can be used to implement a bootloader, capable of

storing code to perform robust In-Application Programming (IAP) of the primary Flash memory.

The CPU executes code from the secondary Flash, while updating code in the primary Flash

memory. New code for the primary Flash memory can be downloaded over any of the

interfaces on the STR91xFA (USB, Ethernet, CAN, UART, etc.)

Additionally, the Secondary Flash memory may also be used to store small data sets by

emulating EEPROM though firmware, eliminating the need for external EEPROM memories.

This raises the data security level because passcodes and other sensitive information can be

securely locked inside the STR91xFA device.

The secondary Flash memory is 32 Kbytes and has four equal length sectors of 8 Kbytes each.

Both the primary Flash memory and the secondary Flash memory can be programmed with

code and/or data using the JTAG In-System Programming (ISP) channel, totally independent of

the CPU. This is excellent for iterative code development and for manufacturing.

2.8

One-time-programmable (OTP) memory

There are 32 bytes of OTP memory ideally suited for serial numbers, security keys, factory

calibration constants, or other permanent data constants. These OTP data bytes can be

programmed only one time through either the JTAG interface or by the CPU, and these bytes

can never be altered afterwards. As an option, a “lock bit” can be set by the JTAG interface or

the CPU which will block any further writing to the this OTP area. The “lock bit” itself is also

OTP. If the OTP array is unlocked, it is always possible to go back and write to an OTP byte

location that has not been previously written, but it is never possible to change an OTP byte

location if any one bit of that particular byte has been written before. The last two OTP bytes are

reserved for the STR91xFA product ID and revision level.

2.8.1 Product ID and revision level

OTP bytes 31 and 30 are programmed at ST factory before shipment and may be read by

firmware to determine the STR91xFA product type and silicon revision so it can optionally take

action based on the silicon on which it is running. Byte 31 contains the the major family

identifier of "9" (for STR9) in the high-nibble location, and the minor family identifier in the low-

nibble location. Today the low-nibble contains "1", but future family members may have other

11/78

Functional overview

STR91xFA

values indicating memory size or other differentiating features. Byte 30 contains the silicon

revision level indicator. See Table 2 for values related to the two revisions of STR9 production

devices. See the Errata Sheet documents for STR91xF and STR91xFA for details of external

identification of silicon revisions.

Table 2.

Product ID and revision level values

Production salestype

Silicon revision

OTP byte 31

OTP byte 30

STR91xFxxxxx

STR91xFAxxxxx

Rev D

Rev G

91h

03h

20h

2.9

Vectored interrupt controller (VIC)

Interrupt management in the STR91xFA is implemented from daisy-chaining two standard ARM

VIC units. This combined VIC has 32 prioritized interrupt request channels and generates two

interrupt output signals to the CPU. The output signals are FIQ and IRQ, with FIQ having higher

priority.

2.9.1 FIQ handling

FIQ (Fast Interrupt reQuest) is the only non-vectored interrupt and the CPU can execute an

Interrupt Service Routine (ISR) directly without having to determine/prioritize the interrupt

source, minimizing ISR latency. Typically only one interrupt source is assigned to FIQ. An FIQ

interrupt has its own set of banked registers to minimize the time to make a context switch. Any

of the 32 interrupt request input signals coming into the VIC can be assigned to FIQ.

2.9.2 IRQ handling

IRQ is a vectored interrupt and is the logical OR of all 32 interrupt request signals coming into

the 32 IRQ channels. Priority of individual vectored interrupt requests is determined by

hardware (IRQ channel Intr 0 is highest priority, IRQ channel Intr 31 is lowest).

However, inside the same VIC (primary or secondary VIC), CPU firmware may re-assign

individual interrupt sources to individual hardware IRQ channels, meaning that firmware can

effectively change interrupt priority levels as needed within the same VIC (from priority 0 to

priority 16).

Note:

Note: VIC0 (primary VIC) interrupts always have higher priority than VIC1 (secondary VIC)

interrupts

When the IRQ signal is activated by an interrupt request, VIC hardware will resolve the IRQ

interrupt priority, then the ISR reads the VIC to determine both the interrupt source and the

vector address to jump to the service code.

The STR91xFA has a feature to reduce ISR response time for IRQ interrupts. Typically, it

requires two memory accesses to read the interrupt vector address from the VIC, but the

STR91xFA reduces this to a single access by adding a 16th entry in the instruction branch

cache, dedicated for interrupts. This 16th cache entry always holds the instruction that reads

the interrupt vector address from the VIC, eliminating one of the memory accesses typically

required in traditional ARM implementations.

12/78

STR91xFA

Functional overview

2.9.3 Interrupt sources

The 32 interrupt request signals coming into the VIC on 32 IRQ channels are from various

sources; 5 from a wake-up unit and the remaining 27 come from internal sources on the

STR91xFA such as on-chip peripherals, see Table 3. Optionally, firmware may force an

interrupt on any IRQ channel.

One of the 5 interrupt requests generated by the wake-up unit (IRQ25 in Table 3) is derived

from the logical OR of all 32 inputs to the wake-up unit. Any of these 32 inputs may be used to

wake up the CPU and cause an interrupt. These 32 inputs consist of 30 external interrupts on

selected and enabled GPIO pins, plus the RTC interrupt, and the USB Resume interrupt.

Each of 4 remaining interrupt requests generated by the wake-up unit (IRQ26 in Table 3) are

derived from groupings of 8 interrupt sources. One group is from GPIO pins P3.2 to P3.7 plus

the RTC interrupt and the USB Resume interrupt; the next group is from pins P5.0 to P5.7; the

next group is from pins P6.0 to P6.7; and last the group is from pins P7.0 to P7.7. This allows

individual pins to be assigned directly to vectored IRQ interrupts or one pin assigned directly to

the non-vectored FIQ interrupt.

Table 3.

VIC IRQ Channels

IRQ Channel

hardware

priority

VIC input

channel

Logic Block

Interrupt Source

0 (high priority)

VIC0.0

VIC0.1

VIC0.2

VIC0.3

VIC0.4

VIC0.5

VIC0.6

VIC0.7

VIC0.8

VIC0.9

VIC0.10

WatchDog

CPU Firmware

CPU Core

TIM Timer 0

TIM Timer 1

TIM Timer 2

TIM Timer 3

USB

Timeout in WDT mode, Terminal Count in Counter Mode

Firmware generated interrupt

1

2

Debug Receive Command

3

Debug Transmit Command

4

Logic OR of ICI0_0, ICI0_1, OCI0_0, OCI0_1, Timer overflow

Logic OR of ICI1_0, ICI1_1, OCI1_0, OCI1_1, Timer overflow

Logic OR of ICI2_0, ICI2_1, OCI2_0, OCI2_1, Timer overflow

Logic OR of ICI3_0, ICI3_1, OCI3_0, OCI3_1, Timer overflow

Logic OR of high priority USB interrupts

5

6

7

8

9

USB

Logic OR of low priority USB interrupts

10

CCU

Logic OR of all interrupts from Clock Control Unit

Logic OR of Ethernet MAC interrupts via its own dedicated

DMA channel.

11

12

VIC0.11

VIC0.12

Ethernet MAC

DMA

Logic OR of interrupts from each of the 8 individual DMA

channels

13

14

15

16

17

18

VIC0.13

VIC0.14

VIC0.15

VIC1.0

VIC1.1

VIC1.2

CAN

IMC

Logic OR of all CAN interface interrupt sources

Logic OR of 8 Induction Motor Control Unit interrupts

End of AtoD conversion interrupt

ADC

UART0

UART1

UART2

Logic OR of 5 interrupts from UART channel 0

Logic OR of 5 interrupts from UART channel 1

Logic OR of 5 interrupts from UART channel 2

Logic OR of transmit, receive, and error interrupts of I2C

channel 0

19

20

VIC1.3

VIC1.4

I2C0

I2C1

Logic OR of transmit, receive, and error interrupts of I2C

channel 1

21

22

23

24

VIC1.5

VIC1.6

VIC1.7

VIC1.8

SSP0

SSP1

Logic OR of all interrupts from SSP channel 0

Logic OR of all interrupts from SSP channel 1

LVD warning interrupt

BROWNOUT

RTC

Logic OR of Alarm, Tamper, or Periodic Timer interrupts

13/78

Functional overview

STR91xFA

Table 3.

VIC IRQ Channels

IRQ Channel

hardware

priority

VIC input

channel

Logic Block

Interrupt Source

Logic OR of all 32 inputs of Wake-Up unit (30 pins, RTC, and

USB Resume)

25

26

VIC1.9

Wake-Up (all)

Logic OR of 8 interrupt sources: RTC, USB Resume, pins

P3.2 to P3.7

VIC1.10

Wake-up Group 0

27

28

29

30

VIC1.11

VIC1.12

VIC1.13

VIC1.14

Wake-up Group 1 Logic OR of 8 interrupts from pins P5.0 to P5.7

Wake-up Group 2 Logic OR of 8 interrupts from pins P6.0 to P6.7

Wake-up Group 3 Logic OR of 8 interrupts from pins P7.0 to P7.7

USB

USB Bus Resume Wake-up (also input to wake-up unit)

Special use of interrupts from Prefetch Queue and Branch

Cache

31 (low priority)

VIC1.15

PFQ-BC

2.10 Clock control unit (CCU)

The CCU generates a master clock of frequency f

. From this master clock the CCU also

MSTR

generates individually scaled and gated clock sources to each of the following functional blocks

within the STR91xFA.

●

CPU, f

CPUCLK

Advanced High-performance Bus (AHB), f

HCLK

Advanced Peripheral Bus (APB), f

PCLK

Flash Memory Interface (FMI), f

FMICLK

External Memory Interface (EMI), f

BCLK

BAUD

UART Baud Rate Generators, f

USB, f

USB

2.10.1 Master clock sources

The master clock in the CCU (f

) is derived from one of three clock input sources. Under

MSTR

firmware control, the CPU can switch between the three CCU inputs without introducing any

glitches on the master clock output. Inputs to the CCU are:

●

Main Oscillator (f

). The source for the main oscillator input is a 4 to 25 MHz external

OSC

crystal connected to STR91xFA pins X1_CPU and X2_CPU, or an external oscillator

device connected to pin X1_CPU.

●

PLL (f ). The PLL takes the 4 to 25 MHz oscillator clock as input and generates a master

PLL

clock output up to 96 MHz (programmable). By default, at power-up the master clock is

sourced from the main oscillator until the PLL is ready (locked) and then the CPU may

switch to the PLL source under firmware control. The CPU can switch back to the main

oscillator source at any time and turn off the PLL for low-power operation. The PLL is

always turned off in Sleep mode.

●

RTC (f

). A 32.768 kHz external crystal can be connected to pins X1_RTC and

RTC

X2_RTC, or an external oscillator connected to pin X1_RTC to constantly run the real-time

clock unit. This 32.768 kHz clock source can also be used as an input to the CCU to run

the CPU in slow clock mode for reduced power.

14/78

STR91xFA

Functional overview

As an option, there are a number of peripherals that do not have to receive a clock sourced

from the CCU. The USB interface can receive an external clock on pin P2.7, TIM timers TIM0/

TIM1 can receive an external clock on pin P2.4, and timers TIM2/TIM3 on pin P2.5.

Figure 2. Clock control

32.768 kHz

25MHz

RTCSEL

PHYSEL

JRTCLK

EMI_BCLK

1/2

MII_PHYCLK

HCLK

PCLK

RCLK

AHB DIV

X1_CPU

f

MSTR

f

Main

OSC

PLL

RCLK

DIV

4-25MHz

PLL

(1,2,4)

f

OSC

APB DIV)

(1,2,4,8)

(1,2,4,8,16,1024)

Master CLK

32.768 kHz

X1_RTC

X2_RTC

RTC

OSC

f

RTC

FMICLK

1/2

Timer 0 & 1

CPUCLK

EXTCLK_T0T1

External clock

BRCLK

Timer 2 & 3

To UART

1/2

EXTCLK_T2T3

USB_CLK48M

External clock

USBCLK

To USB

48MHz

2.10.2 Reference clock (RCLK)

The main clock (f

) can be divided to operate at a slower frequency reference clock (RCLK)

MSTR

for the ARM core and all the peripherals. The RCLK provides the divided clock for the ARM

core, and feeds the dividers for the AHB, APB, External Memory Interface, and FMI units.

2.10.3 AHB clock (HCLK)

The RCLK can be divided by 1, 2 or 4 to generate the AHB clock. The AHB clock is the bus

clock for the AHB bus and all bus transfers are synchronized to this clock. The maximum HCLK

frequency is 96 MHz.

2.10.4 APB clock (PCLK)

The RCLK can be divided by 1, 2, 4 or 8 to generate the APB clock. The APB clock is the bus

clock for the APB bus and all bus transfers are synchronized to this clock. Many of the

peripherals that are connected to the AHB bus also use the PCLK as the source for external

bus data transfers. The maximum PCLK frequency is 48 MHz.

2.10.5 Flash memory interface clock (FMICLK)

The FMICLK clock is an internal clock derived from RCLK, defaulting to RCLK frequency at

power up. The clock can be optionally divided by 2. The FMICLK determines the bus bandwidth

15/78

Functional overview

STR91xFA

between the ARM core and the Flash memory. Typically, codes in the Flash memory can be

fetched one word per FMICLK clock in burst mode. The maximum FMICLK frequency is

96MHz.

2.10.6 Baud rate clock (BRCLK)

The baud rate clock is an internal clock derived from f

that is used by the three on-chip

MSTR

UART peripherals for baudrate generation. The frequency can be optionally divided by 2.

2.10.7 External memory interface bus clock (BCLK)

The BCLK is an internal clock that controls the EMI bus. All EMI bus signals are synchronized

to the BCLK. The BCLK is derived from the HCLK and the frequency can be configured to be

the same or half that of the HCLK. Refer to Table 12 on page 53 for the maximum BCLK

frequency (f

). The BCLK clock is available on the LFBGA package as an output pin.

BCLK

2.10.8 USB interface clock

Special consideration regarding the USB interface: The clock to the USB interface must operate

at 48 MHz and comes from one of three sources, selected under firmware control:

●

CCU master clock output of 48 MHz.

●

CCU master clock output of 96 MHz. An optional divided-by-two circuit is available to

produce 48 MHz for the USB while the CPU system runs at 96MHz.

●

STR91xFA pin P2.7. An external 48 MHz oscillator connected to pin P2.7 can directly

source the USB while the CCU master clock can run at some frequency other than 48 or

96 MHz.

2.10.9 Ethernet MAC clock

Special consideration regarding the Ethernet MAC: The external Ethernet PHY interface device

requires it’s own 25 MHz clock source. This clock can come from one of two sources:

●

A 25 MHz clock signal coming from a dedicated output pin (P5.2) of the STR91xFA. In this

case, the STR91xFA must use a 25 MHz signal on its main oscillator input in order to pass

this 25 MHz clock back out to the PHY device through pin P5.2. The advantage here is that

an inexpensive 25 MHz crystal may be used to source a clock to both the STR91xFA and

the external PHY device.

●

An external 25 MHz oscillator connected directly to the external PHY interface device. In

this case, the STR91xFA can operate independent of 25 MHz.

2.10.10 External RTC calibration clock

The RTC_CLK can be enabled as an output on the JRTCK pin. The RTC_CLK is used for RTC

oscillator calibration. The RTC_CLK is active in Sleep mode and can be used as a system wake

up control clock.

2.10.11 Operation example

As an example of CCU operation, a 25 MHz crystal can be connected to the main oscillator

input on pins X1_CPU and X2_CPU, a 32.768 kHz crystal connected to pins X1_RTC and

X2_RTC, and the clock input of an external Ethernet PHY device is connected to STR91xFA

output pin P5.2. In this case, the CCU can run the CPU at 96 MHz from PLL, the USB interface

16/78

STR91xFA

Functional overview

at 48 MHz, and the Ethernet interface at 25 MHz. The RTC is always running in the background

at 32.768 kHz, and the CPU can go to very low power mode dynamically by running from

32.768 kHz and shutting off peripheral clocks and the PLL as needed.

2.11 Flexible power management

The STR91xFA offers configurable and flexible power management control that allows the user

to choose the best power option to fit the application. Power consumption can be dynamically

managed by firmware and hardware to match the system’s requirements. Power management

is provided via clock control to the CPU and individual peripherals.

Clocks to the CPU and peripherals can be individually divided and gated off as needed. In

addition to individual clock divisors, the CCU master clock source going to the CPU, AHB, APB,

EMI, and FMI can be divided dynamically by as much as 1024 for low power operation.

Additionally, the CCU may switch its input to the 32.768 kHz RTC clock at any time for low

power.

The STR91xFA supports the following three global power control modes:

●

Run Mode: All clocks are on with option to gate individual clocks off via clock mask

registers.

Idle Mode: CPU and FMI clocks are off until an interrupt, reset, or wake-up occurs. Pre-

configured clock mask registers selectively allow individual peripheral clocks to continue

run during Idle Mode.

●

Sleep Mode: All clocks off except RTC clock. Wake up unit remains powered, PLL is

forced off.

A special mode is used when JTAG debug is active which never gates off any clocks even if the

CPU enters Idle or Sleep mode.

2.11.1 Run mode

This is the default mode after any reset occurs. Firmware can gate off or scale any individual

clock. Also available is a special Interrupt Mode which allows the CPU to automatically run full

speed during an interrupt service and return back to the selected CPU clock divisor rate when

the interrupt has been serviced. The advantage here is that the CPU can run at a very low

frequency to conserve power until a periodic wake-up event or an asynchronous interrupt

occurs at which time the CPU runs full speed immediately.

2.11.2 Idle mode

In this mode the CPU suspends code execution and the CPU and FMI clocks are turned off

immediately after firmware sets the Idle Bit. Various peripherals continue to run based on the

settings of the mask registers that exist just prior to entering Idle Mode. There are 3 ways to exit

Idle Mode and return to Run Mode:

●

Any reset (external reset pin, watchdog, low-voltage, power-up, JTAG debug command)

Any interrupt (external, internal peripheral, RTC alarm or interval)

Input from wake-up unit on GPIO pins

Note:

It is possible to remain in Idle Mode for the majority of the time and the RTC can be

programmed to periodically wake up to perform a brief task or check status.

17/78

Functional overview

STR91xFA

2.11.3 Sleep mode

In this mode all clock circuits except the RTC are turned off and main oscillator input pins

X1_CPU and X2_CPU are disabled. The RTC clock is required for the CPU to exit Sleep Mode.

The entire chip is quiescent (except for RTC and wake-up circuitry). There are three means to

exit Sleep Mode and re-start the system:

●

Some resets (external reset pin, low-voltage, power-up, JTAG debug command)

RTC alarm

Input from wake-up unit

2.12 Voltage supplies

The STR91xFA requires two separate operating voltage supplies. The CPU and memories

operate from a 1.65V to 2.0V on the VDD pins, and the I/O ring operates at 2.7V to 3.6V on the

VDDQ pins.

2.12.1 Independent A/D converter supply and reference voltage

The ADC unit on 128-pin and 144-ball packages has an isolated analog voltage supply input at

pin AVDD to accept a very clean voltage source, independent of the digital voltage supplies.

Additionally, an isolated analog supply ground connection is provided on pin AVSS only on 128-

pin and 144-ball packages for further ADC supply isolation. On 80-pin packages, the analog

voltage supply is shared with the ADC reference voltage pin (as described next), and the

analog ground is shared with the digital ground at a single point in the STR91xFA device on pin

AVSS_VSSQ.

A separate external analog reference voltage input for the ADC unit is available on 128-pin and

144-ball packages at the AVREF pin for better accuracy on low voltage inputs. For 80-pin

packages, the ADC reference voltage is tied internally to the ADC unit supply voltage at pin

AVREF_AVDD, meaning the ADC reference voltage is fixed to the ADC unit supply voltage.

See Table 7: Operating conditions, for restrictions to the relative voltage levels of VDDQ, AVDD,

AVREF, and AVREF_AVDD.

2.12.2 Battery supply

An optional stand-by voltage from a battery or other source may be connected to pin VBATT to

retain the contents of SRAM in the event of a loss of the V supply. The SRAM will

DD

automatically switch its supply from the internal V source to the VBATT pin when the voltage

DD

of V drops below that of VBATT.

DD

The VBATT pin also supplies power to the RTC unit, allowing the RTC to function even when

the main digital supplies (V and V

) are switched off. By configuring the RTC register, it is

DD

DDQ

possible to select whether or not to power from VBATT only the RTC unit, or power the RTC unit

and the SRAM when the STR91xFA device is powered off.

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STR91xFA

Functional overview

2.13 System supervisor

The STR91xFA monitors several system and environmental inputs and will generate a global

reset, a system reset, or an interrupt based on the nature of the input and configurable settings.

A global reset clears all functions on the STR91xFA, a system reset will clear all but the Clock

Control Unit (CCU) settings and the system status register. At any time, firmware may reset

individual on-chip peripherals. System supervisor inputs include:

●

GR: CPU voltage supply (V ) drop out or brown out

DD

●

GR: I/O voltage supply (V

GR: Power-Up condition

) drop out or brown out

DDQ

●

SR: Watchdog timer timeout

SR: External reset pin (RESET_INn)

SR: JTAG debug reset command

Note:

GR: means the input causes Global Reset, SR: means the input causes System Reset

The CPU may read a status register after a reset event to determine if the reset was caused by

a watchdog timer timeout or a voltage supply drop out. This status register is cleared only by a

power up reset.

2.13.1 Supply voltage brownout

Each operating voltage source (V and V

) is monitored separately by the Low Voltage

DDQ

DD

Detect (LVD) circuitry. The LVD will generate an early warning interrupt to the CPU when

voltage sags on either V or V voltage inputs. This is an advantage for battery powered

DD

DDQ

applications because the system can perform an orderly shutdown before the batteries become

too weak. The voltage trip point to cause a brown out interrupt is typically 0.25V above the LVD

dropout thresholds that cause a reset.

CPU firmware may prevent all brown-out interrupts by writing to interrupt mask registers at run-

time.

2.13.2 Supply voltage dropout

LVD circuitry will always cause a global reset if the CPU’s V source drops below it’s fixed

DD

threshold of 1.4V.

However, the LVD trigger threshold to cause a global reset for the I/O ring’s V

source is set

DDQ

to one of two different levels, depending if V

will be operated in the range of 2.7V to 3.3V, or

DDQ

3.0V to 3.6V. If V

operation is at 2.7V to 3.3V, the LVD dropout trigger threshold is 2.4V. If

DDQ

V

operation is 3.0V and 3.6V, the LVD threshold is 2.7V. The choice of trigger level is made

DDQ

by STR91xFA device configuration software from STMicroelectronics or IDE from 3rd parties,

and is programmed into the STR91xFA device along with other configurable items through the

JTAG interface when the Flash memory is programmed.

CPU firmware may prevent some LVD resets if desired by writing a control register at run-time.

Firmware may also disable the LVD completely for lowest-power operation when an external

LVD device is being used.

2.13.3 Watchdog timer

The STR91xFA has a 16-bit down-counter (not one of the four TIM timers) that can be used as

a watchdog timer or as a general purpose free-running timer/counter. The clock source is the

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Functional overview

STR91xFA

peripheral clock from the APB, and an 8-bit clock pre-scaler is available. When enabled by

firmware as a watchdog, this timer will cause a system reset if firmware fails to periodically

reload this timer before the terminal count of 0x0000 occurs, ensuring firmware sanity. The

watchdog function is off by default after a reset and must be enabled by firmware.

2.13.4 External RESET_INn pin

This input signal is active-low with hystereses (V

). Other open-drain, active-low system

RHYS

reset signals on the circuit board (such as closure to ground from a push-button) may be

connected directly to the RESET_INn pin, but an external pull-up resistor to V

present as there is no internal pullup on the RESET_INn pin.

must be

DDQ

A valid active-low input signal of t

duration on the RESET_INn pin will cause a system

RINMIN

reset within the STR91xFA. There is also a RESET_OUTn pin on the STR91xFA that can drive

other system components on the circuit board. RESET_OUTn is active-low and has the same

timing of the Power-On-Reset (POR) shown next, t

.

POR

2.13.5 Power-up

The LVD circuitry will always generate a global reset when the STR91xFA powers up, meaning

internal reset is active until V and V are both above the LVD thresholds. This POR

DDQ

DD

condition has a duration of t

, after which the CPU will fetch its first instruction from address

POR

0x0000.0000 in Flash memory. It is not possible for the CPU to boot from any other source

other than Flash memory.

2.13.6 JTAG debug command

When the STR91xFA is in JTAG debug mode, an external device which controls the JTAG

interface can command a system reset to the STR91xFA over the JTAG channel.

2.13.7 Tamper detection

On 128-pin and 144-ball STR91xFA devices only, there is a tamper detect input pin,

TAMPER_IN, used to detect and record the time of a tamper event on the end product such as

malicious opening of an enclosure, unwanted opening of a panel, etc. The activation mode of

the tamper pin is programmable to one of two modes. One is Normally Closed/Tamper Open,

the other mode will detect when a signal on the tamper input pin is driven from low-to-high, or

high-to-low depending on firmware configuration. Once a tamper event occurs, the RTC time

(millisecond resolution) and the date are recorded in the RTC unit. Simultaneously, the SRAM

standby voltage source will be cut off to invalidate all SRAM contents. Tamper detection control

and status logic are part of the RTC unit.

2.14 Real-time clock (RTC)

The RTC combines the functions of a complete time-of-day clock (millisecond resolution) with

an alarm programmable up to one month, a 9999-year calender with leap-year support,

periodic interrupt generation from 1 to 512 Hz, tamper detection (described in Section 2.13.7),

and an optional clock calibration output on the JRTCK pin. The time is in 24 hour mode, and

time/calendar values are stored in binary-coded decimal format.

The RTC also provides a self-isolation mode that is automatically activated during power down.

This feature allows the RTC to continue operation when V

and V are absent, as long as

DDQ

DD

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STR91xFA

Functional overview

an alternate power source, such as a battery, is connected to the VBATT input pin. The current

drawn by the RTC unit on the VBATT pin is very low in this standby mode, I

.

RTC_STBY

2.15 JTAG interface

An IEEE-1149.1 JTAG interface on the STR91xFA provides In-System-Programming (ISP) of

all memory, boundary scan testing of pins, and the capability to debug the CPU.

STR91xFA devices are shipped from ST with blank Flash memories. The CPU can only boot

from Flash memory (selection of which Flash bank is programmable). Firmware must be initially

programmed through JTAG into one of these Flash memories before the STR91xFA is used.

Six pins are used on this JTAG serial interface. The five signals JTDI, JTDO, JTMS, JTCK, and

JTRSTn are all standard JTAG signals complying with the IEEE-1149.1 specification. The sixth

signal, JRTCK (Return TCK), is an output from the STR91xFA and it is used to pace the JTCK

clock signal coming in from the external JTAG test equipment for debugging. The frequency of

the JTCK clock signal coming from the JTAG test equipment must be at least 10 times less than

the ARM966E-S CPU core operating frequency (f

). To ensure this, the signal JRTCK is

CPUCLK

output from the STR91xFA and is input to the external JTAG test equipment to hold off

transitions of JTCK until the CPU core is ready, meaning that the JTAG equipment cannot send

the next rising edge of JTCK until the equipment receives a rising edge of JRTCK from the

STR91xFA. The JTAG test equipment must be able to interpret the signal JRTCK and perform

this adaptive clocking function. If it is known that the CPU clock will always be at least ten times

faster than the incoming JTCK clock signal, then the JRTCK signal is not needed.

The two die inside the STR91xFA (CPU die and Flash memory die) are internally daisy-chained

on the JTAG bus, see Figure 3 on page 22. The CPU die has two JTAG Test Access Ports

(TAPs), one for boundary scan functions and one for ARM CPU debug. The Flash memory die

has one TAP for program/erase of non-volatile memory. Because these three TAPs are daisy-

chained, only one TAP will converse on the JTAG bus at any given time while the other two

TAPs are in BYPASS mode. The TAP positioning order within this JTAG chain is the boundary

scan TAP first, followed by the ARM debug TAP, followed by the Flash TAP. All three TAP

controllers are reset simultaneously by one of two methods:

●

A chip-level global reset, caused only by a Power-On-Reset (POR) or a Low Voltage

Detect (LVD).

●

A reset command issued by the external JTAG test equipment. This can be the assertion

of the JTAG JTRSTn input pin on the STR91xFA or a JTAG reset command shifted into the

STR91xFA serially.

This means that chip-level system resets from watchdog time-out or the assertion of

RESET_INn pin do not affect the operation of any JTAG TAP controller. Only global resets

effect the TAPs.

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Functional overview

STR91xFA

Figure 3. JTAG chaining inside the STR91xFA

STR91xx

BURST FLASH

MEMORY DIE

MAIN FLASH

SECONDARY FLASH

JTAG

Instruction

register length

is 8 bits

JTAG TAP CONTROLLER #3

TDI

TDO

TMS TCK TRST

JTDO

JTRSTn

JTCK

JTMS

JTDI

ARM966ES DIE

JRTCK

JTAG

Instruction

TMS TCK TRST

TDO

TMS

TDO

TDI

TRST TCK

register length:

5 bits for TAP #1

4 bits for TAP #2

JTAG TAP CONTROLLER #1

JTAG TAP CONTROLLER #2

BOUNDARY SCAN

CPU DEBUG

2.15.1 In-system-programming

The JTAG interface is used to program or erase all memory areas of the STR91xFA device. The

pin RESET_INn must be asserted during ISP to prevent the CPU from fetching invalid

instructions while the Flash memories are being programmed.

Note that the 32 bytes of OTP memory locations cannot be erased by any means once

programmed by JTAG ISP or the CPU.

2.15.2 Boundary scan

Standard JTAG boundary scan testing compliant with IEEE-1149.1 is available on the majority

of pins of the STR91xFA for circuit board test during manufacture of the end product.

STR91xFA pins that are not serviced by boundary scan are the following:

●

JTAG pins JTCK, JTMS, JTDI, JTDO, JTRSTn, JRTCK

Oscillator input pins X1_CPU, X2_CPU, X1_RTC, X2_RTC

Tamper detect input pin TAMPER_IN (128-pin and 144-pin packages only)

2.15.3 CPU debug

The ARM966E-S CPU core has standard ARM EmbeddedICE-RT logic, allowing the

STR91xFA to be debugged through the JTAG interface. This provides advanced debugging

features making it easier to develop application firmware, operating systems, and the hardware

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STR91xFA

Functional overview

itself. Debugging requires that an external host computer, running debug software, is connected

to the STR91xFA target system via hardware which converts the stream of debug data and

commands from the host system’s protocol (USB, Ethernet, etc.) to the JTAG EmbeddedICE-

RT protocol on the STR91xFA. These protocol converters are commercially available and

operate with debugging software tools.

The CPU may be forced into a Debug State by a breakpoint (code fetch), a watchpoint (data

access), or an external debug request over the JTAG channel, at which time the CPU core and

memory system are effectively stopped and isolated from the rest of the system. This is known

as Halt Mode and allows the internal state of the CPU core, memory, and peripherals to be

examined and manipulated. Typical debug functions are supported such as run, halt, and

single-step. The EmbeddedICE-RT logic supports two hardware compare units. Each can be

configured to be either a watchpoint or a breakpoint. Breakpoints can also be data-dependent.

Debugging (with some limitations) may also occur through the JTAG interface while the CPU is

running full speed, known as Monitor Mode. In this case, a breakpoint or watchpoint will not

force a Debug State and halt the CPU, but instead will cause an exception which can be tracked

by the external host computer running monitor software. Data can be sent and received over

the JTAG channel without affecting normal instruction execution. Time critical code, such as

Interrupt Service Routines may be debugged real-time using Monitor Mode.

2.15.4 JTAG security bit

This is a non-volatile bit (Flash memory based), which when set will not allow the JTAG

debugger or JTAG programmer to read the Flash memory contents.

Using JTAG ISP, this bit is typically programmed during manufacture of the end product to

prevent unwanted future access to firmware intellectual property. The JTAG Security Bit can be

cleared only by a JTAG “Full Chip Erase” command, making the STR91xFA device blank and

ready for programming again. The CPU can read the status of the JTAG Security Bit, but it may

not change the bit value.

2.16 Embedded trace module (ARM ETM9, v. r2p2)

The ETM9 interface provides greater visibility of instruction and data flow happening inside the

CPU core by streaming compressed data at a very high rate from the STR91xFA though a

small number of ETM9 pins to an external Trace Port Analyzer (TPA) device. The TPA is

connected to a host computer using USB, Ethernet, or other high-speed channel. Real-time

instruction flow and data activity can be recorded and later formatted and displayed on the host

computer running debugger software, and this software is typically integrated with the debug

software used for EmbeddedICE-RT functions such as single-step, breakpoints, etc. Tracing

may be triggered and filtered by many sources, such as instruction address comparators, data

watchpoints, context ID comparators, and counters. State sequencing of up to three triggers is

also provided. TPA hardware is commercially available and operates with debugging software

tools.

The ETM9 interface is nine pins total, four of which are data lines, and all pins can be used for

GPIO after tracing is no longer needed. The ETM9 interface is used in conjunction with the

JTAG interface for trace configuration. When tracing begins, the ETM9 engine compresses the

data by various means before broadcasting data at high speed to the TPA over the four data

lines. The most common ETM9 compression technique is to only output address information

when the CPU branches to a location that cannot be inferred from the source code. This means

23/78

Functional overview

STR91xFA

the host computer must have a static image of the code being executed for decompressing the

ETM9 data. Because of this, self-modified code cannot be traced.

2.17 Ethernet MAC interface with DMA

STR91xFA devices in 128-pin and 144-ball packages provide an IEEE-802.3-2002 compliant

Media Access Controller (MAC) for Ethernet LAN communications through an industry

standard Medium Independent Interface (MII). The STR91xFA requires an external Ethernet

physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.).

The PHY is connected to the STR91xFA MII port using as many as 18 signals (see pins which

have signal names MII_* in Table 5).

The MAC corresponds to the OSI Data Link layer and the PHY corresponds to the OSI Physical

layer. The STR91xFA MAC is responsible for:

●

Data encapsulation, including frame assembly before transmission, and frame parsing/

error detection during and after reception.

●

Media access control, including initiation of frame transmission and recover from

transmission failure.

The STR91xFA MAC includes the following features:

●

Supports 10 and 100 Mbps rates

Tagged MAC frame support (VLAN support)

Half duplex (CSMA/CD) and full duplex operation

MAC control sublayer (control frames) support

32-bit CRC generation and removal

Several address filtering modes for physical and multicast address (multicast and group

addresses)

●

32-bit status code for each transmitted or received frame

Internal FIFOs to buffer transmit and receive frames. Transmit FIFO depth is 4 words (32

bits each), and the receive FIFO is 16 words deep.

A 32-bit burst DMA channel residing on the AHB is dedicated to the Ethernet MAC for high-

speed data transfers, side-stepping the CPU for minimal CPU impact during transfers. This

DMA channel includes the following features:

●

Direct SRAM to MAC transfers of transmit frames with the related status, by descriptor

chain

Direct MAC to SRAM transfers of receive frames with the related status, by descriptor

chain

Open and Closed descriptor chain management

2.18 USB 2.0 slave device interface with DMA

The STR91xFA provides a USB slave controller that implements both the OSI Physical and

Data Link layers for direct bus connection by an external USB host on pins USBDP and

USBPN. The USB interface detects token packets, handles data transmission and reception,

and processes handshake packets as required by the USB 2.0 standard.

The USB slave interface includes the following features:

24/78

STR91xFA

Functional overview

●

Supports USB low and full-speed transfers (12 Mbps), certified to comply with the USB 2.0

specification

●

Supports isochronous, bulk, control, and interrupt endpoints

Configurable number of endpoints allowing a mixture of up to 20 single-buffered

monodirectional endpoints or up to 10 double-buffered bidirectional endpoints

●

Dedicated, dual-port 2 Kbyte USB Packet Buffer SRAM. One port of the SRAM is

connected by a Packet Buffer Interface (PBI) on the USB side, and the CPU connects to

the other SRAM port.

●

CRC generation and checking

NRZI encoding-decoding and bit stuffing

USB suspend resume operations

2.18.1 Packet buffer interface (PBI)

The PBI manages a set of buffers inside the 2 Kbyte Packet Buffer, both for transmission and

reception. The PBI will choose the proper buffer according to requests coming from the USB

Serial Interface Engine (SIE) and locate it in the Packet SRAM according to addresses pointed

by endpoint registers. The PBI will also auto-increment the address after each exchanged byte

until the end of packet, keeping track of the number of exchanged bytes and preventing buffer

overrun. Special support is provided by the PBI for isochronous and bulk transfers,

implementing double-buffer usage which ensures there is always an available buffer for a USB

packet while the CPU uses a different buffer.

2.18.2 DMA

A programmable DMA channel may be assigned by CPU firmware to service the USB interface

for fast and direct transfers between the USB bus and SRAM with little CPU involvement. This

DMA channel includes the following features:

●

Direct USB Packet Buffer SRAM to system SRAM transfers of receive packets, by

descriptor chain for bulk or isochronous endpoints.

Direct system SRAM to USB Packet Buffer SRAM transfers of transmit packets, by

descriptor chain for bulk or isochronous endpoints.

Linked-list descriptor chain support for multiple USB packets

2.18.3 Suspend mode

CPU firmware may place the USB interface in a low-power suspend mode when required, and

the USB interface will automatically wake up asynchronously upon detecting activity on the

USB pins.

2.19 CAN 2.0B interface

The STR91xFA provides a CAN interface complying with CAN protocol version 2.0 parts A and

B. An external CAN transceiver device connected to pins CAN_RX and CAN_TX is required for

connection to the physical CAN bus.

The CAN interface manages up to 32 Message Objects and Identifier Masks using a Message

SRAM and a Message Handler. The Message Handler takes care of low-level CAN bus activity

such as acceptance filtering, transfer of messages between the CAN bus and the Message

25/78

Functional overview

STR91xFA

SRAM, handling of transmission requests, and interrupt generation. The CPU has access to

the Message SRAM via the Message Handler using a set of 38 control registers.

The follow features are supported by the CAN interface:

●

Bitrates up to 1 Mbps

Disable Automatic Retransmission mode for Time Triggered CAN applications

32 Message Objects

Each Message Object has its own Identifier Mask

Programmable FIFO mode

Programmable loopback mode for self-test operation

The CAN interface is not supported by DMA.

2.20 UART interfaces with DMA

The STR91xFA supports three independent UART serial interfaces, designated UART0,

UART1, and UART2. Each interface is very similar to the industry-standard 16C550 UART

device. All three UART channels support IrDA encoding/decoding, requiring only an external

LED transceiver to pins UARTx_RX and UARTx_Tx for communication. One UART channel

(UART0) supports full modem control signals.

UART interfaces include the following features:

●

Maximum baud rate of 1.5 Mbps

●

Separate FIFOs for transmit and receive, each 16 deep, each FIFO can be disabled by

firmware if desired

●

Programmable FIFO trigger levels between 1/8 and 7/8

Programmable baud rate generator based on CCU master clock, or CCU master clock

divided by two

●

Programmable serial data lengths of 5, 6, 7, or 8 bits with start bit and 1 or 2 stop bits

Programmable selection of even, odd, or no-parity bit generation and detection

False start-bit detection

Line break generation and detection

Support of IrDA SIR ENDEC functions for data rates of up to 115.2K bps

IrDA bit duration selection of 3/16 or low-power (1.14 to 2.23 µsec)

Channel UART0 supports modem control functions CTS, DCD, DSR, RTS, DTR, and RI

For your reference, only two standard 16550 UART features are not supported, 1.5 stop bits

and independent receive clock.

2.20.1 DMA

A programmable DMA channel may be assigned by CPU firmware to service channels UART0

and UART1 for fast and direct transfers between the UART bus and SRAM with little CPU

involvement. Both DMA single-transfers and DMA burst-transfers are supported for transmit

and receive. Burst transfers require that UART FIFOs are enabled.

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STR91xFA

Functional overview

2.21 I²C interfaces with DMA

The STR91xFA supports two independent I2C serial interfaces, designated I2C0, and I2C1.

Each interface allows direct connection to an I2C bus as either a bus master or bus slave

device (firmware configurable). I2C is a two-wire communication channel, having a bi-

directional data signal and a single-directional clock signal based on open-drain line drivers,

requiring external pull-up resistors.

Byte-wide data is transferred between a Master device and a Slave device on two wires. More

than one bus Master is allowed, but only one Master may control the bus at any given time.

Data is not lost when another Master requests the use of a busy bus because I2C supports

collision detection and arbitration. More than one Slave device may be present on the bus, each

having a unique address. The bus Master initiates all data movement and generates the clock

that permits the transfer. Once a transfer is initiated by the Master, any device that is addressed

is considered a Slave. Automatic clock synchronization allows I2C devices with different bit

rates to communicate on the same physical bus. A single device can play the role of Master or

Slave, or a single device can be a Slave only. A Master or Slave device has the ability to

suspend data transfers if the device needs more time to transmit or receive data.

Each I2C interface on the STR91xFA has the following features:

●

Programmable clock supports various rates up to I2C Standard rate (100 KHz) or Fast rate

(400 KHz).

Serial I/O Engine (SIOE) takes care of serial/parallel conversion; bus arbitration; clock

generation and synchronization; and handshaking

●

Multi-master capability

7-bit or 10-bit addressing

2.21.1 DMA

A programmable DMA channel may be assigned by CPU firmware to service each I2C channel

for fast and direct transfers between the I2C bus and SRAM with little CPU involvement. Both

DMA single-transfers and DMA burst-transfers are supported for transmit and receive.

2.22 SSP interfaces (SPI, SSI, and Microwire) with DMA

The STR91xFA supports two independent Synchronous Serial Port (SSP) interfaces,

designated SSP0, and SSP1. Primary use of each interface is for supporting the industry

standard Serial Peripheral Interface (SPI) protocol, but also supporting the similar Synchronous

Serial Interface (SSI) and Microwire communication protocols.

SPI is a three or four wire synchronous serial communication channel, capable of full-duplex

operation. In three-wire configuration, there is a clock signal, and two data signals (one data

signal from Master to Slave, the other from Slave to Master). In four-wire configuration, an

additional Slave Select signal is output from Master and received by Slave.

The SPI clock signal is a gated clock generated from the Master and regulates the flow of data

bits. The Master may transmit at a variety of baud rates, up to 24 MHz

In multi-Slave operation, no more than one Slave device can transmit data at any given time.

Slave selection is accomplished when a Slave’s “Slave Select” input is permanently grounded

or asserted active-low by a Master device. Slave devices that are not selected do not interfere

with SPI activities. Slave devices ignore the clock signals and keep their data output pins in

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Functional overview

STR91xFA

high-impedance state when not selected. The STR91xFA supports SPI multi-Master operation

because it provides collision detection.

Each SSP interface on the STR91xFA has the following features:

●

Full-duplex, three or four-wire synchronous transfers

Master or Slave operation

Programmable clock bit rate with prescaler, up to 24 MHz for Master mode and 4 MHz for

Slave mode

●

Separate transmit and receive FIFOs, each 16-bits wide and 8 locations deep

Programmable data frame size from 4 to 16 bits

Programmable clock and phase polarity

Specifically for Microwire protocol:

–

Half-duplex transfers using 8-bit control message

●

Specifically for SSI protocol:

–

Full-duplex four-wire synchronous transfer

Transmit data pin tri-stateable when not transmitting

2.22.1 DMA

A programmable DMA channel may be assigned by CPU firmware to service each SSP

channel for fast and direct transfers between the SSP bus and SRAM with little CPU

involvement. Both DMA single-transfers and DMA burst-transfers are supported for transmit

and receive. Burst transfers require that FIFOs are enabled.

2.23 General purpose I/O

There are up to 80 GPIO pins available on 10 I/O ports for 128-pin and 144-ball devices, and up

to 40 GPIO pins on 5 I/O ports for 80-pin devices. Each and every GPIO pin by default (during

and just after a reset condition) is in high-impedance input mode, and some GPIO pins are

additionally routed to certain peripheral function inputs. CPU firmware may initialize GPIO pins

to have alternate input or output functions as listed in Table 5. At any time, the logic state of any

GPIO pin may be read by firmware as a GPIO input, regardless of its reassigned input or output

function.

Bit masking is available on each port, meaning firmware may selectively read or write individual

port pins, without disturbing other pins on the same port during a write.

Firmware may designate each GPIO pin to have open-drain or push-pull characteristics.

All GPIO pins are 5V tolerant, meaning in they can drive a voltage level up to V

safely driven by a voltage up to 5.5V.

, and can be

DDQ

There are no internal pull-up or pull-down resistors on GPIO pins. As such, it is recommended

to ground, or pull up to V with a 100KΩ resistor, all unused GPIO pins to minimize power

DDQ

consumption and noise generation.

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STR91xFA

Functional overview

2.24 A/D converter (ADC) with DMA

The STR91xFA provides an eight-channel, 10-bit successive approximation analog-to-digital

converter. The ADC input pins are multiplexed with other functions on Port 4 as shown in

Table 5. Following are the major ADC features:

●

Fast conversion time, as low as 0.7 usec

Accuracy. Integral and differential non-linearity are typically within 4 conversion counts.

0 to 3.6V input range. External reference voltage input pin (AVREF) available on 128-pin

packages for better accuracy on low-voltage inputs. See Table 7: Operating conditions, for

restrictions to the relative voltage levels of VDDQ, AVDD, AVREF, and AVREF_AVDD.

●

CPU Firmware may convert one ADC input channel at a time, or it has the option to set the

ADC to automatically scan and convert all eight ADC input channels sequentially before

signalling an end-of-conversion

●

Automatic continuous conversion mode is available for any number of designated ADC

input channels

Analog watchdog mode provides automatic monitoring of any ADC input, comparing it

against two programmable voltage threshold values. The ADC unit will set a flag or it will

interrupt the CPU if the input voltage rises above the higher threshold, or drops below the

lower threshold.

●

The ADC unit goes to stand-by mode (very low-current consumption) after any reset event.

CPU firmware may also command the ADC unit to stand-by mode at any time.

ADC conversion can be started or triggered by software command as well as triggers from

Timer/Counter (TIM), Motor Controller and input from external pin.

2.24.1 DMA

A programmable DMA channel may be assigned by CPU firmware to service each ADC

conversion result for fast DMA single-transfer.

2.25 Standard timers (TIM) with DMA

The STR91xFA has four independent, free-running 16-bit timer/counter modules designated

TIM0, TIM1, TIM2, and TIM3. Each general purpose timer/counter can be configured by

firmware for a variety of tasks including; pulse width and frequency measurement (input

capture), generation of waveforms (output compare and PWM), event counting, delay timing,

and up/down counting.

Each of the four timer units have the following features:

●

16-bit free running timer/counter

●

Internal timer/counter clock source from a programmable 8-bit prescale of the CCU PCLK

clock output

●

Optional external timer/counter clock source from pin P2.4 shared by TIM0/TIM1, and pin

P2.5 shared by TIM2/TIM3. Frequency of these external clocks must be at least 4 times

less the frequency of the internal CCU PCLK clock output.

Two dedicated 16-bit Input Capture registers for measuring up to two input signals. Input

Capture has programmable selection of input signal edge detection

●

Two dedicated 16-bit Output Compare registers for generation up to two output signals

PWM output generation with 16-bit resolution of both pulse width and frequency

29/78

Functional overview

STR91xFA

●

One pulse generation in response to an external event

A dedicated interrupt to the CPU with five interrupt flags

The OCF1 flag (Output Compare 1) from the timer can be configured to trigger an ADC

conversion

2.25.1 DMA

A programmable DMA channel may be assigned by CPU firmware to service each timer/

counter module TIM0 and TIM1 for fast and direct single transfers.

2.26 Three-phase induction motor controller (IMC)

The STR91xFA provides an integrated controller for variable speed motor control applications.

Six PWM outputs are generated on high current drive pins P6.0 to P6.5 for controlling a three-

phase AC induction motor drive circuit assembly. Rotor speed feedback is provided by

capturing a tachometer input signal on pin P6.6, and an asynchronous hardware emergency

stop input is available on pin P6.7 to stop the motor immediately if needed, independently of

firmware.

The IMC unit has the following features:

●

Three PWM outputs generated using a 10 or 16-bit PWM counter, one for each phase U,

V, W. Complimentary PWM outputs are also generated for each phase.

●

Choice of classic or zero-centered PWM generation modes

10 or 16-bit PWM counter clock is supplied through a programmable 8-bit prescaler of the

APB clock.

●

Programmable 6 or 10-bit dead-time generator to add delay to each of the three

complimentary PWM outputs

●

8-bit repetition counter

Automatic rotor speed measurement with 16-bit resolution. Schmitt trigger tachometer

input with programmable edge detection

●

Hardware asynchronous emergency stop input

A dedicated interrupt to CPU with eight flags

Enhanced Motor stop output polarity configuration

Double update option when PWM counter reaches the max and min values in Zero-

centered mode

●

Locking feature to prevent some control register bits from being advertently modified

Trigger output to start an ADC conversion

2.27 External memory interface (EMI)

STR91xFA devices in 128-pin and 144-ball packages offer an external memory bus for

connecting external parallel peripherals and memories. The EMI bus resides on ports 7, 8, and

9 and operates with either an 8 or 16-bit data path. The configuration of 8 or 16 bit mode is

specified by CPU firmware writing to configuration registers at run-time. If the application does

not use the EMI bus, then these port pins may be used for general purpose I/O as shown in

Table 5.

30/78

STR91xFA

Functional overview

The EMI has the following features:

●

Supports static asynchronous memory access cycles, including page mode for non-mux

operation. The bus control signals include:

–

EMI_RDn - read signal, x8 or x16 mode

EMI_BWR_WRLn - write signal in x8 mode and write low byte signal in x16 mode

EMI_WRHn - write high byte signal in x16 mode

EMI_ALE - address latch signal for x8 or x16 mux bus mode with programmable

polarity

●

Four configurable memory regions, each with a chip select output (EMI_CS0n ...

EMI_CS3n)

●

Programmable wait states per memory region for both write and read operations

16-bit multiplexed data mode (Figure 4): 16 bits of data and 16 bits of low-order address

are multiplexed together on ports 8 and 9, while port 7 contains eight more high-order

address signals. The output signal on pin EMI_ALE is used to demultiplex the signals on

ports 8 and 9, and the polarity of EMI_ALE is programmable. The output signals on pins

EMI_BWR_WRLn and EMI_WRHn are the write strobes for the low and high data bytes

respectively. The output signal EMI_RDn is the read strobe for both the low and high data

bytes.

●

8-bit multiplexed data mode: This is a variant of the 16-bit multiplexed mode. Although

this mode can provide 24 bits of address and 8 bits of data, it does require an external

latch device on Port 8. However, this mode is most efficient when connecting devices that

only require 8 bits of address on an 8-bit multiplexed address/data bus, and have simple

read, write, and latch inputs as shown in Figure 5

To use all 24 address bits, the following applies: 8 bits of lowest-order data and 8 bits of

lowest-order address are multiplexed on port 8. On port 9, 8-bits of mid-order address are

multiplexed with 8 bits of data, but these 8 data values are always at logic zero on this port

during a write operation, and these 8 data bits are ignored during a read operation. An

external latch device (such as a ‘373 latch) is needed to de-multiplex the mid-order 8

address bits that are generated on port 8. Port 7 outputs the 8 highest-order address

signals directly (not multiplexed). The output signal on pin EMI_ALE is used to demultiplex

the signals on ports 8 and 9, and the polarity of EMI_ALE is programmable. The output

signal on pin EMI_BWR_WRLn is the data write strobe, and the output on pin EMI_RDn is

the data read strobe.

●

8-bit non-multiplexed data mode (Figure 6): Eight bits of data are on port 8, while 16 bits

of address are output on ports 7 and 9. The output signal on pin EMI_BWR_BWLn is the

data write strobe and the output on pin EMI_RDn is the data read strobe.

Burst Mode Support (LFBGA package only): The EMI bus supports synchronized burst

read and write bus cycle in multiplexed and non-multiplexed mode. The additional EMI

signals in the LFBGA package that support the burst mode are:

–

EMI_BCLK -the bus clock output. The EMI_BCLK has the same frequency or half of

that of the HCLK and can be disabled by the user

–

EMI_WAITn - the not ready or wait input signal for synchronous access

EMI_BAAn - burst address advance or burst enable signal

EMI_WEn - write enable signal

EMI_UBn, EMI_LBn - upper byte and lower byte enable signals. These two signals

share the same pins as the EMI_WRLn and EMI_WRHn and are user configurable

through the EMI register.

31/78

Functional overview

STR91xFA

By defining the bus parameters such as burst length, burst type, read and write timings in

the EMI control registers, the EMI bus is able to interface to standard burst memory

devices. The burst timing specification and waveform will be provided in the next data

sheet release

Figure 4. EMI 16-bit multiplexed connection example

STR91xx

16-BIT

DEVICE

EMI_CS3n

EMI_CS2n

EMI_CS1n

EMI_CS0n

CHIP_SELECT

EMI_WRHn

WRITE_HIGH_BYTE

WRITE_LOW_BYTE

EMI_BWR_WRLn

EMI_RDn

READ

EMI_ALE

ADDR_LATCH

P7.7

P7.6

P7.5

P7.4

P7.3

P7.2

P7.1

P7.0

EMI_A23

EMI_A22

EMI_A21

EMI_A20

EMI_A19

EMI_A18

EMI_A17

EMI_A16

A23

A22

A21

A20

A19

A18

A17

A16

P9.7

P9.6

P9.5

P9.4

P9.3

P9.2

P9.1

P9.0

EMI_AD15

EMI_AD14

EMI_AD13

EMI_AD12

EMI_AD11

EMI_AD10

EMI_AD9

EMI_AD8

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

P8.7

P8.6

P8.5

P8.4

P8.3

P8.2

P8.1

P8.0

EMI_AD7

EMI_AD6

EMI_AD5

EMI_AD4

EMI_AD3

EMI_AD2

EMI_AD1

EMI_AD0

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Figure 5. EMI 8-bit multiplexed connection example

STR91xx

8-BIT

DEVICE

EMI_CS3n

EMI_CS2n

EMI_CS1n

EMI_CS0n

CHIP_SELECT

EMI_BWR_WRLn

EMI_RDn

EMI_ALE

WRITE

READ

ADDR_LATCH

P8.7

EMI_AD7

P8.6

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

EMI_AD6

P8.5

EMI_AD5

P8.4

EMI_AD4

P8.3

EMI_AD3

P8.2

EMI_AD2

P8.1

EMI_AD1

P8.0

EMI_AD0

32/78

STR91xFA

Functional overview

Figure 6. EMI 8-bit non-multiplexed connection example

STR91xx

8-BIT

DEVICE

EMI_CS3n

EMI_CS2n

EMI_CS1n

EMI_CS0n

CHIP_SELECT

EMI_BWR_WRLn

EMI_RDn

WRITE

READ

P9.7

P9.6

P9.5

P9.4

P9.3

P9.2

P9.1

P9.0

EMI_A15

EMI_A14

EMI_A13

EMI_A12

EMI_A11

EMI_A10

EMI_A9

A15

A14

A13

A12

A11

A10

A9

EMI_A8

A8

P7.7

P7.6

P7.5

P7.4

P7.3

P7.2

P7.1

P7.0

EMI_A7

EMI_A6

EMI_A5

EMI_A4

EMI_A3

EMI_A2

EMI_A1

EMI_A0

A7

A6

A5

A4

A3

A2

A1

A0

P8.7

P8.6

P8.5

P8.4

P8.3

P8.2

P8.1

P8.0

EMI_D7

EMI_D6

EMI_D5

EMI_D4

EMI_D3

EMI_D2

EMI_D1

EMI_D0

D7

D6

D5

D4

D3

D2

D1

D0

33/78


型号：	STR910FAM32X6
厂家：	ST
描述：	ARM966E-S⑩ 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA ARM966E - S⑩ 16位/ 32位闪存单片机，以太网， USB ， CAN ，交流电机控制， 4个定时器， ADC ， RTC ， DMA 闪存微控制器和处理器外围集成电路电机 PC 以太网时钟
文件：	总78页 (文件大小：1473K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STR910FAM32X6 [STMICROELECTRONICS]

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