STPMS2H-PUR [STMICROELECTRONICS]
Smart sensor II dual-channel 1-bit, 4 MHz, second-order sigma-delta modulator with embedded PGLNA; 智能传感器II双信道1位， 4兆赫，第二阶Σ -Δ调制器具有嵌入式PGLNA
| 型号： | STPMS2H-PUR |
| 厂家： | 
ST |
| 描述： | Smart sensor II dual-channel 1-bit, 4 MHz, second-order sigma-delta modulator with embedded PGLNA |
| 文件： | 总33页 (文件大小：2141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STPMS2
Smart sensor II dual-channel 1-bit, 4 MHz,
second-order sigma-delta modulator with embedded PGLNA
Features
■ V
supply range 3.2 V - 5.5 V
CC
■ Two second-order sigma-delta (ΣΔ)
modulators
■ Programmable chopper-stabilized low noise
and low offset amplifier
■ Supports 50-60 Hz, EN 50470-1, EN 50470-3,
IEC 62053-21, IEC 62053-22 and IEC 62053-
23 standards specs for class 1, class 0.5 and
class 0.2 AC watt meters
QFN16 (4 x 4)
■ STPM02H: less than 0.5% error over 1:10000
range
or multi-phase energy meters along with the
STPMC1 device, a digital signal processor
designed for energy measurement. This device
can be used in medium and high resolution
measurement applications where single or double
inputs must be monitored at the same time. The
STPMS2 are mixed signal ICs consisting of an
analog and digital section. The analog section
consists of a programmable gain, low noise
choppered amplifier, two second-order ΔΣ
modulator blocks, a band-gap voltage reference,
a low-drop voltage regulator and DC buffers, while
the digital section consists of a clock generator
and output multiplexer.
■ STPM02L: less than 0.5% error over 1:5000
range
■ Precision voltage reference: 1.23 V with
programmable TC (STPMS2L only)
■ Internal low drop regulator @ 3 V (typ.)
Applications
■ Power metering
■ Motor control
■ Industrial process control
■ Weight scales
■ Pressure transducers
Description
The STPMS2, also called “smart sensor” devices,
are ASSPs designed for effective measurement in
power line systems utilizing Rogowski coil, current
transformer, Hall or shunt sensors. These devices
are designed as building blocks for single-phase
Table 1.
Device summary
Order codes
Package
Packaging
STPMS2H-PUR
STPMS2L-PUR
QFN16 (4 x 4 mm)
QFN16 (4 x 4 mm)
4500 parts per reel
4500 parts per reel
October 2011
Doc ID 16525 Rev 3
1/33
www.st.com
33
Contents
STPMS2
Contents
1
2
3
4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
6
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1
6.2
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
8
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.1
8.2
8.3
General operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional description of the analog part . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional description of the digital part . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.3.1
8.3.2
Decoder for different modes of operation . . . . . . . . . . . . . . . . . . . . . . . 21
Generator for clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.4
8.5
Hard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Soft mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.5.1
Writing to the configuration register in Soft mode . . . . . . . . . . . . . . . . . 27
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10
2/33
Doc ID 16525 Rev 3
STPMS2
Introduction
1
Introduction
The STPMS2 is a device designed to measure electrical line parameters (voltage and
current) via analog signals from voltage sensors (current divider) and current sensors
(inductive Rogowski coil, current transformer or shunt resistors). The device is used
together with a digital signal processing circuit to implement an effective measuring system
for multi-phase power meters.
The device consists of two analog measuring channels, consisting of second-order sigma-
delta modulators with appropriate non-overlapping control signal generator. The STPMS2
also includes a temperature compensated band-gap reference voltage generator, a low-
drop supply voltage stabilizer and minimal digital circuitry that includes BIST (built-in self-
test) structures. In a current signal processing channel, a low-noise preamplifier is included
in front of the sigma-delta converter. All reference voltages (band-gap, AGND) are internally
buffered to eliminate channel crosstalk.
The STPMS2 can operate in fast or low-power mode. In fast mode, a nominal clock
frequency of 4.1 or 4.9 MHz is applied to the clock input. In this mode, signal bandwidth is
specified between 0 and 4 kHz. In low-power mode, the nominal clock is four times slower in
order to reduce the power consumption of the circuit. In low-power mode, the quiescent bias
currents of the preamplifier and sigma-delta integrators are lowered and the signal
bandwidth is narrowed to the frequency bandwidth of 0 to 1 kHz.
Doc ID 16525 Rev 3
3/33
Internal block diagram
STPMS2
2
Internal block diagram
Figure 1.
STPMS2 internal block diagram
VDDav
EINCHPV
VIP
VIN
DAT
DATN
MS3
MS2
MS1
2nd ord ΣΔ
modulator
MUX
MV, NV
ECHPLFV,
ECHPHFV
PDV
EINCHPC,
EINCHPV
EPRSV
DIGITAL
FRONT
END
GAIN
BIST DAC
EPRSV
ECHPLFC,
ECHPHFC
MC, NC
GAIN
2nd ord ΣΔ
modulator
MUX
PLNA
CIP
CIN
MS0
CLK
EINCHPC
VDDac
VCC
TC
VRefV
VRefC
VOLTAGE
REFERENCE
LDR
GND VDDa
VBG
AM09892v1
4/33
Doc ID 16525 Rev 3
STPMS2
3
Pin configuration
Pin configuration
Figure 2.
Pin connections
16
13
15
14
1
MS2
MS1
12
11
VCC
VDDac
VDDa
VBG
2
3
4
GND
MS0
10
9
VDDav
5
6
7
8
AM09382v1
Table 2.
Pin n°
Pin description
Symbol
Description
1
2
3
VCC
VDDac
VDDa
Unregulated supply voltage for pad-ring, bandgap, low-drop and level shifters
Current channel modulator supply input
Output of internal + 3.0 V low drop regulated power supply
Output of internal + 1.23 V bias generator (STPMS2L);
Input of external precision reference voltage (STPMS2H)
4
VBG
5
6
CIN
CIP
Current channel -
Current channel +
7
VIN
Voltage channel -
8
VIP
Voltage channel +
9
VDDav
MS0
MS1
MS2
MS3
CLK
Voltage channel modulator supply input
Input for configurator 0
Input for configurator 1
Input for configurator 2
Input for configurator 3
Input for external measurement clock
10
11
12
13
14
Output of multiplexed ΣΔ signal
Output of current ΣΔ signal
15
DAT
Output of inverted multiplexed ΣΔ signal
Output of voltage ΣΔ signal
16
DATn
GND
Exp PAD
Ground level for signals and pin protection
Doc ID 16525 Rev 3
5/33
Maximum ratings
STPMS2
4
Maximum ratings
Table 3.
Absolute maximum ratings
Parameter
Symbol
Value
Unit
VCC
IPIN
VID
DC Input voltage
-0.3 to 6
150
V
mA
V
Current on any pin (sink/source)
Input voltage at any pin
-0.3 to VCC +0.3
-0.7 to 0.7
2
VIA
Input voltage at analog pins (VIP, VIN, IIP, IIN)
Human body model (all pins)
Operating ambient temperature
Junction temperature
V
ESD
TOP
TJ
kV
°C
°C
°C
-40 to 85
-40 to 150
-55 to 150
TSTG
Storage temperature range
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Table 4.
Thermal data
Symbol
Parameter
Value
Unit
(1)
RthJA
Thermal resistance junction-ambient
38.66
°C/W
1. This value is referred to single-layer PCB, JEDEC standard test board.
6/33
Doc ID 16525 Rev 3
STPMS2
Maximum ratings
4.1
General operating conditions
V
= 5 V, T
= 25 °C, 1 µF between V , VDDa, VDDac, VDDav and GND, 100 nF
CC
AMB CC
between VBG and GND, f
= 4.19 MHZ unless otherwise specified.
CLK
Table 5.
Symbol
General operating conditions
Parameter
Test conditions
Min.
Typ.
Max.
Unit
General section
Operating supply
VCC
3.135
5.25
1.5
5
V
voltage
LP, 1.229MHz; VCC=3.3V; CL=100nF;
no loads
1.2
ICC
Quiescent current
mA
HP, 4.915MHz; VCC=3.2V; CL=100nF;
no loads
4
VPOR Power on reset on VCC
2.5
3.00
V
V
Regulated supply
1.049MHz; VCC=3.2V; CL=100nF; no
loads
VDD
2.95
3.05
voltage
Current injection latch-
ILATCH
300
mA
Hz
up immunity
fBW
Effective bandwidth
Limited by chopper
0
4091
DC measurement accuracy
Resolution
11
16
bit
Result referred to a 16-bit word of CIP-
CIN channel, HP mode, fCLK= 2.047MHz
3.3
3.9
INL
Integral non linearity
Differential linearity
Offset error
LSB
Result referred to a 12-bit word of VIP-
VIN channel, HP mode, fCLK=2.047MHz
Result referred to a 16-bit word of CIP-
CIN channel, HP mode, fCLK=2.047MHz
0.3
DNL
LSB
LSB
Result referred to a 12-bit word of VIP-
VIN channel, HP mode, fCLK=2.047MHz
0.5
Result referred to a 16-bit word of CIP-
CIN channel, HP mode, fCLK=2.047MHz
0.02
0.005
Result referred to a 12 bit-word of VIP-
VIN channel, HP mode, fCLK=2.047MHz
Result referred to a 16-bit word of CIP-
CIN channel, HP mode, fCLK=2.047MHz
0.04
0.4
Gain error
Noise floor
LSB/uV
dB
Result referred to a 12-bit word of VIP-
VIN channel, HP mode, fCLK=2.047MHz
0.003
CIP-CIN channel gain 2x
CIP-CIN channel gain 16x
VIP-VIN channel
120
118
95
NF
Doc ID 16525 Rev 3
7/33
Maximum ratings
STPMS2
Table 5.
Symbol
General operating conditions (continued)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Voltage signal: 200 mVrms/50Hz
Current signal: 10 mVrms/50Hz
fCLK=2.048 MHz
Power supply DC
rejection
PSRRDC
90
dB
VCC=3.3V 10%, 5V 10%
AC measurement accuracy
CIP-CIN channel – Vin= 230mV @
55Hz gain 2x over 4 kHz bandwidth
82
52
SNR
SINAD
THD
Signal to noise ratio
dB
dB
dB
dB
VIP-VIN channel – Vin= 230mV @
55Hz over 4 kHz bandwidth
CIP-CIN channel – Vin= 230mV @
55Hz gain 2x over 4 kHz bandwidth
82
Signal to noise ratio +
distortion
VIP-VIN channel – Vin= 230mV @
55Hz over 4 kHz bandwidth
52
CIP-CIN channel – Vin= 230mV @
55Hz gain 2x over 4 kHz bandwidth
-105
-78
90
Total harmonic distortion
VIP-VIN channel – Vin= 230mV @
55Hz over 4 kHz bandwidth
CIP-CIN channel – Vin= 230mV @
55Hz gain 2x over 4 kHz bandwidth
Spurious free dynamic
range
SFDR
VIP-VIN channel – Vin= 230mV @
55Hz over 4 kHz bandwidth
68
Voltage signal: 200 mVrms/50Hz
Current signal: 10 mVrms/50Hz
fCLK=2.048 MHz
Power supply AC
rejection
PSRRAC
120
-0.3
dB
VCC=3.3V+0.2Vrms1@100Hz
VCC=5.0V+0.2Vrms1@100Hz
Analog inputs (CIP, CIN, VIP, VIN)
VIP-VIN channel
+0.3
V
V
STPMS2L CIP-CIN channel
Gain 2x
Gain 4x
Gain 8x
Gain 16x
-0.3
-0.15
-0.075
-0.0375
+0.3
+0.15
+0.075
+0.0375
Maximum input signal
VMAX
levels
-VREF
GAIN
/
+VREF
GAIN
/
STPMS2H CIP-CIN channel
fSPL
Voff
ZIP
A/D sampling frequency
Amplifier offset
fCLK
Hz
mV
kΩ
kΩ
20
400
50
VIP, VIN impedance
CIP, CIN impedance
Over total operating voltage range
Over total operating voltage range
100
35
ZIN
Gain error of current
channels
GERR
10
%
8/33
Doc ID 16525 Rev 3
STPMS2
Maximum ratings
Table 5.
Symbol
General operating conditions (continued)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Voltage channel leakage
current
IILV
VCC=5.25V, fCLK=4.19MHz
-1
-1
1
1
µA
VCC=5.25V, fCLK=4.19MHz
Current channel leakage
current
IILI
VCC=5.25V, fCLK=4.19MHz input
enabled
-10
10
Crosstalk between
channels
130
dB
Digital I/O (CLK, DAT, DATN, MS0, MS1, MS2, MS3)
0.75VC
VIH
VIL
Input High voltage
Input Low Voltage
5.3
V
V
C
0.25VC
-0.3
C
VOH
VOL
IUP
tTR
tL
Output high voltage
Output low voltage
Pull up current
Transition time
Latency
IO=-1mA, CL=50pF, VCC=3.2V
IO=+1mA, CL=50pF, VCC=3.2V
VCC-0.4
V
V
0.4
40
15
10
µA
ns
ns
CLOAD=50pF
From 50% of CLK to 50% to DAT
Clock input
Low precision mode
High precision mode
Very high precision mode
1.0
2.0
4.0
1.228
2.458
4.915
fCLK
Nominal frequencies
MHz
On chip reference voltage
VREF
Zout
IL
Reference voltage
Output impedance
Maximum load current
STPMS2L only (1)
1.21
30
1.23
1.25
200
V
kΩ
0
µA
TC
Temperature coefficient After calibration
30
50
ppm/°C
1. This level may be delivered from external source in STPMS2H.
Doc ID 16525 Rev 3
9/33
Maximum ratings
STPMS2
Figure 3.
Timing diagram
AM09383v1
CLK - clock signal on CLK pin
CLKsample - sigma-delta sampling frequency
bsV - sigma-delta bit stream of voltage signal
bsC - sigma-delta bit stream of current signal
DATA - multiplexed data of voltage and current signal on DAT pin
10/33
Doc ID 16525 Rev 3
STPMS2
Application
5
Application
The choice of external components in the transduction section of the application is a crucial
point in the application design, affecting the precision and the resolution of the entire
system.
Among the several considerations, a compromise should be found between the following
requirements:
1. Maximize the signal-to-noise ratio in the voltage and current channel
2. Choose the current-to-voltage conversion ratio Ks and the voltage divider ratio in a way
that calibration can be achieved
3. Choose Ks to take advantage of the whole current dynamic range in accordance with
desired maximum current and resolution.
To maximize the signal-to-noise ratio of the current channel, the voltage divider resistors
ratio should be as close as possible to those shown in Table 6.
Figure 4 below provides a reference application schematic diagram:
●
●
●
P = 64000 imp/kWh
I
I
= 5 A
NOM
MAX
= 60 A
Typical sensitivity values for the current sensors are indicated inTable 6.
Figure 4.
Detailed application schematic
L
N
VCC
C14
C5
C6
1µ
1µ
1µ
R7 1K1%
U1
4
3
2
1
17 18
C7
4.7n
L3
E4622_X503
STPMS2H/L
R6
3.3 1%
19
20
e3
e4
5
6
7
8
cin
cip
vin
vip
9
16
R8 1K1%
C8
4.7n
DATn
DAT
CLK
MS3
15
14
13
DAT
CLK
VN
R5
C3
470 1%
10n
VL
10
11
12
R3 150k
R4 150k
R2 150k
C9
MS0 = CLK HP Ampl x4
MS1 =
MS2 =
MS3 =
0
0
0
TC = 50 ppm/rC
Voltage channel ON, DAT =(CLK)? bsV : bsC
HardMode, BIST Mode OFF
CLK
1µ
L1
1µ
AM09379v1
Doc ID 16525 Rev 3
11/33
Application
Table 6.
STPMS2
Recommended external components in metering applications
Function
Component
Description
Value
Tolerance
Unit
Calculator
STPMC1
---
1:1650
1:830
0.15
---
---
---
R to R ratio VRMS=230V
R to R ratio VRMS=110V
Line voltage
interface
Resistor
divider
±1%
50ppm/°C
V/V
Rogowski coil
CT
±5%
±5%
±5%
Line current
interface
Current-to-voltage ratio KS
1.7
50ppm/°C
mV/A
Shunt
0.43
Note:
Above listed components refer to typical metering application. Anyhow, STPMS2 operation
is not limited to the choice of these external components.
Figure 5.
Simplified application schematics for STPMC1 based energy metering
R S T N
M S 0 M S 1 M S 2 M S 3
CL K
Ant i Al i a s i ng
Ne t wor k
DAT
VIP
VIN
DAT n
VDD
VCC
VBG
GND
M S 0 M S 1 M S 2 M S 3
CL K
CL K
Ant i Al i a s i ng
Ne t wor k
Ca lc ula t or
S T PMC1A
DAT
DAS
DAR
DAT
VIP
VIN
DAT n
VDD
VCC
VBG
GND
M S 0 M S 1 M S 2 M S 3
CL K
Ant i Al i a s i ng
Ne t wor k
DAT
VIP
VIN
DAT n
VDD
VCC
VBG
GND
LOAD
AM09893v1
12/33
Doc ID 16525 Rev 3
STPMS2
Figure 6.
Application
Connection schematics for DSP-based applications
MS0
MS1 MS2
MS3
CLK
DAT
Anti Aliasing
Network
DSP
VIP
VIN
Anti Aliasing
DATn
VDD
Network
VCC
VBG
GND
AM09380v1
Doc ID 16525 Rev 3
13/33
Terminology
STPMS2
6
Terminology
6.1
Conventions
The lowest analog and digital power supply voltage is called GND which represents the
system ground. All voltage specifications for digital input/output pins are referred to GND.
The highest power supply voltage is called V . The highest core power supply is internally
CC
generated and is called V
.
DD
Positive currents flow into a pin. Sinking current means that the current is flowing into the pin
and thus it is positive. Sourcing current means that the current is flowing out of the pin and
thus it is negative.
A positive logic convention is used in all equations.
6.2
Notation
Output bit streams of the modulator are indicated as bsV and bsC for voltage and current
channels, respectively.
14/33
Doc ID 16525 Rev 3
STPMS2
Typical performance characteristics
7
Typical performance characteristics
Figure 7.
V
/V
at 25 deg vs. temp
Figure 8.
SNHR of I channel, gain 16x
REF REF
AM09901v1
90
80
70
60
50
40
30
20
10
0
Current16x, Fsig
Current16x, Fsig
Current16x, Fsig
Current16x, Fsig
Current16x, Fsig
=
=
=
=
=
55Hz, HP mode 2.047MHz, 3.3V, -30deg
55Hz, HP mode 2.047MHz, 3.3V, 0deg
55Hz, HP mode 2.047MHz, 3.3V, 25deg
55Hz, HP mode 2.047MHz, 3.3V, 60deg
55Hz, HP mode 2.047MHz, 3.3V, 85deg
-10
10
100
1000
10000
100000
1000000
I peak-peak [µV]
Figure 9.
SNHR of I channel, gain 2x
Figure 10. SNHR of V channel, gain 2x
AM09902v1
AM09903v1
90
80
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
-10
Voltage 2x, Fsig
Voltage 2x, Fsig
Voltage 2x, Fsig
Voltage 2x, Fsig
Voltage 2x, Fsig
=
=
=
=
=
55Hz, HP mode 2.047MHz, 3.3V, -30deg
Current2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, -30deg
55Hz, HP mode 2.047MHz, 3.3V, 0deg
55Hz, HP mode 2.047MHz, 3.3V, 25deg
55Hz, HP mode 2.047MHz, 3.3V, 60deg
55Hz, HP mode 2.047MHz, 3.3V, 85deg
Current2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 0deg
Current2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 25deg
Current2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 60deg
Current2x, Fsig = 55Hz, LP mode 2.047MHz, 3.3V, 85deg
-20
-30
-40
-10
-20
10
100
1000
10000
100000
1000000
10000000
100
1000
10000
100000
1000000
10000000
U peak-peak [µV]
I peak-peak [µV]
Figure 11. SINAD of I channel, gain 16x (temp. Figure 12. SINAD of I channel, gain 16x (temp.
variation) variation)
AM09904v1
AM09905v1
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
-10
-20
-30
-40
Current16x, Fsig
Current16x, Fsig
Current16x, Fsig
Current16x, Fsig
Current16x, Fsig
=
=
=
=
=
55Hz, HP mode 2.047MHz, 3.3V, -30deg
Voltage 2x, Fsig
Voltage 2x, Fsig
Voltage 2x, Fsig
Voltage 2x, Fsig
Voltage 2x, Fsig
=
=
=
=
=
55Hz, HP mode 2.047MHz, 3.3V, -30deg
55Hz, HP mode 2.047MHz, 3.3V, 0deg
55Hz, HP mode 2.047MHz, 3.3V, 25deg
55Hz, HP mode 2.047MHz, 3.3V, 60deg
55Hz, HP mode 2.047MHz, 3.3V, 85deg
55Hz, HP mode 2.047MHz, 3.3V, 0deg
55Hz, HP mode 2.047MHz, 3.3V, 25deg
55Hz, HP mode 2.047MHz, 3.3V, 60deg
55Hz, HP mode 2.047MHz, 3.3V, 85deg
-10
10
100
1000
10000
100000
1000000
100
1000
10000
100000
1000000
10000000
I peak-peak [µV]
U peak-peak [µV]
Doc ID 16525 Rev 3
15/33
Typical performance characteristics
STPMS2
Figure 13. Relative gain error of I channel,
gain 16x
Figure 14. Relative gain error of I channel,
gain 2x
AM09899v1
AM09900v1
1.1
1.08
1.06
1.04
1.02
1
1.1
1.08
1.06
1.04
1.02
1
0.98
0.96
0.94
0.92
0.9
0.98
Current 4x, Fsig = 55Hz, HP mode 2.455MHz, 3.3V
Current 4x, Fsig = 55Hz, HP mode 2.455MHz, 5.0V
Current 4x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V
Current 4x, Fsig = 55Hz, HP mode 2.047MHz, 5.0V
Current 4x, Fsig = 55Hz, LP mode 1.229MHz, 3.3V
Current 4x, Fsig = 55Hz, LP mode 1.229MHz, 5.0V
Current 4x, Fsig = 55Hz, LP mode 1.048MHz, 3.3V
Current 4x, Fsig = 55Hz, LP mode 1.048MHz, 5.0V
0.96
0.94
0.92
0.9
Current 32x, Fsig = 55Hz, HP mode 2.455MHz, 3.3V
Current 32x, Fsig = 55Hz, HP mode 2.455MHz, 5.0V
Current 32x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V
Current 32x, Fsig = 55Hz, HP mode 2.047MHz, 5.0V
Current 32x, Fsig = 55Hz, LP mode 1.229MHz, 3.3V
Current 32x, Fsig = 55Hz, LP mode 1.229MHz, 5.0V
Current 32x, Fsig = 55Hz, LP mode 1.048MHz, 3.3V
Current 32x, Fsig = 55Hz, LP mode 1.048MHz, 5.0V
10
100
1000
10000
100000
1000000
10000000
10
100
1000
10000
100000
1000000
I peak-peak [µV]
I peak-peak [µV]
Figure 15. Accuracy over dynamic range
AM09906v1
0.5%
0.4%
0.3%
0.2%
0.1%
0.0%
0.076%
0.097%
0.035%
0.040%
-0.008%
0.035%
0.027%
-0.065%
-0.096%
-0.087%
-0.096% -0.096%
-0.1%
-0.2%
-0.3%
-0.4%
-0.5%
-0.6%
-0.087%
Class 0.2 limits
-0.352%
-0.435%
-0.487%
0.01%
0.10%
1.00%
10.00%
100.00%
1000.00%
% of FS
16/33
Doc ID 16525 Rev 3
STPMS2
Theory of operation
8
Theory of operation
8.1
General operation description
The STPMS2 performs second-order analog modulation of two channels in parallel, with
appropriate non-overlapping control signal generator, of signals with frequencies varying
from DC to 4 kHz on two independent channels in parallel. The outputs of the converters
provide two streams of digital ones and zeros which can be then be multiplexed in time to
reduce the number of external connections.
The STPMS2 converts analog signals on two independent channels in parallel via delta-
sigma (ΣΔ) analog-to-digital converters into a binary stream of sigma-delta signals. The
device is particularly suitable to measure electrical line parameters (voltage and current) via
analog signals from voltage sensors (current divider) and current sensors (inductive
Rogowski coil, current transformer or shunt resistors). There is a current channel for
measuring line current and a voltage channel for measuring line voltage. The current
channel input is connected through an external anti-aliasing RC filter to a Rogowski coil,
current transformer (CT) or shunt current sensor which converts line current into an
appropriate voltage signal. The current channel includes a low-noise voltage preamplifier
with programmable gain. The voltage channel is connected directly through a resistor
voltage divider and anti-aliasing filter to a line voltage modulator (ADC). Both channels have
quiescent zero signal point at GND, so the STPMS2 is able to sample differential signals on
both channels with their zero point around GND.
The converted ΣΔ signals are multiplexed in time in order to reduce the number of external
connections. The conversion and the multiplex are driven by external clock signal CLK.
The device is used in conjunction with a digital signal processing circuit to implement an
effective measuring system of a multi-phase power meter.
The STPMS2 also includes a temperature compensated band-gap reference voltage
generator, low-drop supply voltage regulator and minimal digital circuitry that includes BIST
(built-in self-test) structures. In a current signal processing channel, a low-noise preamplifier
is included upstream of the sigma-delta converter. All reference voltages are designed to
eliminate channel crosstalk.
The STPMS2 can operate in fast (HP) or low-power (LP) mode (see also Table 7). In fast
mode, a nominal clock frequency of up to 4.1 / 4.9 MHz is applied to the clock input. In this
mode, signal bandwidth is specified between 0 and 4 kHz. In low-power mode, the nominal
clock is four times slower (1 MHz) to lower the power consumption of the circuit. In low-
power mode, the quiescent bias currents of the preamplifier and sigma-delta integrators are
reduced and the signal bandwidth is narrowed to the frequency bandwidth of 0 to 1 kHz.
The mode of operation and configuration of the device can be selected by wiring
configuration pins (MS0, MS1, MS2 and MS3) to V , GND, CLK or NCLK signal. This
CC
approach can be used to change the settings of a current channel, sigma-delta stream
output mode and temperature compensation curve of an internal band-gap reference.
These pins can act as a serial port to change the configuration of the device.
8.2
Functional description of the analog part
The supply pins for the analog part are VCC, VDDa, VDDac, VDDav, VBG and GND.
The GND pin also represents a reference point. The VDDa is an analog I/O pin of the
internal +3.0 V low drop voltage regulator and the VDDac and VDDav are the modulator
Doc ID 16525 Rev 3
17/33
Theory of operation
STPMS2
supply inputs. A 1 µF capacitor should be connected between VDDxx and GND. The input of
the regulator is VCC, which also powers the band-gap and bias generators. The band-gap
output is VBG, which should be connected to GND via a 100 nF capacitor.
Figure 16. Power supply external connection scheme
Analog Supply
3.3 - 5.0 V
VDDac
VDDa
VBG
MS2
MS1
1 µF
1 µF
GND
MS0
VDDav
1 µF
100 nF
AM09381v1
The analog part of the STPMS2 consists of:
●
●
●
●
●
●
●
pre-amplifier in the current channel
1.23 V reference voltage generator (STPMS2L only)
+3 V low-drop supply voltage regulator
nd
two sigma-delta 2 order modulators
BIST DAC
AGND and V
reference buffers
REF
bias current generators
The voltage channel has a pre-amplification gain of 2, which defines the maximum
differential voltage on voltage channel inputs to 300 mV. The relative gain of the current
channel is selectable among 2, 4, 8 or 16, which defines the maximum differential voltage on
the current channel to 300 mV, 150 mV, 75 mV or 37.5 mV, respectively. The full
range of gains is available only in soft mode (see Section 8.5), while in hard mode only 2
and 16 are selectable.
The temperature-compensated reference voltage generator produces V
= 1.23 V. This
REF
generator is implemented as a band gap generator, whose temperature compensation
curve can be selected through configuration.
The low drop regulator fixes and stabilizes the core supply voltage to VDDa = 3 V. All digital
pads tolerate 5 V logic levels.
The STPMS2 is clocked by an external clock signal connected to pin CLK.
The STPMS2L sigma-delta modulators work in several operating modes, shown in Table 7
below.
18/33
Doc ID 16525 Rev 3
STPMS2
Table 7.
Theory of operation
Operating modes
Operating mode
Current
consumption
Device
fCLK
LP (low power)
HP (fast)
LPR (low precision)
HPR (high precision)
STPMS2L
STPMS2L
STPMS2H
1 MHZ
2 MHz – 4MHz
4 MHz
1,2 mA typ
4 mA typ
HHPR (very high precision)
LPR (low precision): f
= 1 MHz and settings defined by MS0 through MS3
CLK
HPR (high precision): the normal mode of operation with f
= 2 MHz to 4 MHz
CLK
The STPMS2H sigma-delta modulators work in the following mode:
HHPR (very high precision) external reference must be connected to VBG, f
= 4 MHz.
CLK
The STPMS2 performs operations in 2 basic modes: Hard mode and Soft mode.
In Hard mode the configuration is set through external pins MS0, MS1, MS2 and MS3.
In Soft mode, 40 configuration bits can be accessed through CFG[39:0], via serial
communication. The pins used for serial communication are: MS0, MS1 and MS2.
Switching between Hard and Soft modes is achieved through pin MS3.
●
Hard mode: In this case the device configuration is bootstrapped at startup and signals
come from VIN and VIP for voltage channels, and CIP and CIN for current channels or
from internal BIST DAC.
●
Soft mode: In this mode all possible settings from Hard mode are accessible, as well
as the additional settings described in Section 8.5.
Figure 17. Block diagram of the modulator
dithering
input
stream out
∫
∫
-
-
1st integrator
2nd integrator
comparator
a1
a2
D/A
AM09894v1
The STPMS2 sends to the DAT and DATn pins selected signals based on the configuration
used.
Both outputs have cross-current and slew rate limiters to prevent excessive current spikes
on supply lines.
Doc ID 16525 Rev 3
19/33
Theory of operation
STPMS2
Figure 18. Example of sigma-delta modulator output in case of sinusoidal waveform
AM09895v1
8.3
Functional description of the digital part
The digital section (DFE) includes:
●
●
●
a decoder for different modes of operation
a generator for clock frequency
level shifters, pull-up stages and power buffers outside the DFE block
Figure 19. Block diagram and definition of DFE digital signals
Outputs for analog part
Clock Generator
MS0
MS1
MS2
MS3
Clock signals
Chopper
DECODER
CLK
Pseudo
Random
DOMUL
DTMC
DAT
Sigma-Delta streams
Synchro
Mux
DATn
CLK
CLK
AM09896v1
20/33
Doc ID 16525 Rev 3
STPMS2
Theory of operation
8.3.1
Decoder for different modes of operation
The decoder defines the operating mode according to the state of the bootstrap MS0, MS1,
MS2 and MS3 pins. Two different operational modes can be defined:
●
Hard mode: In this case the device configuration is bootstrapped at startup and signals
come from VIN and VIP for voltage channels, and CIP and CIN for current channels or
from internal BIST DAC.
●
Soft mode: In this mode all possible settings from Hard mode are accessible, as well as
additional settings such as dither and chopper signal frequencies and operation (see
Section 8.5).
8.3.2
Generator for clock frequency
Chopper and BIST frequency generator
The Chopper block generates the chopper frequencies and BIST signals for the voltage and
current channels. The BIST DAC output levels are appropriately adjusted for the current
channel according to the gain selection, while for the voltage channel the max DC voltage is
used.
The levels are 300 mV for the voltage channel and 300 mV / 150 mV / 75 mV / 37.5 mV for
the current channel, in accordance with gain settings 2/4/8/16, respectively, when operating
in Soft mode, while 300 mV / 37.5 mV based on gain settings 2/16 when operating in Hard
mode.
Pseudo random
The Pseudo random block generates pseudo random signals for the voltage and current
channels. These random signals are used to implement a dithering technique to de-
correlate the output of the modulators and avoid accumulation points on the frequency
spectrum.
Synchro
In Synchro block the synchronization of sigma-delta input streams with strobe signals from
analog part and clock signal is performed.
Mux
In the Mux block, which signals are connected to output pins DAT and DATn are selected.
In HardMode, the output signals are selected by input pin MS2.
In SoftMode, the output signals are selected by 8 configuration bits.
8.4
Hard mode
The STPMS2 operates in Hard mode when input pin MS3 is connected to GND or VCC, as
described in Table 11.
In Hard mode, the STPMS2 has four digital input pins (MS0, MS1, MS2 and MS3) to
configure the basic operating parameters:
●
●
●
●
BIST DAC enable
temperature curve of reference voltage
current and voltage channels settings
output mode settings
Doc ID 16525 Rev 3
21/33
Theory of operation
STPMS2
In this way it is possible to access 128 different combinations, which are controlled through
pins MS0, MS1, MS2 and MS3.
MS0 sets the operating mode and amplifier gain selection as described in Table 8.
For the STPMS2L:
●
●
MS0=GND or CLK to select LPR (low precision); f
frequency and low power mode is selected.
= 1 MHz is the typical input clock
CLK
MS0=NCLK or VCC to select HPR (high precision): f
clock frequency and accuracy is enhanced.
= 2 MHz is the typical input
CLK
For the STPMS2H, LPR mode is not used and the settings should be chosen between
MS0=NCLK or VCC. In this case, f = 4 MHz is typical.
CLK
The relative gain of the current channel is selectable between 2 or 16, which defines the
maximum differential voltage on the current channel to 300 mV or 37.5 mV, respectively.
The voltage channel gain setting is fixed at 2, which defines the maximum differential
voltage on the voltage channel inputs to 300 mV.
Table 8.
MS0
Precision mode and input amplifier gain selection
Mode
Description
LPR, amplifier GAIN selection g3 = 16
GND
CLK
0
1
2
3
LPR, amplifier GAIN selection g0 = 2
HPR, amplifier GAIN selection g0 = 2
HPR, amplifier GAIN selection g3 = 16
NCLK
VCC
MS1 defines the temperature compensation (TC) curve of the internal voltage reference of
the STPMS2L, as described in Table 9. This bootstrap function is not used with the
STPMS2H. The temperature-compensated reference voltage generator produces V
=
REF
1.23 V. This generator is implemented as a band gap generator, whose temperature
compensation curve can be selected through the MS1 configuration pin.
Table 9.
MS1
TC of the band-gap reference
Mode
Description
GND
CLK
0
1
2
3
TC = 60 ppm/°C
Flattest TC = +30 ppm/°C
TC = +160 ppm/°C
TC = -160 ppm/°C
NCLK
VCC
MS2 defines the outputs of the device:
The STPMS2 sends to the DAT and DATn pins the sigma-delta streams synchronous to the
CLK signal. The output mode can be configured according to Table 10 as follows:
●
The output current channel's sigma-delta stream on DAT and the voltage channel's
sigma-delta stream on DATn
●
Output multiplexed signals, so when CLK = 0, the current channel output sigma-delta
value is set on the DAT pin, and when CLK = 1, the voltage channel output sigma-delta
value is set on the DAT pin. The DATn pin tracks DAT, so DATn = ~DAT.
●
Output current channel's sigma-delta stream on DAT and the current channel's sigma-
delta stream negated on DATn
22/33
Doc ID 16525 Rev 3
STPMS2
Theory of operation
Table 10. Control of voltage channel and output signals
MS2
Mode
Description
GND
CLK
0
1
2
3
Voltage channel ON, DATn = ~ [DAT =(CLK) ? bsV : bsC)]
Voltage channel OFF, DATn = bsCn, DAT = bsC
Voltage channel OFF, DATn = bsCn, DAT = bsC
Voltage channel ON, DATn = bsC, DAT = bsV
NCLK
VCC
MS3 enables or disables the BIST DAC output levels.
If enabled (MS3=VCC), the input of the modulators are disconnected from pin VIP, VIN and
CIP, and CIN, and connected to the output of BIST DAC which generates 2 different levels
appropriately adjusted for the current channel 300 mV / 37.5 mV depending on gain settings
2/16, while for the voltage channel, 300 mV is used. This mode is used as auto diagnostic
methodology of good behavior of the two modulators.
When disabled (MS3=GND), the input of the modulators comes from pins VIP, VIN and CIP,
and CIN. This is the normal operating condition.
Table 11. Selection of Hard, Soft or Test mode and enable of BIST
MS3
Mode
Description
GND
CLK
0
1
2
3
HardMode, BIST mode OFF
Soft mode
NCLK
VCC
Reserved
HardMode, BIST mode ON
8.5
Soft mode
The STPMS2 switches to Soft mode when MS3 is connected to CLK. In Soft mode, input
pins MS0, MS1 and MS2 control the serial communication port, as described in Table 12.
This way, all settings of the 40 internal configuration bits can be changed. The old values
remain in the registers until they are overwritten.
Table 12. Pins for SPI communication
Pin
Function
Description
MS0
MS1
MS2
MS3
SCL
TDI
Clock input
Data input
Enable
TDS
CLK
SPI operation
Doc ID 16525 Rev 3
23/33
Theory of operation
STPMS2
Table 13. Description of output signals and configuration bits CFG[39:0]
Hard mode
Soft mode
Internal signal
Description
Operating mode:
LP/HP=0: LPR
LP/HP=1: HPR
MS0
MS0
CFG[0]
CFG[1]
LP/HP
Gain selector of current channel pre-amplifier:
GAIN=0: x2
GAIN=1: x4
GAIN=2: x8
GAIN=3: x16
GAIN
TC
MS0
MS1
MS1
CFG[2]
CFG[3]
CFG[4]
Temperature compensation of voltage reference:
TC=0: TC = 60 ppm/°C
TC=1: Flattest TC = +30 ppm/°C
TC=2: TC = +160 ppm/°C
TC=3: TC = -160 ppm/°C
Output multiplexer enable:
MS2
MS2
CFG[5]
CFG[6]
DOMUL
PDV
DOMUL=0: outputs not multiplexed
DOMUL=1: outputs multiplexed
Power-down of voltage modulator:
PDV=0: Voltage modulator on
PDV=1: Voltage modulator off
Current modulator BIST DAC enable:
EBISTC=0: BISTC disabled
EBISTC=1: BISTC enabled
MS3
MS3
CFG[7]
CFG[8]
EBISTC
EBISTV
– EBISTC
Frequency output
0
CLK/215 x LFC
0
1
Voltage modulator BIST DAC enable:
EBISTC=0: BISTV disabled
EBISTC=1: BISTV enabled
– EBISTV
Frequency output
0
1
0
CLK/215 x LFV
CIP, CIN input pin enable:
MS3
MS3
1
CFG[9]
CFG[10]
CFG[11]
EINCHPC
EINCHPV
ECHPLFC
EINCHPC=0: CIN CIP disabled
EINCHPC=1: CIN CIP enabled
VIP, VIN input pin enable:
EINCHPC=0: VIN VIP disabled
EINCHPC=1: VIN VIP enabled
Low frequency chopper of current modulator enable:
ECHPLFC=0: LFC disabled
ECHPLFC=1: LFC enabled (1)
24/33
Doc ID 16525 Rev 3
STPMS2
Theory of operation
Table 13. Description of output signals and configuration bits CFG[39:0] (continued)
Hard mode
Soft mode
Internal signal
Description
1
0
CFG[12]
CFG[13]
LFC of current channel frequency selector:
– MC[2:0]
Frequency
CLK/1024
CLK/512
CLK/256
CLK/128
CLK/64
000
001 (1)
010
MC
011
0
CFG[14]
100
101 (2)
110 (2)
111 (2)
CLK/64
CLK/64
CLK/64
High Frequency Chopper of current modulator enable:
ECHPHFC=0: HFC disabled
ECHPHFC=1: HFC enabled (1)
1
CFG[15]
ECHPHFC
1
1
CFG[16]
CFG[17]
HFC of current channel frequency selector
– NC[2:0]
000 (2)
001 (2)
010
Frequency
CLK/256
CLK/128
CLK/256
CLK/128
CLK/64
NC
011 (1)
0
CFG[18]
100
101
CLK/32
110
CLK/16
111
CLK/8
Low Frequency Chopper of voltage modulator enable:
ECHPLFV=0: LFV disabled
ECHPLFV=1: LFV enabled (1)
1
CFG[19]
ECHPLFV
1
0
CFG[20]
CFG[21]
LFC of voltage channel frequency selector:
– MV[2:0]
Frequency
CLK/1024
CLK/512
CLK/256
CLK/128
CLK/64
000
001 (1)
010
MV
011
0
1
CFG[22]
CFG[23]
100
(2)
101
CLK/64
(2)
110
CLK/64
(2)
111
CLK/64
High Frequency Chopper of voltage modulator enable:
ECHPHFC=0: HFV disabled
ECHPHFC=1: HFV enabled (1)
ECHPHFV
Doc ID 16525 Rev 3
25/33
Theory of operation
STPMS2
Table 13. Description of output signals and configuration bits CFG[39:0] (continued)
Hard Mode
Soft mode
Internal signal
Description
1
1
CFG[24]
CFG[25]
HFC of voltage channel frequency selector:
– NV[2:0]
000 (2)
001 (2)
010
Frequency
CLK/256
CLK/128
CLK/256
CLK/128
CLK/64
CLK/32
CLK/16
CLK/8
NV
011 (1)
0
CFG[26]
100
101
110
111
Current modulator pseudo random signals enable:
EPRSC=0: PRSC disabled
1
1
CFG[27]
CFG[28]
EPRSC
EPRSV
EPRSC=1: PRSC enabled (1)
Voltage modulator pseudo random signals enable:
EPRSV=0: PRSV disabled
EPRSV=1: PRSV enabled (1)
0
0
0
0
0
0
0
0
CFG[29]
CFG[30]
CFG[31]
CFG[32]
CFG[33]
CFG[34]
CFG[35]
CFG[36]
-
-
-
Reserved
Reserved
Reserved
DAT and DAT output signal selector:
– DTMC[5:0]
00XXXX
00XXXX
00XXXX
00XXXX
01XX00
01XX01
01XX10
01XX11
1000XX
1001XX
1010XX
1011XX
110000
pdV
0
domul
DAT
bsV
DATn
bsC
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
0
(bsV,bsC) (bsVn,bsCn)
1
bsC
bsC
bsCn
bsCn
1
0
bsV
LFC
0
(bsV,bsC)
bsC
HFC
1
BISTC
PRSC
bsC
DTMC
1
bsC
0
LFV
0
HFV
(bsVn,bsCn)
bsCn
0
CFG[37]
1
BISTV
PRSV
LFV
1
bsCn
X
X
X
X
LFC
110101
HFV
HFC
111010
BISTV
PRSV
BISTC
PRSC
111111
0
0
CFG[38]
CFG[39]
-
-
Reserved
Reserved
1. Default value for Hard mode
2. Combinations not used
26/33
Doc ID 16525 Rev 3
STPMS2
Theory of operation
8.5.1
Writing to the configuration register in Soft mode
All 40 configuration bits must be overwritten.
Figure 20. Timings to switch to Soft mode after POR
CLK
MS0/SCL
CFG[0]
CFG[1]
CFG[2]
CFG[38]
CFG[39]
MS1/TDI
MS2/TDS
MS3/CLK
delay1
NEW values
CFG
AM09897v1
1. After power-on reset, Soft mode is selected (MS3=CLK), the bits MS0 .. MS2 must be stable at least 5*CLK
Figure 21. Timings to switch to Soft mode
CLK
MS0/SCL
CFG[1]
CFG[2]
CFG[3]
CFG[38]
CFG[0]
CFG[39]
MS1/TDI
MS2/TDS
MS3/CLK
delay2
OLD values
Hard Mode
NEW values
CFG
AM09898v1
2. After switching into Soft mode (MS3=CLK), the bits MS0 .. MS2 must be stable at least 2*CLK. The same
rule applies when switching from Soft mode to Hard mode: MS0 .. MS2 must be stable at least 2*CLK
Doc ID 16525 Rev 3
27/33
Package mechanical data
STPMS2
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Table 14. QFN16 (4 x 4 mm.) mechanical data
mm.
Dim.
Min.
0.80
0.00
Typ.
0.90
0.02
0.20
0.30
4.00
Max.
1.00
0.05
A
A1
A3
b
0.25
3.90
2.50
3.90
2.50
0.35
4.10
2.80
4.10
2.80
D
D2
E
4.00
E2
e
0.65
0.40
L
0.30
0.50
28/33
Doc ID 16525 Rev 3
STPMS2
Package mechanical data
Figure 22. QFN16 (4 x 4 mm.) drawing
7571203_A
Doc ID 16525 Rev 3
29/33
Package mechanical data
STPMS2
Tape & reel QFNxx/DFNxx (4x4) mechanical data
mm.
Typ.
inch.
Typ.
Dim.
Min.
Max.
330
Min.
Max.
12.992
0.519
A
C
12.8
20.2
99
13.2
0.504
0.795
3.898
D
N
101
3.976
T
14.4
0.567
Ao
Bo
Ko
Po
P
4.35
4.35
1.1
4
0.171
0.171
0.043
0.157
0.315
8
30/33
Doc ID 16525 Rev 3
STPMS2
Package mechanical data
Figure 23. QFN16 (4 x 4) footprint recommended data (dimension in mm.)
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Revision history
STPMS2
10
Revision history
Table 15. Document revision history
Date
Revision
Changes
23-Oct-2009
06-Jul-2011
11-Oct-2011
1
2
3
Initial release.
Document status promoted from preliminary data to datasheet.
Modified: 100 µF ==> 100 nF Section 8.2 on page 17.
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Doc ID 16525 Rev 3
STPMS2
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