STP6NK70Z [STMICROELECTRONICS]
N-CHANNEL 700V - 1.5ohm - 5A TO-220/TO-220FP Zener-Protected SuperMESH MOSFET; N沟道700V - 1.5ohm - 5A TO- 220 / TO- 220FP齐纳保护超网MOSFET![STP6NK70Z](http://pdffile.icpdf.com/pdf1/p00022/img/icpdf/STP6NK70Z_106379_icpdf.jpg)
型号: | STP6NK70Z |
厂家: | ![]() |
描述: | N-CHANNEL 700V - 1.5ohm - 5A TO-220/TO-220FP Zener-Protected SuperMESH MOSFET |
文件: | 总12页 (文件大小:338K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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STP6NK70Z
STF6NK70Z
N-CHANNEL 700V - 1.5Ω - 5A TO-220/TO-220FP
Zener-Protected SuperMESH™MOSFET
Table 1: General Features
Figure 1: Package
TYPE
V
R
I
D
Pw
DSS
DS(on)
STP6NK70Z
STF6NK70Z
700 V < 1.8 Ω
700 V < 1.8 Ω
5 A
5 A (*)
110 W
30 W
■ TYPICAL R (on) = 1.5 Ω
DS
■ EXTREMELY HIGH dv/dt CAPABILITY
■ IMPROVED ESD CAPABILITY
■ 100% AVALANCHE RATED
3
3
2
1
2
1
■ GATE CHARGE MINIMIZED
■ VERY LOW INTRINSIC CAPACITANCES
■ VERY GOOD MANUFACTURING
REPEATIBILITY
TO-220
TO-220FP
DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
stripbased PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOS-
FETs including revolutionary MDmesh™ products.
Figure 2: Internal Schematic Diagram
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR OFF-LINE POWER SUPPLIES,
ADAPTORS AND PFC
Table 2: Order Codes
SALES TYPE
STP6NK70Z
STF6NK70Z
MARKING
P6NK70Z
F6NK70Z
PACKAGE
TO-220
PACKAGING
TUBE
TO-220FP
TUBE
Rev. 3
September 2005
1/12
STP6NK70Z - STF6NK70Z
Table 3: Absolute Maximum ratings
Symbol
Parameter
Value
Unit
STP6NK70Z
STF6NK70Z
V
Drain-source Voltage (V = 0)
700
700
± 30
V
V
DS
GS
V
DGR
Drain-gate Voltage (R = 20 kΩ)
GS
V
Gate- source Voltage
V
GS
I
Drain Current (continuous) at T = 25°C
5
5 (*)
3.15 (*)
20 (*)
30
A
D
C
I
D
Drain Current (continuous) at T = 100°C
3.15
20
A
C
I
( )
Drain Current (pulsed)
A
DM
P
Total Dissipation at T = 25°C
110
0.87
W
TOT
C
Derating Factor
0.24
W/°C
V
V
Gate source ESD(HBM-C=100pF, R=1.5KΩ)
Peak Diode Recovery voltage slope
Insulation Withstand Voltage (DC)
4000
4.5
ESD(G-S)
dv/dt (1)
V/ns
V
V
ISO
-
2500
T
T
stg
Operating Junction Temperature
Storage Temperature
-55 to 150
-55 to 150
°C
°C
j
( ) Pulse width limited by safe operating area
(1) I ≤5A, di/dt ≤100A/µs, V ≤ V , T ≤ T
JMAX.
SD
DD
(BR)DSS
j
(*) Limited only by maximum temperature allowed
Table 4: Thermal Data
TO-220
1.14
TO-220FP
Rthj-case
Rthj-amb
Thermal Resistance Junction-case Max
4.2
°C/W
°C/W
°C
Thermal Resistance Junction-ambient Max
Maximum Lead Temperature For Soldering Purpose
62.5
300
T
l
Table 5: Avalanche Characteristics
Symbol
Parameter
Max Value
Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
5
A
(pulse width limited by T max)
j
E
AS
Single Pulse Avalanche Energy
200
mJ
(starting T = 25 °C, I = I , V = 50 V)
j
D
AR
DD
Table 6: Gate-Source Zener Diode
Symbol
BV
Parameter
Test Conditions
Igs=± 1mA (Open Drain)
Min.
30
Typ.
Max.
Unit
Gate-Source Breakdown
Voltage
V
GSO
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
2/12
STP6NK70Z - STF6NK70Z
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
Table 7: On /Off
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
Drain-source Breakdown
Voltage
I
D
= 1 mA, V = 0
700
V
(BR)DSS
GS
I
Zero Gate Voltage
V
V
= Max Rating
= Max Rating, T = 125°C
1
50
µA
µA
DSS
DS
Drain Current (V = 0)
GS
DS
C
I
Gate-body Leakage
V
GS
= ± 20 V
± 10
µA
GSS
Current (V = 0)
DS
V
V
V
= V , I = 100 µA
3
4.5
1.8
V
Gate Threshold Voltage
3.75
1.5
GS(th)
DS
GS
D
R
Static Drain-source On
Resistance
= 10 V, I = 2.5 A
Ω
DS(on
GS
D
Table 8: Dynamic
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
g
(1)
Forward Transconductance
V
= 15 V , I = 2.5 A
4.4
S
fs
DS
DS
D
C
C
C
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
= 25 V, f = 1 MHz, V = 0
930
105
22
pF
pF
pF
iss
GS
oss
rss
C
(3) Equivalent Output
V
V
= 0 V, V = 0 to 560 V
70
pF
OSS eq
.
GS
DS
Capacitance
t
t
Turn-on Delay Time
Rise Time
Turn-off-Delay Time
= 350 V, I = 2.5 A,
17
18
45
30
ns
ns
ns
ns
d(on)
DD
D
t
r
R = 4.7 Ω, V = 10 V
G GS
(see Figure 17)
d(off)
Fall Time
t
f
Q
V
V
= 560 V, I = 5 A,
= 10 V
34
6.5
17
47
nC
nC
nC
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
g
DD
D
Q
gs
gd
GS
Q
(see Figure 20)
Table 9: Source Drain Diode
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I
5
20
A
A
Source-drain Current
Source-drain Current (pulsed)
SD
(2)
I
SDM
V
(1)
I
I
= 5 A, V = 0
Forward On Voltage
1.6
V
SD
SD
GS
t
rr
= 5 A, di/dt = 100 A/µs
= 35V
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
432
2.37
11
ns
µC
A
SD
Q
V
DD
(see Figure 18)
rr
I
RRM
t
Q
I
V
= 5 A, di/dt = 100 A/µs
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
588
3.38
11.5
ns
µC
A
rr
SD
= 35V, T = 150°C
rr
DD
j
I
(see Figure 18)
RRM
(1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(2) Pulse width limited by safe operating area.
(3) C
is defined as a constant equivalent capacitance giving the same charging time as C when V increases from 0 to 80% V
.
DSS
oss eq.
oss
DS
3/12
STP6NK70Z - STF6NK70Z
Figure 3: Safe Operating Area
Figure 6: Thermal Impedance
Figure 4: Safe Operating Area for TO-220FP
Figure 7: Thermal Impedance for TO-220FP
Figure 5: Output Characteristics
Figure 8: Transfer Characteristics
4/12
STP6NK70Z - STF6NK70Z
Figure 9: Transconductance
Figure 12: Static Drain-source On Resistance
Figure 10: Gate Charge vs Gate-source Voltage
Figure 13: Capacitance Variations
Figure 11: Source-Drain Diode Forward Char-
acteristics
Figure 14: Normalizzed BVdss vs Temperature
5/12
STP6NK70Z - STF6NK70Z
Figure 15: Avalanche Energy vs Starting Tj
6/12
STP6NK70Z - STF6NK70Z
Figure 16: Unclamped Inductive Load Test Cir-
cuit
Figure 19: Unclamped Inductive Wafeform
Figure 17: Switching Times Test Circuit For
Resistive Load
Figure 20: Gate Charge Test Circuit
Figure 18: Test Circuit For Inductive Load
Switching and Diode Recovery Times
7/12
STP6NK70Z - STF6NK70Z
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These
packages have a Lead-free second level interconnect . The category of second level interconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an
ST trademark. ECOPACK specifications are available at: www.st.com
8/12
STP6NK70Z - STF6NK70Z
TO-220FP MECHANICAL DATA
mm.
inch
DIM.
MIN.
4.4
TYP
MAX.
4.6
2.7
2.75
0.7
1
MIN.
0.173
0.098
0.098
0.017
0.030
0.045
0.045
0.195
0.094
0.393
TYP.
MAX.
0.181
0.106
0.108
0.027
0.039
0.067
0.067
0.204
0.106
0.409
A
B
2.5
D
2.5
E
0.45
0.75
1.15
1.15
4.95
2.4
F
F1
F2
G
1.7
1.7
5.2
2.7
10.4
G1
H
10
L2
L3
L4
L5
L6
L7
Ø
16
0.630
28.6
9.8
2.9
15.9
9
30.6
10.6
3.6
1.126
.0385
0.114
0.626
0.354
0.118
1.204
0.417
0.141
0.645
0.366
0.126
16.4
9.3
3
3.2
L3
L6
L7
1 2
L4
3
L5
L2
9/12
STP6NK70Z - STF6NK70Z
TO-220 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
4.60
0.88
1.70
0.70
15.75
10.40
2.70
5.15
1.32
6.60
2.72
14
MIN.
0.173
0.024
0.045
0.019
0.60
MAX.
0.181
0.034
0.066
0.027
0.620
0.409
0.106
0.202
0.052
0.256
0.107
0.551
0.154
A
b
4.40
0.61
1.15
0.49
15.25
10
b1
c
D
E
0.393
0.094
0.194
0.048
0.244
0.094
0.511
0.137
e
2.40
4.95
1.23
6.20
2.40
13
e1
F
H1
J1
L
L1
L20
L30
øP
Q
3.50
3.93
16.40
28.90
0.645
1.137
3.75
2.65
3.85
2.95
0.147
0.104
0.151
0.116
10/12
STP6NK70Z - STF6NK70Z
Table 10: Revision History
Date
Revision
Description of Changes
24-Sep-2004
04-Nov-2004
06-Sep-2005
1
2
3
First release.
Complete version
Inserted Ecopack indication
11/12
STP6NK70Z - STF6NK70Z
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2005 STMicroelectronics - All Rights Reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
12/12
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