STP60NS04ZB [STMICROELECTRONICS]
N-CHANNEL CLAMPED 10mohm - 60A TO-220 FULLY PROTECTED MESH OVERLAY⑩ MOSFET; N沟道钳位为10Mohm - 60A TO- 220充分保障MESH OVERLAY⑩ MOSFET
| 型号： | STP60NS04ZB |
| 厂家： | 
ST |
| 描述： | N-CHANNEL CLAMPED 10mohm - 60A TO-220 FULLY PROTECTED MESH OVERLAY⑩ MOSFET |
| 文件： | 总8页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STP60NS04ZB
N-CHANNEL CLAMPED 10mΩ - 60A TO-220
FULLY PROTECTED MESH OVERLAY™ MOSFET
TYPE
V
DSS
R
I
D
DS(on)
STP60NS04ZB
CLAMPED < 0.015 Ω
60 A
■
■
■
■
TYPICAL R (on) = 0.010 Ω
100% AVALANCHE TESTED
LOW CAPACITANCE AND GATE CHARGE
175°C MAXIMUM JUNCTION TEMPERATURE
DS
3
2
1
DESCRIPTION
TO-220
This fully clamped MOSFET is produced by using
the latest advanced Company’s Mesh Overlay pro-
cess which is based on a novel strip layout. The in-
herent benefits of the new technology coupled with
the extra clamping capabilities make this product
particularly suitable for the harshest operation con-
ditions such as those encountered in the automotive
environment .Any other application requiring extra
ruggedness is also recommended.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
■
■
■
ABS,SOLENOID DRIVERS
MOTOR CONTROL
DC-DC CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
DS
Drain-source Voltage (V = 0)
CLAMPED
GS
V
Drain-gate Voltage
CLAMPED
V
DG
V
Gate- source Voltage
CLAMPED
V
GS
I
Drain Current (continuous) at T = 25°C
60
42
± 50
± 50
240
150
1
A
D
C
I
Drain Current (continuous) at T = 100°C
A
D
C
I
Drain Gate Current (continuous)
Gate Source Current (continuous)
Drain Current (pulsed)
mA
mA
A
DG
I
GS
I
( )
DM
P
Total Dissipation at T = 25°C
W
TOT
C
Derating Factor
W/°C
kV
kV
kV
V
V
Gate-Source ESD(HBM-C=100 pF, R=1.5 KΩ)
Gate-Drain ESD(HBM-C=100 pF, R=1.5 KΩ)
Drain-Source ESD(HBM-C=100 pF, R=1.5 KΩ)
Storage Temperature
6
ESD(G-S)
4
ESD(G-D)
V
4
ESD(D-S)
T
stg
–65 to 175
°C
T
Max. Operating Junction Temperature
j
(•)Pulse width limited by safe operating area
November 2002
1/8
STP60NS04ZB
THERMAL DATA
Rthj-case
Rthj-amb
Thermal Resistance Junction-case Max
1.0
62.5
300
°C/W
°C/W
°C
Thermal Resistance Junction-ambient Max
T
Maximum Lead Temperature For Soldering Purpose
l
AVALANCHE CHARACTERISTICS
Symbol
Parameter
Max Value
Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
60
A
(pulse width limited by T max, δ < 1%)
j
E
Single Pulse Avalanche Energy
400
mJ
AS
(starting T = 25 °C, I = I , V = 30 V )
j
D
AR
DD
ELECTRICAL CHARACTERISTICS (T
= 25°C UNLESS OTHERWISE SPECIFIED)
CASE
OFF
Symbol
Parameter
Clamped Voltage
Test Conditions
= 1 mA, V = 0
Min.
Typ.
Max.
Unit
V
I
33
V
(BR)DSS
D
GS
-40 < Tj < 175 °C
I
V
V
= 16 V,T = 150 °C
50
µA
µA
DSS
DS
DS
j
Zero Gate Voltage
Drain Current (V = 0)
GS
= 16 V,T = 175 °C
100
j
I
V
V
= ±10 V,T = 175 °C
50
150
µA
µA
Gate-body Leakage
GSS
GS
GS
j
Current (V = 0)
= ±16 V,T = 175 °C
DS
j
V
Gate-Source
I
= ±100 µA
GS
18
V
GSS
Breakdown Voltage
ON (1)
Symbol
Parameter
Test Conditions
= V , I = 1 mA
Min.
Typ.
Max.
Unit
V
GS(th)
Gate Threshold Voltage
V
1.7
3
4.2
V
DS
GS
D
-40 < Tj < 150 °C
R
Static Drain-source On
Resistance
V
V
= 10 V, I = 30 A
11
10
15
14
mΩ
mΩ
DS(on)
GS
GS
D
= 16 V, I = 30 A
D
DYNAMIC
Symbol
Parameter
Forward Transconductance
Input Capacitance
Test Conditions
Min.
Typ.
40
Max.
Unit
S
g
(1)
V
=15 V ,I = 30 A
20
fs
DS
D
C
C
V
= 25 V, f = 1 MHz, V = 0
1700
800
190
2100
1000
240
pF
pF
pF
iss
DS
GS
Output Capacitance
oss
C
rss
Reverse Transfer
Capacitance
2/8
STP60NS04ZB
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol
Parameter
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Test Conditions
Min.
Min.
Typ.
48
Max.
Unit
nC
Q
V
V
= 18 V, I = 60 A,
62
g
DD
GS
D
= 10 V
Q
13
nC
gs
Q
16
nC
gd
SWITCHING OFF
Symbol
Parameter
Test Conditions
Typ.
Max.
Unit
t
Off Voltage Rise Time
Fall Time
Cross-over Time
V
= 30 V, I = 60 A,
60
45
100
75
60
130
ns
ns
ns
r(Voff)
CLAMP
D
t
f
R = 4.7 Ω, V = 10 V
G GS
(see test circuit, Figure 3)
t
c
SOURCE DRAIN DIODE
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
60
Unit
A
I
Source-drain Current
SD
I
(2)
(1)
Source-drain Current (pulsed)
Forward On Voltage
240
1.5
A
SDM
V
I
I
= 60 A, V = 0
V
SD
SD
SD
GS
t
= 60 A, di/dt = 100 A/µs
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
50
62
ns
nC
A
rr
V
= 15 V, T = 150°C
j
DD
Q
rr
RRM
(see test circuit, Figure 5)
I
2.6
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedance
3/8
STP60NS04ZB
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/8
STP60NS04ZB
Normalized Gate Thereshold Voltage vs Temp.
Normalized On Resistance vs Temperature
ZeroGateVoltageDrainCurrentvsTemperature
Source-drain Diode Forward Characteristics
Normalized BVDSS vs Temperature
5/8
STP60NS04ZB
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For
Fig. 4: Gate Charge test Circuit
Resistive Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/8
STP60NS04ZB
TO-220 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
4.40
1.23
2.40
TYP.
MAX.
4.60
1.32
2.72
MIN.
0.173
0.048
0.094
MAX.
0.181
0.051
0.107
A
C
D
D1
E
1.27
0.050
0.49
0.61
1.14
1.14
4.95
2.4
0.70
0.88
1.70
1.70
5.15
2.7
0.019
0.024
0.044
0.044
0.194
0.094
0.393
0.027
0.034
0.067
0.067
0.203
0.106
0.409
F
F1
F2
G
G1
H2
L2
L4
L5
L6
L7
L9
DIA.
10.0
10.40
16.4
0.645
13.0
2.65
15.25
6.2
14.0
2.95
15.75
6.6
0.511
0.104
0.600
0.244
0.137
0.147
0.551
0.116
0.620
0.260
0.154
0.151
3.5
3.93
3.85
3.75
L2
Dia.
L5
L9
L7
L6
L4
P011C
7/8
STP60NS04ZB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2002 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
© http://www.st.com
8/8
相关型号：
STP60NS04ZB_06
N-channel clamped - 10mohm - 60A - TO-220 Fully protected Mesh Overlay Power MOSFET
STMICROELECTR
STP62NS04Z_06
N-channel clamped 12.5mOHM - 62A - TO-220 Fully protected MESH OVERLAY Power MOSFET
STMICROELECTR
STP6308
STP6308 is the dual P-Channel enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology.
STANSON
STP6621
STP6621 is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology.
STANSON
STP6N120K3
N-channel 1200 V, 1.95 Ω typ., 6 A SuperMESH3⢠Power MOSFET in TO-3PF, TO-220 and TO-247 packages
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明