STOTG04E [STMICROELECTRONICS]
USB-OTG Full-speed Transceiver; USB- OTG全速收发器
| 型号： | STOTG04E |
| 厂家： | 
ST |
| 描述： | USB-OTG Full-speed Transceiver |
| 文件： | 总26页 (文件大小：479K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STOTG04E
USB-OTG Full-speed Transceiver
Feature summary
■ Meets USB specification Rev. 2.0 And on-the-
go supplement to the USB 2.0 specification
■ Analog car kit-compatible
■ Four operating modes: USB, I2C, UART and
Audio
QFN24 (4mmx4mm)
■ Configurable using I2C serial interface
■ Capable of 12Mbit/s full-speed and 1.5Mbit/s
low-speed modes of operation
Description
■ Standard digital interface compliant with the
OTG transceiver specification
The STOTG04 is a USB On-The-Go full-speed
transceiver. It provides complete physical layer
(PHY) solution for any USB-OTG device. It
contains VBUS charge pump and comparators, ID
line detector and interrupt generator, and the USB
differential driver and receivers. The STOTG04
transceiver is suitable for mobile and battery
powered devices because of its low power
consumption and power-down operating mode.
■ Supports the session request protocol (SRP)
and host negotiation protocol (HNP)
■ 35mA typical VBUS charge pump output current
for 3.3V supply voltage
■ Ability to control external charge pump for
higher VBUS currents
■ Integrated pull-up/-down resistors
The transceiver is capable of operation in several
different modes. It can operate in basic USB-OTG
mode, as an I2C and UART transceiver, or in
audio mode. Behavior of the transceiver is fully
configurable through the two-wire I2C serial bus.
The transceiver supports session request protocol
and host negotiation protocol.
■
6kV ESD Protection on all USB pins (contact
discharge)
■ +1.6V to +3.6V Digital power supply and +2.7V
to +5.5V analog supply voltage range
■ Power-down mode with very low power
consumption for battery powered devices
The applications are mobile phones, PDAs, MP3
players, printers and digital cameras.
Applications
■ Mobile phones
■ PDAs
■ MP3 players
■ Digital cameras
■ Printers
Order code
Part number
Package
QFN24 (4mm x 4mm)
Packaging
STOTG04EQTR
October 2006
4000 parts per reel
Rev. 3
1/26
www.st.com
26
Contents
STOTG04E
Contents
1
2
3
4
5
6
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Charge pump characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
V
BUS
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ID Line detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Driver and receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.7.1 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.7.2 USB Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.7.3 UART and I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.7.4 Audio mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.8
6.9
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2
I C Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.10 Device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.11 Bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.12 External charge pump switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26
STOTG04E
Pin configuration
1
Pin configuration
Figure 1. Pin connections (Bottom View )
Table 1.
PlN N°
Pin description
SYMBOL
ADR_PSW
SDA
I/O
I/O
I/O
NAME AND FUNCTION
Least significant bit of the I2C address of the transceiver input latched on reset;
PSW output enabling or disabling an external charge pump
1
2
I2C serial data (1)
I2C clock
Active low logic reset
Active low interrupt signal (open-drain)
Mode of the transceiver (0 = low-speed, 1 = full-speed) (2)
Internal voltage regulator output; an external decoupling capacitor should be
connected (3)
3
4
5
6
SCL
RESET/
INT/
I
I
O
I
SPEED
VTRM
7
8
Power
I
SUSPEND
Power down input (0 = active mode, 1 = power down) (See Table 8)
Output enable of the differential driver in the USB mode, I2C data enable in the
I2C mode or interrupt output
9
OE_TP_INT/
I/O
10
11
12
VM
VP
RCV
O
O
O
-
D– single-ended receiver output
D+ single-ended receiver output
Differential receiver output
Not Connected
ExpPad
Single-ended zero input/output in the DAT_SE0 transmit mode, negative data
input/output in the single-ended transmit mode or TXD in the UART mode
Data input/output in the DAT_SE0 transmit mode, positive data input/output in
the single-ended transmit mode or RXD in the UART mode
Negative data line in the USB mode, I2C clock output in the I2C mode or serial
data output in the UART mode
13
14
15
SE0_VM
DAT_VP
D-
I/O
I/O
I/O
Positive data line in the USB mode, I2C serial data in the I2C mode or serial data
input in the UART mode
16
D+
I/O
17
18
19
GND
ID
VBUS
Power Common analog and digital ground
I/O
I/O
ID pin of the USB connector used for protocol identification
VBUS line of the USB interface – it needs an external capacitor of 4.7µF
3/26
Pin configuration
STOTG04E
PlN N°
SYMBOL
I/O
NAME AND FUNCTION
VBAT
20
21
22
23
24
Power Analog power supply voltage (+2.7V to +5.5V)
CAP1
CAP2
CGND
VIF
I/O
I/O
External capacitor pin for the charge pump
External capacitor pin for the charge pump
Power Ground for the charge pump
Power Logic power supply (+1.6V to 3.6V)
(1) Input and open-drain output
(2) Input with internal pull-up resistor
(3) Internal regulator can be bypassed by connecting V
to this pin when the V
is in range of 2.7V to 3.6V
BAT
BAT
Figure 2. Functional diagram
4/26
STOTG04E
Maximum ratings
2
Maximum ratings
Table 2.
Absolute maximum ratings
Parameter
Symbol
VIF
Value
Unit
Logic Supply Voltage
-0.5 to + 4.5
-0.5 to + 6.5
-0.5 to + 4.5
V
V
VBAT
Analog Supply Voltage
VDCDIG
TSTG
DC Input Voltage on any logic interface pin
Storage Temperature Range
V
-65 to + 150
°C
Human Body Model
Contact Discharge (*)
± ± 8
± ± 6
Electrostatic discharge voltage
on USB pins
VESD
kV
(*) In accordance to IEC61000-4-2, level 3.
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional Operation under these con-
ditions is not implied.
Table 3.
Thermal data
Symbol
Parameter
Value
Unit
RthJA
Thermal Resistance Junction-Ambient
59
°C/W
Table 4.
Symbol
VIF
Recommended operating condition
Parameter
Min.
1.6
2.7
-40
100
1
Typ.
Max.
3.6
Unit
V
Logic Supply Voltage
1.8
3.3
VBAT
TA
Analog Supply Voltage
5.5
V
Operating Temperature Range
Charge pump external capacitor
Charge pump tank capacitor
Voltage regulator external capacitor
Data lines impedance matching resistor
+85
470
6.5
°C
nF
µF
µF
Ω
CEXT
CT
220
4.7
1
CTRM
RS
20
Table 5.
Symbol
ESD Performance
Parameter
Value
Unit
Air discharge (10 pulses)
Contact discharge (10 pulses)
Air discharge (10 pulses)
± ± 8
± ± 6
± ± 2
± ± 2
IEC-61000-4-2 (D+, D-, VBUS, ID)
ESD
kV
IEC-61000-4-2 (other pins)
Contact discharge (10 pulses)
5/26
Electrical characteristics
STOTG04E
3
Electrical characteristics
Table 6.
Electrical characteristics
Characteristics measured over recommended operating conditions unless otherwise is
noted. All typical values are referred to TA = 25°C, VIF = 1.8V, VBAT = 3.3V, RS = 20Ω,
C
EXT = 220nF, CT = 4.7µF and CTRM = 1µF
Symbol
Parameter Test Conditions
Min.
Typ.
Max. Unit
Active mode (1,2)
Power down mode
Transceiver current while
transmitting and receiving (1, 2)
Charge pump current, ILOAD = 8mA
0.6
1.6
1
mA
µA
IIF
Digital Part Supply Current
Operating Supply Current
4.5
17
7
mA
µA
IBAT
25
1
Power down mode (4)
LOGIC INPUTS AND OUTPUTS
IOH = -100µA
IOH = -2mA
IOL = 100µA
IOL = 2mA
VIF-0.15
VIF-0.40
V
V
VOH
VOL
HIGH level output voltage
LOW level output voltage
0.15
0.40
V
V
VIH
VIL
0.7VIF
HIGH level input voltage
LOW level input voltage
Input leakage current
Off-state output current
V
0.3VIF
V
ILKG
IOZ
VBUS
VBUS
-1
-5
1
5
µA
µA
VBUS output voltage
ILOAD = 8mA
4.4
4.9
3
5.25
200
60
V
VBUS_LKG VBUS leakage voltage
VBUS_RIP VBUS output ripple
No Load
mV
mV
ILOAD = 8mA, CT = 4.7µF
30
Charge-pump switching
fCP
0.5
40
0.8
1.5
MHz
frequency (2)
RVBUS
IVBUS
VBUS input impedance
Maximum VBUS source current CEXT = 220 nF, VBUS > 4.4V
76
35
100
kΩ
mA
20
VBUS valid comparator
threshold
Session valid comparator
threshold for both A and B
devices
Low to high transition
High to low transition
Low to high transition
4.40
4.40
0.8
VBUS_VLD
V
2.0
2.0
VSES_VLD
V
High to low transition
0.8
281
656
RVBUS_PU VBUS charge pull-up resistance
640
Ω
Ω
VBUS discharge pull-down
RVBUS_PD
1260
resistance
ID
VID_BIAS
RID_PU
RID_GND
RID_FLOAT
RCP_ID = 140kΩ, ± VBAT ≤5V
ID pin bias voltage
1.3
70
1.9
3.0
130
10
V
ID pin pull-up resistance
105
kΩ
Ω
kΩ
ID line short resistance to detect id_gnd state
ID line short resistance to detect id_float state
800
6/26
STOTG04E
Electrical characteristics
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Unit
DIFFERENTIAL DRIVER
ZDRV
Excluding external RS
RLH = 14.25kΩ, ± VTRM = 3.3V
LH = 14.25kΩ, ± VTRM = 2.7V
RLL = 1.425kΩ
CLOAD = 50 to 600pF
Output Impedance
8
16
24
3.6
3.0
0.3
2.0
Ω
V
V
V
V
2.8
2.6
0
VOH_DRV
HIGH level output voltage
R
VOL_DRV
VCRS
LOW level output voltage
Driver crossover voltage
1.3
1.67
DIFFERENTIAL AND SINGLE-ENDED RECEIVERS
Differential receiver input
sensitivity (VD+ - VD-)
VDI
VCM = 0.8 to 2.5V
-200
200
mV
V
Low to high transition
High to low transition
0.8
0.8
1.5
1.6
1.1
2.0
2.0
SE receivers switching
threshold
VSE-TH
RIN
CIN
Input resistance
PU/PD resistor deactivated
MΩ
pF
Input capacitance
10
30
Bus Idle
Receiving mode
900
1425
1300 1575
2200 3090
Data line pull-up resistance on
pin D+
Data line pull-up resistance on
pin D-
RPU_D+
RPU_D-
Ω
Ω
900
1300 1575
RPD
Data line pull-down resistance
Data line leakage voltage
14.25
17.0
200
24.8
342
kΩ
mV
VDT_LKG
RPU_EXT = 300kΩ
CAR KIT INTERRUPT DETECTOR
VCR_INT_TH
Car kit Interrupt threshold
I2C AND UART MODES – D+ AND D- PINS
0.4
0.6
V
VOH
VOL
IOH= -2mA
IOL = 2mA
HIGH level output voltage (3)
LOW level output voltage
HIGH level input voltage
LOW level input voltage
2.4
0
3.6
0.4
V
V
V
V
Ω
VIH
2.0
VIL
0.8
RDP_I2C
SDA line internal pull-up resist.
1425
2200 3090
VOLTAGE REGULATOR
VBAT = 3.3 to 5V, no load; 2V7en=0
VBAT = 2.8 to 5V, no load; 2V7en=1
VBAT = 3.6V, VTRM > 3V; 2V7en=0
3.0
2.6
3.3
3.6
2.9
20
V
V
VTRM
ITRM
Internal power supply voltage
2.75
mA
mA
Voltage regulator output
current
VBAT = 3.0V, VTRM >2.6V; 2V7en=1
10
(1) Transmitting and receiving at 12Mbit/s, loads of 50pF on D+ and D- pins, no capacitive loads on VP and VM pins
(2) Not tested in production; characterization only
(3) Except D+ pin in the I2C mode where this pin is open-drain with internal pull-up resistor
(4) See paragraph 6.7.1
7/26
Electrical characteristics
STOTG04E
Table 7.
Symbol
Switching characteristics
Over recommended operating conditions unless otherwise is noted. All the typical values are
referred to TA = 25°C, VIF = 1.8V, VBAT = 3.3V, RS = 20Ω, CEXT = 220nF, CT = 4.7µF, and
CTRM = 1µF
Parameter
Test Conditions
Min.
Typ.
Max. Unit
TVBUS_RISE VBUS rise time
ILOAD = 8mA, CT = 10µF
1
100
ms
DIFFERENTIAL DRIVER
Full-speed mode, CLOAD = 50pF
Low-speed mode, CLOAD = 600pF
Full-speed mode, CLOAD = 50pF
Low-speed mode, CLOAD = 600pF
Full-speed mode, CLOAD = 50pF
Low-speed mode, CLOAD = 600pF
Full-speed mode, CLOAD = 50pF
Low-speed mode, CLOAD = 600pF
Full-speed mode, CLOAD = 50pF
Low-speed mode, CLOAD = 600pF
Full-speed mode, CLOAD = 50pF
Low-speed mode, CLOAD = 600pF
4
75
4
8.5
110
8.5
20
300
20
tR
tF
Data signal rise time
Data signal rise time
ns
ns
ns
ns
ns
ns
75
110
300
38
Propagation delay of the driver,
rising edge; DAT_SE0 mode
280
55
tP_DRV_R
Propagation delay of the driver,
rising edge; VP_VM mode
300
38
Propagation delay of the driver,
falling edge; DAT_SE0 mode
280
55
tP_DRV_F
Propagation delay of the driver,
rising edge; VP_VM mode
300
111.11
Rise and fall time matching (tR/ Full-speed mode
90
80
tRFM
tF) excluding the first transition
from the idle state
%
Low-speed mode
125
SINGLE-ENDED RECEIVERS
Full-speed mode, input slope 15ns
Low-speed mode, input slope
150ns
Full-speed mode, input slope 15ns
Low-speed mode, input slope
150ns
18
18
18
18
Propagation delay of the SE
receiver, rising edge
tP_SE_R
ns
ns
Propagation delay of the SE
receiver, falling edge
tP_SE_F
DIFFERENTIAL RECEIVER
Propagation delay of the SE
Full-speed mode, input slope 15ns
Low-speed mode, input slope
150ns
Full-speed mode, input slope 15ns
Low-speed mode, input slope
150ns
24
24
24
24
tP_DIF_R
ns
ns
receiver, rising edge
Propagation delay of the SE
receiver, falling edge
tP_DIF_F
DIGITAL INTERFACE
tSET_OE
Output enable setup time
50
0
ns
ns
Output to input bus turnaround
time (1, 2)
Output to input bus turnaround
time (1, 2)
tTA_OI
5
5
tTA_IO
0
ns
I2C BUS (3)
fSCL
SCL clock frequency
100
kHz
µs
tLOW
Low period of the SCL clock
High period of the SCL clock
4.7
4.0
tHIGH
µs
Rise time of both SDA and SCL
signals
tIICR
1000
ns
8/26
STOTG04E
Electrical characteristics
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Unit
Fall time of both SDA and SCL
signals
Setup time for a repeated START
condition
Hold time for the START and
repeated START conditions
tIICF
300
ns
µs
µs
tSU_STA
4.7
4.0
tHD_STA
tSU_DAT
tHD_DAT
tSU_STO
Data setup time
Data hold time
250
0
ns
µs
Setup time for the STOP
condition
Bus free time between a STOP
and START condition
4.0
4.7
µs
µs
tBUF
NOTE 1: Parameter applies to the OE_TP_INT/, DAT_VP, and SE0_VM signals
NOTE 2: Not tested in production; characterization only
NOTE 3: Requirements defined by the I2C-Bus Specification, version 2.1
9/26
Charge pump characteristics
STOTG04E
4
Charge pump characteristics
Figure 3.
Output characteristics
Figure 4.
Output ripple
10/26
STOTG04E
Timing diagrams
5
Timing diagrams
Figure 5. Rise and fall times
Figure 6. Differential driver propagation delay
Figure 7. Differential receiver propagation delay
11/26
Timing diagrams
STOTG04E
Figure 8. Output enable setup time
tSET_OE
VIH
OE_TP_INT/
VIL
VIH
DAT_VP
SE0_VM
USB Idle State
Data to Transmit
VIL
Figure 9. Bus turnaround time
tTA_OI
VIH
OE_TP_INT/
tTA_IO
VIL
VIH
DAT_VP
SE0_VM
output
input
output
VIL
Figure 10. I2C BUS timing
tLOW
tIIC_F
tHIGH
tIIC_R
tHD_STA
tSU_STO
SCL
SDA
S
Sr
P
S
tIIC_F
tHD_STA
tSU_DAT
tHD_DAT
tSU_STA
tIIC_R
tBUF
12/26
STOTG04E
Timing diagrams
Figure 11. Block diagram
V B A T
A D R _ P S W
S C L
C A P 1
C A P 2
V B U S
C h a r g e
P u m p
S D A
O s c illa to r
V B A T
S P E E D
S U S P E N D
B a n d g a p
R e f e r e n c e
V T R M
O E _ T P _ IN T /
D A T _ V P
S E 0 _ V M
D +
D -
R C V
V P
V B A T
V T R M
V o lt a g e
R e g u la to r
V M
V B A T
ID
I N T /
R E S E T /
13/26
Block description
STOTG04E
6
Block description
The STOTG04 integrates a charge pump and comparators for the VBUS, ID line detector and interrupt
switch, differential data driver, differential and single-ended receivers, low dropout voltage regulator and
control logic. The STOTG04 provides a complete solution for connection of a digital USB OTG controller
to the physical Universal Serial Bus.
6.1
Charge pump
The VBUS line voltage is provided using the internal charge pump. It is capable of sourcing up to 35mA
load current. The charge pump can be powered by voltage from 2.7V to 5.5V. It needs two capacitors for
its operation: an external capacitor of 220nF connected between the CAP1 and CAP2 pins and a 4.7µF
decoupling tank capacitor on the VBUS. If an application needs current that is higher than 35mA, an
external charge pump or a switch controlled by the ADR_PSW pin may be used.
6.2
V
Comparators
BUS
These comparators monitor the VBUS voltage. They provide current status information for the VBUS line.
VBUS valid status means that the voltage is above VBUS_VLD. Session valid status means that the VBUS
voltage is above VSES_VLD level.
6.3
Voltage regulator
An internal low-dropout voltage regulator provides power for the bus drivers and receivers. The regulator
needs an external capacitor of 1µF on the VTRM pin for proper operation. The regulator can provide 3.3V
or 2.75V output voltages according to 2V7_en bit in Control Register 3.
The regulator can be bypassed by tying the VTRM pin to the VBAT power supply voltage when the analog
supply voltage is in the range of 3.0V (or 2.7V) to 3.6V.
6.4
ID Line detector
This block senses ID line status. It is capable of detecting three different line states:
• pin floating;
• pin tied to ground;
• pin grounded via a 140kΩ resistor.
The ID detector can also generate an interrupt by shorting the pin to ground.
6.5
Driver and receivers
The driver can operate in several different modes. It can act as a simple low-speed and full-speed
differential USB driver, as two independent single-ended drivers in the UART mode, or as an open-drain
driver in the I2C mode.
This block contains one differential receiver for the USB operation mode and two single-ended receivers
for USB signaling as well as UART and I2C receivers.
14/26
STOTG04E
Block description
6.6
Control logic
This block controls the behavior of whole chip. It communicates with the external environment via the I2C
serial bus. The control logic block consists of I2C slave interface, configuration and status registers, and
some glue logic.
6.7
Modes of operation
The STOTG04 can operate in two different power modes and in three operating modes. They can be
controlled by logic signals and control registers.
6.7.1 Power modes
When there is no need for the USB function, the STOTG04 reduces power consumption by implementing
the Power-down mode. The power modes can be controlled by the Suspend Bit of Control Register 1 or/
and the SUSPEND pin (see Table 8).
Table 8.
Power modes
SUSPEND BIT
SUSPEND PIN
Power Mode
0
X
1
X
0
1
normal operation
power-down
Although in power down mode all analog blocks should be switched off, some of them could be turned on
by bits in the control registers having higher priority than suspend bit. In order to obtain minimum power
consumption in power down mode the device must be configured has shown in Table 9. The digital part is
fully static so that it almost does not consume power. All of the interrupts (except BDIS_ACON) are fully
operational in Power-down mode, as is the I2C interface.
Table 9.
Power down mode setup
SUSPEND BIT
SUSPEND PIN
Control register 1
Control register 2
Control register 3
1
1
X1X0XX0-
00XX00X0
-XXXX0XX
X = Don’t care
- = Reserved
Bit order: 0...7
6.7.2 USB Modes
The STOTG04 transceiver has two basic USB operational modes. These modes define how the digital IO
pins of the transceiver will be used. Independently of USB operating mode, some signals always have the
same function (see Table 10).
Table 10. Digital interface signals
Signal
Function
RCV
VP
VM
Differential receiver output
D+ single-ended receiver output
D- single-ended receiver output
OE_TP_INT/
Output enable signal of the differential driver
The RCV signal is active in the VP_VM mode only. Its output driver is controlled by the OE_TP_INT/
signal. Operating modes are described below. The meanings of the DAT_VP and SE0_VM signals
depend on the mode of operation. Both of these signals can be bidirectional or unidirectional. The
15/26
Block description
STOTG04E
direction is controlled by bidi_en Bit of Control Register 3 (described later). When these signals are
bidirectional, the direction is controlled by the OE_TP_INT/ signal (see Tables 11 and 12).
The actual mode of operation is controlled by the dat_se0 Bit of Control Register 1 (see Tables 11 and 12)
Table 11. DAT_SE0 (dat_se0 = 1)
bidi_en
OE/*
DAT_VP
Differential driver input
Differential receiver output
Differential driver input
SE0_VM
SE0 driver input
SE0 detector output
SE0 driver input
0
1
X
1
0
Table 12. VP_VM (dat_se0 = 0)
bidi_en
OE/*
DAT_VP
SE0_VM
0
1
X
D+ driver input
D+ receiver output
D+ driver input
D- driver input
D- receiver output
D- driver input
1
0
* State of the OE_TP_INT/ signal.
In the USB mode of operation it is necessary to control the rise and fall times of the transmission driver.
These times are different for low-speed and full-speed USB settings. Selection of actual USB speed can
be done using the bit speed of Control Register 1 or/and the SPEED pin (see table 13).
Table 13. USB Speed selection
speed bit
SPEED Pin
USB Mode
low-speed
full-speed
0
X
1
X
0
1
2
6.7.3 UART and I C modes
The actual mode of operation is selectable by the transp_en and uart_en Bits of Control Register 1 (see
table 14).
Table 14. Transceiver modes
transp_en
uart_en
STOTG04 Mode
0
0
1
1
0
1
0
1
USB
UART
I2C
UART (1)
(1) In reality, it is not possible to set both these bits at the same time. In this case, only uart_en bit will remain set.
In the I2C mode the D+ and D- lines act respectively as I2C SDA and SCL signals when the OE_TP_INT/
signal is low. The transceiver automatically enables the pull-up resistor on the SDA line in this mode. The
internal I2C slave interface of the transceiver does not react to commands from the master.
Communication addressed to the STOTG04 device is mirrored to the D+ pin and responses from this pin
are mirrored back to the SDA pin. The D– pin mirrors the SCL clock.
In the UART mode it is possible to select driver direction on both the D+ and D– pins. The selection is
done using the bdir[1] and bdir[0] Bits of Control Register 3 (see table 15).
16/26
STOTG04E
Block description
Table 15. UART Drivers direction
bdir[1]
bdir[0]
DAT_VP ↔±D+
SE0_VM ↔ D-
0
0
1
1
0
1
0
1
→
→
←
←
→
←
→
←
6.7.4 Audio mode
In this mode the transceiver has to release all of its drivers and pull-up/pull-down resistors on the D+, D-
and ID pins, leaving them in a high impedance state. This allows these lines to be used for transmission
of audio signals. The transceiver should not provide voltage on its VBUS output in this mode. Conditions
described in Table 16 force the transceiver into the audio mode.
Table 16. Audio mode setup
transp_en bit
uart_en bit
OE_TP_INT/ signal
Control Register 2
0
0
1
00000000
6.8
Registers
The STOTG04 transceiver device is controlled using register settings (see Table 17). These registers can
be set and read via the I2C bus.
Table 17. Register set
Acc (1)
Addr (2)
Register
Size (bits)
Description
Vendor ID
Product ID
Control 1
Control 2
Control 3
16
16
8
8
8
8
8
8
8
r
r
00h
02h
04h 05h
06h 07h
12h 13h
08h
STMicroelectronics ID (0483h) - LSB first
ID of the STOTG04 (A0C4h) - LSB first
First Control Register
Second Control Register
Third Control Register
r/s/c
r/s/c
r/s/c
r
r/s/c
r/s/c
r/s/c
Interrupt Source
Interrupt Latch
Interrupt Mask False
Interrupt Mask True
Current state of signals generating interrupts
0Ah 0Bh Latched source that generated interrupt
0Ch 0Dh Enables interrupts on falling edge
0Eh 0Fh Enables interrupts on rising edge
(1) Access type can be: read (r), set (s), clear (c).
(2) The first address is to set, the second one to clear bits.
When writing to the set address, any “1” will set the associated Bit to logic “1”. When writing to the clear
address, any “1” will set the associated Bit to logic “0”. It is possible to read from any address, whether it
is a set or clear address. See Tables 18, 19, 20, 21 for bit setting details.
17/26
Block description
STOTG04E
Table 18. Control register 1
R(1)
Name
Bit
Description
0 = low-speed mode
1 = full-speed mode
0 = normal operation
1 = power-down mode
0 = VP_VM mode
Speed
0
1
Suspend
dat_se0
1
2
1
0
1 = DAT_SE0 mode
Enable transparent I2C mode
Enable A-device to connect if B-device disconnect detected
When set and suspend = 1, then OE_TP_INT/ becomes
interrupt output
Enable UART mode (higher priority than transp_en bit)
Reserved
transp_en
3
4
0
0
bdis_acon_en
oe_int_en
uart_en
5
0
0
6
7
(1) State of the bit after reset.
Setting the bdis_acon_en bit enables automatic switching of the D+ pull-up resistor when the device
receives an SE0 longer than half of the bit period. This function should not be used in low-speed
operation.
Table 19. Control register 2
Name
Bit
R
Description
dp_pull-up
dm_pull-up
dp_pull-down
dm_pull-down
id_gnd_drv
vbus_drv
0
1
2
3
4
5
0
0
1
1
0
0
Connect D+ pull-up
Connect D- pull-up
Connect D+ pull-down
Connect D- pull-down
Connect ID pin to ground
Provide power to VBUS
Discharge VBUS through a resistor to ground
Charge VBUS through a resistor
vbus_dischrg
vbus_chrg
6
7
0
0
It is not possible to set vbus_drv, vbus_dischrg and vbus_chrg at the same time; the bit having higher
priority will remain set while the others will be cleared. Vbus_drv has higher priority than vbus_dischrg
which has higher priority than vbus_chrg.
Table 20. Control register 3
Name
Bit
R
Description
0
1
0
0
Reserved
rec_bias_en
bidi_en
Enables transmitter bias even during USB receive
When set, then DAT_VP and SE0_VM pins become bidirectional
otherwise they are inputs only
2
1
bdir[0]
bdir[1]
audio_en
3
4
5
0
1
0
Direction of the drivers between DAT_VP↔DP and
SE0_VM↔DM in the UART mode
Enables car-kit interrupt detector
Enables external charge pump control on the ADR_PSW pin.
Disables internal charge pump.
Enables 2.7V voltage regulation instead of 3.3V
psw_en
2V7_en
6
7
0
0
18/26
STOTG04E
Block description
Table 21. Interrupt registers (*)
Name
Bit
R
Description
A-device VBUS valid comparator
vbus_vld
sess_vld
dp_hi
id_gnd
dm_hi
0
1
2
3
4
5
0
0
0
0
0
0
Session valid comparator
D+ pin is asserted high during SRP
ID pin grounded
D- pin is asserted high
ID pin floating
id_float
Set when bdis_acon_en bit is set and transceiver asserts dp_pull-up after
detecting B-device disconnect
bdis_acon
6
0
cr_int
7
0
Car-kit interrupt
(*) Bit order is the same for all four interrupt related registers. Meaning of each register is described in Table 17.
2
6.9
I C Bus interface
All of the STOTG04 transceiver registers are accessible through the I2C bus (see Figure 12). The device
contains a slave controller which provides communication with an external master. The I2C interface
consists of three pins:
• SDA (Serial Data);
• SCL (Serial Clock);
• ADR_PSW (is the LSB of the device address).
6.10 Device address
The USB-OTG transceiver has following 7-bit I2C device address:
0
1
0
1
1
0
adr
The adr bit represents current state of the ADR_PSW device pin. It means that the address can be either
2Ch or 2Dh according to the ADR_PSW pin.
6.11 Bus protocol
Any device that sends data to the bus is defined as the transmitter. Any device that reads the data is the
receiver. The device that controls data transfers is the bus master, while the transmitter or receiver is the
slave device. The master initiates data transfers and provides the serial clock. The STOTG04 is always
the slave device.
Operation of the I2C bus is described by following figure 12.
19/26
Block description
STOTG04E
Figure 12. Basic operation of the I2C Bus
Start condition is identified by a falling edge of the SDA signal while the SCL is stable at high level. The
start condition must precede any data transfer on the bus.
Stop condition is identified by a rising edge of the SDA signal while the SCL is stable at high level. The
stop condition terminates any communication between device and master.
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter releases the SDA
line after sending eight data bits. During the ninth clock period the receiver pulls the SDA line low to
acknowledge the receipt of the eight data bits. If the receiver is a slave device and it does not generate
acknowledge bit then the bus master can generate the stop condition in order to abort the transfer.
Below is described format of I2C commands. All tables use common format and symbols. Every data
word consists of eight bits with most significant bit first and least significant bit last.
Symbols used in the tables are:
• S – start condition
• P – stop condition
• A – acknowledge bit
• N – negative acknowledge
WRITE Command to the transceiver device is described by following table. It is possible to write into
several consecutive registers during one write command.
S
Device address
A
0
A
Reg. address K
Data (K+N)
A
P
Data (K)
Data (K+1)
A
..
A
READ command consists of dummy write to set proper address of a register followed by real read
sequence.
S
S
Device address
Device address
A
0
A
Reg. address K
Data (K)
Data (K+N)
A
P
A
1
A
A
Data (K+1)
Data (K+2)
...
N
P
20/26
STOTG04E
Block description
6.12 External charge pump switch
The ADR_PSW pin has two functions. State of this pin is always latched into a register on the rising edge
of the RESET/ signal. The latched value is used as a least significant bit of the I2C address. After the
address is latched, this pin can be set as an output by setting the PSW_EN bit of the Control Register 3.
Output value of the pin can be controlled by the VBUS_DRV bit of the Control Register 2. The output is
active low when the pin is high during reset; otherwise the output is active high.
When the PSW_EN bit is set the internal charge pump is switched off.
Example connection of an external charge pump is shown in following figure. When the charge pump
control signal would be active high, the ADR_PSW pin should be pulled down instead of high.
Figure 13. External charge pump application
21/26
Package mechanical data
STOTG04E
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages.
These packages have a Lead-free second level interconnect. The category of second Level
Interconnect is marked on the package and on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.st.com.
22/26
STOTG04E
Package mechanical data
QFN24 (4x4) MECHANICAL DATA
mm.
mils
DIM.
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
A1
b
1.00
39.4
0.00
0.18
3.9
0.05
0.30
4.1
0.0
7.1
2.0
11.8
161.4
88.6
161.4
88.6
D
153.5
76.8
153.5
76.8
D2
E
1.95
3.9
2.25
4.1
E2
e
1.95
2.25
0.50
19.7
L
0.40
0.60
15.7
23.6
23/26
Package mechanical data
STOTG04E
Tape & Reel QFNxx/DFNxx (4x4) MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
99
13.2
0.504
0.795
3.898
D
N
101
3.976
0.567
T
14.4
Ao
Bo
Ko
Po
P
4.35
4.35
1.1
4
0.171
0.171
0.043
0.157
0.315
8
24/26
STOTG04E
Revision history
8
Revision history
Table 22. Revision history
Date
Revision
Changes
13-Jan-2006
01-Feb-2006
1
2
First Release.
Mistake on Table 1.
Added details in paragraph 6.7.1, comments to table 19 and description in
paragraph 6.12.
17-Oct-2006
3
25/26
STOTG04E
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