STM708RAM6E [STMICROELECTRONICS]
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8;
| 型号： | STM708RAM6E |
| 厂家： | 
ST |
| 描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 光电二极管 |
| 文件： | 总32页 (文件大小：696K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM706T/S/R, STM706P, STM708T/S/R
3 V supervisor
Features
■ Precision V monitor
CC
8
– STM706/708
T: 3.00 V ≤ V
≤ 3.15 V
RST
S: 2.88 V ≤ V
≤ 3.00 V
1
RST
R: STM706P: 2.59 V ≤ V
≤ 2.70 V
RST
SO8 (M)
■ RST and RST outputs
■ 200 ms (typ.) t
rec
■ Watchdog timer - 1.6 s (typ.)
■ Manual reset input (MR)
■ Power-fail comparator (PFI/PFO)
■ Low supply current - 40 µA (typ.)
■ Guaranteed RST (RST) assertion down to
= 1.0 V
(1)
TSSOP8 3x3 (DS)
V
CC
■ Operating temperature: –40 °C to 85 °C
1. Contact local ST sales office for availability.
(industrial grade)
■ RoHS compliance
– Lead-free components are compliant with
the RoHS directive
Table 1.
Device summary
Watchdog
input
Watchdog
output
Active-low
RST
Active-high
Manual
reset input
Power-fail
comparator
(1)
(1)
(1)
RST
STM706T/S/R
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
(2)
STM706P
✓
✓
STM708T/S/R
1. Push-pull output.
2. The STM706P is identical to the STM706R, except its reset output is active-high.
September 2011
Doc ID 10518 Rev 11
1/32
www.st.com
1
Contents
STM706T/S/R, STM706P, STM708T/S/R
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Push-button reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Watchdog input (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . 11
Watchdog output (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . 11
Power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ensuring a valid reset output down to V = 0 V . . . . . . . . . . . . . . . . . . . 12
CC
Interfacing to microprocessors with bi-directional reset pins . . . . . . . . . . 13
4
5
6
7
8
9
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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STM706T/S/R, STM706P, STM708T/S/R
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SO8 - 8-lead plastic small outline, 150 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size,
Table 8.
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9.
Table 10.
Table 11.
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List of figures
STM706T/S/R, STM706P, STM708T/S/R
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Logic diagram (STM708T/S/R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
STM706T/S/R and STM706P SO8 connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM706T/S/R and STM706P TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM708T/S/R SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
STM708T/S/R TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram (STM706T/S/R and STM706P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block diagram (STM708T/S/R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10. Reset output valid to ground circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Interfacing to microprocessors with bi-directional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13.
V
threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PFI
Figure 14. Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. Power-up t vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
rec
Figure 16. Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17. Watchdog timeout period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 18. PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 19. Output voltage vs. load current (V = 5 V; T = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CC
A
Figure 20. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 26. Power-fail comparator waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 28. Watchdog timing (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 29. SO8 – 8-lead plastic small outline, 150 mils body width,
package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 30. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline. . . . . . . . . . . . . . 28
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Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R
Description
1
Description
The STM70x supervisors are self-contained devices which provide microprocessor
supervisory functions. A precision voltage reference and comparator monitors the V input
CC
for an out-of-tolerance condition. When an invalid V condition occurs, the reset output
CC
(RST) is forced low (or high in the case of RST).
These devices also offer a watchdog timer (except for STM708T/S/R) as well as a power-fail
comparator to provide the system with an early warning of impending power failure.
The STM706P is identical to the STM706R, except its reset output is active-high. These
devices are available in a standard 8-pin SOIC package or a space-saving 8-pin TSSOP
package.
Figure 1.
Logic diagram (STM706T/S/R and STM706P)
V
CC
WDI
MR
PFI
WDO
STM706T/S/R,
STM706P
(1)
RST (RST)
PFO
V
SS
AI08841
1. For STM706P only.
Figure 2.
Logic diagram (STM708T/S/R)
V
CC
RST
MR
RST
PFO
STM708T/S/R
PFI
V
SS
AI08842
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Description
STM706T/S/R, STM706P, STM708T/S/R
Name
Table 2.
Symbol
Signal names
MR
WDI
WDO
RST
Push-button reset input
Watchdog input
Watchdog output
Active-low reset output
Active-high reset output
Supply voltage
(1)
RST
V
CC
PFI
Power-fail input
Power-fail output
Ground
PFO
V
SS
NC
No connect
1. For STM706P and STM708T/S/R only.
Figure 3.
STM706T/S/R and STM706P SO8 connections
SO8
1
2
3
4
8
7
6
5
MR
WDO
(1)
V
RST(RST)
CC
V
WDI
PFO
SS
PFI
AI08837
1. For STM706P reset output is active-high.
Figure 4.
STM706T/S/R and STM706P TSSOP8 connections
TSSOP8
(1)
RST(RST)
1
2
3
4
8
7
6
5
WDI
PFO
PFI
WDO
MR
V
V
CC
SS
AI08838
1. For STM706P reset output is active-high.
6/32
Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R
Description
Figure 5.
STM708T/S/R SO8 connections
SO8
MR
1
2
3
4
8
7
6
5
RST
RST
NC
V
CC
V
SS
PFI
PFO
AI08839
Figure 6.
STM708T/S/R TSSOP8 connections
TSSOP8
RST
RST
MR
1
2
3
4
8
7
6
5
NC
PFO
PFI
V
V
CC
SS
AI08840
Doc ID 10518 Rev 11
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Pin descriptions
STM706T/S/R, STM706P, STM708T/S/R
2
Pin descriptions
2.1
MR
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for t after MR returns high. This active-low input has an internal pull-up. It can be
rec
driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
2.2
2.3
WDI
If WDI remains high or low for 1.6 s, the internal watchdog timer runs out and reset (or
WDO) is triggered. The internal watchdog timer clears while reset is asserted or when WDI
sees a rising or falling edge.
The watchdog function cannot be disabled by allowing the WDI pin to float.
WDO
WDO goes low when a transition does not occur on WDI within 1.6 s, and remains low until
a transition occurs on WDI (indicating the watchdog interrupt has been serviced). WDO also
goes low when V falls below the reset threshold; however, unlike the reset output, WDO
CC
goes high as soon as V exceeds the reset threshold. Output type is push-pull.
CC
Note:
For those devices with a WDO output, a watchdog timeout will not trigger reset unless WDO
is connected to MR.
2.4
RST
Pulses low for t when triggered, and stays low whenever V is below the reset
rec
CC
threshold or when MR is a logic low. It remains low for t after either V rises above the
rec
CC
reset threshold, the watchdog triggers a reset, or MR goes from low to high.
2.5
2.6
RST
Pulses high for t when triggered, and stays high whenever V is above the reset
threshold or when MR is a logic high. It remains high for t after either V falls below the
reset threshold, the watchdog triggers a reset, or MR goes from high to low.
rec
CC
rec
CC
PFI
When PFI is less than V , PFO goes low; otherwise, PFO remains high. Connect to
PFI
ground if unused.
8/32
Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R
Pin descriptions
2.7
PFO
When PFI is less than V , PFO goes low; otherwise, PFO remains high. Output type is
PFI
push-pull. PFO pin is not supposed to be forced low by a processor. MR input is gated off
during the period PFO is forced low. Leave open if unused.
Table 3.
Pin description
Pin
Name
Function
STM706P
STM706T/S/R
SO8 TSSOP8
STM708T/S/R
SO8
TSSOP8
SO8
TSSOP8
1
6
3
8
1
3
1
—
—
7
3
—
—
1
MR
WDI
WDO
RST
RST
Push-button reset input
Watchdog input
6
8
8
2
8
2
Watchdog output (push-pull)
Active-low reset output
Active-high reset output
Supply voltage
—
7
—
1
7
1
—
2
—
4
8
2
2
4
2
4
V
CC
4
6
4
6
4
6
PFI
Power-fail input
5
7
5
7
5
7
PFO
Power-fail output (push-pull)
Ground
3
5
3
5
3
5
V
SS
—
—
—
—
6
8
NC
No connect
Figure 7.
Block diagram (STM706T/S/R and STM706P)
WDI
transitional
detector
WATCHDOG
TIMER
WDI
WDO
V
CC
V
COMPARE
RST
V
CC
t
(1)
rec
generator
RST (RST)
PFO
MR
PFI
V
COMPARE
PFI
AI08829
1. For STM706P only.
Doc ID 10518 Rev 11
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Pin descriptions
STM706T/S/R, STM706P, STM708T/S/R
Figure 8.
Block diagram (STM708T/S/R)
VCC
COMPARE
VRST
RST
VCC
t
rec
RST
MR
PFI
generator
VPFI
COMPARE
PFO
AI08830
Figure 9.
Hardware hookup
Regulator
Unregulated
voltage
V
V
V
CC
IN
CC
STM706T/S/R;
STM706P;
0.1 μF
STM708T/S/R
(1)
(1)
WDO
WDI
To microprocessor IRQ
To microprocessor NMI
R1
R2
From microprocessor
PFI
MR
PFO
RST
(2)
To microprocessor reset
Push-button
RST
AI08843
1. For STM706T/S/R and STM706P.
2. For STM706P and STM708T/S/R.
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Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R
Operation
3
Operation
3.1
Reset output
The STM70x supervisor asserts a reset signal to the MCU whenever V goes below the
CC
reset threshold (V
), a watchdog timeout occurs (if WDO is connected to MR), or when the
RST
push-button reset input (MR) is taken low. RST is guaranteed to be a logic low (logic high for
STM706P and STM708T/S/R) for V < V down to V =1 V for T = 0 °C to 85 °C.
CC
RST
CC
A
During power-up, once V exceeds the reset threshold an internal timer keeps RST low for
CC
the reset timeout period, t . After this interval RST returns high.
rec
If V drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
CC
low for at least the reset timeout period (t ). Any time V goes below the reset threshold
rec
CC
the internal timer clears. The reset timer starts when V returns above the reset threshold.
CC
3.2
3.3
Push-button reset input
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t (see
rec
Figure 27) after it returns high. The MR input has an internal 40 kΩ pull-up resistor, allowing
it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with
open-drain / collector outputs. Connect a normally open momentary switch from MR to GND
to create a manual reset function; external debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor
from MR to GND to provide additional noise immunity. MR may float, or be tied to V when
not used.
CC
Watchdog input (STM706T/S/R and STM706P)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the watchdog input (WDI) within t
(1.6 s), the watchdog output pin (WDO) is
WD
asserted. The internal 1.6s timer is cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.
See Figure 28 for STM706T/S/R and STM706P.
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting.
3.4
Watchdog output (STM706T/S/R and STM706P)
When V drops below the reset threshold, WDO will go low even if the watchdog timer has
CC
not yet timed out. However, unlike the reset output, WDO goes high as soon as V
CC
exceeds the reset threshold. WDO may be used to generate a reset pulse by connecting it
to the MR input.
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Operation
STM706T/S/R, STM706P, STM708T/S/R
3.5
Power-fail input/output
The power-fail input (PFI) is compared to an internal reference voltage (independent from
the V comparator). If PFI is less than the power-fail threshold (V ), the power-fail
RST
PFI
output (PFO) will go low. This function is intended for use as an undervoltage detector to
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see Figure 9) to either the unregulated DC input (if it is available) or the regulated output of
the V regulator. The voltage divider can be set up such that the voltage at PFI falls below
CC
V
several milliseconds before the regulated V input to the STM70x or the micro-
PFI
CC
processor drops below the minimum operating voltage.
If the comparator is unused, PFI should be connected to V and PFO left unconnected.
SS
PFO may be connected to MR on the STM70x so that a low voltage on PFI will generate
a reset output.
3.6
Ensuring a valid reset output down to VCC = 0 V
When V falls below 1 V, the state of the RST output can no longer be guaranteed, and
CC
becomes essentially an open circuit. If a high value pulldown resistor is added to the RST
pin, the output will be held low during this condition. A resistor value of approximately
100 kΩ will be large enough to not load the output under operating conditions, but still
sufficient to pull RST to ground during this low voltage condition (see Figure 10).
Figure 10. Reset output valid to ground circuit
STM70x
RST
R1
AI08844
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Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R
Operation
3.7
Interfacing to microprocessors with bi-directional reset pins
Microprocessors with bi-directional reset pins can contend with the STM70x reset output.
For example, if the reset output is driven high and the micro wants to pull it low, signal
contention will result. To prevent this from occurring, connect a 4.7kΩ resistor between the
reset output and the micro's reset I/O as in Figure 11.
Figure 11. Interfacing to microprocessors with bi-directional reset I/O
Buffered reset to other
system components
V
V
CC
CC
STM70x
Microprocessor
4.7 kΩ
RST
RST
GND
GND
AI08845
Doc ID 10518 Rev 11
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Typical operating characteristics
STM706T/S/R, STM706P, STM708T/S/R
4
Typical operating characteristics
Typical values are at T = 25 °C.
A
Figure 12. Supply current vs. temperature (no load)
30
25
20
15
10
5
V
= 2.7 V
= 3.0 V
= 3.6 V
= 4.5 V
= 5.5 V
CC
V
CC
V
CC
V
CC
V
CC
0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09141b
14/32
Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R
Typical operating characteristics
Figure 13.
V
threshold vs. temperature
PFI
1.270
1.265
1.260
1.255
1.250
1.245
1.240
1.235
1.230
1.225
V
= 2.5 V
= 3.0 V
= 3.3 V
= 3.6 V
CC
V
CC
V
CC
V
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09142b
Figure 14. Reset comparator propagation delay vs. temperature
30
28
26
24
22
20
18
16
14
12
10
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09143b
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15/32
Typical operating characteristics
STM706T/S/R, STM706P, STM708T/S/R
Figure 15. Power-up t vs. temperature
rec
240
235
230
225
220
215
210
V
= 3.0 V
= 4.5 V
= 5.5 V
CC
V
CC
V
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09144b
Figure 16. Normalized reset threshold vs. temperature
1.004
1.002
1.000
0.998
0.996
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09145b
16/32
Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R
Typical operating characteristics
Figure 17. Watchdog timeout period vs. temperature
1.90
1.85
1.80
1.75
1.70
1.65
1.60
V
= 3.0 V
= 4.5 V
= 5.5 V
CC
V
V
CC
CC
–40
–20
0
20
40
60
80
100
120
Temperature (˚C)
AI09146b
Figure 18. PFI to PFO propagation delay vs. temperature
4.0
V
= 3.0 V
= 3.6 V
= 4.5 V
= 5.5 V
CC
V
CC
3.0
2.0
1.0
0.0
V
CC
V
CC
–40
–20
0
20
40
60
80
100
120
Temperature (˚C)
AI09148b
Doc ID 10518 Rev 11
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Typical operating characteristics
STM706T/S/R, STM706P, STM708T/S/R
Figure 19. Output voltage vs. load current (V = 5 V; T = 25 °C)
CC
A
5.00
4.98
4.96
4.94
0
10
20
30
40
50
I
(mA)
OUT
AI10496
Figure 20. RST output voltage vs. supply voltage
5
4
3
5
4
V
RST
V
CC
3
2
V
2
(V)
CC
1
0
1
0
500 ms / div
AI09149b
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STM706T/S/R, STM706P, STM708T/S/R
Typical operating characteristics
Figure 21. RST output voltage vs. supply voltage
5
5
4
3
2
1
V
RST
V
CC
4
3
V
2
(V)
CC
1
0
0
500 ms / div
AI09150b
Figure 22. Power-fail comparator response time (assertion)
5 V
1 V / div
PFO
0 V
1.3 V
PFI
500 mV / div
0 V
500 ns / div
AI09153b
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19/32
Typical operating characteristics
STM706T/S/R, STM706P, STM708T/S/R
Figure 23. Power-fail comparator response time (de-assertion)
5 V
1 V / div
PFO
0 V
PFI
1.3 V
500 mV / div
0 V
500 ns / div
AI09154b
Figure 24. Maximum transient duration vs. reset threshold overdrive
6000
5000
4000
Reset occurs
above the curve
3000
2000
1000
0
0.001
0.01
0.1
1
10
Reset comparator overdrive, V
– V
(V)
CC
RST
AI09156b
20/32
Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R
Maximum ratings
5
Maximum ratings
Stressing the device above the rating listed in the Table 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
T
Storage temperature (V off)
–55 to 150
260
°C
°C
V
STG
(1)
CC
T
Lead solder temperature for 10 seconds
Input or output voltage
Supply voltage
SLD
(2)
V
–0.3 to V +0.3
IO
CC
V
–0.3 to 7.0
20
V
CC
I
Output current
mA
mW
O
P
Power dissipation
320
D
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
2. Negative undershoot of –1.5 V for up to 10 ns or positive overshoot of VCC + 1.5 V for up to 10 ns is
allowable on the WDI and MR input pins.
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DC and AC parameters
STM706T/S/R, STM706P, STM708T/S/R
6
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 5, operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 5.
Operating and AC measurement conditions
Parameter STM70x
supply voltage
Unit
V
1.0 to 5.5
–40 to 85
≤ 5
V
°C
ns
V
CC
Ambient operating temperature (T )
A
Input rise and fall times
Input pulse voltages
0.2 to 0.8 V
0.3 to 0.7 V
CC
CC
Input and output timing ref. voltages
V
Figure 25. AC testing input/output waveforms
0.8 V
CC
0.7 V
0.3 V
CC
CC
0.2 V
CC
AI02568
Figure 26. Power-fail comparator waveform
V
CC
V
RST
t
rec
PFO
RST
AI08860a
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STM706T/S/R, STM706P, STM708T/S/R
DC and AC parameters
Figure 27. MR timing waveform
MR
t
MLRL
(1)
RST
t
t
rec
MLMH
AI07837a
1. RST for STM706P and STM708T/S/R.
Figure 28. Watchdog timing (STM706T/S/R and STM706P)
V
CC
t
RST
WDI
rec
t
WD
WDO
AI08833
Doc ID 10518 Rev 11
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DC and AC parameters
STM706T/S/R, STM706P, STM708T/S/R
Table 6.
Symbol
DC and AC characteristics
Description
(1)
Test condition
Min.
Typ. Max. Unit
(2)
V
Operating voltage
supply current
1.2
5.5
50
60
V
CC
V
V
< 3.6 V
< 5.5 V
35
40
µA
µA
CC
CC
I
V
CC
CC
Input leakage current
(WDI)
0 V < V < V
–1
+1
µA
nA
IN
CC
CC
Input leakage current
(PFI)
0 V < V < V
–25
2
+25
IN
I
LI
V
(max.) < V < 3.6 V
25
75
80
250
300
µA
µA
V
RST
CC
Input leakage current
(MR)
4.5 V < V < 5.5 V
125
CC
4.5 V < V < 5.5 V
2.0
CC
V
V
Input high voltage (MR)
Input high voltage (WDI)
Input low voltage (MR)
Input low voltage (WDI)
IH
IH
V
V
(max.) < V < 3.6 V
0.7 V
V
RST
RST
CC
CC
CC
(max.) < V < 5.5 V
0.7 V
V
CC
4.5 V < V < 5.5 V
0.8
0.6
V
CC
V
V
IL
IL
V
V
(max.) < V < 3.6 V
V
RST
CC
(max.) < V < 5.5 V
0.3 V
CC
V
RST
CC
Output low voltage (PFO,
RST, RST, WDO)
V
= V
(max.),
RST
CC
I
V
0.3
0.3
0.3
V
V
V
V
V
OL
OL
OH
= 3.2 mA
SINK
I
= 50 µA, V = 1.0 V,
CC
SINK
T = 0 °C to 85 °C
A
V
Output low voltage (RST)
I
= 100 µA,
SINK
V
= 1.2 V
CC
Output high voltage (RST,
RST, WDO)
I
V
= 1 mA,
= V (max.)
RST
SOURCE
V
2.4
CC
Output high voltage
(PFO)
I
V
= 75 µA,
SOURCE
0.8 V
CC
= V
(max.)
CC
RST
Power-fail comparator
PFI falling
(STM70xP/R, V = 3.0 V;
V
PFI input threshold
1.20
1.25
2
1.30
V
PFI
CC
STM70xS/T, V = 3.3 V)
CC
PFI to PFO propagation
delay
t
µs
PFD
24/32
Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R
DC and AC parameters
Table 6.
Symbol
DC and AC characteristics (continued)
(1)
Description
Test condition
Min.
Typ. Max. Unit
Reset thresholds
STM706P/70xR
STM70xS
2.55
2.85
3.00
2.63
2.93
3.08
2.70
3.00
3.15
V
V
V
(3)
V
Reset threshold
RST
STM70xT
Reset threshold
hysteresis
20
mV
ms
Blank (see Table 9)
140
160
200
200
280
280
t
RST pulse width
rec
(4)
A
(see Table 9)
Push-button reset input
V
V
(max.) < V < 3.6 V
500
150
ns
ns
ns
ns
RST
CC
t
MLMH
MR pulse width
(or t
)
MR
4.5 V < V < 5.5 V
CC
(max.) < V < 3.6 V
750
250
RST
CC
t
MLRL
MR to RST output delay
(or t
)
MRD
4.5 V < V < 5.5 V
CC
Watchdog timer (STM706T/S/R and STM706P)
STM706P/70xR,
1.12
1.60
2.24
s
V
= 3.0 V
CC
t
Watchdog timeout period
WD
STM70xS/70XT,
= 3.3 V
V
CC
4.5 V < V < 5.5 V
50
ns
ns
CC
WDI pulse width
V
(max.) < V < 3.6 V
100
RST
CC
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = VRST (max.) to 5.5 V (except where noted).
2. VCC (min) = 1.0 V for TA = 0 °C to +85 °C.
3. For VCC falling.
4. STM706P/STM70xR, VCC = 3 V; STM706xS/STM70xT, VCC = 3.3 V.
Doc ID 10518 Rev 11
25/32
Package mechanical data
STM706T/S/R, STM706P, STM708T/S/R
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
26/32
Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R
Package mechanical data
Figure 29. SO8 – 8-lead plastic small outline, 150 mils body width,
package mechanical
A2
A
C
B
ddd
e
D
8
1
E
H
A1
L
SO-A
Note:
Drawing is not to scale.
Table 7.
SO8 - 8-lead plastic small outline, 150 mils body width,
package mechanical data
mm
inches
Min.
Symbol
Typ.
Min.
Max.
Typ.
Max.
A
A1
B
—
—
—
—
—
—
—
1.27
—
—
—
—
8
1.35
0.10
0.33
0.19
4.80
—
1.75
0.25
0.51
0.25
5.00
0.10
4.00
—
—
—
0.053
0.004
0.013
0.007
0.189
—
0.069
0.010
0.020
0.010
0.197
0.004
0.157
—
—
C
—
D
—
ddd
E
—
3.80
—
—
0.150
—
e
0.050
—
H
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
h
—
L
—
α
—
N
8
Doc ID 10518 Rev 11
27/32
Package mechanical data
STM706T/S/R, STM706P, STM708T/S/R
Figure 30. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline
D
8
1
5
4
c
E1
E
A1
L
A
A2
L1
CP
b
e
TSSOP8BM
Note:
Drawing is not to scale.
Table 8.
TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size,
mechanical data
mm
inches
Min.
Symbol
Typ.
Min.
Max.
Typ.
Max.
A
A1
A2
b
—
—
—
0.05
0.75
0.25
0.13
—
1.10
0.15
0.95
0.40
0.23
0.10
3.10
—
—
—
—
0.043
0.006
0.037
0.016
0.009
0.004
0.122
—
0.002
0.030
0.010
0.005
—
0.85
—
0.034
—
c
—
—
CP
D
—
—
3.00
0.65
4.90
3.00
0.55
0.95
—
2.90
—
0.118
0.026
0.193
0.118
0.022
0.037
—
0.114
—
e
E
4.65
2.90
0.40
—
5.15
3.10
0.70
—
0.183
0.114
0.016
—
0.203
0.122
0.030
—
E1
L
L1
α
0°
6°
0°
6°
N
8
8
28/32
Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R
Part numbering
8
Part numbering
Table 9.
Ordering information scheme
STM706
Example:
T
M
6
E
Device type
STM706
STM708
Reset threshold voltage
T: 3.00 V ≤ V
S: 2.88 V ≤ V
≤ 3.15 V
≤ 3.00 V
RST
RST
R, STM706P: 2.59 V ≤ V
≤ 2.70 V
RST
RST pulse width
Blank = 140 to 280 ms
(1)
A
= 160 to 280 ms
Package
M = SO8
(2)
DS = TSSOP8
Temperature range
6 = –40 to 85 °C
Shipping method
®
E = ECOPACK packages, tubes
®
F = ECOPACK packages, tape and reel
1. Available in SO8 (M) package only.
2. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Doc ID 10518 Rev 11
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Part numbering
STM706T/S/R, STM706P, STM708T/S/R
Table 10.
Marking description
Part number
Reset threshold
Package
Topside marking
SO8
TSSOP8
SO8
STM706P
STM706T
STM706S
STM706R
STM708T
STM708S
STM708R
2.63 V
706P
3.08 V
2.93 V
2.63 V
3.08 V
2.93 V
2.63 V
706T
706S
706R
708T
708S
708R
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
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Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R
Revision history
9
Revision history
Table 11.
Date
Document revision history
Revision
Changes
Oct-2003
1
Initial release.
Reformatted; update characteristics (Figure 2, 3, 8 to 10, 27 to 29;
Table 6 to 9).
12-Dec-2003
2
16-Jan-2004
09-Apr-2004
25-May-2004
02-Jul-2004
21-Sep-2004
25-Feb-2005
2.1
3
Add Typical operating characteristics (Figure 13, to 19, 21, to 25).
Reformatted; update characteristics (Figure 15, 19, 21, 22, 25; Table 8).
Update characteristics (Table 3, Table 6).
4
5
Datasheet promoted; waveform corrected (Table 27).
Clarify root part numbers; (Figure 2, to 10, 29; Table 1, 3, 6, 9).
Update typical characteristics (Figure 13 to 25).
6
7
Updated Table 1, Table 3, Table 4, Table 6, Table 9, Section 2.3,
Section 2.7, text in Section 7; reformatted document.
02-Nov-2009
8
Updated Table 4, corrected typo in Table 2, Section 2.3, Section 3,
Section 5 and Section 6, Figure 17, Table 7 and Table 8.
30-Apr-2010
06-Aug-2010
06-Sep-2011
9
10
11
Updated Features, Section 4: Typical operating characteristics; Table 9.
Updated Section 2.7, Section 5 and Disclaimer, minor typo
modifications throughout the document.
Doc ID 10518 Rev 11
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STM706T/S/R, STM706P, STM708T/S/R
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Doc ID 10518 Rev 11
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