STM690_10 [STMICROELECTRONICS]
3 V supervisor with battery switchover; 3 V主管与电池切换
| 型号： | STM690_10 |
| 厂家： | 
ST |
| 描述： | 3 V supervisor with battery switchover |
| 文件： | 总42页 (文件大小：956K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM690, STM704, STM795
STM802, STM804, STM805, STM806
3 V supervisor with battery switchover
Features
■ RST or RST outputs
8
■ NVRAM supervisor for external LPSRAM
■ Chip enable gating (STM795 only) for external
1
LPSRAM (7 ns max prop delay)
■ Manual (push-button) reset input
SO8 (M)
■ 200 ms (typ) t
rec
■ Watchdog timer - 1.6 s (typ)
■ Automatic battery switchover
■ Low battery supply current - 0.4 µA (typ)
■ Power-fail comparator (PFI/PFO)
■ Low supply current - 40 µA (typ)
■ Guaranteed RST (RST) assertion
(1)
TSSOP8 3x3 (DS)
down to V = 1.0 V
CC
■ Operating temperature:
1. Contact local ST sales office for availability.
–40 °C to 85 °C (industrial grade)
■ RoHS compliance
– Lead-free components are compliant with
the RoHS directive
Table 1.
Device summary
Manual
reset
input
Watchdog Active- low Active-high
Battery
switchover comparator
Power-fail Chip enable
Input
RST(1)
RST(1)
gating
STM690T/S/R
STM704T/S/R
STM795T/S/R
STM802T/S/R
STM804T/S/R
STM805T/S/R
STM806T/S/R
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
(2)
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
(2)
✓
(2)
✓
✓
✓
1. All RST outputs push-pull (unless otherwise noted).
2. Open drain output.
August 2010
Doc ID 10519 Rev 9
1/42
www.st.com
1
Contents
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.1.8
1.1.9
1.1.10
1.1.11
MR (manual reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WDI (watchdog input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
RST (active-low reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
RST (active-high reset - open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PFI (power-fail input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PFO (power-fail output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
V
(supply output voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
OUT
Vccsw (V switch output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
E (chip enable input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
E
V
(conditional chip enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
(backup battery input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CON
BAT
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Push-button reset input (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Watchdog input (NOT available on STM704/795/806) . . . . . . . . . . . . . . . 14
Backup battery switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chip enable gating (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip enable input (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip enable output (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-fail input/output (NOT available on STM795) . . . . . . . . . . . . . . . . 17
Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.10 Using a SuperCap™ as a backup power source . . . . . . . . . . . . . . . . . . . 19
2.11 Negative-going VCC transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
4
5
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Contents
6
7
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Doc ID 10519 Rev 9
3/42
List of tables
STM690, STM704, STM795, STM802, STM804, STM805, STM806
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I/O status in battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SO8 - 8-lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data . . . . . . 38
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 9.
Table 10.
Table 11.
Table 12.
4/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic diagram (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
STM690/802/804/805 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
STM704/806 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
STM795 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Chip enable gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Chip enable waveform (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Power-fail comparator waveform (STM690/704/802/804/805/806) . . . . . . . . . . . . . . . . . . 18
Figure 14. Using a SuperCap™. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15.
Figure 16.
V
V
to V
on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
OUT
CC
OUT
to V
BAT
Figure 17. Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. Battery current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19.
V
threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PFI
Figure 20. Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 21. Power-up t vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
rec
Figure 22. Normalized reset threshold vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 23. Watchdog time-out period vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 24. E to E
on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CON
Figure 25. PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 26. Output voltage vs. load current (V = 5 V; V
= 2.8 V; T = 25 °C) . . . . . . . . . . . . . . . 25
CC
BAT
A
Figure 27. Output voltage vs. load current (V = 0 V; V
= 2.8 V; T = 25 °C) . . . . . . . . . . . . . . . 26
A
CC
BAT
Figure 28. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 29. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 30. Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 31. Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 32. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 33. E to E
Figure 34. E to E
propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
propagation delay test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CON
CON
Figure 35. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 36. MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 37. Watchdog timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 38. SO8 – 8-lead plastic small outline, 150 mils body width,
package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 39. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline. . . . . . . . . . . . . . 38
Doc ID 10519 Rev 9
5/42
Description
STM690, STM704, STM795, STM802, STM804, STM805, STM806
1
Description
The STM690/704/795/802/804/805/806 supervisors are self-contained devices which
provide microprocessor supervisory functions with the ability to non-volatize and write-
protect external LPSRAM. A precision voltage reference and comparator monitors the V
CC
input for an out-of-tolerance condition. When an invalid V condition occurs, the reset
CC
output (RST) is forced low (or high in the case of RST). These devices also offer a watchdog
timer (except for STM704/795/806) as well as a power-fail comparator (except for STM795)
to provide the system with an early warning of impending power failure.
These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin
TSSOP package.
Figure 1.
Logic diagram (STM690/802/804/805)
V
V
CC BAT
V
OUT
WDI
PFI
STM690/
802/804/
805
(1)
RST (RST)
PFO
V
SS
AI08846
1. For STM804/805, reset output is active-high and open drain.
Figure 2.
Logic diagram (STM704/806)
V
V
CC BAT
V
OUT
MR
PFI
STM704
STM806
RST
PFO
V
SS
AI08847
6/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Description
Figure 3.
Logic diagram (STM795)
V
V
CC BAT
V
OUT
V
CCSW
STM795
RST
E
E
CON
V
SS
AI08848
Table 2.
Signal names
MR
Push-button reset input
Watchdog input
WDI
RST
Active-low reset output
Active-high reset output
Chip enable input
RST(1)
E(2)
(2)
ECON
Conditioned chip enable output
VCC switch output
Supply voltage output
Supply voltage
Vccsw(2)
VOUT
VCC
VBAT
PFI
Backup supply voltage
Power-fail input
PFO
VSS
Power-fail output
Ground
1. Open drain for STM804/805 only.
2. STM795.
Doc ID 10519 Rev 9
7/42
Description
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 4.
STM690/802/804/805 connections
SO8/TSSOP8
V
V
V
V
BAT
RST (RST)
WDI
OUT
CC
SS
PFI
1
2
3
4
8
7
6
5
(1)
PFO
AI08849
1. For STM804/805, reset output is active-high and open drain.
Figure 5.
STM704/806 connections
SO8/TSSOP8
V
V
V
V
BAT
RST
MR
PFO
OUT
CC
SS
PFI
1
2
3
4
8
7
6
5
AI08850
Figure 6.
STM795 connections
SO8/TSSOP8
V
V
BAT
1
2
3
4
8
7
6
5
OUT
CC
V
RST
E
V
CON
CCSW
V
E
SS
AI08851
8/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Description
1.1
Pin descriptions
1.1.1
MR (manual reset)
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for t after MR returns high. This active-low input has an internal pull-up. It can be
rec
driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
1.1.2
WDI (watchdog input)
If WDI remains high or low for 1.6 s, the internal watchdog timer runs out and reset is
triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a
rising or falling edge.
The watchdog function cannot be disabled by allowing the WDI pin to float.
1.1.3
1.1.4
RST (active-low reset)
Pulses low for t when triggered, and stays low whenever V is below the reset threshold
rec
CC
or when MR is a logic low. It remains low for t after either V rises above the reset
threshold, the watchdog triggers a reset, or MR goes from low to high.
rec
CC
RST (active-high reset - open drain)
Pulses high for t when triggered, and stays high whenever V is above the reset
rec
CC
threshold or when MR is a logic high. It remains high for t after either V falls below the
rec
CC
reset threshold, the watchdog triggers a reset, or MR goes from high to low.
1.1.5
1.1.6
1.1.7
PFI (power-fail input)
When PFI is less than V
or when V falls below V
(2.4 V), PFO goes low; otherwise,
SW
PFI
CC
PFO remains high. Connect to ground if unused.
PFO (power-fail output)
When PFI is less than V , or V falls below V , PFO goes low; otherwise, PFO remains
PFI
CC
SW
high. Leave open if unused. Output type is push-pull.
V
(supply output voltage)
OUT
When V is above the switchover voltage (V ), V
is connected to V through
CC
SO
OUT
CC
a P-channel MOSFET switch. When V falls below V , V
connects to V
. Connect
CC
SO BAT
OUT
to V if no battery is used.
CC
1.1.8
Vccsw (V switch output)
CC
When V
switches to battery, Vccsw is high. When V
switches back to V , Vccsw is
CC
OUT
OUT
low. It can be used to drive gate of external PMOS transistor for I
exceeding 75 mA. Output type is push-pull.
requirements
OUT
Doc ID 10519 Rev 9
9/42
Description
STM690, STM704, STM795, STM802, STM804, STM805, STM806
1.1.9
E (chip enable input)
The input to the chip enable gating circuit. Connect to ground if unused.
1.1.10
1.1.11
E
(conditional chip enable)
CON
E
goes low only when E is low and reset is not asserted. If E
is low when reset is
CON
CON
asserted, E
disabled mode, E
will remain low for 15 µs or until E goes high, whichever occurs first. In the
CON
is pulled up to V
.
CON
OUT
V
(backup battery input)
BAT
When V falls below V , V
switches from V to V . When V rises above V
+
SO
CC
SO OUT
CC
BAT
CC
hysteresis, V
reconnects to V . V
may exceed V . Connect to V if no battery is
OUT
CC BAT CC CC
used.
Table 3.
STM795
Pin description
Pin
Name
Function
STM690
STM802
STM704
STM806
STM804
STM805
—
—
7
—
6
6
—
7
—
6
MR
WDI
RST
RST
PFI
Push-button reset input
Watchdog input
7
—
7
Active-low reset output
Active-high reset output
Power-fail input
—
—
—
1
—
4
—
4
4
5
5
5
PFO
VOUT
VCC
Vccsw
VSS
Power-fail output (push-pull)
Supply output for external LPSRAM
Supply voltage
1
1
1
2
2
2
2
3
—
3
—
3
—
3
VCC switch output (push-pull)
Ground
4
5
—
—
8
—
—
8
—
—
8
E
Chip enable input
6
ECON
VBAT
Conditioned chip enable output
Backup battery input
8
10/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Description
Figure 7.
Block diagram (STM690/802/804/805)
V
V
CC
OUT
V
BAT
COMPARE
COMPARE
V
V
SO
RST
t
(1)
rec
WATCHDOG
TIMER
RST (RST)
WDI
PFI
generator
V
COMPARE
PFO
PFI
AI07897
1. For STM804/805, reset output is active-high and open drain.
Figure 8.
Block diagram (STM704/806)
V
V
CC
OUT
V
BAT
COMPARE
COMPARE
V
V
SO
RST
t
rec
RST
PFO
MR
PFI
generator
V
COMPARE
PFI
AI07898
Doc ID 10519 Rev 9
11/42
Description
Figure 9.
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Block diagram (STM795)
V
V
CC
OUT
V
BAT
V
CCSW
COMPARE
COMPARE
V
V
SO
t
rec
generator
RST
RST
E
OUTPUT
CON
CONTROL
E
E
CON
PFI
V
COMPARE
PFO
PFI
AI08852
12/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 10. Hardware hookup
Description
(2)
V
Regulator
CCSW
Unregulated
voltage
V
V
V
V
V
OUT
CC
IN
CC
CC
V
CC
LPSRAM
STM690/704/
795/802/804/
805/806
0.1
F
E
E
0.1
F
(1)
WDI
(2)
From microprocessor
(2)
(3)
E
E
CON
PFO
R1
R2
(3)
(4)
PFI
MR
V
To microprocessor NMI
To microprocessor reset
RST
Push-button
BAT
AI08853
1. For STM690/802/804/805.
2. For STM795 only.
3. Not available on STM795.
4. For STM704/806.
Doc ID 10519 Rev 9
13/42
Operation
STM690, STM704, STM795, STM802, STM804, STM805, STM806
2
Operation
2.1
Reset output
The STM690/704/795/802/804/805/806 supervisor asserts a reset signal to the MCU
whenever V goes below the reset threshold (V ), a watchdog time-out occurs, or when
CC
RST
the push-button reset input (MR) is taken low. RST is guaranteed to be a logic low (logic
high for STM804/805) for 0 V < V < V if V is greater than 1 V. Without a backup
CC
RST
BAT
battery, RST is guaranteed valid down to V = 1 V.
CC
During power-up, once V exceeds the reset threshold an internal timer keeps RST low for
CC
the reset time-out period, t . After this interval RST returns high.
rec
If V drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
CC
low for at least the reset time-out period (t ). Any time V goes below the reset threshold
rec
CC
the internal timer clears. The reset timer starts when V returns above the reset threshold.
CC
2.2
Push-button reset input (STM704/806)
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t (see
rec
Figure 36) after it returns high. The MR input has an internal 40 kΩ pull-up resistor, allowing
it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with
open-drain/ collector outputs. Connect a normally open momentary switch from MR to GND
to create a manual reset function; external debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environment, connect a 0.1µF capacitor
from MR to GND to provide additional noise immunity. MR may float, or be tied to V when
CC
not used.
2.3
Watchdog input (NOT available on STM704/795/806)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the watchdog input (WDI) within t
watchdog timer is cleared by either:
(1.6 s typ), the reset is asserted. The internal
WD
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.
If WDI is tied high or low, a reset pulse is triggered every 1.8 s (t + t ).
WD
rec
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting (see Figure 37).
Note:
Input frequency greater than 20 ns (50 MHz) will be filtered.
14/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Operation
2.4
Backup battery switchover
In the event of a power failure, it may be necessary to preserve the contents of external
SRAM through V . With a backup battery installed with voltage V , the devices
OUT
BAT
automatically switch the SRAM to the backup supply when V falls.
CC
Note:
When the battery is first connected without V power applied, the device does not
CC
immediately provide battery backup voltage on V
. Only after V exceeds V
will the
OUT
CC
RST
switchover operate as described below. This mode allows a battery to be attached during
manufacturing but not used until after the system has been activated for the first time. As a
result, no battery power is consumed by the device during storage and shipment. If the
backup battery is not used, connect both V
and V
to V
.
BAT
OUT
CC
This family of supervisors does not always connect V
to V
when V
is greater than
(through a 100 Ω switch) when V is below V (2.4 V) or
OUT CC SW
BAT
OUT
BAT
V
V
. V
connects to V
CC BAT
(whichever is lower). This is done to allow the backup battery (e.g., a 3.6 V lithium cell)
BAT
to have a higher voltage than V
.
CC
Assuming that V
> 2.0 V, switchover at V ensures that battery backup mode is entered
SO
BAT
before V
gets too close to the 2.0 V minimum required to reliably retain data in most
OUT
external SRAMs. When V recovers, hysteresis is used to avoid oscillation around the V
CC
SO
point. V
is connected to V through a 3 Ω PMOS power switch.
OUT
CC
Note:
The backup battery may be removed while V is valid, assuming V
is adequately
BAT
CC
decoupled (0.1 µF typ), without danger of triggering a reset.
Table 4.
Pin
I/O status in battery backup
Status
VOUT
VCC
PFI
Connected to VBAT through internal switch
Disconnected from VOUT
Disabled
PFO
E
Logic low
High impedance
Logic high
ECON
WDI
MR
Watchdog timer is disabled
Disabled
RST
RST
VBAT
Vccsw
Logic low
Logic high
Connected to VOUT
Logic high (STM795)
Doc ID 10519 Rev 9
15/42
Operation
STM690, STM704, STM795, STM802, STM804, STM805, STM806
2.5
Chip enable gating (STM795 only)
Internal gating of the chip enable (E) signal prevents erroneous data from corrupting the
external CMOS RAM in the event of an undervoltage condition. The STM795 uses a series
transmission gate from E to E
(see Figure 11). During normal operation (reset not
CON
asserted), the E transmission gate is enabled and passes all E transitions. When reset is
asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS
RAM. The short E propagation delay from E to E
enables the STM795 to be used with
CON
most µPs. If E is low when reset asserts, E
current write cycle to complete.
remains low for typically 10 µs to permit the
CON
2.6
Chip enable input (STM795 only)
The chip enable transmission gate is disabled and E is high impedance (disabled mode)
while reset is asserted. During a power-down sequence when V passes the reset
CC
threshold, the chip enable transmission gate disables and E immediately becomes high
impedance if the voltage at E is high. If E is low when reset asserts, the chip enable
transmission gate will disable 10 µs after reset asserts (see Figure 12). This permits the
current write cycle to complete during power-down.
Any time a reset is generated, the chip enable transmission gate remains disabled and E
remains high impedance (regardless of E activity) for the first half of the reset time-out
period (t /2). When the chip enable transmission gate is enabled, the impedance of E
rec
appears as a 40 Ω resistor in series with the load at E
. The propagation delay through
the chip enable transmission gate depends on V , the source impedance of the drive
CON
CC
connected to E, and the loading on E
. The chip enable propagation delay is production
CON
tested from the 50% point on E to the 50% point on E
using a 50 Ω driver and a 50 pF
CON
load capacitance (see Figure 35). For minimum propagation delay, minimize the capacitive
load at E and use a low-output impedance driver.
CON
2.7
Chip enable output (STM795 only)
When the chip enable transmission gate is enabled, the impedance of E
is equivalent to
CON
a 40 Ω resistor in series with the source driving E. In the disabled mode, the transmission
gate is off and an active pull-up connects E
off when the transmission gate is enabled.
to V
(see Figure 11). This pull-up turns
CON
OUT
Figure 11. Chip enable gating
V
CC
t
rec
RST
COMPARE
generator
V
RST
V
OUT
E
OUTPUT
CON
CONTROL
E
E
CON
AI08802
16/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 12. Chip enable waveform (STM795)
Operation
V
E
V
CC
RST
V
BAT
CON
½ tr
ec
½ t
rec
t
10 µs
t
rec
RST
E
rec
AI08855c
2.8
Power-fail input/output (NOT available on STM795)
The Power-Fail Input (PFI) is compared to an internal reference voltage (independent from
the V comparator). If PFI is less than the power-fail threshold (V ), the Power-Fail
RST
PFI
Output (PFO) will go low. This function is intended for use as an undervoltage detector to
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see Figure 10) to either the unregulated DC input (if it is available) or the regulated output
of the V regulator. The voltage divider can be set up such that the voltage at PFI falls
CC
below V several milliseconds before the regulated V input to the STM690/704/795/802/
PFI
CC
804/805/806 or the microprocessor drops below the minimum operating voltage.
During battery backup, the power-fail comparator is turned off and PFO goes (or remains)
low (see Figure 13). This occurs after V drops below V
(2.4 V). When power returns,
CC
SW
the power-fail comparator is enabled and PFO follows PFI. If the comparator is unused, PFI
should be connected to V and PFO left unconnected. PFO may be connected to MR on
SS
the STM704/806 so that a low voltage on PFI will generate a reset output.
2.9
Applications information
These supervisor circuits are not short-circuit protected. Shorting V
to ground -
OUT
excluding power-up transients such as charging a decoupling capacitor - destroys the
device. Decouple both V and V
pins to ground by placing 0.1 µF capacitors as close to
CC
BAT
the device as possible.
Doc ID 10519 Rev 9
17/42
Operation
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 13. Power-fail comparator waveform (STM690/704/802/804/805/806)
V
CC
V
RST
V
(2.4 V )
SW
t
rec
PFO
PFO follows PFI
PFO follows PFI
RST
AI08861a
18/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Operation
2.10
Using a SuperCap™ as a backup power source
SuperCaps™ are capacitors with extremely high capacitance values (e.g., order of 0.47 F)
for their size. Figure 14 shows how to use a SuperCap as a backup power source. The
SuperCap may be connected through a diode to the V supply. Since V
can exceed
CC
BAT
V
while V is above the reset threshold, there are no special precautions when using
CC
CC
these supervisors with a Super-Cap.
Figure 14. Using a SuperCap™
5 V
VCC
VOUT
To external SRAM
STMXXX
VBAT
To µP
RST
GND
AI08805
2.11
Negative-going VCC transients
The STM690/704/795/802/804/805/806 supervisors are relatively immune to negative-going
transients (glitches). Figure 32 was generated using a negative pulse applied to V
V
,
CC
CC
starting at V
+ 0.3 V and ending below the reset threshold by the magnitude indicated
RST
(comparator overdrive). The graph indicates the maximum pulse width a negative V
transient can have without causing a reset pulse. As the magnitude of the transient
CC
increases (further below the threshold), the maximum allowable pulse width decreases. Any
combination of duration and overdrive which lies under the curve will NOT generate a reset
signal. Typically, a V transient that goes 100 mV below the reset threshold and lasts 40 µs
CC
or less will not cause a reset pulse. A 0.1 µF bypass capacitor mounted as close as possible
to the V pin provides additional transient immunity.
CC
Doc ID 10519 Rev 9
19/42
Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806
3
Typical operating characteristics
Note:
Typical values are at T = 25 °C.
A
Figure 15. V to V
on-resistance vs. temperature
CC
OUT
5.0
4.0
3.0
2.0
1.0
V
= 3.0 V
= 4.5 V
= 5.5 V
CC
V
CC
V
CC
0.0
0
20
40
60
80
100
120
–40
–20
Temperature (°C)
AI10498
Figure 16. V
to V
on-resistance vs. temperature
BAT
OUT
160
140
120
100
80
60
V
= 2.0 V
BAT
V
= 3.0 V
= 3.3 V
= 3.6 V
BAT
40
V
BAT
20
V
BAT
0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09140b
20/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics
Figure 17. Supply current vs. temperature (no load)
30
25
20
15
V
= 2.7 V
= 3.0 V
= 3.6 V
= 4.5 V
= 5.5 V
CC
V
CC
10
5
V
CC
V
CC
V
CC
0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09141b
Figure 18. Battery current vs. temperature
1000
100
10
V
= 2.0 V
= 3.0 V
= 3.6 V
BAT
V
V
BAT
BAT
1
0.1
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI10499
Doc ID 10519 Rev 9
21/42
Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 19. V threshold vs. temperature
PFI
1.270
1.265
V
= 2.5 V
= 3.0 V
= 3.3 V
= 3.6 V
CC
1.260
1.255
1.250
1.245
1.240
1.235
1.230
1.225
V
CC
V
CC
V
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09142b
Figure 20. Reset comparator propagation delay vs. temperature
30
28
26
24
22
20
18
16
14
12
10
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09143b
22/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics
Figure 21. Power-up t vs. temperature
rec
240
235
230
225
220
215
210
V
= 3.0 V
= 4.5 V
= 5.5 V
CC
V
CC
V
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09144b
Figure 22. Normalized reset threshold vs. temperature
1.004
1.002
1.000
0.998
0.996
–40
–20
0
20
40
60
80
100
120
AI09145b
Temperature (°C)
Doc ID 10519 Rev 9
23/42
Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 23. Watchdog time-out period vs. temperature
1.90
1.85
1.80
1.75
V
= 3.0 V
= 4.5 V
= 5.5 V
CC
1.70
1.65
1.60
V
V
CC
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09146b
Figure 24. E to E
on-resistance vs. temperature
CON
60
50
40
30
20
10
V
= 3.0 V
= 4.5 V
= 5.5 V
CC
V
CC
V
CC
0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09147b
24/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics
Figure 25. PFI to PFO propagation delay vs. temperature
4.0
V
= 3.0 V
= 3.6 V
= 4.5 V
= 5.5 V
CC
V
CC
3.0
2.0
1.0
0.0
V
CC
V
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09148b
Figure 26. Output voltage vs. load current (V = 5 V; V
= 2.8 V; T = 25 °C)
CC
BAT
A
5.00
4.98
4.96
4.94
0
10
20
30
40
50
I
(mA)
OUT
AI10496
Doc ID 10519 Rev 9
25/42
Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 27. Output voltage vs. load current (V = 0 V; V
= 2.8 V; T = 25 °C)
CC
BAT
A
2.80
2.78
2.76
2.74
2.72
2.70
2.68
2.66
0.0
0.2
0.4
0.6
0.8
1.0
I
(mA)
OUT
AI10497
Figure 28. RST output voltage vs. supply voltage
5
4
3
5
4
V
RST
V
CC
3
2
2
1
0
1
0
500 ms / div
AI09149b
26/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics
Figure 29. RST output voltage vs. supply voltage
5
4
3
2
1
0
5
4
3
2
1
0
V
RST
V
CC
500 ms / div
AI09150b
Figure 30. Power-fail comparator response time (assertion)
5 V
1 V / div
PFO
0 V
1.3 V
PFI
500 mV / div
0 V
500 ns / div
AI09153b
Doc ID 10519 Rev 9
27/42
Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 31. Power-fail comparator response time (de-assertion)
5 V
1 V / div
PFO
0 V
PFI
1.3 V
500 mV / div
0 V
500 ns / div
AI09154b
Figure 32. Maximum transient duration vs. reset threshold overdrive
6000
5000
4000
Reset occurs
above the curve
3000
2000
1000
0
0.001
0.01
0.1
1
10
Reset comparator overdrive, V
– V
(V)
CC
RST
AI09156b
28/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics
Figure 33. E to E
propagation delay vs. temperature
CON
4.0
3.0
2.0
1.0
V
= 3.0 V
= 4.5 V
= 5.5 V
CC
V
V
CC
CC
0.0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09157b
Doc ID 10519 Rev 9
29/42
Maximum ratings
STM690, STM704, STM795, STM802, STM804, STM805, STM806
4
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5.
Symbol
TSTG
Absolute maximum ratings
Parameter
Value
Unit
Storage temperature (VCC off)
Lead solder temperature for 10 seconds
Input or output voltage
Supply voltage
–55 to 150
260
°C
°C
V
(1)
TSLD
VIO
–0.3 to VCC +0.3
–0.3 to 6.0
20
VCC/VBAT
IO
V
Output current
mA
mW
PD
Power dissipation
320
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
30/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived tests performed under the measurement conditions summarized in
Table 6. Designers should check that the operating conditions in their circuit match the
operating conditions when relying on the quoted parameters.
Table 6.
Operating and AC measurement conditions
STM690/704/795/
802/804/805/806
Parameter
Unit
VCC/VBAT supply voltage
1.0 to 5.5
–40 to 85
V
°C
ns
V
Ambient operating temperature (TA)
Input rise and fall times
≤
55
Input pulse voltages
0.2 to 0.8 VCC
0.3 to 0.7 VCC
Input and output timing ref. voltages
V
Figure 34. E to E
propagation delay test circuit
CON
V
CC
V
CC
V
BAT
3.6 V
STM690/704/
795/802/804/
805/806
25 equivalent
source impedance
E
E
CON
50
50 cable
50
(1)
50 pF C
L
GND
AI08854
1. CL includes load capacitance and scope probe capacitance.
Figure 35. AC testing input/output waveforms
0.8 V
CC
0.7 V
CC
CC
0.3 V
0.2 V
CC
AI02568
Doc ID 10519 Rev 9
31/42
DC and AC parameters
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 36. MR timing waveform
MR
t
MLRL
(1)
RST
t
t
rec
MLMH
AI07837a
1. RST for STM805.
Figure 37. Watchdog timing
V
CC
t
rec
RST
WDI
t
WD
AI07891
Table 7.
Sym
DC and AC characteristics
Alter-
Description
Test condition(1)
Min
Typ
Max
Unit
native
VCC
VBAT
,
Operating voltage
TA = –40 to +85 °C
1.1(3)
5.5
V
(2)
Excluding IOUT (VCC < 5.5 V)
Excluding IOUT (VCC < 3.6 V)
Excluding IOUT (VBAT = 2.3 V,
40
35
60
50
µA
µA
V
CC supply current
ICC
VCC supply current in battery
backup mode
25
35
µA
µA
V
VCC = 2.0 V, MR = VCC
)
VBAT supply current in battery
backup mode
(4)
IBAT
Excluding IOUT (VBAT = 3.6 V)
IOUT1 = 5 mA(5)
0.4
1.0
VCC
0.03
–
VCC –
0.015
VCC
0.3
–
VCC
0.15
–
VOUT1
VOUT voltage (active)
IOUT1 = 75 mA
V
VCC
0.0015 0.0006
–
VCC –
I
OUT1 = 250 µA, VCC > 2.5 V(5)
V
VBAT
0.1
–
VBAT
0.034
–
I
OUT2 = 250 µA, VBAT = 2.3 V
V
VOUT2
VOUT voltage (battery backup)
VCC to VOUT on-resistance
VBAT
0.14
–
I
OUT2 = 1 mA, VBAT = 2.3 V
V
3
4
Ω
32/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
DC and AC parameters
Table 7.
Sym
DC and AC characteristics (continued)
Alter-
native
Description
Test condition(1)
Min
Typ
100
75
Max
Unit
Ω
VBAT to VOUT on-resistance
Input leakage current (MR)
STM704/806 only;
20
350
µA
MR = 0 V, VCC = 3 V
I
LI
Input leakage current (PFI)
Input leakage current (WDI)
0 V < VIN < VCC
0 V < VIN < VCC
STM804/805/795;
–20
–1
2
+25
+1
nA
µA
I
Output leakage current
–1
+1
µA
LO
(6)
0 V < VIN < VCC
VIH
VIL
Input high voltage (MR, WDI)
Input low voltage (MR, WDI)
VRST (max) < VCC < 5.5 V
VRST (max) < VCC < 5.5 V
0.7 VCC
V
V
0.3 VCC
0.3
Output low voltage (PFO,
RST, RST, Vccsw)
VCC = VRST (max),
ISINK = 3.2 mA
V
V
VOL
VCC = VRST (max),
Output low voltage (ECON
)
0.2 VCC
0.3
IOUT = 1.6 mA, E = 0 V
IOL = 40 µA,
VCC = 1.0 V, VBAT = VCC
,
V
V
TA = 0 °C to 85 °C
VOL
Output low voltage (RST)
IOL = 200 µA,
0.3
VCC = 1.2 V, VBAT = VCC
Output high voltage (RST,
RST)(7)
ISOURCE = 1 mA,
VCC = VRST (max)
2.4
V
V
V
V
V
VCC = VRST (max),
IOUT = 1.6 mA, E = VCC
VOH
Output high voltage (ECON
Output high voltage (PFO)
)
0.8 VCC
0.8 VCC
0.8VBAT
0.8VBAT
I
V
SOURCE = 75 µA,
CC = VRST (max)
VOH battery backup (Vccsw,
RST)
ISOURCE = 100 µA,
CC = 0 V, VBAT = 2.8 V
V
VOHB
I
SOURCE = 75 µA,
VOH battery backup (ECON
)
VCC = 0 V, VBAT = 2.8 V
Power-fail comparator (NOT available on STM795)
STM802/
804/806
1.212 1.237
1.187 1.237
1.262
V
V
PFI falling
(VCC < 3.6 V)
VPFI
PFI input threshold
STM690/
704/805
1.287
20
PFI hysteresis
PFI rising (VCC < 3.6 V)
10
2
mV
µs
tPFD
PFI to PFO propagation delay
Doc ID 10519 Rev 9
33/42
DC and AC parameters
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Table 7.
Sym
DC and AC characteristics (continued)
Alter-
Description
Test condition(1)
Min
Typ
Max
Unit
native
PFO output short to GND
current
ISC
VCC = 3.6 V, PFO = 0 V
0.1
0.75
2.0
mA
Battery switchover
VBAT > VSW
VSW
VBAT
VSW
VBAT
2.4
V
V
Power-down
Power-up
VBAT < VSW
VBAT > VSW
VBAT < VSW
Battery backup switchover
voltage(8)(9)
V
VSO
V
VSW
V
Hysteresis
40
mV
Reset thresholds
VCC falling 3.00
3.075
3.085
3.075
3.085
2.925
2.935
2.925
2.935
2.625
2.635
2.625
2.635
200
3.15
3.17
3.12
3.14
3.00
3.02
3.00
3.02
2.70
2.72
2.70
2.72
280
V
V
STM690T/
704T/795T/ 805T
VCC rising
3.00
VCC falling 3.00
V
STM802T/
804T/806T
VCC rising
3.00
V
VCC falling 2.85
V
STM690S/
704S/795S/ 805S
VCC rising
2.85
V
(10)
VRST
Reset threshold
VCC falling 2.88
VCC rising 2.88
CC falling 2.55
V
STM802S/
804S/806S
V
V
V
STM690R/
704R/795R/ 805R
VCC rising
2.55
V
VCC falling 2.59
V
STM802R/
804R/806R
VCC rising
2.59
140
V
trec
RST pulse width
VCC < 3.6 V
ms
Push-button reset input (STM704/806)
tMLMH
tMLRL
tMR MR pulse width
100
20
60
ns
ns
tMRD MR to RST output delay
500
Watchdog timer (NOT available on STM704/795/806)
tWD
Watchdog timeout period
WDI pulse width
VRST (max) < VCC < 3.6 V
VRST (max) < VCC < 3.6 V
1.12
100
1.60
20
2.24
s
ns
Chip enable gating (STM795 only)
E to ECON resistance
VCC = VRST (max)
46
Ω
34/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
DC and AC parameters
Table 7.
Sym
DC and AC characteristics (continued)
Alter-
native
Description
Test condition(1)
Min
Typ
Max
Unit
E to ECON propagation delay
Reset to ECON high delay
VCC = VRST (max)
2
7
ns
µs
10
VCC = 3.6 V, disable mode,
ECON = 0 V
ISC
ECON short circuit current
0.1
0.75
2.0
mA
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = VRST (max) to 5.5 V; and VBAT = 2.8 V (except where
noted).
2. VCC supply current, logic input leakage, watchdog functionality, push-button reset functionality, PFI functionality,
state of RST and RST tested at VBAT = 3.6 V, and VCC = 5.5 V. The state of RST or RST and PFO is tested at VCC = VCC
(min). Either VCC or VBAT can go to 0 V if the other is greater than 2.0 V.
3. VCC (min) = 1.0 V for TA = 0 °C to +85 °C.
4. Tested at VBAT = 3.6 V, VCC = 3.5 V and 0 V.
5. Guaranteed by design.
6. The leakage current measured on the RST pin (STM804/805) or RST pin (STM795) is tested with the reset output not
asserted (output high impedance).
7. Not valid for STM795/804/805 (open drain).
8. When VBAT > VCC > VSW, VOUT remains connected to VCC until VCC drops below VSW
.
9. When VSW > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) - 75 mV.
10. The reset threshold tolerance is wider for VCC rising than for VCC falling due to the 10 mV (typ) hysteresis, which prevents
internal oscillation.
Doc ID 10519 Rev 9
35/42
Package mechanical data
STM690, STM704, STM795, STM802, STM804, STM805, STM806
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
36/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Package mechanical data
Figure 38. SO8 – 8-lead plastic small outline, 150 mils body width,
package mechanical drawing
A2
A
C
B
ddd
e
D
8
1
E
H
A1
L
SO-A
Table 8.
SO8 - 8-lead plastic small outline, 150 mils body width,
package mechanical data
mm
Min
inches
Min
Symb
Typ
Max
Typ
Max
A
A1
B
—
—
1.35
0.10
0.33
0.19
4.80
—
1.75
0.25
0.51
0.25
5.00
0.10
4.00
—
—
—
0.053
0.004
0.013
0.007
0.189
—
0.069
0.010
0.020
0.010
0.197
0.004
0.157
—
—
—
C
—
—
D
—
—
ddd
E
—
—
—
3.80
—
—
0.150
—
e
1.27
—
0.050
—
H
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
h
—
—
L
—
—
α
—
—
N
8
8
Doc ID 10519 Rev 9
37/42
Package mechanical data
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 39. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline
D
8
1
5
4
c
E1
E
A1
L
A
A2
L1
CP
b
e
TSSOP8BM
Table 9.
TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size,
mechanical data
mm
Min
inches
Min
Symb
Typ
Max
Typ
Max
A
A1
A2
b
—
—
—
0.05
0.75
0.25
0.13
—
1.10
0.15
0.95
0.40
0.23
0.10
3.10
—
—
—
—
0.043
0.006
0.037
0.016
0.009
0.004
0.122
—
0.002
0.030
0.010
0.005
—
0.85
—
0.034
—
c
—
—
CP
D
—
—
3.00
0.65
4.90
3.00
0.55
0.95
—
2.90
—
0.118
0.026
0.193
0.118
0.022
0.037
—
0.114
—
e
E
4.65
2.90
0.40
—
5.15
3.10
0.70
—
0.183
0.114
0.016
—
0.203
0.122
0.030
—
E1
L
L1
α
0°
6°
0°
6°
N
8
8
38/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Part numbering
7
Part numbering
Table 10. Ordering information scheme
Example:
STM690
T
M
6
E
Device type
STM690/704/795/802/804/805/806
Reset threshold voltage
T = STM690/704/795/805 = VRST = 3.00 V to 3.15 V
STM802/804/806 = VRST = 3.00 V to 3.12 V
S = STM690/704/795/805 = VRST = 2.85 V to 3.00 V
STM802/804/806 = VRST = 2.88 V to 3.00 V
R = STM690/704/795/805 = VRST = 2.55 V to 2.70 V
STM802/804/806 = VRST = 2.59 V to 2.70 V
Package
M = SO8
DS(1)= TSSOP8
Temperature range
6 = –40 to 85 °C
Shipping method
E = ECOPACK® package, tubes
F = ECOPACK® package, tape and reel
1. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Doc ID 10519 Rev 9
39/42
Part numbering
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Table 11. Marking description
Part number
Reset threshold
Package
Topside marking
SO8
TSSOP8
SO8
STM690T
3.075
690T
STM690S
STM690R
STM704T
STM704S
STM704R
STM795T
STM795S
STM795R
STM802T
STM802S
STM802R
STM804T
STM804S
STM804R
STM805T
STM805S
STM805R
STM806T
STM806S
STM806R
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
690S
690R
704T
704S
704R
795T
795S
795R
802T
802S
802R
804T
804S
804R
805T
805S
805R
806T
806S
806R
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
40/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Revision history
8
Revision history
Table 12. Document revision history
Date
Revision
Changes
31-Oct-2003
1
Initial release.
Reformatted; update characteristics (Figure 1, 3, 4, 11, 13, 14, 37;
Table 1, 3, 4, 7, 9, 11).
22-Dec-2003
16-Jan-2004
2
Added Typical operating characteristics (Figure 17, 18, 20 to 26, 29,
30 to 34).
2.1
07-Apr-2004
25-May-2004
2.2
3
Updated characteristics (Figure 13, 29, 30, Table 1, 3, 7)
Update characteristics (Table 3, 7)
Update package availability, pin description; promote document
(Figure 1, 14; Table 3, 10)
02-Jul-2004
29-Sep-2004
4
5
Clarify root part numbers, pin descriptions, update characteristics
(Figure 2, to, 11, 13, 14, 35; Table 1, 3, 6, 7, 10)
25-Feb-2005
05-Apr-2006
6
7
Update characteristics (Figure 11, 16, to 35; Table 7)
Update characteristics (Figure 13)
Updated Section 1.1.6, Section 1.1.8, Figure 10, 11, 19, Table 3, 5, 7;
added text to Section 6.
20-Nov-2009
18-Aug-2010
8
9
Updated Features, Section 2.4: Backup battery switchover.
Doc ID 10519 Rev 9
41/42
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2010 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
42/42
Doc ID 10519 Rev 9
相关型号：
©2020 ICPDF网 联系我们和版权申明