STM32L4R5ZG [STMICROELECTRONICS]
Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 150DMIPS, up to 2MB Flash, 640KB SRAM, LCD-TFT & MIPI DSI, ext. SMPS;
| 型号： | STM32L4R5ZG |
| 厂家： | 
ST |
| 描述： | Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 150DMIPS, up to 2MB Flash, 640KB SRAM, LCD-TFT & MIPI DSI, ext. SMPS CD 静态存储器 |
| 文件： | 总307页 (文件大小：5991K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32L4R5xx STM32L4R7xx
STM32L4R9xx
Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 150DMIPS,
up to 2MB Flash, 640KB SRAM, LCD-TFT & MIPI DSI, ext. SMPS
Datasheet- production data
Features
• Ultra-low-power with FlexPowerControl
– 1.71 V to 3.6 V power supply
LQFP144 (20 × 20)
LQFP100 (14 x 14)
UFBGA169 (7 x 7)
UFBGA144 (10 x 10)
UFBGA132 (7 × 7)
WLCSP144
– -40 °C to 85/125 °C temperature range
– Batch acquisition mode (BAM)
– 305 nA in VBAT mode: supply for RTC and
32x32-bit backup registers
– Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
±0.25 % accuracy)
– 33 nA Shutdown mode (5 wakeup pins)
– 125 nA Standby mode (5 wakeup pins)
– 420 nA Standby mode with RTC
– 2.8 μA Stop 2 with RTC
– Internal 48 MHz with clock recovery
– 3 PLLs for system clock, USB, audio, ADC
• RTC with HW calendar, alarms and calibration
– 110 μA/MHz Run mode (LDO mode)
• Up to 24 capacitive sensing channels: support
– 43 μA/MHz Run mode (@ 3.3 V SMPS
mode)
touchkey, linear and rotary touch sensors
• Advanced graphics features
– 5 µs wakeup from Stop mode
– Chrom-ART Accelerator (DMA2D) for
enhanced graphic content creation
– Brownout reset (BOR) in all modes except
shutdown
– Chrom-GRC (GFXMMU) allowing up to
20% of graphic resources optimization
– Interconnect matrix
®
®
®
• Core: Arm 32-bit Cortex -M4 CPU with FPU,
adaptive real-time accelerator (ART
– MIPI DSI Host controller with two DSI
lanes running at up to 500 Mbits/s each
Accelerator) allowing 0-wait-state execution
from Flash memory, frequency up to 120 MHz,
MPU, 150 DMIPS/1.25 DMIPS/MHz
– LCD-TFT controller
• 16x timers: 2 x 16-bit advanced motor-control,
2 x 32-bit and 5 x 16-bit general purpose, 2x
16-bit basic, 2x low-power 16-bit timers
(available in Stop mode), 2x watchdogs,
SysTick timer
(Dhrystone 2.1), and DSP instructions
• Performance benckmark
– 1.25 DMIPS/MHz (Drystone 2.1)
®
– 409.20 Coremark (3.41 Coremark/MHz
• Up to 136 fast I/Os, most 5 V-tolerant, up to 14
@120 MHz)
I/Os with independent supply down to 1.08 V
• Energy benckmark
• Memories
– 233 ULPMark™CP score
– 2-Mbyte Flash, 2 banks read-while-write,
proprietary code readout protection
– 56.5 ULPMark™PP score
• Clock sources
– 640 Kbytes of SRAM including 64 Kbytes
with hardware parity check
– 4 to 48 MHz crystal oscillator
– External memory interface for static
memories supporting SRAM, PSRAM,
NOR, NAND and FRAM memories
– 32 kHz crystal oscillator for RTC (LSE)
– Internal 16 MHz factory-trimmed RC (±1%)
– Internal low-power 32 kHz RC (±5%)
– 2 x OctoSPI memory interface
• 4x digital filters for sigma delta modulator
January 2020
DS12023 Rev 5
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This is information on a product in full production.
www.st.com
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
• Rich analog peripherals (independent supply)
– 6x USARTs (ISO 7816, LIN, IrDA, modem)
– 3x SPIs (5x SPIs with the dual OctoSPI)
– CAN (2.0B Active) and SDMMC
– 12-bit ADC 5 Msps, up to 16-bit with
hardware oversampling, 200 µA/Msps
– 2x 12-bit DAC, low-power sample and hold
– 2x operational amplifiers with built-in PGA
– 2x ultra-low-power comparators
• 14-channel DMA controller
• True random number generator
• CRC calculation unit, 96-bit unique ID
• 20x communication interfaces
• 8- to 14-bit camera interface up to 32 MHz
– USB OTG 2.0 full-speed, LPM and BCD
(black and white) or 10 MHz (color)
– 2x SAIs (serial audio interface)
• Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell
(ETM)
– 4x I2C FM+(1 Mbit/s), SMBus/PMBus
Table 1. Device summary
Part numbers
Reference
STM32L4R5VI, STM32L4R5QI, STM32L4R5ZI, STM32L4R5AI, STM32L4R5AG,
STM32L4R5QG, STM32L4R5VG, STM32L4R5ZG
STM32L4R5xx
STM32L4R7xx
STM32L4R9xx
STM32L4R7VI, STM32L4R7ZI, STM32L4R7AI
STM32L4R9VI, STM32L4R9ZI, STM32L4R9AI, STM32L4R9AG, STM32L4R9VG,
STM32L4R9ZG
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Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . . 18
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 22
3.10 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.10.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.10.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.10.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.10.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.11 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.13 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.14 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.15 DMA request router (DMAMux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.16 Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.17 Chrom-GRC (GFXMMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.18 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.18.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 44
3.18.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 44
3.19 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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3.19.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.19.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.19.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.20 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.21 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.22 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.23 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.24 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.25 LCD-TFT controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.26 DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.27 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 51
3.28 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.29 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.30 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.30.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.30.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.30.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.30.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 54
3.30.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.30.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.30.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.31 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 56
3.32 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.33 Universal synchronous/asynchronous receiver transmitter (USART) . . . 58
3.34 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 59
3.35 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.36 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.37 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.38 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 61
3.39 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 62
3.40 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.41 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 62
3.42 OctoSPI interface (OctoSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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3.43 OctoSPI IO manager (OctoSPIIOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.44 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.44.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.44.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4
5
6
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 142
Embedded reset and power control block characteristics . . . . . . . . . . 142
Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.3.7
6.3.8
6.3.9
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 190
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
6.3.10 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
6.3.11 MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.3.12 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.3.13 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.3.15 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
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6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
6.3.19 Extended interrupt and event controller input (EXTI) characteristics . . 213
6.3.20 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
6.3.21 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 214
6.3.22 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 227
6.3.23 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 232
6.3.24 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
6.3.25 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 235
6.3.26 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
6.3.27
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
BAT
6.3.28 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
6.3.29 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
6.3.30 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 243
6.3.31 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
6.3.32 OctoSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
6.3.33 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 276
6.3.34 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 277
6.3.35 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . 278
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
7.1
7.2
7.3
7.4
7.5
7.6
7.7
UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
WLCSP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
7.7.1
7.7.2
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 301
8
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
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List of tables
List of tables
Table 1.
Table 2.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 19
STM32L4R5xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Table 3.
Table 4.
Table 5.
Table 6.
peripherals interconnect matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
STM32L4Rxxx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 142
Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Current consumption in Run and Low-power run modes, code with data
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) . 147
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ART enable (Cache ON Prefetch OFF)
Table 26.
and power supplied by external SMPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Current consumption in Run and Low-power run modes, code with data
processing running from Flash in dual bank, ART enable (Cache ON Prefetch OFF) . . . 149
Consumption in Run and Low-power run modes, code with data processing
Table 27.
Table 28.
running from Flash in dual bank, ART enable (Cache ON Prefetch OFF)
and power supplied by external SMPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Current consumption in Run and Low-power run modes,
code with data processing running from Flash in single bank, ART disable. . . . . . . . . . . 151
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single bank, ART disable and power supplied by external SMPS . 152
Current consumption in Run and Low-power run modes,
code with data processing running from Flash in dual bank, ART disable . . . . . . . . . . . . 153
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ART disable and power supplied by external SMPS . . 154
Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1 and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . 156
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
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STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Table 35.
Table 36.
Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 157
Typical current consumption in Run and Low-power run modes, with
different codes running from Flash, ART enable (Cache ON Prefetch OFF)
and power supplied by external SMPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Typical current consumption in Run and Low-power run modes,
Table 37.
Table 38.
Table 39.
Table 40.
with different codes running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Typical current consumption in Run and Low-power run modes with different codes
running from Flash, ART disable and power supplied by external SMPS . . . . . . . . . . . . 162
Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Typical consumption in Run and Low-power run modes, with different codes
running from SRAM1 and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . 164
Current consumption in Sleep and Low-power sleep mode, Flash ON . . . . . . . . . . . . . . 165
Current consumption in Sleep and Low-power sleep modes,
Table 41.
Table 42.
Flash ON and power supplied by external SMPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Current consumption in Low-power sleep mode, Flash in power-down . . . . . . . . . . . . . . 167
Current consumption in Stop 2 mode, SRAM3 disabled . . . . . . . . . . . . . . . . . . . . . . . . . 168
Current consumption in Stop 2 mode, SRAM3 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
LSE
HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . 199
DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
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Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
OPAMP characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
V
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
BAT
BAT
DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
WWDG min/max timeout value at 120 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 100. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 101. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 102. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 103. USB OTG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 104. USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 105. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 254
Table 106. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 254
Table 107. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 255
Table 108. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 256
Table 109. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 110. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 257
Table 111. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 112. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 259
Table 113. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 114. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Table 115. Synchronous non-multiplexed NOR/PSRAM
read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 116. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 117. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Table 118. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Table 119. OctoSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 120. OctoSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Table 121. OctoSPI characteristics in DTR mode (with DQS)/Octal and HyperBus™. . . . . . . . . . . . 271
Table 122. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table 123. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 124. Dynamics characteristics:
SD / eMMC characteristics at VDD = 2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 125. Dynamics characteristics:
eMMC characteristics at VDD = 1.71 V to 1.9 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 126. UFBGA169 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Table 127. UFBGA169 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 283
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Table 128. UFBGA144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Table 129. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 286
Table 130. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 131. WLCSP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 132. WLCSP144 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 133. UFBGA132 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Table 134. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 296
Table 135. LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Table 136. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Table 137. STM32L4Rxxx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 138. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
10/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx block diagram . . . . . . . . . . . . . . . . . . 17
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STM32L4R5xx and STM32L4R7xx power supply overview. . . . . . . . . . . . . . . . . . . . . . . . 24
STM32L4R5xxxP and STM32L4R7xxxP with external SMPS power supply overview . . . 25
STM32L4R9xx power supply overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
(1)
STM32L4R5xx and STM32L4R7xx UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . 66
(1)
Figure 10. STM32L4R9xx UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 11. STM32L4R5xxxP UFBGA169 external SMPS ballout
Figure 12. STM32L4R5xx and STM32L4R7xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 13. STM32L4R9xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 14. STM32L4R5ZxxxP external SMPS LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 15. STM32L4R9xx UFBGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 16. STM32L4R9xx WLCSP144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 17. STM32L4R9ZxxxP WLCSP144 external SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 18. STM32L4R5xx WLCSP144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 19. STM32L4R5xx UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 20. STM32L4R5xxxP UFBGA132 external SMPS ballout
Figure 21. STM32L4R5xx and STM32L4R7xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . 67
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . 73
(1)
(1)
Figure 22. STM32L4R9xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 23. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 24. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 25. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 26. Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 27. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 28. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 29. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 30. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 31. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 32. HSI16 frequency versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 33. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 34. HSI48 frequency versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 35. MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 36. MIPI D-PHY HS/LP data lane transition timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 37. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
(1)
Figure 38. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 39. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 40. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 41. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 42. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 43. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 44. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 45. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 46. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 47. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 48. USB OTG timings – definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . 251
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12
List of figures
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Figure 49. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 253
Figure 50. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 255
Figure 51. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 52. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 53. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 54. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 55. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 56. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 57. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 58. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 59. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 267
Figure 60. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 268
Figure 61. OctoSPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 62. OctoSPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 63. OctoSPI HyperBus™ clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 64. OctoSPI HyperBus™ read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 65. OctoSPI HyperBus™ read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 66. OctoSPI HyperBus™ write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Figure 67. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Figure 68. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Figure 69. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Figure 70. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Figure 71. UFBGA169 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Figure 72. UFBGA169 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 73. UFBGA169 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 74. UFBGA144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Figure 75. UFBGA144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 76. UFBGA144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 77. LQFP144 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 78. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 79. LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
(2)
Figure 80. LQFP144 external SMPS device marking (package top view) . . . . . . . . . . . . . . . . . . . 291
Figure 81. WLCSP144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Figure 82. WLCSP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 83. WLCSP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Figure 84. UFBGA132 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Figure 85. UFBGA132 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 86. UFBGA132 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Figure 87. LQFP100 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Figure 88. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 89. LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
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DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L4Rxxx microcontrollers.
This document should be read in conjunction with the STM32L4Rxxx reference manual
(RM0432). The reference manual is available from the STMicroelectronics website
www.st.com.
®(a)
®
®
For information on the Arm
Cortex -M4 core, refer to the Cortex -M4 Technical
Reference Manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS12023 Rev 5
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65
Description
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
2
Description
The STM32L4R5xx, STM32L4R7xx and STM32L4R9xx devices are an ultra-low-power
microcontrollers family (STM32L4+ Series) based on the high-performance
®
®
Arm Cortex -M4 32-bit RISC core. They operate at a frequency of up to 120 MHz.
The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all
®
the Arm single-precision data-processing instructions and all the data types. The Cortex-
M4 core also implements a full set of DSP (digital signal processing) instructions and a
memory protection unit (MPU) which enhances the application’s security.
These devices embed high-speed memories (2 Mbytes of Flash memory and 640 Kbytes of
SRAM), a flexible external memory controller (FSMC) for static memories (for devices with
packages of 100 pins and more), two OctoSPI Flash memories interface (available on all
packages) and an extensive range of enhanced I/Os and peripherals connected to two APB
buses, two AHB buses and a 32-bit multi-AHB bus matrix.
The STM32L4Rxxx devices embed several protection mechanisms for embedded Flash
memory and SRAM: readout protection, write protection, proprietary code readout
protection and a firewall.
These devices offer a fast 12-bit ADC (5 Msps), two comparators, two operational
amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two
general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven
general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four
digital filters for external sigma delta modulators (DFSDM). In addition, up to 24 capacitive
sensing channels are available.
They also feature standard and advanced communication interfaces such as:
•
•
•
•
•
•
•
•
•
Four I2Cs
Three SPIs
Three USARTs, two UARTs and one low-power UART
Two SAIs
One SDMMC
One CAN
One USB OTG full-speed
Camera interface
DMA2D controller
The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C
junction) temperature ranges from a 1.71 to 3.6 V for V power supply when using internal
DD
LDO regulator and a 1.05 to 1.32 V V
power supply when using external SMPS supply.
DD12
A comprehensive set of power-saving modes allows the design of low-power applications.
Some independent power supplies are supported like an analog independent supply input
for ADC, DAC, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and up to
14 I/Os, which can be supplied independently down to 1.08 V. A VBAT input allows to
backup the RTC and backup the registers. Dedicated V
power supplies can be used to
DD12
bypass the internal LDO regulator when connected to an external SMPS.
The STM32L4Rxxx family offers six packages from 100-pin to 169-pin.
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DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Description
Table 2. STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
features and peripheral counts
R5VI
R9VI
R5QI
R5ZI
R9ZI
R5AI
R9AI
R7AI
Peripheral
R7VI
R7ZI
R5VG
R9VG R5QG
R5ZG
R9ZG
R5AG
R9AG
1 Mbyte for xxxG devices
2 Mbyte for xxxI devices
Flash memory
System
Backup
640 (192 + 64 + 384) Kbyte
128 byte
SRAM
External memory
controller for static
memories (FSMC)
Yes(1)
1
Yes
OctoSPI
2
Advanced
control
2 (16-bit)
General
purpose
5 (16-bit)
2 (32-bit)
Basic
2 (16-bit)
2 (16-bit)
1
Timers
Low-power
SysTick timer
Watchdog
timers
(independent,
window)
2
SPI
3
4
I2C
USART/UART
UART
LPUART
3
2
1
Comm
.
interfa
ces
SAI
2
CAN
1
USB OTG FS
SDMMC
Yes
Yes
Digital filters for sigma-
delta modulators
Yes
(4 filters)
Number of channels
RTC
8
Yes
3
Tamper pins
Camera interface
Yes
Chrom-ART
Accelerator
Yes
Chrom-GRC
No
Yes
No
Yes
No
Yes
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65
Description
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Table 2. STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
features and peripheral counts (continued)
R5VI
R9VI
R5QI
R5ZI
R9ZI
R5AI
R9AI
Peripheral
R7VI
R7ZI
R7AI
R5VG
R9VG R5QG
R5ZG
R9ZG
R5AG
R9AG
LCD - TFT
No
Yes
No
No
Yes
No
Yes
MIPI DSI Host(2)
No
Yes
No
Yes
No
Yes
Random number
generator
Yes
GPIOs(3)
83
5
77
4
110
5
115
5
112(4)
5
140
5
131
4
Wakeup pins
Nb of I/Os down to
1.08 V
0
0
14
14
11
14
13
Capacitive sensing
Number of channels
21
16
18
14
24
1
12-bit ADCs
Number of channels
16
14
2
2
12-bit DAC
Number of channels
Internal voltage
reference buffer
Yes
Analog comparator
Operational amplifiers
Max. CPU frequency
Operating voltage
2
2
120 MHz
1.71 to 3.6 V
(VDD
)
Operating voltage
1.05 to 1.32 V
(VDD12
)
Operating temperature
Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C
LQFP144,
LQFP144
WLCSP144
LQFP100
UFBGA132
LQFP144
UFBGA144
WLCSP144
UFBGA169
Packages
1. For the LQFP100 package, only FMC bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory
using the NE1 chip select.
2. The DSI Host interface is only available on the STM32L4R9xx sales types.
3. In the case of an external SMPS package type is used, 2 GPIOs are replaced by VDD12 pins to connect the SMPS power
supplies hence reducing the number of available GPIOs by 2.
4. 110 GPIOs available for WLCSP144 and LQFP144 packages.
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DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Description
Figure 1. STM32L4R5xx, STM32L4R7xx and STM32L4R9xx block diagram
CLK, NE[4:1], NL, NBL[1:0],
Flexible static memory controller (FSMC):
SRAM, PSRAM, NOR Flash, NAND Flash
A[25:0], D[15:0], NOE, NWE,
NWAIT, NCE, INT as AF, FRAM
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
JTAG & SW
ETM
MPU
NVIC
OctoSPI1 memory interface
OctoSPI2 memory interface
IO[7:0],
CLK, NCS. DQS
TRACECLK
TRACED[3:0]
D-BUS
ARM Cortex-M4
120 MHz
FPU
RNG
I-BUS
Flash
up to
2 MB
S-BUS
HSYNC, VSYNC,
PIXCLK, D[13:0]
LCD_R[7:0], LCD_G[7:0], LCD_B[7:0],
LCD_HSYNC, LCD_VSYNC, LCD_DE,
LCD_CLK
Camera Interface
LCD - TFT
@ VDDUSB
SRAM1 192 KB
SRAM2 64 KB
SRAM3 384 KB
CHROM-ART
DMA2D
DP
DM
USB
OTG
ID, VBUS, SOF
Chrom-GRC
(GFXMMU)
Power management
VDD
D[7:0]
CMD, CK as AF
AHB2 120 MHz
SDIO / MMC
DMA2
Voltage
regulator
3.3 to 1.2 V
VDD = 1.71 to 3.6 V
VSS
@ VDD
@ VDD
DMA1
Supply
supervision
reset
Int
MSI
RC HSI
VDDIO, VDDUSB
VDDA, VSSA
VDD, VSS, NRST
8 Groups of 4 channels max as AF
Touch sensing controller
BOR
RC LSI
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[15:0]
PG[15:0]
PH[15:0]
PI[11:0]
GPIO PORT A
PVD, PVM
@VDD
PLL 1&2&3
GPIO PORT B
GPIO PORT C
OSC_IN
OSC_OUT
XTAL OSC
4- 16MHz
IWDG
GPIO PORT D
Standby
interface
@VBAT
GPIO PORT E
GPIO PORT F
GPIO PORT G
Reset & clock
control
OSC32_IN
XTAL 32 kHz
RTC
AWU
Backup register
OSC32_OUT
RTC_TS
RTC_TAMPx
RTC_OUT
GPIO PORT H
GPIO PORT I
VBAT = 1.55 to 3.6 V
4 channels, ETR as AF
TIM2
32b
CRC
Temperature sensor
@ VDD
TIM3
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
16b
8 analog inputs common to the ADC
TIM4
16b
@ VDDA
ADC1
ITF
TIM5
32b
smcard
irDA
USART2
RX, TX, CK, CTS, RTS as AF
RX, TX, CK, CTS, RTS as AF
@ VDDA
VREF+
114 AF
VREF Buffer
smcard
irDA
USART3
AHB/APB2
AHB/APB1
EXT IT. WKUP
UART4
RX, TX, CTS, RTS as AF
RX, TX, CTS, RTS as AF
UART5
SPI2
MOSI, MISO, SCK, NSS as AF
3 compl. channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF
16b
16b
TIM1 / PWM
TIM8 / PWM
SPI3
MOSI, MISO, SCK, NSS as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
3 compl. Channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF
I2C1/SMBUS
I2C2/SMBUS
I2C3/SMBUS
I2C4/SMBUS
WWDG
2 channels,
1 compl. channel, BKIN as AF
16b
16b
16b
TIM15
TIM16
1 channel,
1 compl. channel, BKIN as AF
1 channel,
1 compl. channel, BKIN as AF
TIM17
bxCAN1
TX, RX as AF
RX, TX, CK,CTS,
RTS as AF
MOSI, MISO,
SCK, NSS as AF
smcard
irDA
USART1
SPI1
TIM6
TIM7
16b
16b
@VDDA
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
OUT, INN, INP
OUT, INN, INP
SAI1
SAI2
OpAmp1
OpAmp2
SDCKIN[7:0], SDDATIN[7:0],
SDCKOUT,SDTRIG as AF
DFSDM
DSI_D0 P/N
DSI_D1 P/N
DSI_CK P/N
DSI Host
VDD12DSI, VDDSI, VSSDSI
VCAPDSI
DSI_TE
@ VDDA
@ VDDA
INP, INN, OUT
INP, INN, OUT
COMP1
COMP2
DAC1
DAC2
LPUART1
LPTIM1
RX, TX, CTS, RTS as AF
IN1, IN2, OUT, ETR as AF
IN1, OUT, ETR as AF
ITF
Firewall
LPTIM2
DAC1_OUT
DAC2_OUT
MSv49327V2
Note:
AF: alternate function on I/O pins.
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STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
3
Functional overview
3.1
Arm® Cortex®-M4 core with FPU
®
®
®
The Arm Cortex -M4 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
the MCU implementation, with a reduced pin count and with low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
®
®
The Arm Cortex -M4 with FPU 32-bit RISC processor features an exceptional code-
®
efficiency, delivering the expected high-performance from an Arm core in a memory size
usually associated with 8-bit and 16-bit devices.
The processor supports a set of DSP instructions which allows an efficient signal processing
and a complex algorithm execution. Its single precision FPU speeds up the software
development by using metalanguage development tools to avoid saturation.
®
®
With its embedded Arm core, the STM32L4Rxxx family is compatible with all Arm tools
and software.
Figure 1 shows the general block diagram of the STM32L4Rxxx family devices.
3.2
Adaptive real-time memory accelerator (ART Accelerator)
The ART Accelerator is a memory accelerator that is optimized for the STM32 industry-
®
®
standard Arm Cortex -M4 processors. It balances the inherent performance advantage of
®
®
the Arm Cortex -M4 over Flash memory technologies, which normally requires the
processor to wait for the Flash memory at higher frequencies.
To release the processor near 150 DMIPS performance at 120 MHz, the accelerator
implements an instruction prefetch queue and a branch cache, which increases the
program’s execution speed from the Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from the Flash memory at a CPU frequency of up to 120 MHz.
3.3
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to eight protected areas, which can
be divided in up into eight subareas each. The protection area sizes range between 32
bytes and the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
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Functional overview
3.4
Embedded Flash memory
The STM32L4Rxxx devices feature 2 Mbytes of embedded Flash memory which is
available for storing programs and data.
The Flash interface features:
–
–
Single or dual bank operating modes
Read-while-write (RWW) in dual bank mode
This feature allows to perform a read operation from one bank while an erase or program
operation is performed to the other bank. The dual bank boot is also supported. Each bank
contains 256 pages of 4 or 8 Kbytes (depending on the read access width).
Flexible protections can be configured thanks to the option bytes:
• Readout protection (RDP) to protect the whole memory. Three levels of protection are
available:
– Level 0: no readout protection
– Level 1: memory readout protection; the Flash memory cannot be read from or written
to if either the debug features are connected or the boot in RAM or bootloader are
selected
– Level 2: chip readout protection; the debug features (Cortex-M4 JTAG and serial
wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
Table 3. Access status versus readout protection level and execution modes
Debug, boot from RAM or boot
User execution
Protection
level
from system memory (loader)
Area
Read
Write
Erase
Read
Write
Erase
1
2
1
2
1
2
1
2
1
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
No
N/A
Yes
N/A
Yes
N/A
No
No
N/A
No
No
N/A
No
Main
memory
System
memory
No
No
N/A
Yes
N/A
No
N/A
Yes
Yes
No
Yes
Option
bytes
No
N/A
N/A(1)
N/A
No(1)
N/A
Yes
Yes
Yes
Yes
N/A(1)
N/A
Yes(1)
Yes
Backup
registers
N/A
No
N/A
No
SRAM2
N/A
N/A
1. Erased when RDP change from Level 1 to Level 0.
•
Write protection (WRP): the protected area is protected against erasing and
programming:
–
–
In single bank mode, four areas can be selected with 8-Kbyte granularity.
In dual bank mode, two areas per bank can be selected with 4-Kbyte granularity.
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STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
•
Proprietary code readout protection (PCROP): a part of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only
and it can only be reached by the STM32 CPU as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited:
–
–
In single bank mode, two areas can be selected with 128-bit granularity.
In dual bank mode, one area per bank can be selected with 64-bit granularity.
An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or
not when the RDP protection is changed from Level 1 to Level 0.
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
•
•
•
Single error detection and correction
Double error detection
The address of the ECC fail can be read in the ECC register.
3.5
Embedded SRAM
The STM32L4R5xx, STM32L4R7xx and STM32L4R9xx devices feature 640 Kbytes of
embedded SRAM. This SRAM is split into three blocks:
•
•
192 Kbytes mapped at address 0x2000 0000 (SRAM1).
64 Kbytes located at address 0x1000 0000 with hardware parity check (SRAM2).
This memory is also mapped at address 0x2003 0000 offering a contiguous address
space with the SRAM1.
This block is accessed through the ICode/DCode buses for maximum performance.
These 64 Kbytes SRAM can also be retained in Standby mode.
The SRAM2 can be write-protected with 1 Kbyte granularity.
•
384 Kbytes mapped at address 0x2004 0000 - (SRAM3).
The memory can be accessed in read/write at CPU clock speed with 0 wait states.
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Functional overview
3.6
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, DMA2D,
SDMMC1, LCD-TFT and GFXMMU) and the slaves (Flash memory, RAM, FMC, OctoSPI,
AHB and APB peripherals). It also ensures a seamless and efficient operation even when
several high-speed peripherals work simultaneously.
Figure 2. Multi-AHB bus matrix
Cortex®-M4
with FPU
DMA1 DMA2 DMA2D LCD-TFT SDMMC1 GFXMMU
ICode
FLASH
2 MB
DCode
SRAM1
SRAM2
SRAM3
GFXMMU
AHB1
peripherals
AHB2
peripherals
FSMC
OCTOSPI1
OCTOSPI2
BusMatrix-S
MSv38490V1
3.7
Firewall
These devices embed a firewall which protects code sensitive and secure data from any
access performed by a code executed outside of the protected areas.
Each illegal access generates a reset which kills immediately the detected intrusion.
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STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
The main features of the firewall are the following:
•
Three segments can be protected and defined thanks to the firewall registers:
–
Code segment (located in Flash or SRAM1 if defined as executable protected
area)
–
–
Non-volatile data segment (located in Flash)
Volatile data segment (located in SRAM1)
•
•
The start address and the length of each segment are configurable:
–
–
–
Code segment: up to 2048 Kbytes with granularity of 256 bytes
Non-volatile data segment: up to 2048 Kbytes with granularity of 256 bytes
Volatile data segment: up to 192 Kbytes of SRAM1 with a granularity of 64 bytes
Specific mechanism implemented to open the firewall to get access to the protected
areas (call gate entry sequence)
•
•
Volatile data segment can be shared or not with the non-protected code
Volatile data segment can be executed or not depending on the firewall configuration
The Flash readout protection must be set to level 2 in order to reach the expected level of
protection.
3.8
Boot modes
At startup, a BOOT0 pin and an nBOOT1 option bit are used to select one of three boot
options:
•
•
•
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on
the value of a user option bit to free the GPIO pad if needed.
A Flash empty-check mechanism is implemented to force the boot from system Flash if the
first Flash memory location is not programmed and if the boot selection is configured to boot
from main Flash.
The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART, I2C, SPI, CAN or USB OTG FS in device mode through the DFU (device
firmware upgrade).
3.9
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator with polynomial value and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the Flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, which
can be ulteriorly compared with a reference signature generated at link-time and which can
be stored at a given memory location.
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Functional overview
3.10
Power supply management
3.10.1
Power supply schemes
The STM32L4x devices require a 1.71 V to 3.6 V V operating voltage supply. Several
DD
independent supplies can be provided for specific peripherals:
•
V
V
= 1.71 V to 3.6 V
DD
is the external power supply for the I/Os, the internal regulator and the system
DD
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
•
V
V
= 1.05 to 1.32 V
DD12
DD12
is the external power supply bypassing the internal regulator when connected to
an external SMPS. It is provided externally through VDD12 pins and only available on
packages with the external SMPS supply option. VDD12 does not require any external
decoupling capacitance and cannot support any external load.
•
•
V
V
= 1.62 V (ADCs/COMPs) / 1.8 V (DACs/OPAMPs) to 2.4 V (VREFBUF) to 3.6 V
is the external analog power supply for A/D converters, D/A converters, voltage
DDA
DDA
reference buffer, operational amplifiers and comparators. The V
independent from the V voltage and should preferably be connected to V when
these peripherals are not used.
voltage level is
DDA
DD
DD
VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. The
VDDUSB voltage level is independent from the VDD voltage and should preferably be
connected to VDD when the USB is not used.
•
•
VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage
level is independent from the VDD voltage and should preferably be connected to VDD
when PG[15:2] are not used.
•
•
•
•
VDDDSI is used to supply the DSI regulator and MIPI D-PHY. This supply must be
connected to the global VDD.
VCAPDSI pin is the output of DSI regulator (1.2 V) which must be connected externally
to VDD12DSI.
VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes
pins. An external capacitor of 2.2 uF must be connected on the VDD12DSI pin.
V
= 1.55 V to 3.6 V
BAT
V
is the power supply for RTC, external clock 32 kHz oscillator and backup registers
BAT
(through power switch) when V is not present.
DD
•
VREF-, VREF+
V
is the input reference voltage for ADCs and DACs. It is also the output of the
REF+
internal voltage reference buffer when enabled.
When V
When V
< 2 V V
≥ 2 V V
must be equal to V
.
DDA
DDA
DDA
REF+
REF+
must be between 2 V and V
.
DDA
V
can be grounded when ADC and DAC are not active.
REF+
The internal voltage reference buffer supports two output voltages, which are
configured with VRS bit in the VREFBUF_CSR register:
–
–
V
V
around 2.048 V. This requires V
equal to or higher than 2.4 V.
REF+
REF+
DDA
around 2.5 V. This requires V
equal to or higher than 2.8 V.
DDA
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STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
VREF- and VREF+ pins are not available on all packages. When not available, they are
bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disable (refer to datasheet for
packages pinout description).
V
must always be equal to V
.
REF-
SSA
An embedded linear voltage-regulator is used to supply the internal digital power V
.
CORE
V
is the power supply for digital peripherals, SRAM1, SRAM2 and SRAM3. The Flash
CORE
is supplied by V
and V
.
CORE
DD
Figure 3. STM32L4R5xx and STM32L4R7xx power supply overview
VDDA domain
1 x A/D converter
VDDA
2 x comparators
2 x D/A converters
2 x operational amplifiers
VSSA
Voltage reference buffer
VDDUSB
USB transceivers
VSS
VDDIO2 domain
VDDIO2
VDDIO2
I/O ring
V
SS
PG[15:2]
VDD domain
VDDIO1
I/O ring
VCORE domain
Reset block
Temp. sensor
Core
3 x PLL, HSI, MSI
SRAM1
SRAM2
SRAM3
Digital
Standby circuitry
(Wakeup logic,
IWDG)
VSS
VDD
VCORE
peripherals
Voltage regulator
Flash memory
Low voltage detector
Backup domain
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
VBAT
MSv49328V1
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Functional overview
Figure 4. STM32L4R5xxxP and STM32L4R7xxxP with external SMPS power supply
overview
VDDA domain
1 x A/D converter
VDDA
2 x comparators
2 x D/A converters
2 x operational amplifiers
VSSA
Voltage reference buffer
VDDUSB
USB transceivers
VSS
VDDIO2 domain
VDDIO2
VDDIO2
I/O ring
V
SS
PG[15:2]
VDD domain
VDDIO1
I/O ring
VCORE domain
Reset block
Temp. sensor
3 x PLL, HSI, MSI
Core
SRAM1
Standby circuitry
(Wakeup logic,
IWDG)
SRAM2
SRAM3
VSS
VDD
Digital
VCORE
Voltage regulator
peripherals
2x VDD12
Flash memory
Low voltage detector
Backup domain
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
VBAT
MSv49333V1
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Functional overview
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Figure 5. STM32L4R9xx power supply overview
VDDA domain
1 x A/D converter
VDDA
VSSA
2 x comparators
2 x D/A converters
2 x operational amplifiers
Voltage reference buffer
VDDUSB
VSS
USB transceivers
VDDIO2 domain
VDDIO2
VDDIO2
VSS
I/O ring
PG[15:2]
VDDDSI
VCAPDSI
DSI
voltage regulator
DSI PHY
VDD12DSI
VDD domain
VDDIO1
I/O ring
VCORE domain
Reset block
Temp. sensor
3 x PLL, HSI, MSI
Core
SRAM1
SRAM2
SRAM3
Digital
Standby circuitry
(Wakeup logic,
IWDG)
VSS
VDD
VCORE
peripherals
Voltage regulator
Flash memory
Low voltage detector
Backup domain
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
VBAT
MSv38488V1
During power-up and power-down phases, the following power sequence requirements
must be respected:
•
When V is below 1 V, other power supplies (V
remain below VDD +300 mV.
, V
, V
and V
) must
LCD
DD
DDA
DDIO2
DDUSB
•
•
When V is above 1 V, all power supplies are independent.
DD
During the power-down phase, V can temporarily become lower than other supplies
DD
only if the energy provided to the MCU remains below 1 mJ; this allows external
decoupling capacitors to be discharged with different time constants during the power-
down transient phase.
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Functional overview
Figure 6. Power-up/down sequence
V
3.6
(1)
VDDX
VDD
VBOR0
1
0.3
Power-on
Invalid supply area
Operating mode
Power-down
VDDX independent from VDD
time
VDDX < VDD + 300 mV
MSv47490V1
1. VDDX refers to any power supply among VDDA, VDDIO2, VDDUSB and VLCD.
3.10.2
Power supply supervisor
The STM32L4R5xx, STM32L4R7xx and STM32L4R9xx devices have an integrated ultra-
low-power Brownout reset (BOR) active in all modes (except for Shutdown mode). The BOR
ensures proper operation of the devices after power-on and during power-down. The
devices remain in reset mode when the monitored supply voltage V is below a specified
DD
threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The devices feature an embedded programmable voltage detector
(PVD) that monitors the V power supply and compares it to the VPVD threshold.
DD
An interrupt can be generated when V drops below the VPVD threshold and/or when V
DD
DD
is higher than the VPVD threshold. The interrupt service routine can then generate a
warning message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a peripheral voltage monitor which compares the
independent supply voltages V
, V
, V
with a fixed threshold in order to ensure
DDA DDUSB DDIO2
that the peripheral is in its functional supply range.
3.10.3
Voltage regulator
Two embedded linear voltage regulators supply most of the digital circuitries: the main
regulator (MR) and the low-power regulator (LPR).
•
•
The MR is used in the Run and Sleep modes and in the Stop 0 mode.
The LPR is used in Low-power run, Low-power sleep, Stop 1 and Stop 2 modes. It is
also used to supply the 64 Kbytes SRAM2 in standby with RAM2 retention.
•
Both regulators are in power-down while they are in standby and Shutdown modes: the
regulator output is in high impedance, and the kernel circuitry is powered down thus
inducing zero consumption.
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Functional overview
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
The ultra-low-power STM32L4Rxxx devices support dynamic voltage scaling to optimize its
power consumption in Run mode. The voltage from the main regulator that supplies the
logic (VCORE) can be adjusted according to the system’s maximum operating frequency.
The main regulator operates in the following ranges:
•
•
•
Range 1 boost mode with the CPU running at up to 120 MHz.
Range 1 normal mode with the CPU running at up to 80 MHz.
Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also
limited to 26 MHz.
The VCORE can be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode.
•
Low-power run mode with the CPU running at up to 2 MHz. Peripherals with
independent clock can be clocked by the HSI16.
When the MR is in use, the device with the external SMPS option allows to force an external
supply on the VDD12 supply pins.
V
CORE
When V
is forced by an external source and that it is higher than the output of the
DD12
internal LDO, the current is taken from this external supply and the overall power efficiency
is significantly improved if using an external step down DC/DC converter.
Note:
The USB and DSIHOST can only be used when the main regulator is in range1 boost mode.
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3.10.4
Low-power modes
The ultra-low-power STM32L4Rxxx devices support seven low-power modes to achieve the best compromise between low-power
consumption, short startup time, available peripherals and available wake-up sources. Table 4 shows the related STM32L4Rxxx
modes overview.
Table 4. STM32L4R5xx modes overview
Mode
Regulator(1)
CPU
Flash
SRAM
Clocks
DMA & Peripherals(2)
Wakeup source
Range 1
All
SMPM rage 2
High
Run
LPRun
Sleep
Yes
ON(3)
ON
Any
N/A
Range 2
All except
OTG_FS, RNG, LCD-TFT
SMPS range 2
Low
Any except
PLL
All except
OTG_FS, RNG, LCD-TFT
LPR
Yes
No
No
ON(3)
ON(3)
ON(3)
ON
N/A
Range 1
All
SMPM rage 2
High
ON(4)
Any
Any interrupt or event
Any interrupt or event
Range 2
All except
OTG_FS, RNG, LCD-TFT
SMPS range 2
Low
Any
LPSleep
LPR
ON(4)
All except OTG_FS, RNG, LCD-TFT
except PLL
Table 4. STM32L4R5xx modes overview (continued)
Mode
Regulator(1)
CPU
Flash
SRAM
Clocks
DMA & Peripherals(2)
Wakeup source
BOR, PVD, PVM
RTC, IWDG
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
Range 1
COMPx (x=1,2)
DACx (x=1,2)
OPAMPx (x=1,2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
***
COMPx (x=1..2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
OTG_FS(8)
LSE
LSI
Stop 0(5)
No
Off
ON
Range 2
All other peripherals are frozen
BOR, PVD, PVM
RTC, IWDG
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1,2)
DACx (x=1,2)
OPAMPx (x=1,2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
***
COMPx (x=1..2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
OTG_FS(8)
LSE
LSI
Stop 1
LPR
No
Off
ON
All other peripherals are frozen
Table 4. STM32L4R5xx modes overview (continued)
Mode
Regulator(1)
CPU
Flash
SRAM
Clocks
DMA & Peripherals(2)
Wakeup source
BOR, PVD, PVM
RTC, IWDG
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
I2C3(7)
COMPx (x=1..2)
I2C3(7)
LPUART1(6)
LSE
LSI
Stop 2
LPR
No
Off
ON
LPTIM1
LPUART1(6)
***
LPTIM1
All other peripherals are frozen
LPR
OFF
SRAM2 ON
BOR, RTC, IWDG
***
Reset pin
5 I/Os (WKUPx)(9)
LSE
LSI
Powered
Off
All other peripherals are powered off
***
Standby
Off
Off
Powered
Off
BOR, RTC, IWDG
I/O configuration can be floating, pull-
up or pull-down
RTC
***
Reset pin
5 I/Os (WKUPx)(9)
RTC
Powered
Off
Powered
Off
All other peripherals are powered off
***
Shutdown
OFF
LSE
I/O configuration can be floating, pull-
up or pull-down(10)
1. LPR means Main regulator is OFF and Low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.
4. The SRAM1, SRAM2 and SRAM3 clocks can be gated on or off independently.
5. SMPS mode can be used in Stop 0 mode, but no significant power gain can be expected.
6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. OTG_FS wakeup by resume from suspend and attach detection protocol event.
9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.
Functional overview
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
By default, the microcontroller is in Run mode after a system or a power reset. It is up to the
user to select one of the low-power modes described below:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Low-power run mode
This mode is achieved with VCORE supplied by the low-power regulator to minimize
the regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.
•
•
Low-power sleep mode
This mode is entered from the Low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the Low-
power run mode.
Stop 0, Stop 1 and Stop 2 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI
RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wake-up capability can enable the HSI16 RC during Stop mode
to detect their wake-up condition.
Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,
most of the VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, allowing a very fast wakeup time but with much higher consumption.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI
up to 48 MHz or HSI16, depending on software configuration.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL,
the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The Brownout reset (BOR) always remains active in Standby mode.
The state of each I/O during Standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1, SRAM3 and register contents are lost except for
registers in the Backup domain and Standby circuitry. Optionally, SRAM2 can be
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STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Functional overview
retained in Standby mode, supplied by the low-power regulator (standby with RAM2
retention mode).
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).
The system clock after wakeup is MSI up to 8 MHz.
•
Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off so that the VCORE domain is powered off. The PLL, the
HSI16, the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2, SRAM3 and register contents are lost except for registers in the
Backup domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).
The system clock after wakeup is MSI at 4 MHz.
DS12023 Rev 5
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65
Functional overview
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
Table 5. Functionalities depending on the working mode
Stop 0/1 Stop 2
Standby Shutdown
Low-
Low-
Peripheral
Run
Sleep power power
VBAT
-
-
-
-
run
sleep
CPU
Y
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Flash memory
(2 Mbytes)
O(2)
O(2)
O(2)
O(2)
SRAM1
(192 Kbytes)
Y
Y
Y
Y(3)
Y(3)
Y(3)
Y
Y
Y
Y(3)
Y(3)
Y(3)
Y
Y
Y
-
-
-
Y
Y
-
-
-
-
O(4)
-
-
-
-
-
-
-
-
-
-
-
-
-
SRAM2 (64 Kbytes)
SRAM3
(384 Kbytes)
Y(3)
FSMC
O
O
Y
O
O
Y
O
O
Y
O
O
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OctoSPIs
Backup Registers
Y
Y
Y
Y
Y
Brownout reset
(BOR)
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
-
-
-
-
-
-
-
Programmable
Voltage Detector
(PVD)
O
O
O
O
O
O
O
O
Peripheral Voltage
Monitor (PVMx;
x=1,2,3,4)
O
O
O
O
O
O
O
O
-
-
-
-
-
DMA
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DMA2D
High speed internal
(HSI16)
(5)
(5)
-
O
O
O
O
O
O
O
-
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Oscillator HSI48
-
-
High speed external
(HSE)
O
O
-
O
O
-
Low speed internal
(LSI)
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
O
O
-
-
-
-
-
-
O
-
-
-
-
-
-
O
-
Low speed external
(LSE)
Multi speed internal
(MSI)
Clock security
system (CSS)
-
-
-
-
-
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DS12023 Rev 5
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Functional overview
(1)
Table 5. Functionalities depending on the working mode (continued)
Stop 0/1 Stop 2 Standby Shutdown
Low-
Low-
Peripheral
Run
Sleep power power
VBAT
-
-
-
-
run
sleep
Clock security
system on LSE
O
O
3
O
O
3
O
O
3
O
O
3
O
O
3
O
O
O
O
O
O
O
O
O
3
O
O
O
-
-
-
RTC / Auto wakeup
O
3
O
3
O
O
O
3
Number of RTC
Tamper pins
Camera interface
LCD-TFT
O
O
O
O
O
-
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GFXMMU
O
O
O
-
O
-
-
DSIHOST
O
O
-
USB OTG FS
O(8)
O(8)
-
-
O
USARTx
(x=1,2,3,4,5)
O
O
O
O
O
O
O
O
O(6) O(6)
-
-
-
-
-
-
-
-
-
-
-
-
Low-power UART
(LPUART)
O(6) O(6) O(6) O(6)
O(7) O(7)
O(7) O(7) O(7) O(7)
I2Cx (x=1,2,4)
I2C3
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPIx (x=1,2,3)
CAN(x=1,2)
SDMMC1
-
-
-
-
-
-
-
-
-
-
-
-
SAIx (x=1,2)
DFSDM1
-
-
-
-
-
-
-
-
ADC
-
-
-
-
DACx (x=1,2)
VREFBUF
O
O
O
O
-
-
-
-
-
-
-
OPAMPx (x=1,2)
COMPx (x=1,2)
Temperature sensor
Timers (TIMx)
-
-
-
O
-
O
-
O
-
-
-
-
-
Low-power timer 1
(LPTIM1)
O
O
O
O
O
O
O
O
O
O
O
O
O
-
O
-
-
-
-
-
-
-
-
-
-
-
Low-power timer 2
(LPTIM2)
DS12023 Rev 5
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65
Functional overview
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
Table 5. Functionalities depending on the working mode (continued)
Stop 0/1
Stop 2
Standby Shutdown
Low-
Low-
Peripheral
Run
Sleep power power
VBAT
-
-
-
-
run
sleep
Independent
watchdog (IWDG)
O
O
O
O
O
O
O
O
O
O
-
-
-
Window watchdog
(WWDG)
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SysTick timer
-
-
-
-
Touch sensing
controller (TSC)
Random number
generator (RNG)
O(8)
O
O(8)
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CRC calculation
unit
O
O
-
-
5
5
(9)
(11)
GPIOs
O
O
O
O
O
O
O
O
pins
pins
-
(10)
(10)
1. Legend: Y = yes (enable). O = optional (disable by default, can be enabled by software). - = not available.
Gray cells highlight the wakeup capability in each mode.
2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAM clock can be gated on or off. In Stop 2 mode, the content of SRAM3 is preserved or not depending on the
RRSTP bit in PWR_CR1 register.
4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling range 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from standby/shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
3.10.5
Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
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DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Functional overview
3.10.6
VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from V when there is no external battery and when an external
DD
supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup
registers. Three anti-tamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when V is not present. An internal VBAT
DD
battery charging circuit is embedded and can be activated when V is present.
DD
Note:
When the microcontroller is supplied from VBAT, neither external interrupts nor RTC
alarm/events exit the microcontroller from the VBAT operation.
3.11
Interconnect matrix
Several peripherals have direct connections between them, which allow autonomous
communication between them and support the saving of CPU resources (thus power supply
consumption). In addition, these hardware connections allow fast and predictable latency.
Depending on the peripherals, these interconnections can operate in Run, Sleep, Low-
power run and Sleep, Stop 0, Stop 1 and Stop 2 modes. See Table 6 for more details.
Table 6. STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
peripherals interconnect matrix
Interconnect
destination
Interconnect source
Interconnect action
TIMx
Timers synchronization or chaining
Conversion triggers
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
ADC
DACx
TIMx
DFSDM1
DMA
Memory to memory transfer trigger
Comparator output blanking
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
COMPx
TIM1, 8
TIM2, 3
Timer input channel, trigger, break from
analog signals comparison
Y
Y
Y
Y
Y
Y
Y
Y
-
-
COMPx
Low-power timer triggered by analog
signals comparison
Y
LPTIMERx
Y
(1)
ADCx
RTC
TIM1, 8
TIM16
Timer triggered by analog watchdog
Timer input channel from RTC events
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
Low-power timer triggered by RTC alarms
or tampers
Y
LPTIMERx
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
(1)
TIM2
All clocks sources (internal
and external)
Clock source used as input channel for
RC measurement and trimming
-
TIM15, 16, 17
DS12023 Rev 5
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65
Functional overview
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Table 6. STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
peripherals interconnect matrix (continued)
Interconnect
Interconnect source
Interconnect action
destination
USB
TIM2
Timer triggered by USB SOF
Y
Y
Y
Y
-
-
-
-
-
-
-
CSS
CPU (hard fault)
RAM (parity error)
Flash memory (ECC error)
COMPx
TIM1,8
Timer break
Y
Y
TIM15,16,17
PVD
DFSDM1 (analog
watchdog, short circuit
detection)
TIMx
External trigger
External trigger
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
LPTIMERx
Y
(1)
GPIO
ADC
DACx
Conversion external trigger
Y
Y
Y
Y
-
-
DFSDM1
1. LPTIM1 only.
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DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Functional overview
3.12
Clocks and startup
The clock controller (see Figure 7) distributes the clocks coming from the different
oscillators to the core and to the peripherals. It also manages the clock gating for low-power
modes and ensures the clock robustness. It features:
•
Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
•
•
•
Safe clock switching: clock sources can be changed safely on the fly in Run mode
through a configuration register.
Clock management: to reduce the power consumption, the clock controller can stop
the clock to the core, individual peripherals or memory.
System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
–
4 to 48 MHz high-speed external crystal or ceramic resonator (HSE), that can
supply a PLL. The HSE can also be configured in bypass mode for an external
clock. The HSE must be available when the DSI-HOST peripheral is used.
–
–
16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the
USB device, saving the need of an external high-speed crystal (HSE). The MSI
can supply a PLL.
–
System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 120 MHz.
•
•
RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48)can
be used to drive the USB, the SDMMC or the RNG peripherals. This clock can be
output on the MCO.
Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the real-time clock:
–
–
32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy.
•
Peripheral clock sources: several peripherals (USB, SDMMC, RNG, SAI, USARTs,
I2Cs, LPTimers, ADC) have their own independent clock whatever the system clock.
Three PLLs, each having three independent outputs allowing the highest flexibility, can
generate independent clocks for the ADC, the USB/SDMMC/RNG, the two SAIs, LCD-
TFT and DSI-HOST. When using DSI-HOST peripheral, the high-speed external crystal
(HSE) must be available.
•
•
Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI16 and a software
DS12023 Rev 5
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65
Functional overview
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
interrupt is generated if enabled. LSE failure can also be detected and generated an
interrupt.
•
Clock-out capability:
–
MCO (microcontroller clock output): it outputs one of the internal clocks for
external use by the application
–
LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
(except VBAT).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 120 MHz.
40/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Functional overview
Figure 7. Clock tree
to IWDG
to RTC
LSI RC 32 kHz
LSCO
OSC32_OUT
LSE OSC
32.768 kHz
/32
OSC32_IN
MCO
to PWR
to AHB bus, core, memory and DMA
FCLK Cortex free running clock
to Cortex system timer
LSE
LSI
MSI
HSI16
HSE
/ 1→16
HCLK
AHB PRESC
/ 1,2,..512
SYSCLK
PLLCLK
HSI48
/ 8
Clock
source
control
PCLK1
to APB1 peripherals
APB1 PRESC
/ 1,2,4,8,16
OSC_OUT
OSC_IN
HSE OSC
4-48 MHz
HSE
x1 or x2
to TIMx
x=2..7
MSI
HSI16
Clock
detector
SYSCLK
LSE
HSI16
to USARTx
X=2..5
to LPUART1
SYSCLK
HSI RC
16 MHz
HSI16
MSI RC
to I2Cx
SYSCLK
100 kHz – 48 MHz
RC 48 MHz
x=1,2,3,4
LSI
LSE
to LPTIMx
x=1,2
HSI16
MSI
MSI
HSI16
HSE
PLL
/ M
OCTOSPI clock
CRS clock
PLLSAI3CLK
/ P
/ Q
/ R
PLL48M1CLK
PLLCLK
PCLK2
APB2 PRESC
/ 1,2,4,8,16
to APB2 peripherals
HSI16
x1 or x2
/ M
to TIMx
PLLSAI1
x=1,8,15,16,17
PLLSAI1CLK
/ P
/ Q
/ R
PLL48M2CLK
PLLADC1CLK
LSE
HSI16
to
SYSCLK
USART1
SDMMC clock
MSI
HSI16
48 MHz clock to USB, RNG
SYSCLK
to ADC
DSIHOST
byte lane clock
≤ 20 MHz
HSE
DSI
PLL
DSI - PHY
≤ 62.5 MHz
< 62.5 MHz
DSIHOST
rxclkesc clock
MSI
HSI16
/ M
PLLSAI2
PLLSAI2CLK
PLLDSICLK
PLLLCDCLK
/ P
/ Q
/ R
DFSDM
audio clock
to SAI1
HSI16
PLLSAI2DIVR
LTDC clock
to SAI2
SAI1_EXTCLK
SAI2_EXTCLK
MSv38434V7
DS12023 Rev 5
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65
Functional overview
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
3.13
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.14
Direct memory access controller (DMA)
The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features
implementation.
Direct memory access (DMA) is used in order to provide a high-speed data transfer
between peripherals and memory as well as from memory to memory. Data can be quickly
moved by DMA without any CPU actions. This keeps the CPU resources free for other
operations.
The two DMA controllers have 14 channels in total, each one dedicated to manage memory
access requests from one or more peripherals. Each controller has an arbiter for handling
the priority between DMA requests.
The DMA supports:
•
14 independently configurable channels (requests)
–
Each channel is connected to a dedicated hardware DMA request, a software
trigger is also supported on each channel. This configuration is done by software.
•
•
Priorities between requests from channels of one DMA are both software
programmable (4 levels: very high, high, medium, low) or hardware programmable in
case of equality (request 1 has priority over request 2, etc.)
Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data size
•
•
Support for circular buffer management
3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error)
logically ORed together in a single interrupt request for each channel
•
•
•
•
Memory-to-memory transfer
Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers
Access to Flash, SRAM, APB and AHB peripherals as source and destination
Programmable number of data to be transferred: up to 65536
Table 7. DMA implementation
DMA features
DMA1
7
DMA2
7
Number of regular channels
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3.15
DMA request router (DMAMux)
When a peripheral indicates a request for DMA transfer by setting its DMA request line, the
DMA request is pending until it is served and the corresponding DMA request line is reset.
The DMA request router allows to route the DMA control lines between the peripherals and
the DMA controllers of the product.
An embedded multi-channel DMA request generator can be considered as one of such
peripherals. The routing function is ensured by a multi-channel DMA request line
multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or
synchronously with events on synchronization inputs.
For simplicity, the functional description is limited to DMA request lines. The other DMA
control lines are not shown in figures or described in the text. The DMA request generator
produces DMA requests following events on DMA request trigger inputs.
3.16
Chrom-ART Accelerator (DMA2D)
Chrom-ART Accelerator (DMA2D) is a graphic accelerator that offers an advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
•
•
•
•
Rectangle filling with a fixed color
Rectangle copy
Rectangle copy with pixel format conversion
Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4 bpp color mode up to 32 bpp
direct color. It embeds a dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
3.17
Chrom-GRC (GFXMMU)
The Chrom-GRC (GFXMMU) is a graphical oriented memory management unit aimed to:
•
•
Optimize memory usage according to the display shape
Manage packing/unpacking for 24 bpp frame buffers
The Chrom-GRC features:
•
•
•
•
•
•
•
•
Fully programmable display shape to physically store only the visible pixel
Up to four virtual buffers
Each virtual buffer have 4096 bytes per line and 1024 lines
Each virtual buffer can be physically mapped to any system memory
24 bpp packing unit to store unpacked 24bpp data in a packed 24 bpp
Packing/un-packing management per buffer
Interrupt in case of buffer overflow (1 per buffer)
Interrupt in case of memory transfer error
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3.18
Interrupts and events
3.18.1
Nested vectored interrupt controller (NVIC)
The STM32L4R5xx, STM32L4R7xx and STM32L4R9xxdevices embed a nested vectored
interrupt controller which is able to manage 16 priority levels, and to handle up to 94
®
maskable interrupt channels plus the 16 interrupt lines of the Cortex -M4.
The NVIC benefits are the following:
•
•
•
•
•
•
•
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.18.2
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 36 edge detector lines used to generate
interrupt/event requests and to wake-up the system from the Stop mode. Each external line
can be independently configured to select the trigger event (rising edge, falling edge, both)
and can be masked independently.
A pending register maintains the status of the interrupt requests. The internal lines are
connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an
external line with a pulse width shorter than the internal clock period. Up to 114 GPIOs can
be connected to the 16 external interrupt lines.
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3.19
Analog-to-digital converter (ADC)
The device embeds a successive approximation analog-to-digital converters with the
following features:
•
•
12-bit native resolution, with built-in calibration
5.33 Msps maximum conversion rate with full resolution
–
–
Down to 18.75 ns sampling time
Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit
resolution)
•
•
Up to 16 external channels
5 internal channels: internal reference voltage, temperature sensor, VBAT/3, DAC1 and
DAC2 outputs
•
One external reference pin is available on some package, allowing the input voltage
range to be independent from the power supply
•
•
Single-ended and differential mode inputs
Low-power design
–
Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
–
Dual clock domain architecture: ADC speed independent from CPU frequency
•
Highly versatile digital interface
–
Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
–
Each ADC support multiple trigger inputs for synchronization with on-chip timers
and external signals
–
–
–
–
–
Results stored into a data register or in RAM with DMA controller support
Data pre-processing: left/right alignment and per channel offset compensation
Built-in oversampling unit for enhanced SNR
Channel-wise programmable sampling time
Analog watchdog for automatic voltage monitoring, generating interrupts and
trigger for selected timers
–
Hardware assistant to prepare the context of the injected channels to allow fast
context switching
3.19.1
Temperature sensor
The temperature sensor (TS) generates a voltage V that varies linearly with temperature.
TS
The temperature sensor is internally connected to the ADC1_IN17 input channels which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
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Table 8. Temperature sensor calibration values
Calibration value name Description Memory address
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
TS_CAL1
TS_CAL2
0x1FFF 75A8 - 0x1FFF 75A9
0x1FFF 75CA - 0x1FFF 75CB
VDDA = VREF+ = 3.0 V (± 10 mV)
TS ADC raw data acquired at a
temperature of 130 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
3.19.2
Internal voltage reference (V
)
REFINT
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN0 input
channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
Table 9. Internal voltage reference calibration values
Calibration value name
Description
Memory address
Raw data acquired at a
VREFINT
temperature of 30 °C (± 5 °C),
0x1FFF 75AA - 0x1FFF 75AB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.19.3
VBAT battery voltage monitoring
This embedded hardware enables the application to measure the V
battery voltage using
BAT
the internal ADC channel ADC1_IN18. As the V
voltage may be higher than the VDDA,
BAT
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 3. As a consequence, the converted digital value is one third of the V
voltage.
BAT
3.20
Digital to analog converter (DAC)
Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in inverting configuration.
This digital interface supports the following features:
•
•
•
•
•
•
•
Up to two DAC output channels
8-bit or 12-bit output mode
Buffer offset calibration (factory and user trimming)
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
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•
•
•
•
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
Sample and hold low-power mode, with internal or external capacitor
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.
3.21
Voltage reference buffer (VREFBUF)
The STM32L4Rxxx devices embed a voltage reference buffer which can be used as voltage
reference for ADC, DACs and also as voltage reference for external components through
the VREF+ pin.
The internal voltage reference buffer supports two voltages:
•
•
2.048 V
2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.
Figure 8. Voltage reference buffer
VREFBUF
VDDA DAC, ADC
Bandgap
+
-
VREF+
Low frequency
cut-off capacitor
100 nF
MSv40197V1
3.22
Comparators (COMP)
The STM32L4Rxxx devices embed two rail-to-rail comparators with programmable
reference voltage (internal or external), hysteresis and speed (low speed for low-power) and
with selectable output polarity.
The reference voltage can be one of the following:
•
•
•
External I/O
DAC output channels
Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers
and can also be combined into a window comparator.
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3.23
Operational amplifier (OPAMP)
The STM32L4Rxxx devices embed two operational amplifiers with external or internal
follower routing and PGA capability.
The operational amplifier features:
•
•
•
•
Low input bias current
Low offset voltage
Low-power mode
Rail-to-rail input
3.24
Touch sensing controller (TSC)
The touch sensing controller provides a simple solution to add capacitive sensing
functionality to any application. A capacitive sensing technology is able to detect finger
presence near an electrode that is protected from direct touch by a dielectric (glass, plastic
or other). The capacitive variation introduced by the finger (or any conductive object) is
measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
The main features of the touch sensing controller are the following:
•
•
•
Proven and robust surface charge transfer acquisition principle
Supports up to 24 capacitive sensing channels
Up to 3 capacitive sensing channels can be acquired in parallel offering a very good
response time
•
•
•
•
•
•
•
•
Spread spectrum feature to improve system robustness in noisy environments
Full hardware management of the charge transfer acquisition sequence
Programmable charge transfer frequency
Programmable sampling capacitor I/O pin
Programmable channel I/O pin
Programmable max count value to avoid long acquisition when a channel is faulty
Dedicated end of acquisition and max count error flags with interrupt capability
One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
components
•
•
Compatible with proximity, touchkey, linear and rotary touch sensor implementation
Designed to operate with STMTouch touch sensing firmware library
Note:
The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.
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3.25
LCD-TFT controller (LTDC)
The LCD-TFT display controller provides a 24-bit parallel digital RGB (red, green, blue) and
delivers all signals to interface directly to a broad range of LCD and TFT panels with the
following features:
•
•
•
•
•
•
•
Two displays layers with dedicated FIFO (64 x 32-bit)
Color look-up table (CLUT) up to 256 colors (256 x 24-bit) per layer
Up to 8 input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to four programmable interrupt events
3.26
DSI Host (DSIHOST)
®
The DSI Host is a dedicated IP that interfaces with the MIPI DSI compliant displays. It
includes a dedicated video interface internally connected to the LTDC and a generic APB
interface that can be used to transmit information to the display.
The interfaces are as follows:
•
•
•
LTDC interface:
–
Used to transmit information in Video Mode, in which the transfers from the host
processor to the peripheral take the form of a real-time pixel stream (DPI)
–
Used to transmit information in full bandwidth in the Adapted Command Mode
(DBI) through a custom mode
APB slave interface:
–
Allows the transmission of generic information in Command mode, and follows a
proprietary register interface
–
Can operate concurrently with either LTDC interface in either Video Mode or
Adapted Command Mode
Video mode pattern generator:
–
Allows the transmission of horizontal/vertical color bar and D-PHY BER testing
pattern without any kind of stimuli
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The DSI Host main features are:
®
•
•
•
Compliant with MIPI Alliance standards
®
Interface with MIPI D-PHY
®
Supports all commands defined in the MIPI Alliance specification for DCS:
–
–
Transmission of all Command mode packets through the APB interface
Transmission of commands in low-power and high-speed during Video Mode
•
•
•
•
•
•
•
•
Supports up to two D-PHY data lanes
Bidirectional communication and escape mode support through data lane 0
Supports non-continuous clock in D-PHY clock lane for additional power saving
Supports Ultra Low-Power mode with PLL disabled
ECC and Checksum capabilities
Support for end of transmission packet (EoTp)
Fault recovery schemes
Configurable selection of system interfaces:
–
–
–
AMBA APB for control and optional support for generic and DCS commands
Video Mode interface through LTDC
Adapted command mode interface through LTDC
•
Independently programmable virtual channel ID in
–
–
–
Video mode
Adapted command mode
APB Slave
Video Mode interfaces features:
•
LTDC interface color coding mappings into 24-bit interface:
–
–
–
16-bit RGB, configurations 1, 2 and 3
18-bit RGB, configurations 1 and 2
24-bit RGB
•
•
Programmable polarity of all LTDC interface signals
Maximum resolution is limited by available DSI physical link bandwidth:
–
–
Number of lanes: 2
Maximum speed per lane: 500 Mbps
Adapted interface features:
•
Support for sending large amounts of data through the memory_write_start (WMS) and
memory_write_continue (WMC) DCS commands
•
LTDC interface color coding mappings into 24-bit interface:
–
–
–
16-bit RGB, configurations 1, 2 and 3
18-bit RGB, configurations 1 and 2
24-bit RGB
Video mode pattern generator:
•
•
Vertical and horizontal color bar generation without LTDC stimuli
BER pattern without LTDC stimuli
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3.27
Digital filter for sigma-delta modulators (DFSDM)
The STM32L4Rxxx devices embed one DFSDM with four digital filters modules and eight
external input serial channels (transceivers) or alternately eight internal parallel inputs
support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to the
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs).
The DFSDM can also interface the PDM (pulse density modulation) microphones and
perform PDM to PCM conversion and filtering in hardware. The DFSDM features optional
parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into
DFSDM).
The DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators) and the DFSDM digital filter modules perform digital processing according to
the user’s selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
•
8 multiplexed input digital serial channels:
–
–
–
–
–
Configurable SPI interface to connect various SD modulator(s)
Configurable Manchester coded 1 wire interface support
PDM (pulse density modulation) microphone input support
Maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
Clock output for SD modulator(s): 0..20 MHz
•
•
Alternative inputs from 8 internal digital parallel channels (up to 16-bit input resolution):
Internal sources: device memory data streams (DMA)
–
4 digital filter modules with adjustable digital signal processing:
x
–
–
Sinc filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
Integrator: oversampling ratio (1..256)
•
•
•
•
Up to 24-bit output data resolution, signed output data format
Automatic data offset correction (offset stored in register by user)
Continuous or single conversion
Start-of-conversion triggered by:
–
–
–
–
Software trigger
Internal timers
External events
Start-of-conversion synchronously with first digital filter module (DFSDM0)
•
•
Analog watchdog feature:
–
–
–
–
Low value and high-value data threshold registers
Dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
Input from final output data or from selected input digital serial channels
Continuous monitoring independently from standard conversion
Short circuit detector to detect saturated analog input values (bottom and top range):
–
–
Up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
Monitoring continuously each input serial channel
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•
•
Break signal generation on analog watchdog event or on short circuit detector event
Extremes detector:
–
–
Storage of minimum and maximum values of final conversion data
Refreshed by software
•
•
DMA capability to read the final conversion data
Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
•
“Regular” or “injected” conversions:
–
“Regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions
–
“Injected” conversions for precise timing and with high conversion priority
3.28
3.29
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
Digital camera interface (DCMI)
The STM32L4Rxxx devices embed a camera interface that can connect with any camera
modules and CMOS sensors through an 8-bit to 14-bit parallel interface in order to receive
video data.
The camera interface can sustain a data transfer rate up to 54 Mbytes/s at 54 MHz. It
features:
•
•
•
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication of 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
•
Supports continuous mode or snapshot (a single frame) mode
Capability to automatically crop the image.
3.30
Timers and watchdogs
The STM32L4Rxxx devices include two advanced control timers, up to nine general-
purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick
timer.
The Table 10 below compares the features of the advanced control, general-purpose and
basic timers.
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Table 10. Timer feature comparison
DMA
request
generation channels
Capture/
compare
Counter
resolution
Counter
type
Prescaler
factor
Complementary
outputs
Timer type
Timer
Any integer
between 1
and 65536
Advanced
control
Up, down,
Up/down
TIM1, TIM8
TIM2, TIM5
TIM3, TIM4
TIM15
16-bit
32-bit
16-bit
16-bit
16-bit
16-bit
Yes
Yes
Yes
Yes
Yes
Yes
4
4
4
2
1
0
3
No
No
1
Any integer
between 1
and 65536
General-
purpose
Up, down,
Up/down
Any integer
between 1
and 65536
General-
purpose
Up, down,
Up/down
Any integer
between 1
and 65536
General-
purpose
Up
Up
Up
Any integer
between 1
and 65536
General-
purpose
TIM16, TIM17
TIM6, TIM7
1
Any integer
between 1
and 65536
Basic
No
3.30.1
Advanced-control timer (TIM1, TIM8)
The advanced-control timers can each be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted dead-
times. They can also be seen as complete general-purpose timers.
The four independent channels can be used for:
•
•
•
Input capture
Output compare
PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
•
One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in
Section 3.30.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
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3.30.2
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17)
There are up to seven synchronizable general-purpose timers embedded in the
STM32L4Rxxx devices (see Table 10 for differences).
Each general-purpose timer can be used to generate PWM outputs, or act as a simple time
base.
•
TIM2, TIM3, TIM4 and TIM5
They are full-featured general-purpose timers:
–
–
TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler
TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other general-
purpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
TIM15, 16 and 17
•
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–
–
TIM15 has two channels and one complementary channel
TIM16 and TIM17 have one channel and one complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.30.3
3.30.4
Basic timers (TIM6 and TIM7)
The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
Low-power timer (LPTIM1 and LPTIM2)
The STM32L4Rxxx devices embed two low-power timers. These timers have an
independent clock and are running in Stop mode if they are clocked by LSE, LSI or an
external clock. They are able to wakeup the system from Stop mode.
LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 mode.
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This low-power timer supports the following features:
•
•
•
•
•
•
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous/ one shot mode
Selectable software/hardware input trigger
Selectable clock source
–
–
Internal clock sources: LSE, LSI, HSI16 or APB clock
External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
•
•
Programmable digital glitch filter
Encoder mode (LPTIM1 only).
3.30.5
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.30.6
3.30.7
System window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
•
•
•
•
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source
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3.31
Real-time clock (RTC) and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
•
•
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
Two programmable alarms
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock
•
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
•
•
Three anti-tamper detection pins with programmable filter
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the V supply when present or from the VBAT pin.
DD
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from standby or Shutdown mode.
The RTC clock sources can be:
•
•
•
•
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator (LSE)
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE) divided by 32
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (alarm, wake-up timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.
3.32
Inter-integrated circuit interface (I2C)
The device embeds four I2C. Refer to Table 11: I2C implementation for the features
implementation.
2
The I C bus interface handles communications between the microcontroller and the serial
2
2
I C bus. It controls all I C bus-specific sequencing, protocol, arbitration and timing.
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Functional overview
The I2C peripheral supports:
•
I2C-bus specification and user manual rev. 5 compatibility:
–
–
–
–
–
–
–
Slave and master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
•
System management bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (packet error checking) generation and verification with ACK
control
–
–
Address resolution protocol (ARP) support
SMBus alert
TM
•
•
Power system management protocol (PMBus ) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 7: Clock tree
•
•
•
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
Table 11. I2C implementation
I2C features(1)
I2C1
I2C2
I2C3
I2C4
Standard-mode (up to 100 kbit/s)
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
Fast-mode (up to 400 kbit/s)
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)
Programmable analog and digital noise filters
SMBus/PMBus hardware support
Independent clock
Wakeup from Stop 0, Stop 1 mode on address match
Wakeup from Stop 2 mode on address match
1. X: supported
DS12023 Rev 5
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65
Functional overview
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
3.33
Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32L4Rxxx devices have three embedded universal synchronous receiver
transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver
transmitters (UART4, UART5).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN master/slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 driver enable. They are able to communicate at speeds of up to
10 Mbit/s.
The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant)
and an SPI-like communication capability.
All USART have a clock domain independent from the CPU clock, allowing the USARTx
(x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 200 Kbaud. The
wake up events from Stop mode are programmable and can be:
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 12. USART/UART/LPUART features
USART modes/features(1)
USART1 USART2 USART3 UART4 UART5 LPUART1
Hardware flow control for modem
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
X
X
X
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
X
X
X
-
X
X
X
X
-
X
X
X
-
X
X
X
-
X
X
X
Smartcard mode
X
-
-
-
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
X
X
X
X
X
-
X
X
X
X
X
-
X
-
X
X
-
Dual clock domain
X
X
X
X
-
Wakeup from Stop 0 / Stop 1 modes
Wakeup from Stop 2 mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver enable
X
-
X
X
X
X
X
X
X
X
X
X
X (4 modes)
X
-
-
X
X
X
X
X
LPUART/USART data length
1. X = supported.
7, 8 and 9 bits
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STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Functional overview
3.34
Low-power universal asynchronous receiver transmitter
(LPUART)
The STM32L4Rxxx devices embed one low-power UART. The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half-
duplex single-wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop
mode are programmable and can be:
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
The LPUART interface can be served by the DMA controller.
3.35
3.36
Serial peripheral interface (SPI)
Three SPI interfaces allow communication up to slave modes, in half-duplex, full-duplex and
simplex modes. The 3-bit prescaler gives eight master mode frequencies and the frame size
is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode
and hardware CRC calculation.
All SPI interfaces can be served by the DMA controller.
Serial audio interfaces (SAI)
The STM32L4Rxxx devices embed two SAI. Refer to Table 13: SAI implementation for the
features implementation. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
The SAI peripheral supports:
•
Two independent audio sub-blocks which can be transmitters or receivers with their
respective FIFO.
•
•
•
•
8-word integrated FIFOs for each audio sub-block.
Synchronous or asynchronous mode between the audio sub-blocks.
Master or slave configuration independent for both audio sub-blocks.
Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode.
•
•
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.
Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out.
DS12023 Rev 5
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65
Functional overview
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
•
Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame.
•
•
•
•
•
•
•
•
Number of bits by frame may be configurable.
Frame synchronization active level configurable (offset, bit length, level).
First active bit position in the slot is configurable.
LSB first or MSB first for data transfer.
Mute mode.
Stereo/Mono audio frame capability.
Communication clock strobing edge configurable (SCK).
Error flags with associated interrupts if enabled respectively.
–
–
–
–
Overrun and underrun detection.
Anticipated frame synchronization signal detection in slave mode.
Late frame synchronization signal detection in slave mode.
Codec not ready for the AC’97 mode in reception.
•
•
Interruption sources when enabled:
–
–
Errors.
FIFO requests.
DMA interface with two dedicated channels to handle access to the dedicated
integrated FIFO of each SAI audio sub-block.
Table 13. SAI implementation
SAI features(1)
SAI1
SAI2
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97
X
X
Mute mode
X
X
Stereo/Mono audio frame capability.
X
X
16 slots
X
X
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
X
X
FIFO size
SPDIF
X (8 Word)
X (8 Word)
X
X
X
-
PDM
1. X: supported
3.37
Controller area network (CAN)
The CAN is compliant with the 2.0A and B (active) specifications with a bit rate of up to
1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. The CAN has three transmit mailboxes, two receive
FIFOS with three stages and 28 shared scalable filter banks (all of them can be used even if
one CAN is used). 256 bytes of SRAM are allocated.
60/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Functional overview
The CAN peripheral supports:
•
•
•
CAN protocol version 2.0 A, B Active
Bit rates of up to 1 Mbit/s
Transmission
–
–
Three transmit mailboxes
Configurable transmit priority
•
Reception
–
–
–
–
Two receive FIFOs with three stages
Scalable filter banks: 28 filter banks
Identifier list feature
Configurable FIFO overrun
•
•
Time-triggered communication option
–
–
–
Disable automatic retransmission mode
16-bit free running timer
Time Stamp sent in last two data bytes
Management
–
–
Maskable interrupts
Software-efficient mailbox mapping at a unique address space
3.38
Secure digital input/output and MultiMediaCards Interface
(SDMMC)
The SD/SDIO, MultiMediaCard (MMC) host interface (SDMMC) provides an interface
between the AHB bus and SD memory cards, SDIO cards and MMC devices.
The SDMMC features include the following:
•
Full compliance with MultiMediaCard System Specification Version 4.51. Card support
for three different databus modes: 1-bit (default), 4-bit and 8-bit
•
•
Full compatibility with previous versions of MultiMediaCards (backward compatibility)
Full compliance with SD Memory Card Specifications Version 4.1. (SDR104
SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode
not supported)
•
Full compliance with SDIO Card Specification Version 4.0: card support for two different
databus modes: 1-bit (default) and 4-bit. (SDR104 SDMMC_CK speed limited to
maximum allowed IO speed, SPI mode and UHS-II mode not supported)
•
•
Data transfer up to 104 Mbyte/s for the 8-bit mode (depending maximum allowed IO
speed)
Data and command output enable signals to control external bidirectional drivers.
DS12023 Rev 5
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65
Functional overview
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
3.39
Universal serial bus on-the-go full-speed (OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume.
The USB OTG controller requires a dedicated 48 MHz clock that can be provided by the
internal multispeed oscillator (MSI) automatically trimmed by 32.768 kHz external oscillator
(LSE).This allows to use the USB device without external high speed crystal (HSE).
The major features are:
•
•
•
•
•
•
•
•
•
•
Combined Rx and Tx FIFO size of 1.25 Kbytes with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
One bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
Eight host channels with periodic OUT support
HNP/SNP/IP inside (no need for any external resistor)
Software configurable to OTG 1.3 and OTG 2.0 modes of operation
OTG 2.0 Supports ADP (Attach detection Protocol)
USB 2.0 LPM (Link Power Management) support
Battery charging specification revision 1.2 support
Internal FS OTG PHY support
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected.
The synchronization for this oscillator can also be taken from the USB data stream itself
(SOF signalization) which allows crystal less operation.
3.40
3.41
Clock recovery system (CRS)
The devices embed a special block which allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
automatic trimming is based on the external synchronization signal, which could be either
derived from USB SOF signalization, from LSE oscillator, from an external signal on
CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.
Flexible static memory controller (FSMC)
The flexible static memory controller (FSMC) includes two memory controllers:
•
•
The NOR/PSRAM memory controller
The NAND/memory controller
This memory controller is also named flexible memory controller (FMC).
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DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Functional overview
The main features of the FMC controller are the following:
•
Interface with static-memory mapped devices including:
–
–
–
–
–
Static random access memory (SRAM)
NOR Flash memory/OneNAND Flash memory
PSRAM (four memory banks)
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
Ferroelectric RAM (FRAM)
•
•
•
•
•
8-,16- bit data bus width
Independent chip select control for each memory bank
Independent configuration for each memory bank
Write FIFO
The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or high-
performance solutions using external controllers with dedicated acceleration.
3.42
OctoSPI interface (OctoSPI)
The OctoSPI is a specialized communication interface targetting single, dual, quad or octal
SPI memories. It can operate in any of the three following modes:
•
•
Indirect mode: all the operations are performed using the OctoSPI registers
Status polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting
•
Memory-mapped mode: the external memory is memory mapped and is seen by the
system as if it were an internal memory supporting read and write operation
The OctoSPI supports two frame formats:
•
Classical frame format with command, address, alternate byte, dummy cycles and data
phase over 1, 2, 4 or 8 data pins
TM
•
HyperBus frame format
The OctoSPI offers the following features:
•
•
•
•
Three functional modes: indirect, status-polling, and memory-mapped
Read and write support in memory-mapped mode
Supports for single, dual, quad and octal communication
Dual-quad mode, where 8 bits can be sent/received simultaneously by accessing two
quad memories in parallel.
•
•
•
•
SDR and DTR support
Data strobe support
Fully programmable opcode for both indirect and memory mapped mode
Fully programmable frame format for both indirect and memory mapped mode
DS12023 Rev 5
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65
Functional overview
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
•
Each of the five following phases can be configured independently (enable, length,
single/dual/quad communication)
–
–
–
–
–
Instruction phase
Address phase
Alternate bytes phase
Dummy cycles phase
Data phase
TM
•
•
•
•
•
•
HyperBus support
Integrated FIFO for reception and transmission
8, 16, and 32-bit data accesses are allowed
DMA channel for indirect mode operations
Timeout management
Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
3.43
OctoSPI IO manager (OctoSPIIOM)
The OctoSPI IO Manager is a low level interface allowing:
•
•
Efficient OctoSPI pin assignment with a full IO Matrix (before alternate function map)
Multiplexing single/dual/quad/octal SPI interface over the same bus
The OctoSPI IO Manager has the following features:
•
•
•
•
Support up to two single/dual/quad/octal SPI Interface
Support up to eight ports for pin assignment
Fully programmable IO matrix for pin assignment by function (data/control/clock)
Muxer for Single/Dual/Quad/Octal SPI interface multiplexing over the same bus
3.44
Development support
3.44.1
Serial wire JTAG debug port (SWJ-DP)
®
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins
could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared
with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
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DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Functional overview
3.44.2
Embedded Trace Macrocell™
®
The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L4Rxxx devices through a small number of ETM pins to an external hardware trace
port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
DS12023 Rev 5
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65
Pinouts and pin description
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
4
Pinouts and pin description
(1)
Figure 9. STM32L4R5xx and STM32L4R7xx UFBGA169 ballout
1
2
3
4
5
6
7
8
9
10
PA14
PI2
11
12
PI0
13
A
B
C
D
E
F
PI10
PI9
PH2
VDD
VSS
PI11
PE2
PE6
PF2
PF3
NRST
PC1
PA0
PA4
VSS
VDD
PE0
PE1
PB8
PB9
PE5
PF1
PF4
PF10
PC2
PA5
PA7
PA6
PB4
PB3
VSS
PG9
PD4
PD5
PD6
PD7
PG13
PE10
PE9
PE8
PE7
VSS
VDD
VDD
PD0
PA15
PI6
PA13
PI1
PH14
PH12
VDD
PA12
PA11
VSS
PI7
PB5
VDDIO2
PG15
PG10
PG11
PG12
PG14
PG1
PH15
VSS
VDD
PE4
PC13
VSS
PB6
PD1
PH13
PC10
PC11
PA10
PC9
PI3
PI8
PE3
PB7
PD2
PI4
PH9
PH6
PC6
PG6
PD15
PG3
PD12
PD8
VSS
VDD
PH7
VBAT
VSS
PH3-BOOT0
PF0
PD3
PI5
VDDUSB
VDDIO2
PC7
PC14-
OSC32_IN
PC12
PA8
PA9
PC8
PG7
PG4
PD14
PD9
PH11
PH8
PC15-
OSC32_OUT
G
H
J
VDD
PF5
VDD
VDD
PD10
PD13
VSS
PH0-OSC_IN
VSS
PC4
PB11
PE15
PE14
PE13
PE12
PE11
PG8
PG5
PH4
VSS
PH1-
OSC_OUT
PC0
PC5
PG0
PG2
K
L
PC3
VSSA/VREF-
VDDA
PA3
PB0
PF15
PF14
PF13
PF12
PD11
VDD
VREF+
PB1
PH5
OPAMP1_VI
NM
M
N
PF11
PB2
PH10
PB10
PB15
PB12
PB14
PB13
OPAMP2_VI
NM
PA2
PA1
MSv38036V4
1. The above figure shows the package top view.
(1)
Figure 10. STM32L4R9xx UFBGA169 ballout
1
2
PH2
3
4
5
PB4
6
7
8
9
10
11
12
PI0
13
PH14
A
B
C
D
E
F
PI10
PI9
VDD
VSS
PI11
PE2
PE6
PF2
PF3
NRST
PC1
PA0
PA5
VSS
VDD
PE0
PE1
PB8
PB9
PE5
PF1
PF4
PF10
PC2
PC4
PA6
PA7
PB0
PB3
VSS
PG9
PD4
PD5
PD6
PD7
PG4
PB11
PE15
PE14
PE7
VSS
VDD
VDD
PD0
PA15
PI6
PA14
PI2
PA13
PI1
PI7
PB5
VDDIO2
PG15
PG10
PG11
PG12
PG13
PE10
PE9
PH15
PH12
VDD
PE4
PC13
VSS
PB6
PD1
PH13
PC10
PC11
PC8
PI3
PH9
PA10
PA8
PC6
PC7
PD14
VSS
VDD
PE3
PB7
PD2
PI4
VDDUSB
PA9
PA12
VBAT
VSS
PH3-BOOT0
PF0
PD3
PI5
PA11
PC14-
OSC32_IN
PC12
PG3
PD13
PD12
PH4
PG8
PG7
PD15
PD10
PD8
PB15
PH11
PH8
VDDIO2
PG6
VSS
PC15-
OSC32_OUT
G
H
J
VDD
PF5
PG5
PG2
PD11
PD9
PC9
PH0-OSC_IN
VSS
PG1
VSS
VDD
PH1-
OSC_OUT
PC0
PG0
DSI_D1P
DSI_CKP
DSI_D0P
VSS
DSI_D1N
DSI_CKN
DSI_D0N
PB14
VSSDSI
VSSDSI
VCAPDSI
VDDDSI
K
L
PC3
VREF+
PA1
VSSA/VREF-
VDDA
PA3
PF15
PB1
PE8
PF14
PF13
PF12
PE13
PE12
PE11
PH5
M
N
PF11
PB2
PH10
PB10
PA2
PA4
VDD
PB12
PB13
MSv45223V2
1. The above figure shows the package top view.
66/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Pinouts and pin description
(1)
Figure 11. STM32L4R5xxxP UFBGA169 external SMPS ballout
1
2
3
4
5
6
7
8
9
10
PA14
PI2
11
12
13
A
B
C
D
E
F
PI10
PI9
PH2
VDD
VSS
PI11
PE2
PE6
PF2
PF3
NRST
PC1
PA0
PA4
VSS
VDD
PE0
PE1
PB8
PB9
PE5
PF1
PF4
PF10
PC2
PA5
PA7
PA6
PB4
PB3
VSS
PG9
PD4
PD5
PD6
PD7
PG13
PE10
PE9
PE8
PE7
VSS
VDD
VDD
PD0
PA15
PI6
PA13
PI1
PI0
PH14
PH12
VDD
PA12
PA11
VSS
PI7
PB5
VDDIO2
VDD12
PG10
PG11
PG12
PG14
PG1
PH15
VSS
VDD
PE4
PC13
VSS
PB6
PD1
PH13
PC10
PC11
PA10
PC9
PI3
PI8
PE3
PB7
PD2
PI4
PH9
PH6
PC6
PG6
PD15
PG3
PD12
PD8
VSS
VDD
PH7
VBAT
VSS
PH3-BOOT0
PF0
PD3
PI5
VDDUSB
VDDIO2
PC7
PC14-
OSC32_IN
PC12
PA8
PA9
PC8
PG7
PG4
PD14
PD9
VDD12
PH8
PC15-
OSC32_OUT
G
H
J
VDD
PF5
VDD
VDD
PD10
PD13
VSS
PH0-OSC_IN
VSS
PC4
PB11
PE15
PE14
PE13
PE12
PE11
PG8
PG5
PH4
VSS
PH1-
OSC_OUT
PC0
PC5
PG0
PG2
K
L
PC3
VSSA/VREF-
VDDA
PA3
PB0
PF15
PF14
PF13
PF12
PD11
VDD
VREF+
PB1
PH5
OPAMP1_
VNM
M
N
PF11
PB2
PH10
PB10
PB15
PB12
PB14
PB13
OPAMP2_
VNM
PA2
PA1
MSv49309V2
1. The above figure shows the package top view.
DS12023 Rev 5
67/307
135
Pinouts and pin description
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
Figure 12. STM32L4R5xx and STM32L4R7xx LQFP144 pinout
PE2
PE3
PE4
PE5
PE6
VBAT
1
2
3
4
5
6
7
8
9
108
107
106
105
104
103
102
101
100
99
VDD
VSS
VDDUSB
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
10
11
12
PF1
PF2
98
97
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PC6
VDDIO2
VSS
PG8
PG7
PG6
PG5
PG4
PG3
LQFP144
PF10
PG2
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA0
PD8
PB15
PB14
PB13
PB12
PA1
PA2
MSv45224V1
1. The above figure shows the package top view.
68/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Pinouts and pin description
(1)
Figure 13. STM32L4R9xx LQFP144 pinout
PE2
PE3
PE4
PE5
PE6
VBAT
1
2
3
4
5
6
7
8
9
108
107
106
105
104
103
102
101
100
99
VDDUSB
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
10
11
12
PF1
PF2
98
97
PC6
PG8
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF10
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
VDD12DSI
DSI_CKN
DSI_CKP
VSSDSI
DSI_D0N
DSI_D0P
VCAPDSI
VDDDSI
LQFP144
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA/VREF-
VREF+
VDDA
PA0
PA1
PA2
PA3
VSS
VDD
MSv45225V1
1. The above figure shows the package top view.
DS12023 Rev 5
69/307
135
Pinouts and pin description
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
Figure 14. STM32L4R5ZxxxP external SMPS LQFP144 pinout
PE2
PE3
PE4
PE5
PE6
VBAT
1
2
3
4
5
6
7
8
9
108
107
106
105
104
103
102
101
100
99
VDD
VSS
VDDUSB
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
10
11
12
PF1
PF2
98
97
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PC6
VDDIO2
VSS
PG8
PG7
PG6
PG5
PG4
PG3
LQFP144
PF10
PG2
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA0
PD8
PB15
PB14
PB13
PB12
PA1
PA2
MSv42236V1
1. The above figure shows the package top view.
70/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Pinouts and pin description
(1)
Figure 15. STM32L4R9xx UFBGA144 ballout
1
2
3
4
PH3-BOOT0
PB8
5
6
7
8
9
10
PA14
PA13
PA10
PA9
11
VDD
12
VSS
A
B
C
D
E
F
VSS
VBAT
VSS
PE0
VDD
PE5
PB9
PE3
PE2
PE4
PF0
PF4
PF10
PC0
PC3
PA0
PA2
PA3
PB4
PB5
PB7
PB6
PF3
PF7
PF12
PB2
PB1
PC5
PC4
PB0
VDDIO2
PB3
VSS
PD6
PD4
PD5
PD7
PG3
PD15
PE11
PE9
PE8
PG0
PF14
PD3
PD1
PD0
PD2
PG8
PG5
PD14
PD10
PE13
PE15
PE10
PG1
PC11
PA15
PC10
PC12
PC7
PA12
PA11
PE1
PG13
PG12
PG10
PG9
VDDUSB
PA8
PC9
PC14-
OSC32_IN
PC15-
OSC32_OUT
PE6
PC6
PF2
PF8
PF1
PF6
VSS
PC13
PF5
PC8
PG7
VDDIO2
PG2
PG6
PG4
VSS
G
H
J
VDD
PF9
PE7
PD12
PD9
PD13
PD8
PD11
VDD
PH1-
OSC_OUT
PH0-OSC_IN
NRST
PC2
PF15
PF13
PF11
VSS
DSI_D1P
DSI_CKP
DSI_D0P
VDD
DSI_D1N
DSI_CKN
DSI_D0N
VCAPDSI
VSS
PC1
VREF+
PA1
PA6
PB15
PB11
PB10
PE12
VSSDSI
PB14
PB12
PE14
K
L
VSSA/VREF-
VDDA
PA4
PA5
M
VSS
VDD
PA7
VDD
PB13
MSv38491V4
1. The above figure shows the package top view.
(1)
Figure 16. STM32L4R9xx WLCSP144 ballout
1
VSS
2
3
4
5
6
7
8
VDDIO2
PB3
9
10
PE0
PB9
PB8
PE6
VBAT
PF4
PF6
PF10
PC3
PA1
PA3
PA7
11
12
A
B
C
D
E
F
PA14
PA15
PD0
PD5
VDD
VSS
PD4
PD3
PC7
PG4
PE9
PE8
PF15
PG0
PG1
PE7
PG12
PG10
PG9
PD7
PD6
PG5
PF14
PB1
PB2
PF11
VDD
PF13
PB7
PE1
PE2
PE3
PC13
VSS
VDD
PE4
VSS
VDD
VDDUSB
PA12
PA13
PC12
PC11
PA9
PD2
PH3-BOOT0
PB6
PA11
PC10
PA8
PD1
PB4
PC8
PC9
PA10
PG6
PG3
PD10
PE14
PE13
PE10
PE11
PE12
PG13
PB5
PE5
PC14-
OSC32_IN
PC15-
OSC32_OUT
PG7
PG8
VDDIO2
PD14
PD13
PB14
PB15
VSSDSI
VCAPDSI
VSS
PC6
PF0
PD15
VSS
PG2
PD12
PD11
PB13
PB12
PE15
PB10
PB11
PF1
PF5
PF3
VSS
PF2
VDD
G
H
J
VDD
PA5
PF7
PD9
PD8
PA2
PC2
NRST
PH0-OSC_IN
PH1-
OSC_OUT
DSI_D1N
DSI_CKP
DSI_D0P
VDD
DSI_D1P
DSI_CKN
DSI_D0N
VDD
PA6
PA0
PC0
K
L
PC5
PA4
VSSA/VREF-
VREF+
VDD
PC1
VDDA
VSS
PF12
VSS
PC4
M
PB0
MSv42219V2
1. The above figure shows the package top view
DS12023 Rev 5
71/307
135
Pinouts and pin description
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
Figure 17. STM32L4R9ZxxxP WLCSP144 external SMPS ballout
1
2
3
4
5
6
7
8
VDDIO2
PB3
PB4
PE1
9
10
PE0
PB9
PB8
PE6
VBAT
PF4
PF6
PF10
PC3
PA1
PA3
PA7
11
VDD12
PE2
12
A
B
C
D
E
F
VSS
PA14
PA15
PD0
PD5
VDD
VSS
PD4
PD3
PC7
PG4
PE9
PE8
PF15
PG0
PG1
PE7
PG12
PG10
PG9
PD7
PD6
PG5
PF14
PB1
PB2
PF11
VDD
PF13
PB7
VSS_3
VDD_3
PE4
VDD
VDDBUS
PA12
PA13
PC12
PC11
PA9
PD2
PH3-BOOT0
PB6
PA11
PC10
PD1
PE3
PC8
PC9
PA8
PA10
PG6
PG3
PD10
PE14
PE13
PE10
PE11
PE12
PE5
PC13
VSS
PC14-
OSC32_IN
PC15-
OSC32_OUT
PG7
PG8
VDDIO2
PD14
PC6
PB5
PF1
PF0
PD15
VSS
PG2
PD12
PD11
PB13
PB12
PE15
PB10
VSS
PF5
PF3
VSS
PF2
VDD
G
H
J
VDD
PD13
PA5
PF7
PD9
PD8
PB14
PA2
PC2
NRST
PH0-OSC_IN
PH1-
OSC_OUT
DSI_D1N
DSI_CKP
DSI_D0P
VDD
DSI_D1P
DSI_CKN
DSI_D0N
VDD
PB15
PA6
PA0
PC0
K
L
VSSDSI
VCAPDSI
VDD12
PC5
PF12
VSS
PA4
VSSA/VREF-
VREF+
VDD
PC1
VDDA
VSS
PC4
M
PB0
MSv49307V1
1. The above figure shows the package top view.
(1)
Figure 18. STM32L4R5xx WLCSP144 ballout
1
2
PA14
VDDUSB
PA12
PC9
3
PA15
PA13
PC10
PA8
4
5
6
7
8
VDDIO2
PB3
9
10
11
12
A
B
C
D
E
F
VSS
VDD
PA11
PC8
PG7
PD15
VSS
PD9
NC
PD0
PD5
VDD
VSS
PD4
PD3
PC7
PG4
PE9
PE8
PF15
PG0
PG1
PE7
PG12
PG10
PG9
PD7
PD6
PG5
PF14
PB1
PB2
PF11
VDD
PF13
PB7
PE0
PB9
PB8
PE6
VBAT
PF4
PE1
PE2
PE3
PC13
VSS
VDD
PE4
VSS
PC12
PC11
PA9
PD2
PH3-BOOT0
PB6
PD1
PB4
PA10
PG6
PG3
PD10
PE14
PE13
PE10
PE11
PE12
PG13
PB5
PE5
PC14-
OSC32_IN
PC15-
OSC32_OUT
PG8
PG2
VDD
PD8
VDDIO2
PD14
PD13
PB14
PB15
VSS
PC6
PF0
PD12
PD11
PB13
PB12
PE15
PB10
PB11
PF1
PF5
PF3
VSS
PF2
VDD
G
H
J
PA5
PF7
PF6
PA2
PC2
PF10
PC3
PA1
PA3
PA7
NRST
PH0-OSC_IN
PH1-
OSC_OUT
NC
PA6
PA0
PC0
K
L
NC
NC
PC5
PA4
VSSA/VREF-
VREF+
VDD
PC1
VDDA
VSS
NC
NC
NC
PF12
VSS
PC4
M
VDD
VDD
VSS
PB0
MSv43442V1
1. The above figure shows the package top view.
NC (not-connected) balls must be left unconnected.
72/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Pinouts and pin description
(1)
Figure 19. STM32L4R5xx UFBGA132 ballout
1
2
3
4
PH3-BOOT0
PB7
5
6
7
8
9
10
11
PA13
PC10
VDDUSB
PA8
12
A
B
C
D
E
F
PE3
PE4
PC13
PE1
PE2
PE5
PE6
VBAT
VSS
VDD
NRST
PC1
PC3
PA0
PA1
PB8
PB9
PE0
VSS
VSS
PF4
PG11
VDD
PC2
PA2
PA3
PD7
PB6
PB5
PF1
PD5
PD6
PG14
PF0
PB4
PD4
PG13
PG12
PB3
PD3
PD2
PG10
PA15
PD1
PD0
PG9
PG5
PG3
PG1
PG0
PF15
PD8
PE12
PE11
PA14
PC12
PC11
PA9
PA12
PA11
PA10
PC9
VDD
PC14-
OSC32_IN
PF2
PC15-
OSC32_OUT
PF3
PC8
PC7
PC6
PH0-OSC_IN
PF5
VSS
VDD
VSS
PG4
VSS
VSS
PH1-
OSC_OUT
G
H
J
PG6
VDDIO2
PG2
VDD
VDD
PD13
PD10
PB13
PB12
PE15
PC0
VSSA/VREF-
PG15
PG7
PD15
PD12
PB15
PB10
PE13
PD14
PD11
PB14
PB11
PE14
PA4
PA7
PC4
PC5
PB0
PG8
PF11
PB2
PB1
PF12
PF13
PE8
PF14
PD9
K
L
PA5
VREF+
PA6
PE10
PE9
OPAMP1_VI OPAMP2_VI
NM NM
M
VDDA
PE7
MSv38035V5
1. The above figure shows the package top view.
(1)
Figure 20. STM32L4R5xxxP UFBGA132 external SMPS ballout
1
2
3
4
PH3-BOOT0
PB7
5
6
7
8
9
10
11
PA13
PC10
VDDUSB
PA8
12
A
B
C
D
E
F
PE3
PE4
PC13
PE1
PE2
PE5
PE6
VBAT
VSS
VDD
NRST
PC1
PC3
PA0
PA1
PB8
PB9
PE0
VSS
VSS
PF4
PG11
VDD
PC2
PA2
PA3
PD7
PB6
PB5
PF1
PD5
PB4
PD4
PG13
PG12
PB3
PD3
PD2
PG10
PA15
PD1
PD0
PG9
PG5
PG3
PG1
PG0
PF15
PD8
PE12
PE11
PA14
PC12
PC11
PA9
PA12
PA11
PA10
PC9
PD6
VDD_3
PF2
VDD12
PF0
PC14-
OSC32_IN
PC15-
OSC32_OUT
PF3
PC8
PC7
PC6
PH0-OSC_IN
PF5
VSS
VDD
VSS
PG4
VSS
VSS
PH1-
OSC_OUT
G
H
J
PG6
VDDIO2
PG2
VDD
VDD
PD13
PD10
PB13
PB12
PE15
PC0
VSSA/VREF-
PG15
PG7
PD15
PD12
PB15
PB10
PE13
PD14
PD11
PB14
VDD12
PE14
PA4
PA7
PC4
PC5
PB0
PG8
PF11
PB2
PB1
PF12
PF13
PE8
PF14
PD9
K
L
PA5
VREF+
PA6
PE10
PE9
OPAMP1_
VINM
OPAMP2_
VINM
M
VDDA
PE7
MSv49308V2
1. The above figure shows the package top view.
DS12023 Rev 5
73/307
135
Pinouts and pin description
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
Figure 21. STM32L4R5xx and STM32L4R7xx LQFP100 pinout
PE2
PE3
1
2
75
74
VDD
VSS
PE4
PE5
PE6
VBAT
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDUSB
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
VSS
VDD
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC6
LQFP100
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA0
PA1
PD8
PB15
PB14
PB13
PB12
PA2
MSv38494V1
1. The above figure shows the package top view.
74/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Pinouts and pin description
(1)
Figure 22. STM32L4R9xx LQFP100 pinout
3(ꢂ
3(ꢆ
3(ꢀ
3(ꢁ
3(ꢃ
9%$7
3&ꢄꢆ
ꢄ
ꢂ
ꢆ
ꢀ
ꢁ
ꢃ
ꢇ
ꢈ
ꢇꢁ
ꢇꢀ
ꢇꢆ
ꢇꢂ
ꢇꢄ
ꢇꢅ
ꢃꢉ
ꢃꢈ
ꢃꢇ
ꢃꢃ
ꢃꢁ
ꢃꢀ
ꢃꢆ
ꢃꢂ
ꢃꢄ
ꢃꢅ
ꢁꢉ
ꢁꢈ
ꢁꢇ
ꢁꢃ
ꢁꢁ
ꢁꢀ
ꢁꢆ
ꢁꢂ
ꢁꢄ
9''86%
3$ꢄꢆ
3$ꢄꢂ
3$ꢄꢄ
3$ꢄꢅ
3$ꢉ
3$ꢈ
3&ꢉ
3&ꢈ
3&ꢄꢀꢊ26&ꢆꢂB,1
3&ꢄꢁꢊ26&ꢆꢂB287
ꢉ
966
9''
3+ꢅꢊ26&B,1
3+ꢄꢊ26&B287
1567
ꢄꢅ
ꢄꢄ
ꢄꢂ
ꢄꢆ
ꢄꢀ
ꢄꢁ
ꢄꢃ
ꢄꢇ
ꢄꢈ
ꢄꢉ
ꢂꢅ
ꢂꢄ
ꢂꢂ
ꢂꢆ
ꢂꢀ
ꢂꢁ
3&ꢇ
3&ꢃ
3'ꢄꢁ
3'ꢄꢀ
3'ꢄꢅ
3'ꢉ
/4)3ꢄꢅꢅ
3&ꢅ
3&ꢄ
3&ꢂ
3&ꢆ
3'ꢈ
9''ꢄꢂ'6,
'6,B&.1
'6,B&.3
966'6,
'6,B'ꢅ1
'6,B'ꢅ3
9&$3'6,
9'''6,
3%ꢄꢁ
966$ꢋ95()ꢊ
9''$ꢋ95()ꢌ
3$ꢅ
3$ꢄ
3$ꢂ
3$ꢆ
966
06Yꢀꢁꢂꢂꢃ9ꢂ
1. The above figure shows the package top view.
DS12023 Rev 5
75/307
135
Pinouts and pin description
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Definition
Table 14. Legend/abbreviations used in the pinout table
Name
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin name
S
I
Supply pin
Pin type
Input only pin
I/O
FT
TT
B
Input / output pin
5 V tolerant I/O
3.6 V tolerant I/O
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os
I/O structure
_f (1)
_l (2)
I/O, Fm+ capable
I/O, with LCD function supplied by VLCD
I/O, with USB function supplied by VDDUSB
I/O, with Analog switch function supplied by VDDA
I/O supplied only by VDDIO2
_u (3)
_a (4)
_s (5)
Notes
Alternate
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Functions selected through GPIOx_AFR registers
functions
Pin
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
1. The related I/O structures in Table 15 are: FT_f, FT_fa, FT_fl, FT_fla.
2. The related I/O structures in Table 15 are: FT_l, FT_fl, FT_lu.
3. The related I/O structures in Table 15 are: FT_u, FT_lu.
4. The related I/O structures in Table 15 are: FT_a, FT_la, FT_fa, FT_fla, TT_a, TT_la.
5. The related I/O structures in Table 15 are: FT_s, FT_fs.
76/307
DS12023 Rev 5
XXX
Table 15. STM32L4Rxxx pin definitions
STM32L4R9xxx
Pin number
STM32L4R5xxx, STM32L4R7xxx
-
-
-
-
-
-
-
-
-
-
-
-
M11 M11
C1 C1
-
-
-
-
-
-
-
-
-
-
M11
C1
VSS
VDD
S
S
-
-
-
-
-
-
-
-
OCTOSPIM_P2_IO0,
EVENTOUT
-
-
-
-
-
-
C3 C3
-
-
-
-
-
C3
PI11
I/O
FT
-
-
TRACECK,
TIM3_ETR,
SAI1_CK1,
1
B2
B2
1
1
B11 D3 D3
1
1
C3 B11 B11 D3
PE2
I/O FT_l
-
TSC_G7_IO1,
LCD_R0, FMC_A23,
SAI1_MCLK_A,
EVENTOUT
-
TRACED0,
TIM3_CH1,
OCTOSPIM_P1_DQS,
TSC_G7_IO2,
2
A1
A1
2
2
C11 D2 D2
2
2
B3 C11 C11 D2
PE3
I/O FT_l
-
-
LCD_R1, FMC_A19,
SAI1_SD_B,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
TRACED1,
TIM3_CH2, SAI1_D2,
DFSDM1_DATIN3,
TSC_G7_IO3,
DCMI_D4, LCD_B0,
FMC_A20,
3
B1
B1
3
3
C12 D1 D1
3
3
D3 C12 C12 D1
PE4
I/O
FT
-
-
SAI1_FS_A,
EVENTOUT
TRACED2,
TIM3_CH3,
SAI1_CK2,
DFSDM1_CKIN3,
TSC_G7_IO4,
DCMI_D6, LCD_G0,
FMC_A21,
4
C2 C2
4
4
D9 E4
E4
4
4
C2 D9 D9 E4
PE5
I/O
FT
-
-
SAI1_SCK_A,
EVENTOUT
TRACED3,
TIM3_CH4, SAI1_D1,
DCMI_D7, LCD_G1,
FMC_A22,
RTC_TAMP3,W
KUP3
5
6
D2 D2
5
6
5
6
D10 E3
E10 E2
E3
E2
5
6
5
6
D4 D10 D10 E3
B1 E10 E10 E2
PE6
I/O
S
FT
-
-
-
SAI1_SD_A,
EVENTOUT
E2
E2
VBAT
-
-
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
-
RTC_TAMP1/RT
C_TS/RTC_OUT
,WKUP2
(1)
7
8
C1 C1
D1 D1
7
8
7
8
D11 E1
E11 F1
E1
F1
7
8
7
8
E4 D11 D11 E1
D1 E11 E11 F1
PC13 I/O
PC14-
FT
FT
EVENTOUT
EVENTOUT
(2)
(1)
(2)
OSC32
I/O
OSC32_IN
_IN
(PC14)
PC15-
(1)
(2)
OSC32
I/O
9
E1
E1
9
9
E12 G1 G1
9
9
D2 E12 E12 G1
FT
EVENTOUT
OSC32_OUT
_OUT
(PC15)
I2C2_SDA,
-
-
D6 D6
D5 D5
D4 D4
10
11
10
11
E9
F8
F5
F4
F5
F4
F3
-
-
10
11
E3
E2
E9
F8
E9
F8
F5
F4
PF0
PF1
I/O FT_f
I/O FT_f
-
-
OCTOSPIM_P2_IO0,
FMC_A0, EVENTOUT
-
-
I2C2_SCL,
OCTOSPIM_P2_IO1,
FMC_A1, EVENTOUT
I2C2_SMBA,
OCTOSPIM_P2_IO2,
FMC_A2, EVENTOUT
-
-
12
13
12 F12 F3
-
-
12
13
E1 F12 F12 F3
E5 F11 F11 G3
PF2
PF3
I/O
I/O
FT
FT
-
-
-
-
OCTOSPIM_P2_IO3,
FMC_A3, EVENTOUT
E4
E4
13 F11 G3 G3
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
OCTOSPIM_P2_CLK,
FMC_A4, EVENTOUT
-
F3
F3
14
14 F10 G4 G4
-
14
F3 F10 F10 G4
F4 F9 F9 G5
PF4
I/O
FT
-
-
-
F4
F2
F4
F2
15
16
17
15
16 G11 F2
17 G12 G2 G2
F9 G5 G5
-
15
16
17
PF5
VSS
VDD
I/O
S
FT
-
-
-
FMC_A5, EVENTOUT
-
-
-
10
11
F2
10
11
L6 G11 G11 F2
G1 G12 G12 G2
-
-
-
-
G2 G2
S
TIM5_ETR,
TIM5_CH1,
-
-
-
18
18 G10
-
-
-
18
F2 G10 G10
-
PF6
I/O
FT
-
-
OCTOSPIM_P1_IO3,
SAI1_SD_B,
-
EVENTOUT
TIM5_CH2,
OCTOSPIM_P1_IO2,
SAI1_MCLK_B,
EVENTOUT
-
-
-
-
-
-
19
20
19
G9
-
-
-
-
-
-
19
-
F5 G9 G9
-
-
PF7
PF8
I/O
I/O
FT
FT
-
-
TIM5_CH3,
OCTOSPIM_P1_IO0,
SAI1_SCK_B,
-
20 NC
F1 NC NC
(3)
EVENTOUT
TIM5_CH4,
OCTOSPIM_P1_IO1,
SAI1_FS_B,
(3)
-
-
-
21
21 NC
-
-
-
-
G4 NC NC
-
PF9
I/O
FT
-
TIM15_CH1,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
OCTOSPIM_P1_CLK,
DFSDM1_CKOUT,
DCMI_D11, SAI1_D3,
TIM15_CH2,
-
-
-
22
23
22 H10 H4 H4
-
20
G3 H10 H10 H4
PF10 I/O
PH0-
FT
-
-
-
EVENTOUT
12
F1
F1
23 H12 H1 H1
12
21
H1 H12 H12 H1 OSC_I I/O
N (PH0)
FT
FT
EVENTOUT
OSC_IN
PH1-
OSC_O
UT
13
14
G1 G1
H2 H2
24
25
24 J12 J1
J1
13
14
22
23
H2 J12 J12 J1
J1 H11 H11 H3
I/O
-
-
EVENTOUT
-
OSC_OUT
-
(PH1)
25 H11 H3 H3
NRST I-O RST
LPTIM1_IN1,
I2C3_SCL,
DFSDM1_DATIN4,
LPUART1_RX,
SAI2_FS_A,
15
H1 H1
26
26 J11 J2
J2
15
24
H3 J11 J11 J2
PC0
I/O FT_fla
-
ADC1_IN1
LPTIM2_IN1,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
TRACED0,
LPTIM1_OUT,
SPI2_MOSI,
I2C3_SDA,
16
J2
J2
27
27 K12 J3
J3
16
25
J2 K12 K12 J3
PC1
I/O FT_fla
-
DFSDM1_CKIN4,
LPUART1_TX,
OCTOSPIM_P1_IO4,
SAI1_SD_A,
ADC1_IN2
EVENTOUT
LPTIM1_IN2,
SPI2_MISO,
17
18
J3
J3
28
29
28
H9
J4
J4
17
18
26
27
H4 H9 H9
J4
PC2
PC3
I/O FT_la
-
-
DFSDM1_CKOUT,
OCTOSPIM_P1_IO5,
EVENTOUT
ADC1_IN3
ADC1_IN4
LPTIM1_ETR,
SAI1_D1, SPI2_MOSI,
OCTOSPIM_P1_IO6,
SAI1_SD_A,
K2
K2
29 J10 K1
K1
J3 J10 J10 K1
I/O FT_a
LPTIM2_ETR,
EVENTOUT
19
20
-
-
-
-
30
31
30
31
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VSSA
S
S
-
-
-
-
-
-
-
-
VREF-
VSSA/V
REF-
-
J1
J1
-
-
K11 K2
K2
19
28
K1 K11 K11 K2
S
-
-
-
-
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
21
L1
L1
32
32 L11 L1
33 L12 L2
L1
L2
-
-
29
K2 L11 L11 L1 VREF+
S
S
-
-
-
-
-
-
VREFBUF_OUT
-
22 M1 M1 33
30
-
L1 L12 L12 L2
VDDA
VDDA/
VREF+
-
23
-
-
-
-
34
-
-
34
-
-
J9
-
-
-
20
21
-
-
K3
-
-
J9
-
-
J9
-
-
K3
-
S
-
-
-
-
-
-
TIM2_CH1,
TIM5_CH1,
TIM8_ETR,
OPAMP1_VINP,
ADC1_IN5,
RTC_TAMP2,W
KUP1
USART2_CTS_NSS,
UART4_TX,
L2
L2
K3
K3
31
PA0
I/O FT_a
SAI1_EXTCLK,
TIM2_ETR,
EVENTOUT
OPAMP
1_VINM
M3 M3
M1 M1
-
I
TT
-
-
TIM2_CH2,
TIM5_CH2,
I2C1_SMBA,
SPI1_SCK,
USART2_RTS_DE,
UART4_RX,
OPAMP1_VINM,
ADC1_IN6
24 M2 M2 35
35 K10 N2 N2
22
32
L2 K10 K10 M1
PA1
I/O FT_la
-
OCTOSPIM_P1_DQS,
TIM15_CH1N,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
TIM2_CH3,
TIM5_CH3,
USART2_TX,
LPUART1_TX,
OCTOSPIM_P1_NCS, WKUP4/LSCO
SAI2_EXTCLK,
ADC1_IN7,
25
K3
K3
36
36
H8 N1 N1
23
33
L3
H8 H8 N1
PA2
I/O FT_la
-
TIM15_CH1,
EVENTOUT
TIM2_CH4,
TIM5_CH4,
SAI1_CK1,
USART2_RX,
OPAMP1_VOUT,
LPUART1_RX,
26
L3
E3
L3
E3
37
37 L10 M2 M2 24
34 M3 L10 L10 M2
PA3
I/O TT_a
-
ADC1_IN8
OCTOSPIM_P1_CLK,
SAI1_MCLK_A,
TIM15_CH2,
EVENTOUT
27
28
38
39
38 M12 H2 H2
39 M11 N3 N3
25
26
35
G2 M12 M12 H2
VSS
VDD
S
S
-
-
-
-
-
-
-
-
H3 H3
36 M2 M11 M11 N3
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
OCTOSPIM_P1_NCS,
SPI1_NSS,
SPI3_NSS,
USART2_CK,
DCMI_HSYNC,
SAI1_FS_B,
LPTIM2_OUT,
EVENTOUT
ADC1_IN9,
DAC1_OUT1
29
30
J4
J4
40
41
40
41
K9
L3
L3
27
28
37
38
K4
L4
K9
K9 N2
PA4
PA5
I/O TT_a
-
-
TIM2_CH1,
TIM2_ETR,
TIM8_CH1N,
SPI1_SCK,
ADC1_IN10,
DAC1_OUT2
K4
K4
G8 K4
K4
G8 G8
L3
I/O TT_a
LPTIM2_ETR,
EVENTOUT
TIM1_BKIN,
TIM3_CH1,
TIM8_BKIN,
DCMI_PIXCLK,
SPI1_MISO,
USART3_CTS_NSS,
LPUART1_CTS,
OCTOSPIM_P1_IO3,
TIM16_CH1,
OPAMP2_VINP,
ADC1_IN11
31
L4
L4
42
42
J8
M4 M4 29
39
J4
J8
J8
L4
PA6
I/O FT_a
-
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
OPAMP
2_VINM
-
M4 M4
-
-
-
N4 N4
-
-
-
-
-
-
I
TT
-
-
-
-
TIM1_CH1N,
TIM3_CH2,
TIM8_CH1N,
I2C3_SCL,
OPAMP2_VINM,
ADC1_IN12
32
J5
J5
43
43 M10 L4
L4
30
40 M4 M10 M10 M4
PA7
I/O FT_fla
SPI1_MOSI,
OCTOSPIM_P1_IO2,
TIM17_CH1,
EVENTOUT
USART3_TX,
OCTOSPIM_P1_IO7,
EVENTOUT
COMP1_INM,
ADC1_IN13
33
34
K5
L5
K5
L5
44
45
44
45
L9
H5 H5
31
-
41
-
L5
L9
K8
L9
K8
K4
-
PC4
PC5
I/O FT_a
I/O FT_a
-
-
SAI1_D3,
USART3_RX,
EVENTOUT
COMP1_INP,
ADC1_IN14,
WKUP5
K8
J5
J5
K5
TIM1_CH2N,
TIM3_CH3,
TIM8_CH2N,
SPI1_NSS,
OPAMP2_VOUT,
ADC1_IN15
35 M5 M5 46
46 M9 K5
K5
32
42 M5 M9 M9 N4
PB0
I/O TT_la
-
USART3_CK,
OCTOSPIM_P1_IO1,
COMP1_OUT,
SAI1_EXTCLK,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N,
DFSDM1_DATIN0,
USART3_RTS_DE,
LPUART1_RTS_DE,
OCTOSPIM_P1_IO0,
LPTIM2_IN1,
COMP1_INM,
ADC1_IN16
36 M6 M6 47
47
48
H7
L5
L5
33
34
43
J5
H7 H7
L5
PB1
PB2
I/O FT_a
-
-
EVENTOUT
RTC_OUT,
LPTIM1_OUT,
I2C3_SMBA,
37
L6
L6
48
J7
N5 N5
44
H5
J7
J7
N5
I/O FT_a
COMP1_INP
DFSDM1_CKIN0,
OCTOSPIM_P1_DQS,
LCD_B1, EVENTOUT
LCD_DE, DCMI_D12,
DSI_TE, EVENTOUT
-
-
K6
J7
K6
J7
49
50
49
50
K7 M5 M5
-
-
45
46
K6
G5
K7
L8
K7 M5
PF11 I/O
PF12 I/O
FT
FT
-
-
-
-
OCTOSPIM_P2_DQS,
LCD_B0, FMC_A6,
EVENTOUT
L8
N6 N6
L8
N6
-
-
-
-
-
-
51
52
51 M8
52 L7
-
-
-
-
47 M1 M8 M8
48 M6 L7 L7
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
N7 N7
N7
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
I2C4_SMBA,
DFSDM1_DATIN6,
LCD_B1, FMC_A7,
EVENTOUT
-
-
K7
J8
J9
K7
J8
J9
53
54
53 M7 M6 M6
-
-
49
J6
M7 M7 M6
PF13 I/O
FT
-
-
-
-
I2C4_SCL,
DFSDM1_CKIN6,
TSC_G8_IO1,
LCD_G0, FMC_A8,
EVENTOUT
54
G7
L6
L6
50 M7 G7 G7
L6
PF14 I/O FT_f
PF15 I/O FT_f
I2C4_SDA,
TSC_G8_IO2,
LCD_G1, FMC_A9,
EVENTOUT
-
-
-
55
56
57
55
56
57
J6
K6
L6
K6
J6
K6
J6
-
-
-
51
52
H6
L7
J6
J6
K6
L6
K5
J5
-
-
-
-
-
-
OCTOSPIM_P2_IO4,
TSC_G8_IO3,
FMC_A10,
H9 H9
G9 G9
K6
PG0
PG1
I/O
I/O
FT
FT
EVENTOUT
OCTOSPIM_P2_IO5,
TSC_G8_IO4,
FMC_A11,
H6 H6
53 M8 L6
H5
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
TIM1_ETR,
DFSDM1_DATIN2,
LCD_B6, FMC_D4,
SAI1_SD_B,
38 M7 M7 58
58 M6 L7
L7
K7
J7
35
36
37
54
G6 M6 M6 L7
PE7
PE8
PE9
I/O
I/O
I/O
FT
FT
FT
-
-
-
-
-
-
EVENTOUT
TIM1_CH1N,
DFSDM1_CKIN2,
LCD_B7, FMC_D5,
SAI1_SCK_B,
39
L7
L7
59
59
60
H6 K7
55
56
K7 H6 H6 K6
EVENTOUT
TIM1_CH1,
DFSDM1_CKOUT,
LCD_G2, FMC_D6,
SAI1_FS_B,
40 M8 M8 60
G6
J7
J7
G6 G6
J6
EVENTOUT
-
-
F6
F6
61
62
61
62
-
-
M7 M7
-
-
57
58
C1
-
-
-
-
-
M7
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
G6 G6
-
-
TIM1_CH2N,
DFSDM1_DATIN4,
TSC_G5_IO1,
41
L8
L8
63
63
K5 H7 H7
38
59
L8
K5
K5 H6
PE10 I/O
FT
-
OCTOSPIM_P1_CLK,
LCD_G3, FMC_D7,
SAI1_MCLK_B,
EVENTOUT
-
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
TIM1_CH2,
DFSDM1_CKIN4,
TSC_G5_IO2,
OCTOSPIM_P1_NCS,
LCD_G4, FMC_D8,
EVENTOUT
42 M9 M9 64
64
L5
N8 N8
39
60
H7
L5
L5
N8
PE11 I/O
FT
FT
-
-
-
-
TIM1_CH3N,
SPI1_NSS,
DFSDM1_DATIN5,
TSC_G5_IO3,
43
L9
L9
65
65 M5 M8 M8 40
61 M9 M5 M5 M8
PE12 I/O
OCTOSPIM_1_IO0,
LCD_G5, FMC_D9,
EVENTOUT
TIM1_CH3,
SPI1_SCK,
DFSDM1_CKIN5,
TSC_G5_IO4,
44 M10 M10 66
66
J5
L8
L8
41
62
J8
J5
J5
L8
PE13 I/O
FT
-
-
OCTOSPIM_P1_IO1,
LCD_G6, FMC_D10,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
TIM1_CH4,
TIM1_BKIN2,
SPI1_MISO,
45 M11 M11 67
67
68
H5 K8
K8
J8
42
43
63 M10 H5 H5 K7
PE14 I/O
FT
FT
-
-
-
-
OCTOSPIM_P1_IO2,
LCD_G7, FMC_D11,
EVENTOUT
TIM1_BKIN,
SPI1_MOSI,
OCTOSPIM_P1_IO3,
LCD_R2, FMC_D12,
EVENTOUT
46 M12 M12 68
K4
J8
64
65
K8
K4
K4
J7
PE15 I/O
TIM2_CH3,I2C4_SCL,
I2C2_SCL, SPI2_SCK,
DFSDM1_DATIN7,
USART3_TX,
LPUART1_RX,
TSC_SYNC,
47 L10 L10 69
69
L4
N9 N9
44
L9
L4
L4
N9
PB10 I/O FT_fl
-
-
OCTOSPIM_P1_CLK,
COMP1_OUT,
SAI1_SCK_A,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
TIM2_CH4,
I2C4_SDA,I2C2_SDA,
DFSDM1_CKIN7,
USART3_RX,
48 NC L11 NC 70 M4 H8 H8
45
66
K9 NC M4 H7
PB11 I/O FT_fl
-
LPUART1_TX,
OCTOSPIM_P1_NCS,
DSI_TE,
-
COMP2_OUT,
EVENTOUT
I2C2_SCL,
OCTOSPIM_P2_DQS,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
K9
L9
K9
L9
-
-
-
-
-
-
-
-
-
-
K8
L9
PH4
PH5
I/O FT_f
I/O FT_f
-
-
-
-
I2C2_SDA,
DCMI_PIXCLK,
EVENTOUT
I2C3_SDA,
OCTOSPIM_P2_IO3,
DCMI_HSYNC,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
N10 N10
M9 M9
-
-
-
-
-
-
-
-
-
-
N10
M9
PH8
I/O FT_f
-
-
-
-
TIM5_CH1,
OCTOSPIM_P2_IO5,
DCMI_D1,
PH10 I/O
FT
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
TIM5_CH2,
OCTOSPIM_P2_IO6,
DCMI_D2,
-
-
-
-
-
-
NC M10
C2 C2
-
-
-
-
-
M10 PH11 I/O
FT
-
-
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C2
-
VSS
VDD12
VSS
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L11
70
M10
-
M3
49 F12 F12 71
50 G12 G12 72
71 M3 A7
A7
46
67 M12 M4 M3 A7
68 L11 M1 M1 N11
72 M1 N11 N11 47
VDD
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS,
DFSDM1_DATIN1,
USART3_CK,
LPUART1_RTS_DE,
TSC_G1_IO1,
SAI2_FS_A,
51 L12 L12 73
73
J4 N12 N12 48
69 L10 J4
J4 N12 PB12 I/O
FT
-
-
TIM15_BKIN,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
TIM1_CH1N,
I2C2_SCL, SPI2_SCK,
DFSDM1_CKIN1,
USART3_CTS_NSS,
LPUART1_CTS,
TSC_G1_IO2,
52 K12 K12 74
74
H4 N13 N13 49
70 M11 H4 H4 N13 PB13 I/O FT_fl
-
-
SAI2_SCK_A,
TIM15_CH1N,
EVENTOUT
TIM1_CH2N,
TIM8_CH2N,
I2C2_SDA,
SPI2_MISO,
DFSDM1_DATIN2,
USART3_RTS_DE,
TSC_G1_IO3,
SAI2_MCLK_A,
TIM15_CH1,
53 K11 K11 75
75
H3 M13 M13 50
71 K10 H3 H3 M12 PB14 I/O FT_fl
-
-
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
RTC_REFIN,
TIM1_CH3N,
TIM8_CH3N,
SPI2_MOSI,
DFSDM1_CKIN2,
TSC_G1_IO4,
SAI2_SD_A,
TIM15_CH2,
EVENTOUT
54 K10 K10 76
76
J3 M12 M12 51
72
J9
J3
J3 L10 PB15 I/O
FT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M2 L12 L12
-
-
73
-
-
-
-
M2 M2
-
M13
-
VDD
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VDDDS
I
-
-
-
-
-
52
-
-
-
-
-
L13 L13
VSS
VCAPD
SI
-
-
-
-
53
74 L12 L3
75 K11 L1
76 K12 L2
L3 L13
L1 L11
L2 L12
DSI_D0
P
(3)
(3)
-
-
-
-
-
-
54
I/O
-
-
-
DSI_D0
N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
55
56
57
I/O
S
-
-
-
-
-
-
-
-
-
77
-
-
-
J13 VSSDSI
-
DSI_CK
(3)
78 J11 K1
K1 K11
I/O
P
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
DSI_CK
N
(3)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
58
59
-
79 J12 K2
K2 K12
I/O
S
-
-
-
-
-
-
-
-
-
-
-
-
VDD12
DSI
80
-
-
-
-
-
-
DSI_D1
P
(3)
H11 J2
J2 J11
J1 J12
I/O
I/O
DSI_D1
N
(3)
-
-
H12 J1
J10 K3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K3 K13 VSSDSI
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K3
L3
L1
L2
K1
K2
J2
J1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VSS
NC
NC
NC
NC
NC
NC
NC
-
-
-
-
-
-
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
USART3_TX,
DCMI_HSYNC,
LCD_R3, FMC_D13,
EVENTOUT
55
56
K9
K8
K9
K8
77
78
77
78
H2 L11 L11 60
81 H10 H2 H2 K10
PD8
PD9
I/O
I/O
FT
FT
-
-
-
-
USART3_RX,
DCMI_PIXCLK,
LCD_R4, FMC_D14,
SAI2_MCLK_A,
EVENTOUT
H1 L10 L10 61
82
H9 H1 H1 K9
USART3_CK,
TSC_G6_IO1,
57 J12 J12 79
79
-
G5 J13 J13 62
83
-
H8 G5 G5 J10 PD10 I/O
FT
-
-
-
LCD_R5, FMC_D15,
SAI2_SCK_A,
-
-
EVENTOUT
-
-
-
-
-
H13 H13
-
-
-
-
-
-
VDD
S
-
I2C4_SMBA,
USART3_CTS_NSS,
TSC_G6_IO2,
LCD_R6, FMC_A16,
SAI2_SD_A,
58 J11 J11 80
80
G4 K12 K12
84 G11 G4 G4
J9
PD11 I/O
FT
-
-
LPTIM2_ETR,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
TIM4_CH1,I2C4_SCL,
USART3_RTS_DE,
TSC_G6_IO3,
59 J10 J10 81
81
82
F4 K11 K11
-
-
85
G9 F4
F4
J8
PD12 I/O FT_fl
-
-
LCD_R7, FMC_A17,
SAI2_FS_A,
-
-
LPTIM2_IN1,
EVENTOUT
TIM4_CH2,
I2C4_SDA,
TSC_G6_IO4,
FMC_A18,
60 H12 H12 82
G3 K13 K13
86 G10 G3 G3 H8
PD13 I/O FT_fl
LPTIM2_OUT,
EVENTOUT
-
-
-
-
-
-
83
84
83
84
G1 H12 H12
G2 G13 G13
-
-
87
-
G1 G1 H12
VSS
VDD
S
S
-
-
-
-
-
-
-
-
88 G12 G2 G2 H13
TIM4_CH3, LCD_B2,
FMC_D0, EVENTOUT
61 H11 H11 85
62 H10 H10 86
85
86
F3 K10 K10 63
F1 H11 H11 64
89
90
G8 F3
G7 F1
F3 H11 PD14 I/O
F1 H10 PD15 I/O
FT
FT
-
-
-
-
TIM4_CH4, LCD_B3,
FMC_D1, EVENTOUT
SPI1_SCK, FMC_A12,
SAI2_SCK_B,
-
G10 G10 87
87
F2 J12 J12
-
91 F12 F2
F2
H9
PG2
I/O FT_s
-
-
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
SPI1_MISO,
FMC_A13,
SAI2_FS_B,
EVENTOUT
-
-
F9
F9
88
88
89
F5 J11 J11
F6 J10 J10
-
-
92
F7
F5
F5 G8
F6 G7
PG3
PG4
I/O FT_s
I/O FT_s
-
-
-
-
SPI1_MOSI,
FMC_A14,
SAI2_MCLK_B,
EVENTOUT
F10 F10 89
93 F10 F6
SPI1_NSS,
LPUART1_CTS,
FMC_A15,
SAI2_SD_B,
EVENTOUT
-
-
E9
E9
90
91
90
91
F7
J9
J9
-
-
94
95
F8
F9
F7
E5
F7 G9
PG5
PG6
I/O FT_s
I/O FT_s
-
-
-
-
OCTOSPIM_P1_DQS,
I2C3_SMBA,
LPUART1_RTS_DE,
LCD_R1, DSI_TE,
EVENTOUT
G4 G4
E5 G11 G11
E5 G12
SAI1_CK1, I2C3_SCL,
OCTOSPIM_P2_DQS,
DFSDM1_CKOUT,
LPUART1_TX,
-
H4 H4
92
92
E1 H10 H10
-
96 E11 E1
E1 G10
PG7
I/O FT_fs
-
-
FMC_INT,
SAI1_MCLK_A,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
I2C3_SDA,
LPUART1_RX,
EVENTOUT
-
J6
J6
93
93
E2 H9 H9
-
97
E8
F11 D12 D12 F13
E12 E3 E3 F12
E2
E2 F10
PG8
VSS
I/O FT_fs
-
-
-
-
-
-
-
-
94
95
94 D12 F13 F13
-
-
-
-
S
S
-
-
-
-
-
-
-
-
VDDIO
2
95
96
E3 F12 F12
TIM3_CH1,
TIM8_CH1,
DFSDM1_CKIN3,
SDMMC1_D0DIR,
TSC_G4_IO1,
DCMI_D0, LCD_R0,
SDMMC1_D6,
SAI2_MCLK_A,
EVENTOUT
63 E12 E12 96
E4 F11 F11 65
98 D12 E4
E4 F11
PC6
I/O
FT
-
-
TIM3_CH2,
TIM8_CH2,
DFSDM1_DATIN3,
SDMMC1_D123DIR,
TSC_G4_IO2,
64 E11 E11 97
97
E6 G12 G12 66
99
E9
E6
E6 G11
PC7
I/O
FT
-
-
DCMI_D1, LCD_R1,
SDMMC1_D7,
SAI2_MCLK_B,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
TIM3_CH3,
TIM8_CH3,
TSC_G4_IO3,
DCMI_D2,
65 E10 E10 98
98
D1 G10 G10 67 100 E10 D1 D1
F9
PC8
I/O
FT
-
-
SDMMC1_D0,
EVENTOUT
TRACED0,
TIM8_BKIN2,
TIM3_CH4,
TIM8_CH4, DCMI_D3,
I2C3_SDA,
66 D12 D12 99
99
D2 G9 G9
68 101 C12 D2 D2 G13
PC9
I/O FT_fl
-
-
TSC_G4_IO4,
OTG_FS_NOE,
SDMMC1_D1,
SAI2_EXTCLK,
EVENTOUT
MCO, TIM1_CH1,
SAI1_CK2,
USART1_CK,
OTG_FS_SOF,
SAI1_SCK_A,
LPTIM2_OUT,
EVENTOUT
67 D11 D11 100 100 D3 G8 G8
69 102 D11 D3 D3 E11
PA8
I/O FT_f
-
-
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
TIM1_CH2,
SPI2_SCK, DCMI_D0,
USART1_TX,
68 D10 D10 101 101 D4 F10 F10 70 103 D10 D4 D4 E12
PA9
I/O FT_flu
-
-
OTG_FS_VBUS
SAI1_FS_A,
TIM15_BKIN,
EVENTOUT
TIM1_CH3, SAI1_D1,
DCMI_D1,
USART1_RX,
OTG_FS_ID,
SAI1_SD_A,
69 C12 C12 102 102 D5
F9
F9
71 104 C10 D5 D5 D11 PA10 I/O FT_flu
-
TIM17_BKIN,
EVENTOUT
TIM1_CH4,
TIM1_BKIN2,
SPI1_MISO,
70 B12 B12 103 103 C1 E13 E13 72 105 B12 C1 C1 E13 PA11 I/O FT_u
-
USART1_CTS_NSS,
CAN1_RX,
-
OTG_FS_DM,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
TIM1_ETR,
SPI1_MOSI,
USART1_RTS_DE,
CAN1_TX,
71 A12 A12 104 104 C2 D13 D13 73 106 B11 C2 C2 D13 PA12 I/O FT_u
-
-
OTG_FS_DP,
EVENTOUT
JTMS/SWDIO,
IR_OUT,
OTG_FS_NOE,
SAI1_SD_B,
EVENTOUT
PA13
(JTMS/
SWDIO
)
-
72 A11 A11 105 105 B3 A11 A11 74 107 B10 B3
73 C11 C11 106 106 B2 E12 E12 75 108 C11 B2
B3 A11
B2 D12
I/O
S
FT
-
-
-
(4)
VDDUS
B
-
-
74 F11 F11 107 107 A1 C12 C12 76 109 A12 A1
75 G11 G11 108 108 B1 C13 C13 77 110 A11 B1
A1 C12
B1 C13
VSS
VDD
S
S
-
-
-
-
-
-
-
-
I2C2_SMBA,
OCTOSPIM_P2_CLK,
DCMI_D8,
-
-
-
-
-
-
-
-
-
-
-
-
E11 E11
D12 D12
-
-
-
-
-
-
-
-
-
-
-
-
PH6
PH7
I/O
FT
-
-
-
-
EVENTOUT
I2C3_SCL, DCMI_D9,
EVENTOUT
I/O FT_f
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
I2C3_SMBA,
OCTOSPIM_P2_IO4,
DCMI_D0,
-
-
-
-
-
-
D11 D11
-
-
-
-
-
C11
PH9
I/O
FT
-
-
EVENTOUT
TIM5_CH3,
OCTOSPIM_P2_IO7,
DCMI_D3,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B13 B13
A13 A13
B12 B12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B13 PH12 I/O
A13 PH14 I/O
B12 PH15 I/O
FT
FT
FT
-
-
-
-
-
-
EVENTOUT
TIM8_CH2N,
DCMI_D4,
EVENTOUT
TIM8_CH3N,
OCTOSPIM_P2_IO6,
DCMI_D11,
EVENTOUT
TIM5_CH4,
OCTOSPIM_P1_IO5,
SPI2_NSS,
-
-
-
-
-
-
-
-
-
-
-
-
A12 A12
C11 C11
-
-
-
-
-
-
-
-
-
-
A12
PI0
PI8
I/O
I/O
FT
FT
-
-
-
-
DCMI_D13,
EVENTOUT
OCTOSPIM_P2_NCS,
DCMI_D12,
-
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
SPI2_SCK, DCMI_D8,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
B11 B11
B10 B10
-
-
-
-
-
-
-
-
-
-
B11
B10
PI1
PI2
I/O
I/O
FT
FT
-
-
-
-
TIM8_CH4,
SPI2_MISO,
DCMI_D9,
EVENTOUT
TIM8_ETR,
SPI2_MOSI,
DCMI_D10,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C10 C10
D10 D10
E10 E10
C9 C9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C10
D10
E10
C9
PI3
PI4
PI5
I/O
I/O
I/O
FT
FT
FT
FT
FT
-
-
-
-
-
-
-
-
-
-
TIM8_BKIN,
DCMI_D5,
EVENTOUT
TIM8_CH1,
OCTOSPIM_P2_NCS,
DCMI_VSYNC,
EVENTOUT
TIM8_CH1N,
CAN1_TX,
EVENTOUT
PH13 I/O
TIM8_CH2,
OCTOSPIM_P2_CLK,
DCMI_D6,
B9
B9
B9
PI6
I/O
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
JTCK/SWCLK,
LPTIM1_OUT,
I2C1_SMBA,
I2C4_SMBA,
OTG_FS_SOF,
SAI1_FS_B,
EVENTOUT
PA14
(JTCK/
SWCLK
)
(4)
76 A10 A10 109 109 A2 A10 A10 78 111 A10 A2
A2 A10
I/O
FT
-
JTDI, TIM2_CH1,
TIM2_ETR,
USART2_RX,
SPI1_NSS,
PA15
(JTDI)
SPI3_NSS,
(4)
77
A9
A9 110 110 A3
A9
A9
79 112 B9
A3
A3
A9
I/O
FT
-
USART3_RTS_DE,
UART4_RTS_DE,
TSC_G3_IO1,
SAI2_FS_B,
EVENTOUT
TRACED1,SPI3_SCK,
USART3_TX,
UART4_TX,
TSC_G3_IO2,
DCMI_D8,
78 B11 B11 111 111 C3 D9 D9
80 113 C9 C3 C3 D9
PC10 I/O
FT
-
-
SDMMC1_D2,
SAI2_SCK_B,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
DCMI_D2,
OCTOSPIM_P1_NCS,
SPI3_MISO,
USART3_RX,
UART4_RX,
TSC_G3_IO3,
DCMI_D4,
79 C10 C10 112 112 C4 E9
E9
81 114 A9 C4 C4 E9
PC11 I/O
FT
-
-
SDMMC1_D3,
SAI2_MCLK_B,
EVENTOUT
TRACED3,
SPI3_MOSI,
USART3_CK,
UART5_TX,
TSC_G3_IO4,
DCMI_D9,
SDMMC1_CK,
SAI2_SD_B,
EVENTOUT
80 B10 B10 113 113 B4
F8
B8
F8
B8
82 115 D9 B4
B4
A4
F8
B8
PC12 I/O
FT
FT
-
-
-
-
SPI2_NSS,
DFSDM1_DATIN7,
CAN1_RX, LCD_B4,
FMC_D2, EVENTOUT
81
C9 C9 114 114 A4
83 116 C8 A4
PD0
I/O
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
SPI2_SCK,
DFSDM1_CKIN7,
CAN1_TX, LCD_B5,
FMC_D3, EVENTOUT
82
83
B9
B9 115 115 C5 C8 C8
84 117 B8 C5 C5 C8
PD1
PD2
I/O
I/O
FT
FT
-
-
-
-
TRACED2,
TIM3_ETR,
USART3_RTS_DE,
UART5_RX,
C8 C8 116 116 B5 D8 D8
85 118 D8 B5
B5 D8
TSC_SYNC,
DCMI_D11,
SDMMC1_CMD,
EVENTOUT
SPI2_SCK, DCMI_D5,
SPI2_MISO,
DFSDM1_DATIN0,
USART2_CTS_NSS,
OCTOSPIM_P2_NCS,
LCD_CLK, FMC_CLK,
EVENTOUT
84
85
B8
B7
B8 117 117 D6 E8
E8
86 119 A8 D6 D6 E8
PD3
PD4
I/O
I/O
FT
FT
-
-
-
-
SPI2_MOSI,
DFSDM1_CKIN0,
USART2_RTS_DE,
OCTOSPIM_P1_IO4,
FMC_NOE,
B7 118 118 C6 C7 C7
87 120 C7 C6 C6 C7
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
USART2_TX,
OCTOSPIM_P1_IO5,
FMC_NWE,
86
A6
A6 119 119 A5 D7 D7
88 121 D7 A5
A5 D7
B6 M3
PD5
I/O
FT
-
-
EVENTOUT
-
-
-
-
-
-
120 120 B6 M3 M3
-
-
122
123
-
-
B6
A6
VSS
VDD
S
S
-
-
-
-
-
-
-
-
121 121 A6
A8
A8
A6
A8
SAI1_D1, DCMI_D10,
SPI3_MOSI,
DFSDM1_DATIN1,
USART2_RX,
OCTOSPIM_P1_IO6,
LCD_DE,
87
88
B6
A5
B6 122 122 E7
E7
E7
89 124 B7
E7
E7
E7
PD6
PD7
I/O
I/O
FT
FT
-
-
-
-
FMC_NWAIT,
SAI1_SD_A,
EVENTOUT
DFSDM1_CKIN1,
USART2_CK,
OCTOSPIM_P1_IO7,
FMC_NCE/FMC_NE1,
EVENTOUT
A5 123 123 D7
F7
F7
90 125 E7 D7 D7
F7
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
OCTOSPIM_P2_IO6,
SPI3_SCK,
USART1_TX,
-
-
-
D9 D9 124 124 C7 B7
B7
-
-
-
126 F6
C7 C7 B7
PG9
I/O FT_s
-
-
-
FMC_NCE/FMC_NE2,
SAI2_SCK_A,
-
-
-
TIM15_CH1N,
EVENTOUT
LPTIM1_IN1,
OCTOSPIM_P2_IO7,
SPI3_MISO,
USART1_RX,
FMC_NE3,
SAI2_FS_A,
TIM15_CH1,
EVENTOUT
D8 D8 125 125 B7 D6 D6
127 E6
B7
B7 D6
PG10 I/O FT_s
LPTIM1_IN2,
OCTOSPIM_P1_IO5,
SPI3_MOSI,
USART1_CTS_NSS,
SAI2_MCLK_A,
TIM15_CH2,
G3 G3 126 126
-
E6
E6
128
-
-
-
E6
PG11 I/O FT_s
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
LPTIM1_ETR,
OCTOSPIM_P2_NCS,
SPI3_NSS,
-
D7 D7 127 127 A7
F6
F6
-
129 D6 A7
A7
F6
PG12 I/O FT_s
-
USART1_RTS_DE,
FMC_NE4,
-
SAI2_SD_A,
EVENTOUT
I2C1_SDA,
USART1_CK,
LCD_R0, FMC_A24,
EVENTOUT
-
-
C7 C7 128 128 D8 G7 G7
-
-
-
-
C6 NC D8 G6
PG13 I/O FT_fs
PG14 I/O FT_fs
-
-
-
-
I2C1_SCL, LCD_R1,
FMC_A25,
NC C6 129 129
F7 F7 130 130
-
-
G6 G6
-
-
-
-
EVENTOUT
-
-
-
-
-
-
130 A7
131 A6
-
-
-
VSS
S
S
-
-
-
-
-
-
-
-
VDDIO
2
G7 G7 131 131 A8
B6
B6
A8
A8
B6
LPTIM1_OUT,
I2C1_SMBA,
-
K1
K1 NC 132
-
NC C6
-
132
-
-
-
C6
PG15 I/O FT_s
-
OCTOSPIM_P2_DQS,
DCMI_D13,
-
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
JTDO/TRACESWO,
TIM2_CH2,
PB3
SPI1_SCK,
(JTDO/
TRACE
SWO)
SPI3_SCK,
89
A8
A8 132 133 B8
A6
A6
91 133 B6
B8
B8
A6
I/O FT_la
-
COMP2_INM
USART1_RTS_DE,
OTG_FS_CRS_SYNC
, SAI1_SCK_B,
EVENTOUT
NJTRST, TIM3_CH1,
I2C3_SDA,
SPI1_MISO,
SPI3_MISO,
PB4
USART1_CTS_NSS,
UART5_RTS_DE,
TSC_G2_IO1,
DCMI_D12,
(4)
90
A7
A7 133 134 C8 A5
A5
92 134 A5 C8 C8 A5 (NJTRS I/O FT_fa
T)
COMP2_INP
SAI1_MCLK_B,
TIM17_BKIN,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
LPTIM1_IN1,
TIM3_CH2,
I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI,
USART1_CK,
UART5_CTS,
TSC_G2_IO2,
DCMI_D10,
91
C5 C5 134 135 E8
B5
B5
93 135 B5
E8
E8
B5
PB5
I/O FT_la
-
-
COMP2_OUT,
SAI1_SD_B,
TIM16_BKIN,
EVENTOUT
LPTIM1_ETR,
TIM4_CH1,
TIM8_BKIN2,
I2C1_SCL, I2C4_SCL,
DFSDM1_DATIN5,
USART1_TX,
TSC_G2_IO3,
DCMI_D5,
92
B5
B5 135 136 C9 C5 C5
94 136 D5 C9 C9 C5
PB6
I/O FT_fa
-
COMP2_INP
SAI1_FS_B,
TIM16_CH1N,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
LPTIM1_IN2,
TIM4_CH2,
TIM8_BKIN,
I2C1_SDA,I2C4_SDA,
DFSDM1_CKIN5,
USART1_RX,
COMP2_INM,
PVD_IN
93
B4
B4 136 137 A9 D5 D5
95 137 C5 A9
A9 D5
PB7
I/O FT_fla
-
UART4_CTS,
TSC_G2_IO4,
DCMI_VSYNC,
DSI_TE, FMC_NL,
TIM17_CH1N,
EVENTOUT
PH3-
BOOT0
94
95
A4
A3
A4 137 138 B9
E5
E5
96 138 A4
B9
B9
E5
I/O
FT
-
-
EVENTOUT
-
-
TIM4_CH3,
SAI1_CK1, I2C1_SCL,
DFSDM1_CKOUT,
DFSDM1_DATIN6,
SDMMC1_CKIN,
CAN1_RX, DCMI_D6,
LCD_B1,
A3 138 139 C10 C4 C4
97 139 B4 C10 C10 C4
PB8
I/O FT_fl
SDMMC1_D4,
SAI1_MCLK_A,
TIM16_CH1,
EVENTOUT
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
IR_OUT, TIM4_CH4,
SAI1_D2, I2C1_SDA,
SPI2_NSS,
DFSDM1_CKIN6,
SDMMC1_CDIR,
CAN1_TX, DCMI_D7,
SDMMC1_D5,
96
B3
B3 139 140 B10 D4 D4
98 140 A3 B10 B10 D4
PB9
I/O FT_fl
-
-
SAI1_FS_A,
TIM17_CH1,
EVENTOUT
TIM4_ETR, DCMI_D2,
LCD_HSYNC,
FMC_NBL0,
97
98
C3 C3 140 141 A10 A4
A4
B4
-
141 A2 A10 A10 A4
PE0
PE1
I/O
I/O
FT
FT
-
-
-
-
TIM16_CH1,
EVENTOUT
DCMI_D3,
LCD_VSYNC,
FMC_NBL1,
TIM17_CH1,
EVENTOUT
A2
C6
A2 141 142 A11 B4
-
-
142 C4 D8 A11 B4
-
-
142
-
-
C6
-
-
-
A11
-
-
VDD12
VSS
-
-
-
-
-
-
-
-
-
-
-
-
-
99
D3 D3 143 143 A12 B3
B3
99 143 A1 A12 A12 B3
S
S
100 C4 C4 144 144 B12 A3
A3 100 144 B2 B12 B12 A3
VDD
Table 15. STM32L4Rxxx pin definitions (continued)
Pin number
STM32L4R5xxx, STM32L4R7xxx
STM32L4R9xxx
OCTOSPIM_P1_IO4,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
A2
B2
A2
B2
-
-
-
-
-
-
-
-
-
-
A2
B2
PH2
PI7
I/O
I/O
FT
FT
-
-
-
-
TIM8_CH3, DCMI_D7,
EVENTOUT
OCTOSPIM_P2_IO2,
CAN1_RX,
-
-
-
-
-
-
-
-
-
-
-
-
B1
A1
B1
A1
-
-
-
-
-
-
-
-
-
-
B1
A1
PI9
I/O
I/O
FT
FT
-
-
-
-
EVENTOUT
OCTOSPIM_P2_IO1,
EVENTOUT
PI10
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (for example to drive a LED).
2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the
system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0432 reference manual.
3. NC (not-connected) balls must be left unconnected. However, non connected (NC) GPIOS are not bonded. They must be configured by software to output push-pull and
forced to 0 in the output data register to avoid extra current consumption in low-power modes.
4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are
activated.
(1)
Table 16. Alternate function AF0 to AF7
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/U
Port
SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS
DM1/DCMI/OCTOS DM1/COMP1/O
OTG_FS/ TIM1/2/5/8/L TIM1/2/3/4/ SART2/OTG_FS/T I2C1/2/3/4/DC
USART1/2/3
SYS_AF
PTIM1
5
IM1/8/OCTOSPIM
_P1
MI
PIM_P1/2
CTOSPIM_P2
PA0
-
-
-
-
TIM2_CH1
TIM2_CH2
TIM2_CH3
TIM2_CH4
TIM5_CH1
TIM5_CH2
TIM5_CH3
TIM5_CH4
TIM8_ETR
-
-
-
-
-
-
USART2_CTS_NSS
USART2_RTS_DE
USART2_TX
-
I2C1_SMBA
SPI1_SCK
PA1
PA2
PA3
-
-
-
-
-
SAI1_CK1
USART2_RX
OCTOSPIM_P1_NC
S
-
-
-
-
-
-
SPI1_NSS
SPI1_SCK
SPI3_NSS
-
USART2_CK
-
PA4
PA5
TIM2_CH1
TIM2_ETR
TIM8_CH1N
PA6
-
TIM1_BKIN
TIM3_CH1
TIM8_BKIN
DCMI_PIXCLK
SPI1_MISO
-
USART3_CTS_NSS
-
TIM1_CH1N
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM3_CH2
TIM8_CH1N
SAI1_CK2
SPI2_SCK
SAI1_D1
I2C3_SCL
SPI1_MOSI
-
-
-
-
-
-
PA7
PA8
Port
A
MCO
-
-
-
-
-
-
USART1_CK
USART1_TX
USART1_RX
-
-
DCMI_D0
DCMI_D1
PA9
PA10
-
TIM1_CH4
TIM1_BKIN2
-
-
SPI1_MISO
-
USART1_CTS_NSS
PA11
-
TIM1_ETR
IR_OUT
-
-
-
-
-
-
SPI1_MOSI
-
-
-
USART1_RTS_DE
-
PA12
PA13
JTMS/SW
DIO
JTCK/SW
CLK
LPTIM1_OUT
TIM2_CH1
-
-
I2C1_SMBA
-
I2C4_SMBA
SPI1_NSS
-
-
PA14
PA15
JTDI
TIM2_ETR
USART2_RX
SPI3_NSS
USART3_RTS_DE
(1)
Table 16. Alternate function AF0 to AF7
(continued)
AF5
AF0
AF1
AF2
AF3
AF4
AF6
AF7
SPI2/SAI1/I2C4/U
SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS
DM1/DCMI/OCTOS DM1/COMP1/O
Port
OTG_FS/ TIM1/2/5/8/L TIM1/2/3/4/ SART2/OTG_FS/T I2C1/2/3/4/DC
USART1/2/3
SYS_AF
PTIM1
5
IM1/8/OCTOSPIM
_P1
MI
PIM_P1/2
CTOSPIM_P2
-
-
TIM1_CH2N
TIM1_CH3N
TIM3_CH3
TIM3_CH4
-
TIM8_CH2N
TIM8_CH3N
-
-
SPI1_NSS
-
USART3_CK
PB0
-
-
-
DFSDM1_DATIN0
DFSDM1_CKIN0
USART3_RTS_DE
-
PB1
PB2
RTC_OUT LPTIM1_OUT
I2C3_SMBA
JTDO/TRA
TIM2_CH2
CESWO
-
-
-
SPI1_SCK
SPI3_SCK
USART1_RTS_DE
PB3
NJTRST
-
-
TIM3_CH1
TIM3_CH2
-
-
I2C3_SDA
SPI1_MISO
SPI1_MOSI
SPI3_MISO
SPI3_MOSI
USART1_CTS_NSS
USART1_CK
PB4
PB5
LPTIM1_IN1
I2C1_SMBA
-
LPTIM1_ETR
TIM4_CH1
TIM8_BKIN2
I2C1_SCL
I2C4_SCL
DFSDM1_DATIN5
USART1_TX
PB6
Port
B
-
-
-
-
-
-
-
-
LPTIM1_IN2
-
TIM4_CH2
TIM8_BKIN
SAI1_CK1
SAI1_D2
I2C4_SCL
I2C4_SDA
TIM1_BKIN
-
I2C1_SDA
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C2_SDA
I2C2_SMBA
I2C2_SCL
I2C2_SDA
I2C4_SDA
DFSDM1_CKOUT
SPI2_NSS
SPI2_SCK
-
DFSDM1_CKIN5
DFSDM1_DATIN6
DFSDM1_CKIN6
DFSDM1_DATIN7
DFSDM1_CKIN7
DFSDM1_DATIN1
DFSDM1_CKIN1
DFSDM1_DATIN2
USART1_RX
-
PB7
PB8
TIM4_CH3
IR_OUT
TIM4_CH4
-
PB9
TIM2_CH3
TIM2_CH4
TIM1_BKIN
TIM1_CH1N
TIM1_CH2N
-
-
-
-
-
USART3_TX
USART3_RX
USART3_CK
USART3_CTS_NSS
USART3_RTS_DE
PB10
PB11
PB12
PB13
PB14
SPI2_NSS
SPI2_SCK
SPI2_MISO
TIM8_CH2N
RTC_
REFIN
TIM1_CH3N
-
TIM8_CH3N
-
SPI2_MOSI
DFSDM1_CKIN2
-
PB15
(1)
Table 16. Alternate function AF0 to AF7
(continued)
AF5
AF0
AF1
AF2
AF3
AF4
AF6
AF7
SPI2/SAI1/I2C4/U
SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS
DM1/DCMI/OCTOS DM1/COMP1/O
Port
OTG_FS/ TIM1/2/5/8/L TIM1/2/3/4/ SART2/OTG_FS/T I2C1/2/3/4/DC
USART1/2/3
SYS_AF
PTIM1
5
IM1/8/OCTOSPIM
_P1
MI
PIM_P1/2
CTOSPIM_P2
-
LPTIM1_IN1
-
-
I2C3_SCL
-
DFSDM1_DATIN4
-
PC0
TRACED0 LPTIM1_OUT
-
SPI2_MOSI
-
I2C3_SDA
-
DFSDM1_CKIN4
-
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
-
-
-
-
-
-
-
LPTIM1_IN2
-
-
SPI2_MISO
DFSDM1_CKOUT
-
LPTIM1_ETR
-
SAI1_D1
-
-
SPI2_MOSI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART3_TX
-
SAI1_D3
TIM8_CH1
TIM8_CH2
TIM8_CH3
TIM8_CH4
-
-
USART3_RX
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
-
DFSDM1_CKIN3
DFSDM1_DATIN3
-
-
-
-
-
-
-
Port
C
TRACED0 TIM8_BKIN2
DCMI_D3
I2C3_SDA
PC10 TRACED1
-
-
-
-
-
-
-
-
-
-
-
SPI3_SCK
SPI3_MISO
SPI3_MOSI
USART3_TX
USART3_RX
USART3_CK
-
DCMI_D2
-
OCTOSPIM_P1_NCS
-
PC11
PC12
TRACED3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PC13
PC14
PC15
(1)
Table 16. Alternate function AF0 to AF7
(continued)
AF5
AF0
AF1
AF2
AF3
AF4
AF6
AF7
SPI2/SAI1/I2C4/U
SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS
DM1/DCMI/OCTOS DM1/COMP1/O
Port
OTG_FS/ TIM1/2/5/8/L TIM1/2/3/4/ SART2/OTG_FS/T I2C1/2/3/4/DC
USART1/2/3
SYS_AF
PTIM1
5
IM1/8/OCTOSPIM
_P1
MI
PIM_P1/2
CTOSPIM_P2
-
-
-
-
-
-
-
-
-
-
SPI2_NSS
SPI2_SCK
DFSDM1_DATIN7
DFSDM1_CKIN7
-
-
PD0
PD1
PD2
TRACED2
-
TIM3_ETR
-
-
-
-
USART3_RTS_DE
-
-
-
-
-
-
-
-
-
SPI2_SCK
DCMI_D5
SPI2_MISO
SPI2_MOSI
-
DFSDM1_DATIN0
USART2_CTS_NSS
USART2_RTS_DE
USART2_TX
PD3
PD4
PD5
-
-
-
-
DFSDM1_CKIN0
-
-
-
-
SAI1_D1
DCMI_D10
SPI3_MOSI
DFSDM1_DATIN1
USART2_RX
PD6
Port
D
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DFSDM1_CKIN1
USART2_CK
PD7
PD8
-
-
-
-
-
-
-
-
-
-
USART3_TX
-
-
USART3_RX
PD9
-
-
USART3_CK
PD10
PD11
PD12
PD13
PD14
PD15
-
I2C4_SMBA
USART3_CTS_NSS
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
I2C4_SCL
USART3_RTS_DE
I2C4_SDA
-
-
-
-
-
(1)
Table 16. Alternate function AF0 to AF7
(continued)
AF5
AF0
AF1
AF2
AF3
AF4
AF6
AF7
SPI2/SAI1/I2C4/U
SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS
DM1/DCMI/OCTOS DM1/COMP1/O
Port
OTG_FS/ TIM1/2/5/8/L TIM1/2/3/4/ SART2/OTG_FS/T I2C1/2/3/4/DC
USART1/2/3
SYS_AF
PTIM1
5
IM1/8/OCTOSPIM
_P1
MI
PIM_P1/2
CTOSPIM_P2
-
-
-
-
TIM4_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PE0
-
-
PE1
PE2
TRACECK
TIM3_ETR
SAI1_CK1
OCTOSPIM_P1_DQ
S
TRACED0
-
TIM3_CH1
-
-
-
-
PE3
TRACED1
-
TIM3_CH2
SAI1_D2
-
-
-
-
-
-
-
-
-
-
-
-
-
DFSDM1_DATIN3
DFSDM1_CKIN3
-
-
-
-
-
-
-
-
-
-
-
-
-
PE4
PE5
TRACED2
-
TIM3_CH3
SAI1_CK2
-
TRACED3
-
TIM3_CH4
SAI1_D1
-
PE6
Port
E
-
-
-
-
-
-
-
-
-
TIM1_ETR
TIM1_CH1N
TIM1_CH1
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
TIM1_CH4
TIM1_BKIN
-
-
-
DFSDM1_DATIN2
DFSDM1_CKIN2
DFSDM1_CKOUT
DFSDM1_DATIN4
DFSDM1_CKIN4
DFSDM1_DATIN5
DFSDM1_CKIN5
-
PE7
-
-
-
PE8
-
-
-
PE9
PE10
PE11
PE12
PE13
PE14
PE15
-
-
-
-
-
-
-
-
SPI1_NSS
SPI1_SCK
SPI1_MISO
SPI1_MOSI
-
-
TIM1_BKIN2
-
TIM1_BKIN2
TIM1_BKIN
-
(1)
Table 16. Alternate function AF0 to AF7
(continued)
AF5
AF0
AF1
AF2
AF3
AF4
AF6
AF7
SPI2/SAI1/I2C4/U
SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS
DM1/DCMI/OCTOS DM1/COMP1/O
Port
OTG_FS/ TIM1/2/5/8/L TIM1/2/3/4/ SART2/OTG_FS/T I2C1/2/3/4/DC
USART1/2/3
SYS_AF
PTIM1
5
IM1/8/OCTOSPIM
_P1
MI
PIM_P1/2
CTOSPIM_P2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C2_SDA
OCTOSPIM_P2_IO0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF0
-
-
-
I2C2_SCL
OCTOSPIM_P2_IO1
-
PF1
PF2
-
-
-
I2C2_SMBA
OCTOSPIM_P2_IO2
-
-
-
-
-
OCTOSPIM_P2_IO3
-
PF3
-
-
-
-
OCTOSPIM_P2_CLK
-
PF4
-
-
-
-
-
-
PF5
TIM5_ETR
TIM5_CH1
-
-
-
-
PF6
-
-
-
-
-
-
-
-
-
TIM5_CH2
-
-
-
-
PF7
Port
F
TIM5_CH3
-
-
-
-
PF8
TIM5_CH4
-
-
-
-
PF9
-
-
-
-
-
-
OCTOSPIM_P1_CLK
-
-
DFSDM1_CKOUT
PF10
PF11
PF12
PF13
PF14
PF15
-
-
-
-
-
-
-
-
-
OCTOSPIM_P2_DQS
-
I2C4_SMBA
I2C4_SCL
I2C4_SDA
-
-
-
DFSDM1_DATIN6
DFSDM1_CKIN6
-
(1)
Table 16. Alternate function AF0 to AF7
(continued)
AF5
AF0
AF1
AF2
AF3
AF4
AF6
AF7
SPI2/SAI1/I2C4/U
SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS
DM1/DCMI/OCTOS DM1/COMP1/O
Port
OTG_FS/ TIM1/2/5/8/L TIM1/2/3/4/ SART2/OTG_FS/T I2C1/2/3/4/DC
USART1/2/3
SYS_AF
PTIM1
5
IM1/8/OCTOSPIM
_P1
MI
PIM_P1/2
CTOSPIM_P2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OCTOSPIM_P2_IO4
OCTOSPIM_P2_IO5
SPI1_SCK
-
-
-
-
-
-
-
-
-
-
-
-
PG0
PG1
PG2
PG3
PG4
PG5
SPI1_MISO
SPI1_MOSI
SPI1_NSS
OCTOSPIM_P1_DQ
S
-
-
-
I2C3_SMBA
-
-
-
PG6
-
-
-
-
-
-
SAI1_CK1
-
I2C3_SCL
I2C3_SDA
OCTOSPIM_P2_DQS DFSDM1_CKOUT
-
-
PG7
PG8
Port
G
-
-
-
-
-
-
-
OCTOSPIM_P2_IO6
SPI3_SCK
USART1_TX
PG9
-
-
-
-
-
-
LPTIM1_IN1
-
-
-
-
-
-
-
-
OCTOSPIM_P2_IO7
SPI3_MISO
USART1_RX
PG10
PG11
PG12
PG13
PG14
PG15
LPTIM1_IN2
OCTOSPIM_P1_IO5
-
-
SPI3_MOSI
USART1_CTS_NSS
LPTIM1_ETR
-
-
-
-
-
OCTOSPIM_P2_NCS
SPI3_NSS
USART1_RTS_DE
-
I2C1_SDA
I2C1_SCL
I2C1_SMBA
-
-
-
-
USART1_CK
-
-
-
-
LPTIM1_OUT
OCTOSPIM_P2_DQS
(1)
Table 16. Alternate function AF0 to AF7
(continued)
AF5
AF0
AF1
AF2
AF3
AF4
AF6
AF7
SPI2/SAI1/I2C4/U
SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS
DM1/DCMI/OCTOS DM1/COMP1/O
Port
OTG_FS/ TIM1/2/5/8/L TIM1/2/3/4/ SART2/OTG_FS/T I2C1/2/3/4/DC
USART1/2/3
SYS_AF
PTIM1
5
IM1/8/OCTOSPIM
_P1
MI
PIM_P1/2
CTOSPIM_P2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PH0
-
-
-
-
PH1
PH2
-
OCTOSPIM_P1_IO4
-
-
-
-
-
-
PH3
-
-
I2C2_SCL
OCTOSPIM_P2_DQS
PH4
-
-
I2C2_SDA
-
PH5
-
-
I2C2_SMBA
OCTOSPIM_P2_CLK
-
PH6
-
-
I2C3_SCL
PH7
Port
H
-
-
I2C3_SDA
OCTOSPIM_P2_IO3
OCTOSPIM_P2_IO4
OCTOSPIM_P2_IO5
OCTOSPIM_P2_IO6
OCTOSPIM_P2_IO7
-
PH8
-
-
I2C3_SMBA
PH9
TIM5_CH1
-
-
-
-
-
-
-
PH10
PH11
PH12
PH13
PH14
PH15
TIM5_CH2
-
TIM5_CH3
-
-
-
-
TIM8_CH1N
TIM8_CH2N
TIM8_CH3N
-
OCTOSPIM_P2_IO6
(1)
Table 16. Alternate function AF0 to AF7
(continued)
AF5
AF0
AF1
AF2
AF3
AF4
AF6
AF7
SPI2/SAI1/I2C4/U
SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS
DM1/DCMI/OCTOS DM1/COMP1/O
Port
OTG_FS/ TIM1/2/5/8/L TIM1/2/3/4/ SART2/OTG_FS/T I2C1/2/3/4/DC
USART1/2/3
SYS_AF
PTIM1
5
IM1/8/OCTOSPIM
_P1
MI
PIM_P1/2
CTOSPIM_P2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM5_CH4
OCTOSPIM_P1_IO5
-
-
-
-
-
-
-
-
-
-
-
-
SPI2_NSS
SPI2_SCK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PI0
-
-
-
-
-
-
-
-
-
-
-
-
PI1
PI2
PI3
PI4
PI5
PI6
PI7
PI8
PI9
PI10
PI11
TIM8_CH4
SPI2_MISO
TIM8_ETR
SPI2_MOSI
TIM8_BKIN
-
TIM8_CH1
OCTOSPIM_P2_NCS
OCTOSPIM_P2_CLK
-
Port I
TIM8_CH2
TIM8_CH3
-
-
-
-
OCTOSPIM_P2_NCS
OCTOSPIM_P2_IO2
OCTOSPIM_P2_IO1
OCTOSPIM_P2_IO0
1. Refer to Table 17 for AF8 to AF15.
(1)
Table 17. Alternate function AF8 to AF15
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/
LPUART1/
CAN2
SDMMC/
COMP1/2/
FMC
OTG_FS/DCMI/
OCTOSPI_P1/P2
TIM2/15/16/17/
LPTIM2
CAN1/TSC
LCD
SAI1/2
EVENOUT
PA0
PA1
UART4_TX
UART4_RX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI1_EXTCLK
TIM2_ETR
TIM15_CH1N
TIM15_CH1
TIM15_CH2
LPTIM2_OUT
LPTIM2_ETR
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
OCTOSPIM_P1_DQS
OCTOSPIM_P1_NCS
OCTOSPIM_P1_CLK
DCMI_HSYNC
-
-
PA2 LPUART1_TX
PA3 LPUART1_RX
SAI2_EXTCLK
SAI1_MCLK_A
SAI1_FS_B
-
PA4
PA5
-
-
LPUART1_CT
S
PA6
-
OCTOSPIM_P1_IO3
-
TIM1_BKIN
TIM8_BKIN
TIM16_CH1
EVENTOUT
PA7
PA8
-
-
-
-
-
-
-
-
OCTOSPIM_P1_IO2
OTG_FS_SOF
-
-
-
-
-
-
-
-
-
-
TIM17_CH1
LPTIM2_OUT
TIM15_BKIN
TIM17_BKIN
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
Port A
SAI1_SCK_A
SAI1_FS_A
SAI1_SD_A
PA9
PA10
OTG_FS_ID
PA11
-
CAN1_RX
OTG_FS_DM
-
TIM1_BKIN2
-
-
EVENTOUT
PA12
PA13
PA14
-
-
-
CAN1_TX
OTG_FS_DP
OTG_FS_NOE
OTG_FS_SOF
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
-
-
SAI1_SD_B
SAI1_FS_B
UART4_RTS_
DE
PA15
TSC_G3_IO1
-
-
-
SAI2_FS_B
-
EVENTOUT
(1)
Table 17. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/
LPUART1/
CAN2
SDMMC/
COMP1/2/
FMC
OTG_FS/DCMI/
OCTOSPI_P1/P2
TIM2/15/16/17/
LPTIM2
CAN1/TSC
LCD
SAI1/2
EVENOUT
PB0
-
-
-
OCTOSPIM_P1_IO1
OCTOSPIM_P1_IO0
-
-
COMP1_OUT SAI1_EXTCLK
-
EVENTOUT
EVENTOUT
LPUART1_
RTS_DE
PB1
-
-
LPTIM2_IN1
PB2
PB3
-
-
-
-
OCTOSPIM_P1_DQS
OTG_FS_CRS_SYNC
LCD_B1
-
-
-
-
-
-
EVENTOUT
EVENTOUT
SAI1_SCK_B
UART5_RTS_
DE
PB4
PB5
TSC_G2_IO1
DCMI_D12
DCMI_D10
-
-
-
SAI1_MCLK_B TIM17_BKIN
EVENTOUT
EVENTOUT
UART5_CTS TSC_G2_IO2
TSC_G2_IO3
COMP2_OUT
SAI1_SD_B
SAI1_FS_B
TIM8_BKIN
TIM16_BKIN
TIM16_CH1N
PB6
-
DCMI_D5
-
TIM8_BKIN2
FMC_NL
EVENTOUT
PB7
PB8
UART4_CTS TSC_G2_IO4
DCMI_VSYNC
DCMI_D6
DSI_TE
LCD_B1
TIM17_CH1N
TIM16_CH1
EVENTOUT
EVENTOUT
SDMMC1_
CAN1_RX
CKIN
Port B
SDMMC1_D4 SAI1_MCLK_A
SDMMC1_D5 SAI1_FS_A
COMP1_OUT SAI1_SCK_A
SDMMC1_
CAN1_TX
CDIR
PB9
DCMI_D7
-
TIM17_CH1
EVENTOUT
PB10 LPUART1_RX TSC_SYNC OCTOSPIM_P1_CLK
-
-
-
EVENTOUT
EVENTOUT
PB11 LPUART1_TX
-
OCTOSPIM_P1_NCS
-
DSI_TE
COMP2_OUT
-
-
LPUART1_RT
PB12
S_DE
TSC_G1_IO1
-
SAI2_FS_A
TIM15_BKIN
EVENTOUT
LPUART1_CT
PB13
S
TSC_G1_IO2
TSC_G1_IO3
-
-
-
-
-
-
SAI2_SCK_A
TIM15_CH1N
TIM15_CH1
EVENTOUT
EVENTOUT
PB14
-
SAI2_MCLK_A
PB15
-
TSC_G1_IO4
-
-
-
SAI2_SD_A
TIM15_CH2
EVENTOUT
(1)
Table 17. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/
LPUART1/
CAN2
SDMMC/
COMP1/2/
FMC
OTG_FS/DCMI/
OCTOSPI_P1/P2
TIM2/15/16/17/
LPTIM2
CAN1/TSC
LCD
SAI1/2
EVENOUT
PC0 LPUART1_RX
PC1 LPUART1_TX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI2_FS_A
LPTIM2_IN1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
OCTOSPIM_P1_IO4
OCTOSPIM_P1_IO5
OCTOSPIM_P1_IO6
OCTOSPIM_P1_IO7
-
SAI1_SD_A
-
PC2
PC3
PC4
PC5
-
-
-
-
-
-
SAI1_SD_A
LPTIM2_ETR
-
-
-
-
SDMMC1_
D0DIR
PC6
PC7
TSC_G4_IO1
TSC_G4_IO2
DCMI_D0
DCMI_D1
LCD_R0
LCD_R1
SDMMC1_D6 SAI2_MCLK_A
SDMMC1_D7 SAI2_MCLK_B
-
-
EVENTOUT
EVENTOUT
SDMMC1_
D123DIR
PC8
PC9
-
-
TSC_G4_IO3
TSC_G4_IO4
DCMI_D2
-
-
SDMMC1_D0
-
-
EVENTOUT
EVENTOUT
Port C
OTG_FS_NOE
SDMMC1_D1 SAI2_EXTCLK
SDMMC1_D2 SAI2_SCK_B
TIM8_BKIN2
PC10
PC11
PC12
UART4_TX TSC_G3_IO2
UART4_RX TSC_G3_IO3
UART5_TX TSC_G3_IO4
DCMI_D8
DCMI_D4
DCMI_D9
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
SDMMC1_D3 SAI2_MCLK_B
SDMMC1_CK
SAI2_SD_B
PC13
PC14
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
(1)
Table 17. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/
LPUART1/
CAN2
SDMMC/
COMP1/2/
FMC
OTG_FS/DCMI/
OCTOSPI_P1/P2
TIM2/15/16/17/
LPTIM2
CAN1/TSC
LCD
SAI1/2
EVENOUT
PD0
-
-
CAN1_RX
CAN1_TX
-
-
LCD_B4
LCD_B5
FMC_D2
FMC_D3
-
-
-
-
EVENTOUT
EVENTOUT
PD1
PD2
SDMMC1_CM
D
UART5_RX
TSC_SYNC
DCMI_D11
-
-
-
EVENTOUT
PD3
PD4
PD5
-
-
-
-
-
-
OCTOSPIM_P2_NCS
OCTOSPIM_P1_IO4
OCTOSPIM_P1_IO5
LCD_CLK
FMC_CLK
FMC_NOE
FMC_NWE
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
-
-
PD6
PD7
-
-
-
-
OCTOSPIM_P1_IO6
OCTOSPIM_P1_IO7
LCD_DE
-
FMC_NWAIT
SAI1_SD_A
-
-
-
EVENTOUT
EVENTOUT
Port D
FMC_NCE/FM
C_NE1
PD8
PD9
-
-
-
-
-
-
-
-
-
DCMI_HSYNC
LCD_R3
LCD_R4
LCD_R5
LCD_R6
LCD_R7
-
FMC_D13
FMC_D14
FMC_D15
FMC_A16
FMC_A17
FMC_A18
FMC_D0
FMC_D1
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
-
DCMI_PIXCLK
SAI2_MCLK_A
-
PD10
PD11
PD12
PD13
PD14
PD15
TSC_G6_IO1
TSC_G6_IO2
TSC_G6_IO3
TSC_G6_IO4
-
-
-
-
-
-
-
SAI2_SCK_A
-
SAI2_SD_A
LPTIM2_ETR
SAI2_FS_A
LPTIM2_IN1
-
-
-
LPTIM2_OUT
LCD_B2
LCD_B3
-
-
-
(1)
Table 17. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/
LPUART1/
CAN2
SDMMC/
COMP1/2/
FMC
OTG_FS/DCMI/
OCTOSPI_P1/P2
TIM2/15/16/17/
LPTIM2
CAN1/TSC
LCD
SAI1/2
EVENOUT
PE0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DCMI_D2
LCD_HSYNC
LCD_VSYNC
LCD_R0
LCD_R1
LCD_B0
LCD_G0
LCD_G1
LCD_B6
LCD_B7
LCD_G2
LCD_G3
LCD_G4
LCD_G5
LCD_G6
LCD_G7
LCD_R2
FMC_NBL0
FMC_NBL1
FMC_A23
FMC_A19
FMC_A20
FMC_A21
FMC_A22
FMC_D4
-
TIM16_CH1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
PE1
PE2
-
DCMI_D3
-
TIM17_CH1
TSC_G7_IO1
-
SAI1_MCLK_A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PE3
TSC_G7_IO2
-
SAI1_SD_B
PE4
TSC_G7_IO3
DCMI_D4
SAI1_FS_A
PE5
TSC_G7_IO4
DCMI_D6
SAI1_SCK_A
PE6
-
-
-
-
DCMI_D7
SAI1_SD_A
PE7
-
-
-
SAI1_SD_B
Port E
PE8
FMC_D5
SAI1_SCK_B
PE9
FMC_D6
SAI1_FS_B
PE10
PE11
PE12
PE13
PE14
PE15
TSC_G5_IO1 OCTOSPIM_P1_CLK
TSC_G5_IO2 OCTOSPIM_P1_NCS
TSC_G5_IO3 OCTOSPIM_1_IO0
TSC_G5_IO4 OCTOSPIM_P1_IO1
FMC_D7
SAI1_MCLK_B
FMC_D8
-
-
-
-
-
FMC_D9
FMC_D10
FMC_D11
FMC_D12
-
-
OCTOSPIM_P1_IO2
OCTOSPIM_P1_IO3
(1)
Table 17. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/
LPUART1/
CAN2
SDMMC/
COMP1/2/
FMC
OTG_FS/DCMI/
OCTOSPI_P1/P2
TIM2/15/16/17/
LPTIM2
CAN1/TSC
LCD
SAI1/2
EVENOUT
PF0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A0
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
PF1
PF2
-
-
-
FMC_A1
-
-
-
-
-
FMC_A2
-
-
PF3
-
-
-
FMC_A3
-
-
PF4
-
-
-
FMC_A4
-
-
PF5
-
-
-
FMC_A5
-
-
PF6
-
OCTOSPIM_P1_IO3
-
-
SAI1_SD_B
-
PF7
-
OCTOSPIM_P1_IO2
-
-
SAI1_MCLK_B
-
Port F
PF8
-
OCTOSPIM_P1_IO0
-
-
SAI1_SCK_B
-
PF9
-
OCTOSPIM_P1_IO1
-
-
SAI1_FS_B
TIM15_CH1
PF10
PF11
PF12
PF13
PF14
PF15
-
DCMI_D11
-
-
SAI1_D3
TIM15_CH2
LCD_DE
DCMI_D12
DSI_TE
LCD_B0
LCD_B1
LCD_G0
LCD_G1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A6
FMC_A7
FMC_A8
FMC_A9
-
TSC_G8_IO1
TSC_G8_IO2
(1)
Table 17. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/
LPUART1/
CAN2
SDMMC/
COMP1/2/
FMC
OTG_FS/DCMI/
OCTOSPI_P1/P2
TIM2/15/16/17/
LPTIM2
CAN1/TSC
LCD
SAI1/2
EVENOUT
PG0
-
-
-
-
-
TSC_G8_IO3
-
-
-
-
-
-
-
-
-
-
FMC_A10
FMC_A11
FMC_A12
FMC_A13
FMC_A14
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
PG1
PG2
PG3
PG4
TSC_G8_IO4
-
-
-
-
SAI2_SCK_B
SAI2_FS_B
SAI2_MCLK_B
LPUART1_CT
S
PG5
PG6
-
-
-
-
FMC_A15
-
SAI2_SD_B
-
-
-
EVENTOUT
EVENTOUT
LPUART1_RT
S_DE
LCD_R1
DSI_TE
PG7 LPUART1_TX
PG8 LPUART1_RX
-
-
-
-
-
-
FMC_INT
-
SAI1_MCLK_A
-
-
-
EVENTOUT
EVENTOUT
Port G
FMC_NCE/FM
C_NE2
PG9
-
-
-
-
SAI2_SCK_A
TIM15_CH1N
EVENTOUT
PG10
PG11
PG12
PG13
PG14
PG15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_NE3
-
SAI2_FS_A
TIM15_CH1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
-
-
SAI2_MCLK_A
TIM15_CH2
-
-
FMC_NE4
FMC_A24
FMC_A25
-
SAI2_SD_A
-
-
-
-
-
LCD_R0
LCD_R1
-
-
-
-
-
DCMI_D13
(1)
Table 17. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/
LPUART1/
CAN2
SDMMC/
COMP1/2/
FMC
OTG_FS/DCMI/
OCTOSPI_P1/P2
TIM2/15/16/17/
LPTIM2
CAN1/TSC
LCD
SAI1/2
EVENOUT
PH0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
PH1
PH2
-
-
-
PH3
-
-
PH4
-
-
PH5
-
DCMI_PIXCLK
DCMI_D8
DCMI_D9
DCMI_HSYNC
DCMI_D0
DCMI_D1
DCMI_D2
DCMI_D3
-
PH6
-
PH7
-
Port H
PH8
-
PH9
-
PH10
PH11
PH12
PH13
PH14
PH15
-
-
-
CAN1_TX
-
-
DCMI_D4
DCMI_D11
(1)
Table 17. Alternate function AF8 to AF15 (continued)
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
Port
UART4/5/
LPUART1/
CAN2
SDMMC/
COMP1/2/
FMC
OTG_FS/DCMI/
OCTOSPI_P1/P2
TIM2/15/16/17/
LPTIM2
CAN1/TSC
LCD
SAI1/2
EVENOUT
PI0
PI1
PI2
PI3
PI4
PI5
PI6
PI7
PI8
PI9
-
-
-
-
-
-
-
-
-
-
-
-
-
DCMI_D13
DCMI_D8
DCMI_D9
DCMI_D10
DCMI_D5
DCMI_VSYNC
DCMI_D6
DCMI_D7
DCMI_D12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
-
-
-
-
-
Port I
-
-
-
CAN1_RX
PI10
PI11
-
-
-
-
1. Refer to Table 16 for AF0 to AF7.
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Memory mapping
5
Memory mapping
For memory map and peripheral register boundary addresses refer to the corresponding
section of reference manual RM0432.
DS12023 Rev 5
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135
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = V = 3 V. They
DDA
are given only as design guidelines and are not tested.
A
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 23.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 24.
Figure 23. Pin loading conditions
Figure 24. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19210V1
MS19211V1
136/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
6.1.6
Power supply scheme
Figure 25. Power supply scheme
VBAT
Backup circuitry
(LSE, RTC,
Backup registers)
1.55 – 3.6 V
Power switch
2 x VDD12
1.05 – 1.32 V
VDD
VCORE
n x VDD
Regulator
VDDIO1
OUT
Kernel logic
(CPU, Digital
& Memories)
IO
logic
n x 100 nF
+1 x 4.7 μF
GPIOs
IN
n x VSS
VDDIO2
m x VDDIO2
VDDIO2
OUT
m x100 nF
+4.7 μF
IO
logic
GPIOs
IN
m x VSS
VDD
VDDDSI
DSI
Voltage regulator
VCAPDSI
VDD12DSI
DSI PHY
2.2 uF
VDDA
VDDA
VREF
ADCs/
DACs/
10 nF
VREF+
VREF-
OPAMPs/
COMPs/
VREFBUF
+1 μF
100 nF +1 μF
VSSA
MSv47759V1
Caution:
Each power supply pair (V /V , V
/V
etc.) must be decoupled with filtering ceramic
DD SS DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
6.1.7
Current consumption measurement
Figure 26. Current consumption measurement
IDD_USB
IDD_VBAT
IDD
VDDUSB
VBAT
VDD
VDDIO2
IDDA
VDDA
MSv47746V1
The I
parameters given in Table 25 to Table 39 represent the total MCU consumption
DD_ALL
including the current supplying V , V
, V
, V
and V
.
DD
DDIO2
DDA
DDUSB
BAT
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics,
Table 19: Current characteristics and Table 20: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
138/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)
Table 18. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage (including VDD
,
VDDX - VSS
-0.3
4.0
VDDA, VDDIO2, VDDUSB, VBAT, VREF+
)
Range 1
Range 2
-0.3
-0.3
VDD12 - VSS External SMPS supply voltage
1.4
min (VDD, VDDA
,
)
V
Input voltage on FT_xxx pins
V
SS-0.3 VDDIO2, VDDUSB
+ 4.0(3)(4)
(2)
VIN
Input voltage on TT_xx pins
Input voltage on BOOT0 pin
Input voltage on any other pins
VSS-0.3
VSS
4.0
9.0
4.0
V
SS-0.3
-
Variations between different VDDX power pins
of the same domain
|ΔVDDx
|
50
mV
V
Variations between all the different ground
pins(5)
|VSSx-VSS
|
-
-
50
V
REF+ - VDDA Allowed voltage difference for VREF+ > VDDA
0.4
1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum
allowed injected current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin
definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
Table 19. Current characteristics
Symbol
Ratings
Max
Unit
∑IVDD
∑IVSS
Total current into sum of all VDD power lines (source)(1) (2)
Total current out of sum of all VSS ground lines (sink)(1) (2)
200
200
100
100
20
IVDD(PIN) Maximum current into each VDD power pin (source)(1)
IVSS(PIN)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin except FT_f
Output current sunk by any FT_f pin
IIO(PIN)
20
mA
Output current sourced by any I/O and control pin
Total output current sunk by sum of all I/Os and control pins(3)
Total output current sourced by sum of all I/Os and control pins(3)
20
100
∑IIO(PIN)
100
Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5 -5/+0(5)
(4)
IINJ(PIN)
Injected current on PA4, PA5
-5/0
25
∑|IINJ(PIN)
|
Total injected current (sum of all I/Os and control pins)(6)
1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supplies, in the permitted range.
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
2. Valid also for VDD12 on SMPS package.
3. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
4. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages
lower than the specified maximum value.
5. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18:
Voltage characteristics for the minimum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of
the negative injected currents (instantaneous values).
Table 20. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
150
°C
°C
Maximum junction temperature
6.3
Operating conditions
6.3.1
General operating conditions
Table 21. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
Internal AHB clock
frequency
fHCLK
-
0
120
120
120
3.6
Internal APB1 clock
frequency
fPCLK1
fPCLK2
VDD
-
-
-
0
0
MHz
Internal APB2 clock
frequency
Standard operating
voltage
1.71
(1)
Up to 120 MHz
1.14
1.08
1.32
1.32
Standard operating
voltage
Up to 80 MHz
Up to 26 MHz
VDD12
1.05
1.32
(2)
At least one I/O in PG[15:2]
used
1.08
3.6
3.6
PG[15:2] I/Os supply
voltage
VDDIO2
V
PG[15:2] not used
ADC or COMP used
DAC or OPAMP used
VREFBUF used
0
1.62
1.8
2.4
VDDA Analog supply voltage
3.6
3.6
ADC, DAC, OPAMP, COMP,
VREFBUF not used
0
VBAT Backup operating voltage
-
1.55
140/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
Table 21. General operating conditions (continued)
Symbol
Parameter
Conditions
USB used
Min
Max
Unit
3.0
0
3.6
3.6
VDDUSB USB supply voltage
USB not used
TT_xx I/O
BOOT0
-0.3
0
VDDIOx+0.3
9
V
MIN(MIN(VDD
,
VIN
I/O input voltage
VDDA, VDDIO2
VDDUSB
,
All I/O except BOOT0 and
TT_xx
-0.3
,
VLCD)+3.6 V,
5.5 V)(3)(4)
LQFP144
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
625
476
385
364
664
156
119
96
LQFP100
Power dissipation at
PD
UFBGA169
UFBGA132
WLCSP144
LQFP144
mW
mW
TA = 85 °C for suffix 6(5)
LQFP100
Power dissipation at
PD
UFBGA169
UFBGA132
WLCSP144
TA = 125 °C for suffix 3(5)
91
831
85
Maximum power dissipation –40
Low-power dissipation(6)
–40
Maximum power dissipation –40
Ambient temperature for
the suffix 6 version
105
125
130
TA
TJ
°C
°C
Ambient temperature for
the suffix 3 version
Low-power dissipation(6)
–40
–40
–40
Junction temperature
range
Suffix 6 version
105
130
Suffix 3 version
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. For Flash erase and program operation, VDD12 min must be 1.08 V.
3. This formula has to be applied only on the power supplies related to the IO structure described by the pin
definition table. Maximum I/O input voltage is the smallest value between MIN(VDD, VDDA, VDDIO2
DDUSB)+3.6 V and 5.5V.
,
V
4. For operation with voltage higher than Min (VDD, VDDA, VDDIO2, VDDUSB) +0.3 V, the internal Pull-up and
Pull-Down resistors must be disabled.
5. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.7: Thermal
characteristics).
6. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Section 7.7: Thermal characteristics).
DS12023 Rev 5
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
6.3.2
Operating conditions at power-up / power-down
The parameters given in Table 22 are derived from tests performed under the ambient
temperature condition summarized in Table 21.
(1)
Table 22. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
Max
Unit
VDD rise time rate
VDD fall time rate
0
10
0
∞
∞
∞
∞
∞
∞
∞
∞
tVDD
-
µs/V
VDDA rise time rate
VDDA fall time rate
VDDUSB rise time rate
VDDUSB fall time rate
VDDIO2 rise time rate
VDDIO2 fall time rate
tVDDA
tVDDUSB
tVDDIO2
-
-
-
µs/V
µs/V
µs/V
10
0
10
0
10
1. At power-up, the VDD12 voltage should not be forced externally.
6.3.3
Embedded reset and power control block characteristics
The parameters given in Table 23 are derived from tests performed under the ambient
temperature conditions summarized in Table 21: General operating conditions.
Table 23. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
Reset temporization after
BOR0 is detected
(2)
tRSTTEMPO
VDD rising
-
250
400
μs
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
1.62
1.6
1.66
1.64
2.1
1.7
(2)
VBOR0
Brown-out reset threshold 0
Brown-out reset threshold 1
Brown-out reset threshold 2
Brown-out reset threshold 3
Brown-out reset threshold 4
V
V
V
V
V
V
V
1.69
2.14
2.04
2.35
2.24
2.66
2.57
2.95
2.86
2.19
2.1
2.06
1.96
2.26
2.16
2.56
2.47
2.85
2.76
2.1
VBOR1
VBOR2
VBOR3
VBOR4
VPVD0
VPVD1
2
2.31
2.20
2.61
2.52
2.90
2.81
2.15
2.05
2.31
2.20
Programmable voltage
detector threshold 0
2
2.26
2.15
2.36
2.25
PVD threshold 1
142/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
Table 23. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.41
2.31
2.56
2.47
2.69
2.59
2.85
2.75
2.92
2.84
2.46
2.36
2.61
2.52
2.74
2.64
2.91
2.81
2.98
2.90
2.51
2.41
2.66
2.57
2.79
2.69
2.96
2.86
3.04
2.96
VPVD2
PVD threshold 2
V
VPVD3
VPVD4
VPVD5
VPVD6
PVD threshold 3
PVD threshold 4
PVD threshold 5
PVD threshold 6
V
V
V
V
Hysteresis in
continuous
mode
-
20
-
Vhyst_BORH0 Hysteresis voltage of BORH0
mV
Hysteresis in
other mode
-
30
100
1.1
-
-
Hysteresis voltage of BORH
Vhyst_BOR_PVD
-
-
-
-
-
mV
µA
V
(except BORH0) and PVD
IDD
BOR(3) (except BOR0) and
1.6
1.26
(BOR_PVD)(2) PVD consumption from VDD
VDDUSB peripheral voltage
monitoring
VPVM1
1.18
1.22
Rising edge
Falling edge
Rising edge
Falling edge
-
1.61
1.6
1.78
1.77
-
1.65
1.64
1.82
1.81
10
1.69
1.68
1.86
1.85
-
VDDA peripheral voltage
monitoring
VPVM3
V
V
VDDA peripheral voltage
monitoring
VPVM4
Vhyst_PVM3
Vhyst_PVM4
IDD
PVM3 hysteresis
PVM4 hysteresis
mV
mV
-
-
10
-
PVM1 and PVM2
consumption from VDD
(PVM1/PVM2)
-
-
-
-
0.2
2
-
-
µA
µA
(2)
IDD
PVM3 and PVM4
consumption from VDD
(PVM3/PVM4)
(2)
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.
DS12023 Rev 5
143/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
6.3.4
Embedded voltage reference
The parameters given in Table 24 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
Table 24. Embedded internal voltage reference
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Internal reference
voltage
VREFINT
–40 °C < TA < +130 °C 1.182 1.212 1.232
V
ADC sampling time
when reading the
internal reference
voltage
(1)
tS_vrefint
-
-
-
4(2)
-
8
-
µs
µs
Start time of reference
voltage buffer when
ADC is enable
tstart_vrefint
-
-
-
12(2)
20(2)
7.5(2)
VREFINT buffer
consumption from VDD
DD(VREFINTBUF) when converted by
12.5
5
µA
mV
I
ADC
Internal reference
voltage spread over
∆VREFINT
VDD = 3 V
the temperature range
Average temperature
coefficient
TCoeff
ACoeff
–40°C < TA < +130°C
1000 hours, T = 25°C
3.0 V < VDD < 3.6 V
-
-
-
30
50(2) ppm/°C
1000(2
Long term stability
300
250
ppm
)
Average voltage
coefficient
1200(2
VDDCoeff
ppm/V
)
VREFINT_DIV1
VREFINT_DIV2
VREFINT_DIV3
1/4 reference voltage
1/2 reference voltage
3/4 reference voltage
24
49
74
25
50
75
26
51
76
%
VREFINT
-
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
144/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
Figure 27. V
versus temperature
REFINT
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
°C
-40
-20
0
20
Mean
40
60
80
100
120
Min
Max
MSv40169V2
DS12023 Rev 5
145/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
6.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code
The current consumption is measured as described in Figure 26: Current consumption
measurement.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted with the minimum wait states number,
depending on the f
frequency (refer to the table “Number of wait states according
HCLK
to CPU clock (HCLK) frequency” available in the RM0432 reference manual).
•
•
When the peripherals are enabled f = f
PCLK
HCLK
The voltage scaling Range 1 is adjusted to f
frequency as follows:
HCLK
–
–
Voltage Range 1 Boost mode for 80 MHz < f
<= 120 MHz
HCLK
Voltage Range 1 Normal mode for 26 MHz < f
<= 80 MHz
HCLK
The parameters given in Table 25 to Table 39 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
146/307
DS12023 Rev 5
Table 25. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF)
Conditions
TYP
MAX(1)
Symbol Parameter
fHCLK
Unit
Voltage
-
25°C 55°C 85°C 105°C 125°C 25°C
55°C
85°C 105°C 125°C
scaling
26 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
3.40
2.20
1.25
3.80
2.55
1.60
4.90
3.70
2.70
2.20
6.55
5.30
4.30
3.80
3.55
3.45
3.35
9.45
8.20
7.20
6.70
6.45
6.35
6.25
3.9
2.6
1.6
1.0
0.7
0.6
0.4
4.8
3.4
2.3
1.8
1.5
1.4
1.2
6.8
5.4
4.3
3.8
3.5
3.4
3.2
11.0
8.7
7.6
7.1
6.8
6.6
6.5
17.0
15.0
14.0
13.0
13.0
13.0
13.0
Range 2
0.740 1.10
0.495 0.860 1.95
0.370 0.740 1.85
fHCLK = fHSE
up to 48 MHz
included,
bypass mode
PLLON above
48 MHz all
peripherals
disable
100 KHz 0.265 0.630 1.75
Supply
IDD(Run) current in
Run mode
Range 1
120 MHz 18.5
19.5
21.0
23.0
27.0
21.0
23.0
26.0
30.0
38.0
mA
Boost Mode
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
2 MHz
11.5
10.5
9.25
7.35
5.00
3.85
2.65
490
12.0
11.0
9.75
7.85
5.50
4.35
3.15
910
13.5
12.5
11.0
9.30
6.95
5.75
4.55
2200
2050
2000
1950
15.5
14.5
13.5
11.5
8.95
7.75
6.55
4050
3900
3800
3750
19.0
18.0
17.0
15.0
12.5
11.5
10.0
7250
7100
7000
7000
13.0
12.0
11.0
8.3
14.0
13.0
12.0
9.3
17.0
16.0
14.0
12.0
9.2
21.0
20.0
18.0
16.0
14.0
12.0
11.0
28.0
27.0
26.0
23.0
21.0
19.0
18.0
Range 1
Normal
Mode
5.7
6.7
4.4
5.4
7.9
3.1
4.1
6.6
690
490
430
380
1600
1500
1400
1400
4000
3900
3800
3700
7700 14000
7500 14000
7500 14000
7400 14000
Supply
1 MHz
305
770
fHCLK = fMSI
all peripherals disable
IDD
current in
µA
(LPRun) Low-power
run mode
400 KHz
100 KHz
250
695
210
645
1. Guaranteed by characterization results, unless otherwise specified.
Table 26. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ART enable (Cache ON Prefetch OFF)
and power supplied by external SMPS
Conditions(1)
TYP
Symbol
Parameter
Unit
-
VDD12
fHCLK
25°C
55°C
85°C
105°C
125°C
VDD12=1.20V
120 MHz
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
26 MHz
16 MHz
8 MHz
7.42
4.13
3.77
3.33
2.64
1.80
1.47
0.95
0.54
0.32
0.21
0.16
0.11
7.82
4.31
3.95
3.50
2.82
1.98
1.64
1.10
0.69
0.47
0.37
0.32
0.27
8.42
4.85
4.49
3.95
3.34
2.50
2.11
1.60
1.16
0.95
0.84
0.80
0.75
9.22
5.57
5.21
4.85
4.13
3.22
2.83
2.29
1.85
1.64
1.53
1.49
1.45
10.83
6.83
6.47
6.11
5.39
4.49
4.08
3.54
3.11
2.89
2.78
2.74
2.70
fHCLK = fHSE up to
48 MHz included,
bypass mode PLL
ON above 48 MHz
all peripherals
Supply
IDD(Run) current in Run
mode
mA
VDD12=1.10V
disable
4 MHz
2 MHz
1 MHz
100 KHz
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%.
Table 27. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in dual bank, ART enable (Cache ON Prefetch OFF)
Conditions
TYP
MAX(1)
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
26 MHz 3.60
16 MHz 2.30
3.95
2.65
1.65
5.05
3.75
2.70
2.20
6.65
5.35
4.30
3.75
3.50
3.35
3.25
9.55
8.20
7.15
6.60
6.35
6.20
6.10
4.2
2.7
1.6
1.0
0.7
0.6
0.4
5.0
3.6
2.4
1.8
1.5
1.4
1.2
7.1
5.6
4.4
3.8
3.5
3.4
3.2
11.0
8.9
7.7
7.1
6.8
6.7
6.5
17.0
15.0
14.0
14.0
13.0
13.0
13.0
8 MHz
1.30
Range 2
4 MHz 0.770 1.10
2 MHz 0.515 0.865 1.95
1 MHz 0.380 0.735 1.80
100 KHz 0.265 0.620 1.70
fHCLK = fHSE
up to 48MHz
included,
bypassmode
PLL ON
above 48
MHz all
Supply
current in
Run mode
Range 1
IDD
(Run)
120 MHz 17.0
80 MHz 12.5
18.0
19.5
21.5
25.5
19.0
21.0
24.0
28.0
36.0 mA
Boost Mode
13.0
11.5
10.5
8.30
5.80
4.55
3.30
905
14.0
13.0
12.0
9.75
7.20
5.95
4.65
16.0
15.0
14.0
11.5
9.20
7.90
6.60
19.5
18.5
17.5
15.0
12.5
11.5
10.0
14.0
13.0
12.0
8.7
15.0
14.0
13.0
9.9
18.0
17.0
15.0
13.0
9.6
22.0
21.0
19.0
17.0
14.0
13.0
11.0
29.0
28.0
26.0
24.0
21.0
20.0
18.0
peripherals
disable
72 MHz
11.0
64 MHz 9.90
48 MHz 7.85
32 MHz 5.35
24 MHz 4.10
16 MHz 2.80
Range 1
Normal
Mode
6.1
7.1
4.7
5.7
8.2
3.3
4.3
6.8
2 MHz
1 MHz
460
355
2150 3950 7100
2000 3800 6950
1950 3700 6850
1900 3650 6800
660
540
410
370
1700 4100 7700 15000
1500 3900 7600 14000
1400 3800 7500 14000
1400 3700 7500 14000
Supply
760
IDD
(LPRun)
fHCLK = fMSI
current in
Low-power
run mode
µA
all peripherals disable
400 KHz 240
100 KHz 200
685
635
1. Guaranteed by characterization results, unless otherwise specified.
Table 28. Consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ART enable (Cache ON Prefetch OFF)
and power supplied by external SMPS
Conditions(1)
TYP
Symbol
Parameter
Unit
-
VDD12
fHCLK
25°C
55°C
85°C
105°C
125°C
VDD12=1.20V
120 MHz
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
26 MHz
16 MHz
8 MHz
6.82
4.49
3.95
3.56
2.82
1.92
1.55
0.99
0.56
0.33
0.22
0.16
0.11
7.22
4.67
4.13
3.77
2.98
2.08
1.70
1.14
0.71
0.47
0.37
0.32
0.27
7.82
5.03
4.67
4.31
3.50
2.59
2.18
1.62
1.16
0.95
0.84
0.78
0.73
8.62
5.75
5.39
5.03
4.13
3.31
2.87
2.31
1.85
1.62
1.51
1.45
1.40
10.23
7.01
6.65
6.29
5.39
4.49
4.12
3.54
3.08
2.85
2.74
2.67
2.63
fHCLK = fHSE up to
48 MHz included,
bypass mode PLL
ON above 48 MHz
all peripherals
Supply
IDD(Run) current in Run
mode
mA
VDD12=1.10V
disable
4 MHz
2 MHz
1 MHz
100 KHz
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%.
Table 29. Current consumption in Run and Low-power run modes,
code with data processing running from Flash in single bank, ART disable
Conditions
TYP
MAX(1)
Symbol Parameter
fHCLK
Unit
Voltage
-
25°C 55°C 85°C 105°C 125°C 25°C
55°C
85°C 105°C 125°C
scaling
26 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
4.00
2.65
1.50
4.40
3.05
1.85
5.55
4.15
2.90
2.35
7.20
5.80
4.45
3.95
3.65
3.50
3.35
10.0
8.75
7.25
6.90
6.55
6.40
6.25
4.60
3.10
1.80
1.20
0.77
0.60
0.44
5.5
4.0
2.6
1.9
1.6
1.4
1.2
7.5
6.0
4.6
3.9
3.6
3.4
3.2
11.0
9.3
7.9
7.2
6.8
6.7
6.5
17.0
16.0
14.0
14.0
13.0
13.0
13.0
Range 2
0.875 1.25
0.565 0.925 2.05
0.405 0.770 1.90
fHCLK = fHSE
up to 48MHz
included,
100 KHz 0.265 0.635 1.75
Supply
IDD(Run) current in
bypassmode
PLL ON
Range 1
120 MHz 18.5
19.5
21.0
23.5
27.0
21.00
23.0
26.0
30.0
38.0
mA
Boost Mode
Run mode above 48
MHz all
peripherals
disable
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
2 MHz
13.0
12.0
10.5
8.75
6.20
4.70
3.35
595
13.5
12.5
11.0
9.30
6.70
5.20
3.85
15.5
14.0
12.5
11.0
8.20
6.70
5.25
17.5
16.0
15.0
13.0
10.0
10.5
7.30
4150
3950
3850
3800
21.0
20.0
18.5
16.5
14.0
12.5
11.0
15.00
14.00
12.00
9.80
17.0
15.0
14.0
12.0
8.2
19.0
18.0
16.0
14.0
11.0
9.0
23.0
22.0
20.0
18.0
15.0
13.0
12.0
30.0
29.0
28.0
25.0
22.0
20.0
19.0
Range 1
Normal
Mode
7.00
5.40
6.5
3.90
4.9
7.4
1000 2300
7350 810.00 1700
7150 560.00 1500
7050 420.00 1400
7000 400.00 1400
4100
3900
3800
3700
7800 15000
7600 14000
7500 14000
7400 14000
Supply
1 MHz
370
800
705
655
2100
2000
1950
fHCLK = fMSI
all peripherals disable
IDD
current in
µA
(LPRun) Low-power
run mode
400 KHz
100 KHz
245
230
1. Guaranteed by characterization results, unless otherwise specified.
Table 30. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single bank, ART disable and power supplied by external SMPS
Conditions(1)
TYP
Symbol
Parameter
Unit
-
VDD12
fHCLK
25°C
55°C
85°C
105°C
125°C
VDD12=1.20V
120 MHz
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
26 MHz
16 MHz
8 MHz
7.4
4.7
4.3
3.8
3.1
2.2
1.7
1.1
0.6
0.4
0.2
0.2
0.1
7.8
4.9
4.5
4.0
3.3
2.4
1.9
1.3
0.8
0.5
0.4
0.3
0.3
8.4
5.6
5.0
4.5
4.0
2.9
2.4
1.8
1.3
1.0
0.9
0.8
0.8
9.4
6.3
5.8
5.4
4.7
3.6
3.1
2.5
1.9
1.7
1.6
1.5
1.4
10.8
7.5
7.2
6.7
5.9
5.0
4.3
3.8
3.1
3.0
2.8
2.8
2.7
fHCLK = fHSE up to
48MHz included,
bypass mode PLL
ON above 48 MHz
all peripherals
disable
Supply
IDD(Run) current in Run
mode
mA
VDD12=1.10V
4 MHz
2 MHz
1 MHz
100 KHz
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%.
Table 31. Current consumption in Run and Low-power run modes,
code with data processing running from Flash in dual bank, ART disable
Conditions
TYP
MAX(1)
Symbol Parameter
fHCLK
Unit
Voltage
-
25°C 55°C 85°C 105°C 125°C 25°C
55°C
85°C 105°C 125°C
scaling
26 MHz
16 MHz
8 MHz
4.10
2.75
1.25
0.91
0.59
0.42
0.27
4.50
3.10
1.90
1.25
0.94
0.77
0.63
5.60
4.25
2.95
2.35
2.00
1.85
1.70
7.20
5.85
4.55
3.90
3.60
3.40
3.25
10.00
8.70
7.35
6.75
6.40
6.25
6.10
4.7
3.2
1.7
1.2
0.8
0.6
0.4
5.6
4.1
2.7
2.0
1.6
1.4
1.2
7.6
6.1
4.7
4.0
3.6
3.4
3.2
11.0
9.4
8.0
7.3
6.9
6.7
6.5
17.0
16.0
14.0
14.0
13.0
13.0
13.0
Range 2
Range 1
4 MHz
2 MHz
fHCLK = fHSE
up to
48MHz
included,
bypass
mode PLL
ON above
48 MHz all
peripherals
disable
1 MHz
100 KHz
Supply
IDD
current in
120 MHz 17.00 18.00 19.50 21.50 25.50
19.0
21.0
24.0
28.0
36.0
mA
Boost
Mode
(Run)
Run mode
80 MHz 13.00 13.50 15.00 17.00 20.50
72 MHz 11.50 12.00 14.00 16.00 19.50
64 MHz 10.50 11.00 12.50 14.50 18.00
15.0
13.0
12.0
11.0
7.3
16.0
15.0
13.0
12.0
8.5
19.0
18.0
16.0
15.0
12.0
9.3
23.0
22.0
20.0
19.0
16.0
14.0
12.0
30.0
29.0
27.0
26.0
23.0
21.0
19.0
Range 1
48 MHz
32 MHz
24 MHz
16 MHz
2 MHz
9.00
6.45
4.90
3.55
590
390
245
195
9.50 11.00 13.00 16.50
Normal
Mode
6.95
5.40
4.00
8.40
6.85
5.40
10.50 14.00
8.80
7.40
12.50
11.00
7200
7000
6900
6850
5.6
6.7
4.1
5.2
7.7
1000 2300
4050
3850
3750
3700
800.0
580.0
420.0
370.0
1800
1600
1400
1400
4200
4000
3800
3700
7800 15000
7600 14000
7500 14000
7500 14000
Supply
1 MHz
805
655
610
2100
1950
1900
IDD
(LPRun)
fHCLK = fMSI
current in
Low-power
run mode
µA
all peripherals disable
400 KHz
100 KHz
1. Guaranteed by characterization results, unless otherwise specified.
Table 32. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ART disable and power supplied by external SMPS
Conditions(1)
TYP
Symbol
Parameter
Unit
-
VDD12
fHCLK
25°C
55°C
85°C
105°C
125°C
VDD12=1.20V
120 MHz
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
26 MHz
16 MHz
8 MHz
6.82
4.67
4.13
3.77
3.24
2.32
1.77
1.19
0.54
0.39
0.25
0.18
0.11
7.22
4.85
4.31
3.95
3.42
2.50
1.94
1.34
0.82
0.54
0.40
0.33
0.27
7.82
5.39
5.03
4.49
3.95
3.02
2.42
1.83
1.27
1.01
0.86
0.80
0.73
8.62
6.11
5.75
5.21
4.67
3.77
3.11
2.52
1.96
1.68
1.55
1.47
1.40
10.23
7.37
7.01
6.47
5.93
5.03
4.31
3.75
3.17
2.91
2.76
2.70
2.63
fHCLK = fHSE up to
48 MHz included,
bypass mode PLL
ON above 48 MHz
all peripherals
Supply
IDD(Run) current in Run
mode
mA
VDD12=1.10V
disable
4 MHz
2 MHz
1 MHz
100 KHz
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%.
Table 33. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1
Conditions
TYP
MAX(1)
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
26 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
3.35
2.20
1.20
0.74
0.49
0.37
3.75
2.55
1.55
1.10
0.85
0.73
0.62
4.85
3.65
2.65
2.15
1.95
1.80
1.70
6.45
5.20
4.25
3.75
3.50
3.40
3.25
9.30
8.10
7.10
6.60
6.35
6.20
6.10
4.70
3.20
1.70
1.20
0.79
0.61
0.44
5.6
4.1
2.7
2.0
1.6
1.4
1.2
7.6
6.1
4.7
4.0
3.6
3.4
3.2
11.0
9.4
8.0
7.3
6.9
6.7
6.5
17.0
16.0
14.0
14.0
13.0
13.0
13.0
Range 2
fHCLK = fHSE
up to 48MHz
included,
100 KHz 0.26
Supply
IDD(Run) current in
Run mode
bypass mode
PLL ON
above 48
MHz all
peripherals
disable
Range 1
120 MHz 18.00 18.50 20.00 22.50 26.50 19.00 21.0
24.0
28.0 36.0(2) mA
23.0 30.0(2)
Boost Mode
80 MHz 11.00 11.50 13.50 15.50 19.00 15.00 16.0
72 MHz 10.00 10.50 12.00 14.00 18.00 13.00 15.0
19.0
18.0
16.0
15.0
12.0
9.3
22.0
20.0
19.0
16.0
14.0
12.0
29.0
27.0
26.0
23.0
21.0
19.0
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
2 MHz
9.10
7.20
4.90
3.75
2.60
435
300
225
180
9.60 11.00 13.00 16.50 12.00 13.0
Range 1
7.70
5.40
4.25
3.10
885
745
655
620
9.20 11.00 14.50 11.00 12.0
Normal
Mode
6.85
5.65
4.50
8.80 12.50 7.30
8.5
6.7
5.2
7.65 11.00
6.45 9.90
5.60
4.10
800
580
420
370
7.7
2150 3950 7100
2000 3800 6950
1900 3700 6850
1900 3650 6800
1800 4200 7800 15000
1600 4000 7600 14000
1400 3800 7500 14000
1400 3700 7500 14000
Supply
current in
(LPRun) Low-power
run mode
fHCLK = fMSI
all peripherals disable
FLASH in power-down
1 MHz
IDD
µA
400 KHz
100 KHz
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production.
Table 34. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1 and power supplied by external SMPS
Conditions(1)
TYP
Symbol
Parameter
Unit
-
VDD12
fHCLK
25°C
55°C
85°C
105°C
125°C
VDD12=1.20V
120 MHz
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
26 MHz
16 MHz
8 MHz
7.22
3.95
3.59
3.27
2.59
1.76
1.45
0.95
0.52
0.32
0.21
0.16
0.11
7.42
4.13
3.77
3.45
2.77
1.94
1.62
1.10
0.67
0.47
0.37
0.31
0.27
8.02
4.85
4.31
3.95
3.31
2.46
2.09
1.57
1.14
0.93
0.84
0.78
0.73
9.02
5.57
5.03
4.67
3.95
3.16
2.78
2.24
1.83
1.62
1.51
1.47
1.40
10.63
6.83
6.47
5.93
5.21
4.49
4.01
3.49
3.06
2.85
2.74
2.67
2.63
fHCLK = fHSE up to
48 MHz included,
bypass mode PLL
ON above 48 MHz
all peripherals
Supply
IDD(Run) current in Run
mode
mA
VDD12=1.10V
disable
4 MHz
2 MHz
1 MHz
100 KHz
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%.
Table 35. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF)
TYP
TYP
TYP
TYP
Conditions
Single Bank
Mode
Dual Bank
Mode
Single Bank Dual Bank
Mode
25°C
Mode
25°C
Symbol Parameter
Code
Unit
Unit
Voltage
scaling
-
25°C
25°C
Reduced
code(1)
3.40
3.60
131
138
Coremark
3.90
4.25
3.65
3.15
3.95
4.30
3.90
3.15
150
163
140
121
152
165
150
121
Range2
mA
µA/MHz
fHCLK=26MHz Dhrystone2.1
Fibonacci
While(1)
Reduced
code(1)
fHCLK=fHSE up
to 48 MHZ
11.5
12.5
144
156
included,
bypass mode
PLL ON above fHCLK= 80
48 MHz all
peripherals
disable
Range 1
Normal Mode
Coremark
13.5
14.5
12.5
10.5
13.5
14.5
14.0
10.5
169
181
156
131
169
181
175
131
Supply
IDD
current in
(Run)
mA
µA/MHz
Dhrystone2.1
Fibonacci
While(1)
Run mode
MHz
Reduced
code(1)
18.5
17.0
154
142
Range 1
Coremark
Dhrystone2.1
Fibonacci
21.5
22.5
20.0
16.5
21.5
22.5
21.0
16.5
179
188
167
138
179
188
175
138
Boost Mode
fHCLK= 120
MHz
mA
µA/MHz
While(1)
Table 35. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) (continued)
TYP
TYP
TYP
TYP
Conditions
Single Bank
Mode
Dual Bank
Mode
Single Bank Dual Bank
Mode
25°C
Mode
25°C
Symbol Parameter
Code
Unit
Unit
Voltage
scaling
-
25°C
25°C
Reduced
code(1)
490
460
245
230
Supply
current in
Coremark
Dhrystone2.1
Fibonacci
520
530
470
455
515
530
495
515
260
265
235
228
258
265
248
258
IDD
fHCLK = fMSI = 2MHz all
µA
µA/MHz
(LPRun) Low-power pripherals disable
run
While(1)
1. Reduced code used for characterization results provided in Table 25, Table 29, Table 33.
Table 36. Typical current consumption in Run and Low-power run modes, with
different codes running from Flash, ART enable (Cache ON Prefetch OFF)
and power supplied by external SMPS
TYP
TYP
TYP
TYP
Single
Single
Bank
Mode
Dual
Bank
Mode
Conditions(1)
Dual Bank
Bank
Symbol Parameter
Unit
Unit
Mode
Mode
-
VDD12
fHCLK
Code
25°C
25°C
25°C
25°C
Reduced
code
1.34
1.41
51
54
Coremark
1.53
1.67
1.43
1.24
1.55
1.69
1.53
1.24
59
64
55
48
60
65
59
48
fHCLK=
VDD12=1.05V
mA
µA/MHz
26 MHz Dhrystone2.1
Fibonacci
While(1)
Reduced
code
1.47
1.55
56
60
fHCLK=fHSE up to
48 MHZ included,
bypass mode
PLL ON above
48 MHz all
Coremark
fHCLK=
26 MHz Dhrystone2.1
1.68
1.83
1.57
1.36
1.70
1.85
1.68
1.36
65
71
61
52
66
71
65
52
Supply
IDD
current in
(Run)
mA
µA/MHz
Run mode
peripherals
disable
Fibonacci
While(1)
VDD12=1.10V
Reduced
code
4.13
4.49
52
56
Coremark
fHCLK=
80 MHz Dhrystone2.1
4.85
5.21
4.49
3.77
4.85
5.21
5.03
3.77
61
65
56
47
61
65
63
47
mA
µA/MHz
Fibonacci
While(1)
Table 36. Typical current consumption in Run and Low-power run modes, with
different codes running from Flash, ART enable (Cache ON Prefetch OFF)
and power supplied by external SMPS (continued)
TYP
TYP
TYP
TYP
Single
Single
Bank
Mode
Dual
Bank
Mode
Conditions(1)
Dual Bank
Bank
Symbol Parameter
Unit
Unit
Mode
Mode
-
VDD12
fHCLK
Code
25°C
25°C
25°C
25°C
fHCLK=fHSE up to
48 MHZ included,
bypass mode
PLL ON above
48 MHz all
Reduced
code
7.4
6.8
62
57
Coremark
Dhrystone2.1
Fibonacci
8.6
9.0
8.0
6.6
8.6
9.0
8.4
6.6
72
75
67
55
72
75
70
55
Supply
IDD
fHCLK=
120
MHz
current in
(Run)
VDD12=1.20V
mA
µA/MHz
Run mode
peripherals
disable
While(1)
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%.
Table 37. Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ART disable
TYP
Single Bank
Mode
TYP
TYP
TYP
Conditions
Single Bank
Mode
Dual Bank
Mode
Dual Bank
Mode
Symbol
Parameter
Code
Unit
Unit
Voltage
scaling
-
25°C
25°C
25°C
25°C
Reduced code(1)
Coremark
4.00
4.15
4.40
3.80
3.15
13.0
13.0
14.0
11.5
10.5
18.5
18.0
19.0
16.0
16.5
595
4.10
3.80
4.00
3.60
3.15
13.0
12.0
12.5
11.0
10.5
17.0
16.0
16.5
15.0
16.5
590
154
160
169
146
121.2
163
163
175
144
131
154
150
158
133
138
298
310
323
335
235
158
146
154
138
121.2
163
150
156
138
131
142
133
138
125
138
295
290
328
290
343
Range2
fHCLK=26
MHz
Dhrystone2.1
mA
µA/MHz
Fibonacci
While(1)
fHCLK=fHSE up
to 48 MHZ
included,
bypass mode
PLL ON
above 48 MHz
all peripherals
disable
Reduced code(1)
Range 1
Coremark
Supply
IDD (Run) current in
Run mode
Normal
Mode
Dhrystone2.1
Fibonacci
mA
mA
µA
µA/MHz
µA/MHz
µA/MHz
fHCLK=
80 MHz
While(1)
Reduced code(1)
Range 1
Coremark
Boost
Mode
fHCLK=
120 MHz
Dhrystone2.1
Fibonacci
While(1)
Reduced code(1)
Coremark
620
580
Supply
current in
IDD
(LPRun)
fHCLK = fMSI = 2MHz all
Low-power pripherals disable
run
Dhrystone2.1
Fibonacci
645
655
670
580
While(1)
470
685
1. Reduced code used for characterization results provided in Table 25, Table 29, Table 33.
Table 38. Typical current consumption in Run and Low-power run modes with different codes
running from Flash, ART disable and power supplied by external SMPS
TYP
TYP
TYP
TYP
Conditions(1)
SingleBank Dual Bank
Single Bank Dual Bank
Symbol Parameter
Unit
Unit
Mode
25°C
Mode
25°C
Mode
25°C
Mode
25°C
-
VDD12
fHCLK
Code
Reduced code
Coremark
1.57
1.63
1.73
1.49
1.24
1.73
1.79
1.90
1.64
1.36
4.67
4.67
5.03
4.13
3.77
7.4
1.61
1.49
1.57
1.41
1.24
1.77
1.64
1.73
1.55
1.36
4.67
4.31
4.49
3.95
3.77
6.8
60
63
67
57
48
66
69
73
63
52
58
58
63
52
47
62
60
64
53
55
62
57
60
54
48
68
63
66
60
52
58
54
56
49
47
57
53
55
50
55
VDD12= fHCLK=
Dhrystone2.1
Fibonacci
mA
µA/MHz
1.05V
26 MHz
While(1)
Reduced code
Coremark
fHCLK=fHSE up to
48 MHZ
included, bypass
mode PLL ON
above 48 MHz
all peripherals
disable
Supply
IDD
fHCLK=
26 MHz
current in
(Run)
Dhrystone2.1
Fibonacci
mA
mA
mA
µA/MHz
µA/MHz
µA/MHz
Run mode
While(1)
VDD12=
1.10V
Reduced code
Coremark
fHCLK=
80 MHz
Dhrystone2.1
Fibonacci
While(1)
Reduced code
Coremark
fHCLK=fHSE up to
48 MHZ
included, bypass
mode PLL ON
above 48 MHz
all peripherals
disable
7.2
6.4
Supply
IDD
fHCLK=
120
VDD12=
1.20V
current in
(Run)
Dhrystone 2.1
Fibonacci
7.6
6.6
Run mode
MHz
6.4
6.0
While(1)
6.6
6.6
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,
VDD12 = 1.10 V.
Table 39. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1
Conditions
TYP
TYP
Symbol
Parameter
Code
Unit
Unit
Voltage
scaling
-
25°C
25°C
Reduced code(1)
Coremark
3.35
3.10
3.65
3.20
2.85
11.0
10.5
12.5
10.5
9.40
18.0
16.5
19.5
17.5
15.0
435
129
119
140
123
110
138
131
156
131
118
150
138
163
146
125
218
198
235
213
228
Range2
fHCLK=26
MHz
Dhrystone2.1
mA
µA/MHz
Fibonacci
While(1)
Reduced code(1)
Range 1
Normal
fHCLK=fHSE up to 48
MHZ included, bypass
Coremark
Supply current in
Run mode
IDD (Run)
mode PLL ON above 48 Mode
Dhrystone2.1
Fibonacci
mA
mA
µA
µA/MHz
µA/MHz
µA/MHz
MHz all peripherals
disable
fHCLK= 80
MHz
While(1)
Reduced code(1)
Range 1
Coremark
Boost
Mode
fHCLK= 120
MHz
Dhrystone2.1
Fibonacci
While(1)
Reduced code(1)
Coremark
395
Supply current in fHCLK = fMSI = 2MHz all pripherals
IDD(LPRun)
Dhrystone2.1
Fibonacci
470
Low-power run
disable
425
While(1)
455
1. Reduced code used for characterization results provided in Table 25, Table 29, Table 33.
Table 40. Typical consumption in Run and Low-power run modes, with different codes
running from SRAM1 and power supplied by external SMPS
Conditions(1)
TYP
TYP
Symbol
Parameter
Unit
Unit
-
VDD12
fHCLK
Code
25°C
25°C
Reduced code
Coremark
1.32
1.22
1.43
1.26
1.12
1.45
1.34
1.57
1.38
1.23
3.95
3.77
4.49
3.77
3.38
7.2
51
47
55
48
43
56
51
61
53
47
59
57
67
57
51
60
55
65
58
50
fHCLK=
26 MHz
VDD12=1.05 V
VDD12=1.10V
VDD12=1.20V
Dhrystone2.1
Fibonacci
mA
µA/MHz
While(1)
Reduced code
Coremark
fHCLK=
26 MHz
Dhrystone2.1
Fibonacci
mA
mA
mA
µA/MHz
µA/MHz
µA/MHz
fHCLK=fHSE up to 48
MHZ included,
While(1)
Supplycurrent bypass mode PLL
in Run mode ON above 48 MHz
all peripherals
IDD (Run)
Reduced code
Coremark
disable
fHCLK=
80 MHz
Dhrystone2.1
Fibonacci
While(1)
Reduced code
Coremark
6.6
fHCLK=
120 MHz
Dhrystone2.1
Fibonacci
7.8
7.0
While(1)
6.0
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%.
Table 41. Current consumption in Sleep and Low-power sleep mode, Flash ON
Conditions
Voltage
TYP
MAX(1)
Symbol Parameter
fHCLK
Unit
-
25°C
55°C
85°C 105°C 125°C 25°C
55°C
85°C 105°C 125°C
scaling
26 MHz 1.10
16 MHz 0.78
1.45
1.15
0.87
0.74
0.63
0.61
0.58
2.55
2.25
1.95
1.85
1.75
1.75
1.70
4.15
3.80
3.55
3.40
3.35
3.30
3.25
7.00
6.65
6.35
6.25
6.15
6.10
6.10
1.40
1.00
0.72
0.57
0.50
0.46
0.43
2.2
1.8
1.5
1.4
1.3
1.3
1.2
4.2
3.8
3.5
3.4
3.3
3.3
3.2
7.5
7.1
6.8
6.7
6.6
6.5
6.5
14.0
14.0
13.0
13.0
13.0
13.0
13.0
8 MHz
4 MHz
2 MHz
1 MHz
0.52
0.38
0.32
0.29
Range 2
fHCLK = fHSE
up to 48MHz
included,
bypass mode
PLL ON
above 48 MHz
all peripherals
disable
100 KHz 0.26
Supply
current in
Sleep mode
Range 1
IDD
(Sleep)
120 MHz 4.20
4.70
6.25
8.40
12.00
4.80
6.0
8.7
13.0
21.0 mA
Boost Mode
80 MHz 2.80
72 MHz 2.55
64 MHz 2.30
48 MHz 2.15
32 MHz 1.55
24 MHz 1.25
16 MHz 0.93
3.25
3.00
2.75
2.60
2.00
1.70
1.40
625
4.65
4.40
4.20
4.00
3.40
3.10
2.80
1950
1900
1900
1900
6.60
6.40
6.15
6.00
5.35
5.05
4.70
3750
3700
3700
3700
10.00
9.85
9.60
9.45
8.80
8.50
8.20
6900
6850
6850
6800
3.30
3.00
2.70
2.60
1.90
1.60
1.20
410
4.3
4.0
6.8
6.5
11.0
11.0
11.0
10.0
9.3
18.0
18.0
18.0
18.0
17.0
16.0
16.0
3.8
6.3
Range 1
3.5
6.0
Normal
Mode
2.9
5.4
2.5
5.0
9.0
2.2
4.7
8.6
2 MHz
1 MHz
235
220
1400
1400
1300
1300
3800
3700
3700
3700
7500 14000
7500 14000
7500 14000
7500 14000
Supply
605
390
IDD
(LPSleep)
fHCLK = fMSI
current in
Low-power
sleep mode
µA
all peripherals disable
400 KHz 215
100 KHz 210
595
390
595
380
1. Guaranteed by characterization results, unless otherwise specified.
Table 42. Current consumption in Sleep and Low-power sleep modes,
Flash ON and power supplied by external SMPS
Conditions(1)
TYP
Symbol
Parameter
Unit
-
VDD12
fHCLK
25°C
55°C
85°C
105°C
125°C
VDD12=1.20V
120 MHz
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
26 MHz
16 MHz
8 MHz
1.68
1.01
0.92
0.83
0.77
0.56
0.47
0.33
0.22
0.16
0.14
0.12
0.11
1.89
1.17
1.08
0.99
0.93
0.72
0.63
0.50
0.38
0.32
0.27
0.26
0.25
2.51
1.67
1.58
1.51
1.44
1.22
1.10
0.97
0.84
0.80
0.75
0.75
0.73
3.37
2.37
2.30
2.21
2.16
1.92
1.79
1.64
1.53
1.47
1.45
1.42
1.40
4.81
3.59
3.54
3.45
3.40
3.16
3.02
2.87
2.74
2.70
2.65
2.63
2.63
mA
fHCLK = fHSE up to
48 MHz included,
bypass mode PLL
ON above 48
MHz all
Supply current in
Sleep mode
IDD(Sleep)
VDD12=1.10V
peripherals
disable
4 MHz
2 MHz
1 MHz
100 KHz
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%.
Table 43. Current consumption in Low-power sleep mode, Flash in power-down
Conditions TYP
MAX(1)
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
2 MHz
1 MHz
255
195
180
175
645 1950 3700 6850
620 1900 3700 6850
600 1900 3700 6800
595 1900 3650 6800
430 1400 3700 7400 14000
370 1300 3700 7400 14000
350 1300 3700 7400 14000
340 1300 3700 7400 14000
Supply
IDD
(LPSleep)
fHCLK = fMSI
all peripherals disable
current in
Low-power
sleep mode
µA
400 KHz
100 KHz
1. Guaranteed by characterization results, unless otherwise specified.
Table 44. Current consumption in Stop 2 mode, SRAM3 disabled
Conditions
-
TYP
MAX(1)
Symbol
Parameter
Unit
VDD
25°C
55°C
85°C 105°C 125°C 25°C
55°C
85°C 105°C 125°C
1.8 V
2.4 V
3 V
2.50
2.50
2.55
2.60
2.75
2.90
3.05
3.20
2.95
3.05
3.25
3.55
2.80
2.90
3.05
3.15
9.10
9.20
9.30
9.50
9.45
9.60
9.85
10.0
9.65
9.85
10.0
10.5
9.30
9.45
9.65
9.95
36.5
37.0
37.5
38.0
36.5
37.0
38.0
38.5
37.0
37.5
38.0
39.0
36.0
36.5
37.0
38.0
84.0
85.0
87.0
89.0
84.5
85.5
87.0
89.5
84.5
86.0
87.5
90.0
84.5
85.5
87.0
89.0
185
185
190
195
185
185
190
195
185
185
190
195
-
7.70
8.00
8.00
8.30
8.30
8.50
8.60
9.00
7.80
7.90
8.10
8.50
7.60
7.70
7.90
8.00
30.0
31.0
31.0
32.0
31.0
32.0
32.0
33.0
25.0
25.0
25.0
27.0
24.0
24.0
25.0
25.0
120
120
120
130
120
120
120
130
93.0
94.0
95.0
98.0
90.0
92.0
93.0
95.0
270
270
280
280
270
270
280
280
220
220
220
230
220
220
220
230
580
590
600
610
580
590
600
610
470
470
480
490
-
Supply
current in
Stop 2 mode,
IDD
(Stop 2)
-
RTC disabled
3.6 V
1.8 V
2.4 V
3 V
RTC clocked by LSI
3.6 V
1.8 V
2.4 V
3 V
µA
Supply
current in
STOP 2
mode,
IDD(Stop2
with RTC)
RTC clocked by LSE
bypassed at 32768 Hz
RTC enabled
3.6 V
1.8 V
2.4 V
3 V
-
-
RTC clocked by LSE
quartz in low drive mode
-
-
3.6 V
-
-
Wakeup clock is MSI = 48
MHz, voltage Range 1(2)
3 V
3 V
3 V
3.55
1.25
2.90
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Supply
IDD(wakeu
p from
current during Wakeup clock is MSI = 4
mA
wakeup from MHz, voltage Range 2(2)
Stop 2)
Stop 2 mode
Wakeup clock is HSI = 16
MHz, voltage Range 1(2)
1. Guaranteed by characterization results, unless otherwise specified.
2. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings.
Table 45. Current consumption in Stop 2 mode, SRAM3 enabled
Conditions
-
TYP
MAX(1)
Symbol
Parameter
Unit
VDD 25°C 55°C
85°C 105°C 125°C 25°C
55°C
85°C 105°C 125°C
1.8 V 3.90
2.4 V 3.95
15.0
15.0
15.0
15.0
15.0
15.5
15.5
16.0
15.5
15.5
16.0
16.5
15.5
16.0
16.0
16.5
59.5
60.0
60.5
61.5
60.5
60.5
61.5
62.5
61.0
61.0
62.0
63.0
63.5
64.0
64.5
65.5
140
140
145
145
140
145
145
145
140
145
145
145
150
150
150
155
310
310
315
320
310
315
320
325
310
315
320
325
-
13.0
14.0
14.0
14.0
11.0
12.0
12.0
12.0
9.50
9.60
9.90
10.0
9.40
9.50
9.60
11.0
52.0
53.0
53.0
54.0
53.0
54.0
54.0
56.0
39.0
39.0
40.0
42.0
39.0
40.0
40.0
42.0
210
210
210
210
210
210
210
220
160
160
160
160
160
160
170
170
480
480
480
490
480
480
480
1100
1100
1100
1100
1100
1100
1100
Supply current
in Stop 2
mode,
IDD(Stop 2)
-
3 V
3.95
RTC disabled
3.6 V 3.95
1.8 V 4.10
2.4 V 4.25
RTC clocked by LSI
3 V
4.50
3.6 V 4.70
1.8 V 4.35
2.4 V 4.50
490 1100(2)
µA
350
370
370
370
380
380
380
390
780
Supply current
in STOP 2
mode,
790
IDD(Stop 2
with RTC)
RTC clocked by LSE
bypassed at 32768 Hz
3 V
4.70
800
RTC enabled
3.6 V 4.80
1.8 V 4.30
2.4 V 4.40
820
-
-
-
-
-
RTC clocked by LSE
quartz in low drive mode
3 V
4.45
-
3.6 V 4.85
-
Wakeup clock is MSI = 48
MHz, voltage Range 1(3)
3 V
3 V
3 V
3.80
1.30
2.95
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Supply current
IDD(wakeup during wakeup Wakeup clock is MSI = 4
mA
from Stop 2) from Stop 2
mode
MHz, voltage Range 2(3)
Wakeup clock is HSI = 16
MHz, voltage Range 1(3)
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production.
3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings.
Table 46. Current consumption in Stop 1 mode
TYP
Conditions
-
MAX(1)
Symbol Parameter
Unit
VDD 25°C
55°C
85°C 105°C 125°C 25°C
55°C
85°C 105°C
125°C
1.8 V
2.4 V
3 V
120
120
125
120
120
125
125
125
120
120
125
125
120
120
120
120
430
430
430
430
430
430
430
435
430
435
435
435
420
420
420
425
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1350
1350
1350
1350
2750
2750
2750
2750
2700
2750
2750
2750
2750
2750
2750
2750
2700
2700
2700
2700
5050
5100
5100
5150
5050
5100
5100
5150
5050
5100
5100
5150
-
280
280
280
280
280
280
280
280
300
300
320
320
300
300
300
300
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
3300
3300
3300
3300
3300
3300
3300
3300
3500
3500
3500
3500
3400
3400
3400
3400
6500
6500
6500
6600
6500
6500
6600
6600
6900
6900
6900
6900
6800
6800
6800
6800
13000
13000
13000
Supplycurrent
in Stop 1
mode,
IDD
(Stop 1)
-
RTC disabled
(2)
3.6 V
1.8 V
2.4 V
3 V
13000
13000
13000
13000
13000
13000
13000
13000
13000
-
RTC clocked by LSI
3.6 V
1.8 V
2.4 V
3 V
µA
IDD
(Stop 1
with
RTC)
Supplycurrent
in STOP 1
mode,
RTC clocked by LSE
bypassed at 32768 Hz
RTC enabled
3.6 V
1.8 V
2.4 V
3 V
-
-
RTC clocked by LSE
quartz in low drive mode
(3)
-
-
3.6 V
-
-
Wakeup clock is MSI = 48
MHz, voltage Range 1
3 V
3 V
3 V
2.10
0.70
1.50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(4)
IDD
Supplycurrent
during
Wakeup clock is MSI = 4
(wakeup
from
mA
(4)
wakeup from MHz, voltage Range 2
Stop 1 mode
Stop 1)
Wakeup clock is HSI = 16
(4)
MHz, voltage Range 1
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production.
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings
Table 47. Current consumption in Stop 0 mode
TYP
Conditions
VDD
MAX(1)
85°C
Symbol
Parameter
Unit
-
25°C
55°C
85°C
105°C 125°C
25°C
55°C
105°C 125°C
1.8 V
2.4 V
3 V
290
295
295
735
735
735
2050
2050
2050
3800
3850
3850
6950
6950
7000
560
560
570
1600
1600
1600
4500
4500
4500
8700
8700
8800
16000
17000
17000
Supply current
in Stop 0 mode,
IDD(Stop 0)
-
µA
RTC disabled
17000
3.6 V
295
740
2050
3850
7000
570
1600
4500
8800
(2)
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production.
Table 48. Current consumption in Standby mode
Conditions
TYP
MAX(1)
Symbol
Parameter
Unit
-
VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
1.8 V
125
135
150
190
295
355
420
510
380
1900 5200 13500 340 1100 5300 15000 41000
2200 6050 15500 350 1300 6100 18000 47000
2700 7500 19500 370 1500 7100 21000 54000
3200 8850 23000 400 1900 8400 24000 62000
No
2.4 V
3 V
440
independent
watchdog
535
Supply current in Standby
mode (backup registers
retained),
3.6 V
1.8 V
2.4 V
3 V
665
IDD
(Standby)
nA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC disabled
With
independent
watchdog
3.6 V
Table 48. Current consumption in Standby mode (continued)
Conditions
TYP
MAX(1)
Symbol
Parameter
Unit
-
VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
1.8 V
370
455
560
640
760
930
2100 5300 13500 1100 1400 6400 16000 41000
2500 6250 15500 1200 1700 6800 18000 47000
3050 7650 19000 1300 1900 8100 21000 55000
62000
RTC clocked
by LSI, no
independent
watchdog
2.4 V
3 V
3.6 V
690
1150 3700 9200 23000 1400 2400 9000 24000
(2)
nA
1.8 V
2.4 V
3 V
420
525
645
795
480
615
770
975
420
520
650
825
380
380
385
400
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC clocked
by LSI, with
independent
watchdog
-
-
Supply current in Standby
mode (backup registers
retained),
IDD
(Standby with
RTC)
3.6 V
1.8 V
2.4 V
3 V
-
750
930
2200 5400 13500
2650 6400 15500
RTC enabled
RTC clocked
by LSE
bypassed at
32768 Hz
1150 3250 7900 19500
1450 3950 9500 23000
3.6 V
1.8 V
2.4 V
3 V
nA
685
830
2150 5400 13500
2550 6400 15500
RTC clocked
by LSE
quartz(3) in low
drive mode
1000 3100 7800 19500
1300 3800 9400 23000
1420 5600 13300 28500
1410 5650 12950 29000
1415 5600 13000 28500
1435 5700 13150 29000
3.6 V
1.8 V
2.4 V
3 V
Supply current to be added in
Standby mode when SRAM2
is retained
IDD
-
nA
(SRAM2)(4)
3.6 V
Table 48. Current consumption in Standby mode (continued)
Conditions
TYP
MAX(1)
Symbol
Parameter
Unit
-
VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
Wakeup clock
IDD (wakeup Supply current during wakeup
from Standby) from Standby mode
is MSI = 4
3 V
2.0
-
-
-
-
-
-
-
-
-
mA
MHz(5)
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production.
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
4. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is:
IIDD_ALL(Standby + RTC) + IDD_ALL(SRAM2).
5. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings.
Table 49. Current consumption in Shutdown mode
Conditions
VDD
TYP
MAX(1)
85°C
Symbol
Parameter
Unit
-
25°C
55°C
85°C
105°C
125°C
25°C
55°C
105°C 125°C
Supply current
in Shutdown
mode (backup
registers
1.8 V
2.4 V
3 V
33.0
43.0
60.0
205
250
320
1250
1450
1850
3650
4300
5450
10500
12000
15500
150
170
190
620
740
920
3800
4400
5200
12000 35000
14000 39000
16000 45000
IDD
(Shutdown)
-
nA
retained) RTC
disabled
3.6 V
92.0
430
2300
6700
18500
270
1200
6200
19000 51000
Table 49. Current consumption in Shutdown mode (continued)
Conditions
VDD
TYP
MAX(1)
85°C
Symbol
Parameter
Unit
-
25°C
55°C
85°C
105°C
125°C
25°C
55°C
105°C 125°C
RTC
clocked by
LSE
bypassed
at 32768
Hz
1.8 V
2.4 V
3 V
245
340
465
420
555
730
1450
1750
2250
3850
4600
5900
10500
12500
15500
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Supply current
in Shutdown
mode (backup
registers
retained) RTC
enabled
IDD
3.6 V
615
945
2850
7250
19000
-
-
-
-
-
nA
(Shutdownwith
RTC)
RTC
1.8 V
2.4 V
3 V
335
435
560
520
650
830
1550
1850
2350
4000
4750
6050
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
clocked by
LSE
quartz(2) in
low drive
mode
3.6 V
730
1050
2950
7400
-
-
-
-
-
-
Supply current
during wakeup
from Shutdown MSI = 4
Wakeup
clock is
IDD(wakeup
from
Shutdown)
3 V
0.5
-
-
-
-
-
-
-
-
-
mA
mode
MHz(3)
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings.
Table 50. Current consumption in VBAT mode
Conditions
TYP
MAX(1)
85°C
Symbol
Parameter
Unit
-
VBAT
25°C
55°C
85°C
105°C 125°C
25°C
55°C
105°C 125°C
1.8 V
2.4 V
3 V
3.00
4.00
6.00
14.0
215
305
415
27.0
31.0
43.0
83.0
240
340
455
165
190
255
485
390
510
680
495
560
1350
8.0
10.0
13.0
34.0
-
67.0
76.0
91.0
200
-
390
440
510
1100
-
1200
3000
1550
1300
3300
RTC
disabled
750
2000
1500
3800
3.6 V
1.8 V
2.4 V
3 V
1450
730
4050
3100
8300
RTC
-
-
-
-
-
-
-
-
-
enabled and
clocked by
LSE
900
-
-
-
Backup domain
supply current
IDD(VBAT)
nA
1200
-
-
-
bypassed at
32768 Hz
3.6 V
540
595
925
1900
-
-
-
-
-
-
1.8 V
2.4 V
3 V
305
395
510
650
345
440
565
740
510
625
865
1600
1800
2300
4450
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC
enabled and
clocked by
LSE
1050
1350
2200
805
quartz(2)
3.6 V
1200
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 75: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 52: Low-power mode wakeup timings), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
ISW = VDDIOx × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
SW
V
is the I/O supply voltage
DDIOx
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
+ C
S
INT
EXT
C is the PCB board capacitance including the pad pin.
S
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
On-chip peripheral current consumption
Electrical characteristics
The current consumption of the on-chip peripherals is given in Table 52. The MCU is placed
under the following conditions:
•
•
All I/O pins are in Analog mode
The given value is calculated by measuring the difference of the current consumptions:
–
–
when the peripheral is clocked on
when the peripheral is clocked off
•
•
Ambient operating temperature and supply voltage conditions summarized in Table 18:
Voltage characteristics
The power consumption of the digital part of the on-chip peripherals is given in
Table 52. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 51. Peripheral current consumption
Range 1
Boost
Mode
Range 1
Normal
Mode
Low-power
run and
sleep
Peripheral
Range 2
Unit
Bus Matrix
10.5
0.25
9.65
0.25
7.7
9
ADC independent
clock domain
0.125
0.5
ADC AHB clock
domain
3
2.75
2.6
3.5
CRC
0.835
7.15
3.15
2.85
29.5
5.35
7.75
10.5
5.6
0.875
6.65
2.9
0.835
5.5
0.5
7
DCMI
DMA1
2.5
2.5
2.5
26
4.5
6.5
9.5
4.5
1
DMA2
2.65
27.5
5.15
7.25
9.65
5.25
1.75
1.65
2.25
1.75
1.75
1.75
2.15
2.15
2.5
DMA2D
DMAMUX
FLASH
FMC
22.5
4.15
6.25
8.35
4.6
AHB
µA/MHz
GFXMMU
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG
GPIOH
1.85
1.75
2.4
1.4
1.35
1.9
1.5
2.5
2
1.85
1.85
2
1.45
1.45
1.55
1.8
1.5
2
2.25
2.35
2.5
2.5
1.8
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Table 51. Peripheral current consumption (continued)
Range 1
Boost
Mode
Range 1
Normal
Mode
Low-power
run and
sleep
Peripheral
Range 2
Unit
GPIOI
1.6
1.4
28
1.25
NA
2
OTG_FS independent
clock domain
25.5
NA
OTG_FS AHB clock
domain
18
0.15
0.665
2.5
16.5
0.115
0.625
2.4
NA
0.084
0.54
2.1
NA
0.5
1
OSPIM independent
clock domain
OSPIM AHB clock
domain
OSPI1 independent
clock domain
2.5
5.5
1
OSPI1 AHB clock
domain
6.15
1.9
5.75
1.65
5.25
4.25
2.5
4.6
OSPI2 independent
clock domain
1.25
4.15
NA
AHB
OSPI2 AHB clock
domain
5.5
5.5
NA
NA
NA
NA
µA/MHz
(Cont.)
RNG independent
clock domain
3.9
RNG AHB clock
domain
2.65
24.5
23.5
NA
SDMMC1 independent
clock domain
23.5
22
NA
SDMMC1 AHB clock
domain
NA
SRAM1
2.65
2.25
5.35
1.85
165
2.65
2
2.1
1.75
4.25
1.65
125
2
2
SRAM2
SRAM3
5
5.5
1
TSC
1.75
150
0.25
4.5
0.25
2.5
All AHB Peripherals
AHB to APB1 bridge
CAN1
145
0.5
4.5
0.5
2.5
0.084
4.85
0.335
2.75
0.165
3.75
0.415
2.1
CRS
APB1
µA/MHz
DAC1
I2C1 independent
clock domain
3.75
3.4
2.9
2.5
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DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
Table 51. Peripheral current consumption (continued)
Range 1
Boost
Mode
Range 1
Normal
Mode
Low-power
run and
sleep
Peripheral
Range 2
Unit
I2C1 APB clock
domain
1.4
3.5
1.4
3.4
1.25
2.5
2
3.5
1
I2C2 independent
clock domain
I2C2 APB clock
domain
1.4
1.25
3.15
1
1.25
2.9
I2C3 independent
clock domain
3.25
1.15
3.5
3
I2C3 APB clock
domain
0.835
2.75
1
1
I2C4 independent
clock domain
3.25
1.25
3
3
I2C4 APB clock
domain
1.35
3.15
1.65
3.6
1.5
3
LPUART1independent
clock domain
2.45
1.3
LPUART1 APB clock
domain
1.5
1.5
3
LPTIM1 independent
clock domain
3.5
2.9
APB1
µA/MHz
(Cont.)
LPTIM1 APB clock
domain
1
0.875
3.25
1
0.835
2.55
0.79
1
LPTIM2 independent
clock domain
3.4
3.5
1
LPTIM2 APB clock
domain
1.1
OPAMP
PWR
RTCAPB
SPI2
0.415
0.5
0.375
0.375
1.15
2.4
0.415
0.415
1.25
2.1
0.5
0.5
1
1.25
2.6
2.5
3
SPI3
3
2.75
5.75
4.9
2.5
TIM2
6.15
5.25
5.15
6.5
4.65
4.15
4.15
5
4.5
5
TIM3
TIM4
4.75
6
5
TIM5
6
TIM6
1.35
1.25
1.15
1.15
1.25
0.835
1
TIM7
1
DS12023 Rev 5
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Table 51. Peripheral current consumption (continued)
Range 1
Boost
Mode
Range 1
Normal
Mode
Low-power
run and
sleep
Peripheral
Range 2
Unit
USART2 independent
clock domain
5.35
3
5
2.75
6
4.15
2.5
5
4.5
2.5
5.5
2.5
4.5
2.5
5
USART2 APB clock
domain
USART3 independent
clock domain
6.35
2.6
5.15
2.5
5.4
2.4
USART3 APB clock
domain
2.4
4.9
2.25
5
2.1
3.75
2.1
4.15
2.1
UART4 independent
clock domain
APB1
µA/MHz
(Cont.)
UART4 APB clock
domain
UART5 independent
clock domain
UART5 APB clock
domain
2.25
2
WWDG
0.75
110
0.625
100
0.15
9
0.835
84
0.5
97
All APB1 on
AHB to APB2 bridge
DFSDM
0.185
9.5
0.125
7.5
0.5
8.5
DSI independent clock
domain
33
34.5
29.5
NA
DSI APB clock domain
FW
13
7.15
29
NA
0.5
0.665
0.625
0.5
LTDC independent
clock domain
35.5
18
34.5
17
40
14
NA
NA
3
LTDC APB clock
domain
APB2
µA/MHz
SAI1 independent
clock domain
3.1
2.9
2.4
3
2.5
1.9
2.55
SAI1 APB clock
domain
2.6
2
SAI2 independent
clock domain
3.15
3
SAI2 APB clock
domain
2.6
2.25
0.565
2.4
2.15
0.6
1.9
1.75
0.5
2.5
1
SPI1
SYSCFG/VREFBUF/C
OMP
0.5
180/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
Table 51. Peripheral current consumption (continued)
Range 1
Boost
Mode
Range 1
Normal
Mode
Low-power
run and
sleep
Peripheral
Range 2
Unit
TIM1
8.25
8.4
4
7.75
8
6.25
6.65
3.35
2.35
2.5
6.5
6.5
2.5
1.5
2
TIM8
TIM15
TIM16
TIM17
3.9
2.9
3
2.9
3.15
APB2
(Cont.)
µA/MHz
USART1 independent
clock domain
6.5
2.9
6.15
2.75
5.25
2.25
6
2
USART1 APB clock
domain
All APB2 on
ALL
80
75
62.5
265
72
340
320
310
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
6.3.6
Wakeup time from low-power modes and voltage scaling
transition times
The wakeup times given in Table 52 are the latency between the event and the execution of
the first user instruction.
The device goes in low-power mode after the WFE (Wait For Event) instruction.
(1)
Table 52. Low-power mode wakeup timings
Symbol
Parameter
Conditions
Typ Max Unit
Wakeup time
from Sleep
tWUSLEEP
-
6
6
mode to Run
mode
Nb of
CPU
Wakeup time
from Low-
Wakeup in Flash with Flash in power-down
cycles
power sleep
mode to Low-
during low-power sleep mode (SLEEP_PD=1
in FLASH_ACR) and with clock MSI = 2 MHz
tWULPSLEEP
7
9
power run
mode
Wakeup clock MSI = 48 MHz
Range 1
9.1
8.5
9.8
9.0
Wake up time
from Stop 0
Wakeup clock HSI16 = 16 MHz
mode to Run
mode in
Wakeup clock MSI = 24 MHz
Range 2 Wakeup clock HSI16 = 16 MHz
Wakeup clock MSI = 4 MHz
18.8 19.7
17.6 18.3
23.9 25.7
Flash
tWUSTOP0
µs
Wakeup clock MSI = 48 MHz
Range 1
1.9
2.6
2.6
2.6
2.5
2.9
3.1
3.0
Wake up time
from Stop 0
Wakeup clock HSI16 = 16 MHz
mode to Run
mode in
Wakeup clock MSI = 24 MHz
Range 2 Wakeup clock HSI16 = 16 MHz
Wakeup clock MSI = 4 MHz
SRAM1
10.0 11.5
182/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)
Table 52. Low-power mode wakeup timings (continued)
Symbol
Parameter
Conditions
Typ Max Unit
Wakeup clock MSI = 48 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock MSI = 24 MHz
12.6 14.5
12.2 14.0
22.1 24.1
21.3 23.3
25.1 27.1
Range 1
Wake up time
from Stop 1
mode to Run in
Flash
Range 2 Wakeup clock HSI16 = 16 MHz
Wakeup clock MSI = 4 MHz
Wakeup clock MSI = 48 MHz
Range 1
5.3
6.2
5.8
6.2
7.0
8.0
7.5
8.0
Wake up time
from Stop 1
Wakeup clock HSI16 = 16 MHz
mode to Run
mode in
Wakeup clock MSI = 24 MHz
Range 2 Wakeup clock HSI16 = 16 MHz
Wakeup clock MSI = 4 MHz
SRAM1
tWUSTOP1
µs
10.9 12.6
Wake up time
from Stop 1
mode to Low-
power run
20.4 22.4
Regulator
in low-
power
mode in Flash
Wakeup clock MSI = 2 MHz
mode
(LPR=1 in
PWR_CR1
)
Wake up time
from Stop 1
mode to Low-
power run
16.8 19.0
mode in
SRAM1
Wakeup clock MSI = 48 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock MSI = 24 MHz
13.1 14.8
12.6 14.4
22.6 24.6
21.7 23.7
25.8 27.9
Range 1
Wake up time
from Stop 2
mode to Run
mode in
Range 2 Wakeup clock HSI16 = 16 MHz
Wakeup clock MSI = 4 MHz
Flash
tWUSTOP2
µs
Wakeup clock MSI = 48 MHz
Range 1
5.8
6.9
6.4
6.9
7.5
8.5
8.0
8.5
Wake up time
from Stop 2
Wakeup clock HSI16 = 16 MHz
mode to Run
mode in
Wakeup clock MSI = 24 MHz
Range 2 Wakeup clock HSI16 = 16 MHz
Wakeup clock MSI = 4 MHz
SRAM1
11.9 13.6
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
Table 52. Low-power mode wakeup timings (continued)
Symbol
Parameter
Conditions
Typ Max Unit
Wakeup time
from Standby
Wakeup clock MSI = 8 MHz
30.7 47.8
tWUSTBY
Range 1
Range 1
mode to Run
mode
Wakeup clock MSI = 4 MHz
Wakeup clock MSI = 8 MHz
Wakeup clock MSI = 4 MHz
40.4 55.6
32.1 49.1
Wakeup time
from Standby
tWUSTBY
with SRAM2 to
Run mode
µs
41.5 55.5
SRAM2
Wakeup time
from
tWUSHDN
Shutdown
Range 1 Wakeup clock MSI = 4 MHz
265.0 339.4
mode to Run
mode
1. Guaranteed by characterization results.
(1)
Table 53. Regulator modes transition times
Symbol
Parameter
Conditions
Typ Max Unit
Wakeup time from Low- power run
mode to Run mode(2)
tWULPRUN
Code run with MSI 2 MHz
Code run with MSI 24 MHz
5
7
μs
Regulator transition time from
Range 2 to Range 1 or
Range 1 to Range 2(3)
tVOST
20
40
1. Guaranteed by characterization results.
2. Time until REGLPF flag is cleared in PWR_SR2.
3. Time until VOSF flag is cleared in PWR_SR2.
(1)
Table 54. Wakeup time using USART/LPUART
Parameter Conditions
Symbol
Typ Max Unit
Wakeup time needed to calculate Stop mode 0
the maximum USART/LPUART
baudrate allowing to wakeup up
-
1.7
tWUUSART
μs
from stop mode when
USART/LPUART clock source is
HSI
tWULPUART
Stop mode 1/2
-
8.5
1. Guaranteed by characterization results.
184/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
6.3.7
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.17. However,
the recommended clock input waveform is shown in Figure 28: High-speed external clock
source AC timing diagram.
(1)
Table 55. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Voltage scaling
Range 1
-
8
48
User external clock
source frequency
fHSE_ext
MHz
Voltage scaling
Range 2
-
8
-
26
OSC_IN input pin high
level voltage
VHSEH
VHSEL
-
-
0.7 VDDIOx
VDDIOx
V
OSC_IN input pin low
level voltage
VSS
7
-
0.3 VDDIOx
Voltage scaling
Range 1
-
-
-
tw(HSEH)
tw(HSEL)
OSC_IN high or low time
ns
Voltage scaling
Range 2
18
-
1. Guaranteed by design.
Figure 28. High-speed external clock source AC timing diagram
t
w(HSEH)
V
HSEH
90%
10%
V
HSEL
t
t
t
t
r(HSE)
f(HSE)
w(HSEL)
T
HSE
MS19214V2
DS12023 Rev 5
185/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.17. However,
the recommended clock input waveform is shown in Figure 29.
(1)
Table 56. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fLSE_ext
-
-
32.768
1000
kHz
OSC32_IN input pin high
level voltage
VLSEH
VLSEL
tw(LSEH)
-
-
-
0.7 VDDIOx
VSS
-
-
-
VDDIOx
0.3 VDDIOx
-
V
OSC32_IN input pin low level
voltage
OSC32_IN high or low time
250
ns
tw(LSEL)
1. Guaranteed by design.
Figure 29. Low-speed external clock source AC timing diagram
t
w(LSEH)
V
LSEH
90%
10%
V
LSEL
t
t
t
r(LSE)
f(LSE)
t
w(LSEL)
T
LSE
MS19215V2
186/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 57. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
(1)
Table 57. HSE oscillator characteristics
Symbol
fOSC_IN Oscillator frequency
RF Feedback resistor
Parameter
Conditions(2)
Min
Typ
Max
Unit
-
4
-
8
200
-
48
-
MHz
kΩ
-
During startup(3)
-
5.5
VDD = 3 V,
Rm = 30 Ω,
CL = 10 pF@8 MHz
-
-
-
-
-
0.44
0.45
0.68
0.94
1.77
-
-
-
-
-
VDD = 3 V,
Rm = 45 Ω,
CL = 10 pF@8 MHz
VDD = 3 V,
IDD(HSE) HSE current consumption
mA
Rm = 30 Ω,
CL = 5 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω,
CL = 10 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω,
CL = 20 pF@48 MHz
Maximum critical crystal
transconductance
Gm
Startup
-
-
-
1.5
-
mA/V
ms
(4)
tSU(HSE)
Startup time
VDD is stabilized
2
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 30). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
DS12023 Rev 5
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 30. Typical application with an 8 MHz crystal
Resonator with integrated
capacitors
CL1
OSC_IN
fHSE
Bias
controlled
gain
8 MHz
resonator
RF
(1)
OSC_OUT
REXT
CL2
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 58. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
188/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)
Table 58. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions(2)
Min
Typ
Max Unit
LSEDRV[1:0] = 00
Low drive capability
-
250
-
LSEDRV[1:0] = 01
Medium low drive capability
-
-
-
-
-
-
315
-
IDD(LSE) LSE current consumption
nA
LSEDRV[1:0] = 10
Medium high drive capability
500
-
LSEDRV[1:0] = 11
High drive capability
630
-
LSEDRV[1:0] = 00
Low drive capability
-
-
-
0.5
LSEDRV[1:0] = 01
Medium low drive capability
0.75
µA/V
1.7
Maximum critical crystal
Gmcritmax
gm
LSEDRV[1:0] = 10
Medium high drive capability
LSEDRV[1:0] = 11
High drive capability
-
-
-
2.7
(3)
tSU(LSE)
Startup time
VDD is stabilized
2
-
s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly
with the crystal manufacturer
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 31. Typical application with a 32.768 kHz crystal
Resonator with integrated
capacitors
CL1
OSC32_IN
fLSE
Drive
32.768 kHz
resonator
programmable
amplifier
OSC32_OUT
CL2
MS30253V2
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
DS12023 Rev 5
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
6.3.8
Internal clock source characteristics
The parameters given in Table 59 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
(1)
Table 59. HSI16 oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fHSI16
HSI16 Frequency
VDD=3.0 V, TA=30 °C
15.88
-
16.08 MHz
Trimming code is not a
multiple of 64
0.2
-4
0.3
-6
0.4
%
TRIM
HSI16 user trimming step
Trimming code is a
multiple of 64
-8
DuCy(HSI16)(2) Duty Cycle
-
45
-1
-2
-
-
-
55
1
%
%
TA= 0 to 85 °C
TA= -40 to 125 °C
HSI16 oscillator frequency
drift over temperature
∆Temp(HSI16)
1.5
%
%
HSI16 oscillator frequency
drift over VDD
∆VDD(HSI16)
VDD=1.62 V to 3.6 V
-0.1
-
0.05
1.2
5
HSI16 oscillator start-up
time
tsu(HSI16)(2)
tstab(HSI16)(2)
IDD(HSI16)(2)
-
-
-
-
-
-
0.8
3
μs
μs
μA
HSI16 oscillator
stabilization time
HSI16 oscillator power
consumption
155
190
1. Guaranteed by characterization results.
2. Guaranteed by design.
190/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
Figure 32. HSI16 frequency versus temperature
MHz
16.4
+2 %
+1.5 %
+1 %
16.3
16.2
16.1
16
15.9
15.8
15.7
15.6
-1 %
-1.5 %
-2 %
-40
-20
0
20
40
60
80
100
120 °C
Mean
min
max
MSv39299V2
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Multi-speed internal (MSI) RC oscillator
Table 60. MSI oscillator characteristics(1)
Conditions
Symbol
Parameter
Min
Typ
Max Unit
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
TA= -0 to 85 °C
98.7
100
200
101.3
197.4
202.6
kHz
405.2
394.8
400
7896
800
810.4
1.013
2.026
4.052
0.987
1
1.974
2
MSI mode
3.948
4
7.896
8
8.104
MHz
16.21
15.79
16
23.69
24
24.31
32.42
48.62
-
31.58
32
MSI frequency
after factory
calibration, done
at VDD=3 V and
TA=30 °C
47.38
48
fMSI
-
98.304
196.608
393.216
786.432
1.016
1.999
3.998
7.995
15.991
23.986
32.014
48.005
-
-
-
kHz
-
-
-
-
-
-
-
-
PLL mode
XTAL=
32.768 kHz
-
-
-
-
MHz
-
-
-
-
-
-
-
-
MSI oscillator
frequency drift
over
-3.5
3
∆
TEMP(MSI)(2)
MSI mode
%
6
TA= -40 to 125 °C
-8
-
temperature
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DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Table 60. MSI oscillator characteristics(1) (continued)
Electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
V
DD=1.62 V
-1.2
-
to 3.6 V
Range 0 to 3
0.5
VDD=2.4 V
to 3.6 V
-0.5
-2.5
-0.8
-5
-
-
-
-
MSI oscillator
frequency drift
VDD=1.62 V
to 3.6 V
∆
VDD(MSI)(2) over VDD
MSI mode Range 4 to 7
0.7
1
%
VDD=2.4 V
(reference is
3 V)
to 3.6 V
VDD=1.62 V
to 3.6 V
Range 8 to 11
VDD=2.4 V
to 3.6 V
-1.6
-
-
Frequency
variation in
sampling
mode(3)
TA= -40 to 85 °C
1
2
4
∆FSAMPLING
MSI mode
%
(MSI)(2)(6)
TA= -40 to 125 °C
-
2
for next
transition
-
-
-
-
-
-
-
-
-
-
-
-
3.458
P_USB
Period jitter for
PLL mode
Range 11
ns
Jitter(MSI)(6) USB clock(4)
for paired
transition
3.916
for next
transition
-
2
1
-
Medium term
MT_USB
PLL mode
Range 11
jitter for USB
ns
Jitter(MSI)(6)
clock(5)
for paired
transition
-
RMS cycle-to-
CC jitter(MSI)(6)
PLL mode Range 11
60
ps
ps
cycle jitter
P jitter(MSI)(6) RMS Period jitter PLL mode Range 11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
50
10
5
-
20
10
8
Range 0
Range 1
Range 2
4
MSI oscillator
start-up time
tSU(MSI)(6)
us
Range 3
3
7
Range 4 to 7
Range 8 to 11
3
6
2.5
6
10 % of final
frequency
-
-
-
-
-
-
0.25
0.5
-
0.5
MSI oscillator
stabilization time Range 11
PLL mode 5 % of final
tSTAB(MSI)(6)
1.25 ms
2.5
frequency
1 % of final
frequency
DS12023 Rev 5
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Table 60. MSI oscillator characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.6
0.8
1.2
1.9
4.7
6.5
11
1
1.2
1.7
2.5
6
MSI oscillator
power
consumption
9
MSI and
PLL mode
IDD(MSI)(6)
µA
15
18.5
62
25
80
85
110
130
190
110
155
1. Guaranteed by characterization results.
2. This is a deviation for an individual part once the initial frequency has been measured.
3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.
4. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter
of MSI @48 MHz clock.
5. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles.
For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28
cycles.
For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over
56 cycles.
6. Guaranteed by design.
Figure 33. Typical current consumption versus MSI frequency
194/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
High-speed internal 48 MHz (HSI48) RC oscillator
Electrical characteristics
(1)
Table 61. HSI48 oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fHSI48
TRIM
HSI48 Frequency
VDD=3.0V, TA=30°C
-
-
-
48
-
MHz
%
HSI48 user trimming step
0.11(2) 0.18(2)
USER TRIM HSI48 user trimming
COVERAGE coverage
±32 steps
-
±3(3)
45(2)
-
±3.5(3)
-
%
%
DuCy(HSI48) Duty Cycle
-
-
55(2)
±3(3)
VDD = 3.0 V to 3.6 V,
Accuracy of the HSI48
ACCHSI48_REL oscillator over temperature
(factory calibrated)
TA = –15 to 85 °C
%
VDD = 1.65 V to 3.6 V,
TA = –40 to 125 °C
-
-
±4.5(3)
VDD = 3 V to 3.6 V
-
-
0.025(3) 0.05(3)
HSI48 oscillator frequency
DVDD(HSI48)
%
0.05(3)
0.1(3)
drift with VDD
VDD = 1.65 V to 3.6 V
HSI48 oscillator start-up
tsu(HSI48)
time
-
-
-
-
2.5(2)
6(2)
μs
HSI48 oscillator power
IDD(HSI48)
340(2)
380(2) μA
consumption
Next transition jitter
NT jitter
PT jitter
Accumulated jitter on 28
-
-
-
-
+/-0.15(2)
-
-
ns
ns
cycles(4)
Paired transition jitter
Accumulated jitter on 56
cycles(4)
+/-0.25(2)
1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Jitter measurement are performed without clock source activated in parallel.
DS12023 Rev 5
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Figure 34. HSI48 frequency versus temperature
%
6
4
2
0
-2
-4
-6
-50
-30
-10
10
30
50
70
90
110
130
°C
Avg
min
max
MSv40989V1
Low-speed internal (LSI) RC oscillator
(1)
Table 62. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
DD = 3.0 V,
31.04
-
32.96
34
TA = 30 °C
fLSI
LSI Frequency
kHz
VDD = 1.62 to 3.6 V,
TA = -40 to 125 °C
29.5
-
LSI oscillator start-up
time
tSU(LSI)(2)
tSTAB(LSI)(2)
IDD(LSI)(2)
-
-
-
-
80
130
180
180
μs
μs
nA
LSI oscillator stabilization
time
5% of final frequency
-
125
110
LSI oscillator power
consumption
1. Guaranteed by characterization results.
2. Guaranteed by design.
196/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
6.3.9
PLL characteristics
The parameters given in Table 63 are derived from tests performed under temperature and
V
supply voltage conditions summarized in Table 21: General operating conditions.
DD
(1)
Table 63. PLL, PLLSAI1, PLLSAI2 characteristics
Symbol
fPLL_IN
Parameter
Conditions
Min
Typ Max Unit
PLL input clock(2)
-
-
2.66
45
-
-
16
55
MHz
%
PLL input clock duty cycle
Voltage scaling Range 1
Normal mode
2.0645
2.0645
-
80
fPLL_P_OUT PLL multiplier output clock P Voltage scaling Range 1
Boost mode
-
-
-
120
26
Voltage scaling Range 2 2.0645
Voltage scaling Range 1
Normal mode
8
80
fPLL_Q_OUT PLL multiplier output clock Q Voltage scaling Range 1
8
8
8
-
-
-
120
26
Boost mode
MHz
Voltage scaling Range 2
Voltage scaling Range 1
Normal mode
80
fPLL_R_OUT PLL multiplier output clock R Voltage scaling Range 1
Boost mode
8
-
120
Voltage scaling Range 2
8
64
64
-
-
26
344
128
40
Voltage scaling Range 1
fVCO_OUT PLL VCO output
-
Voltage scaling Range 2
-
tLOCK
Jitter
PLL lock time
-
15
40
30
150
200
300
520
μs
RMS cycle-to-cycle jitter
RMS period jitter
-
-
System clock 80 MHz
±ps
-
-
VCO freq = 64 MHz
VCO freq = 96 MHz
VCO freq = 192 MHz
VCO freq = 344 MHz
-
200
260
380
650
-
PLL power consumption on
I
DD(PLL)
μA
(1)
VDD
-
-
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M
factor is shared between the 3 PLLs.
6.3.10
MIPI D-PHY characteristics
The parameters given in Table 64 and Table 65 are derived from tests performed under
temperature and V supply voltage conditions summarized in Table 21.
DD
DS12023 Rev 5
197/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
Table 64. MIPI D-PHY characteristics
Parameter Conditions
Hi-speed input/output characteristics
Symbol
Min
Typ
Max
Unit
UINST
UI instantaneous
-
-
2
-
12.5
250
ns
HS transmit common mode
voltage
VCMTX
150
200
VCMTX mismatch when output
is Differential-1 or Differential-0
|ΔVCMTX
|
-
-
-
-
-
-
140
-
-
200
-
5
mV
|VOD
|ΔVOD
VOHHS
ZOS
|
HS transmit differential voltage
270
14
VOD mismatch when output is
Differential-1 or Differential-0
|
HS output high voltage
-
-
360
62.5
Single ended output
impedance
40
50
Ω
Single ended output
impedance mismatch
ΔZOS
-
-
-
-
-
10
%
tHSr & tHSf 20%-80% rise and fall time
100
0.35*UI
ps
LP receiver input characteristics
Logic 0 input voltage (not in
ULP State)
VIL
-
-
-
-
-
-
550
300
Logic 0 input voltage in ULP
State
VIL-ULPS
mV
VIH
Input high level voltage
Voltage hysteresis
-
-
880
25
-
-
-
-
Vhys
LP emitter output characteristics
VIL
Output low level voltage
-
-
1.1
-50
1.2
-
1.2
50
V
VIL-ULPS Output high level voltage
mV
Output impedance of LP
transmitter
VIH
-
-
110
-
-
-
-
Ω
Vhys
15%-85% rise and fall time
25
ns
LP contention detector characteristics
VILCD
VIHCD
Logic 0 contention threshold
Logic 0 contention threshold
-
-
-
-
-
200
-
mV
450
1. Guaranteed by characterization results.
198/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)
Table 65. MIPI D-PHY AC characteristics LP mode and HS/LP transitions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Transmitted length of any Low-
Power state period
TLPX
-
50
-
-
Time that the transmitter drives
the Clock Lane LP-00 Line
TCLK-PREPARE state immediately before the
HS-0 Line state starting the HS
transmission.
-
-
-
38
300
8
-
-
-
95
-
ns
TCLK-PREPARE Time that the transmitter drives
+
the HS-0 state prior to starting
the clock.
TCLK-ZERO
Time that the HS clock shall be
driven by the transmitter prior to
any associated Data Lane
beginning the transition from
LP to HS mode.
TCLK-PRE
-
UI
Time that the transmitter
continues to send HS clock
after the last associated Data
Lane has transitioned to LP
Mode.
TCLK-POST
-
-
-
62+52*UI
-
-
-
-
Time that the transmitter drives
the HS-0 state after the last
payload clock bit of an HS
transmission burst.
TCLK-TRAIL
60
-
Time that the transmitter drives
the Data Lane LP-00 Line state
THS-PREPARE immediately before the HS-0
Line state starting the HS
transmission.
40+4*UI
145+10*UI
85+6*UI
THS-PREPARE+ Time that the
transmitter drives the HS-0
THS-PREPARE
ns
+
-
-
-
-
-
-
state prior to transmitting the
THS-ZERO
Sync sequence.
Time that the transmitter drives
the flipped differential state
after last payload data bit of a
HS transmission burst.
Max
(n*8*UI,
60+n*4*UI)
THS-TRAIL
Time that the transmitter drives
THS-EXIT
-
-
100
-
-
-
-
LP-11 following a HS burst.
TREOT
30%-85% rise time and fall time
35
Transmitted time interval from
the start of THS-TRAIL or
TCLK-TRAIL, to the start of the
LP-11 state following a HS
burst.
105+
n*12UI
TEOT
-
-
-
1. Guaranteed by characterization results.
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Figure 35. MIPI D-PHY HS/LP clock lane transition timing diagram
TCLK-POST
TEOT
VIL
Clock
Lane
TCLK-TRAIL THS-EXIT
TLPX TCLK-PREPARE TCLK-ZERO TCLK-PRE
TLPX THS-PREPARE
VIL
Data
Lane
MS38282V1
Figure 36. MIPI D-PHY HS/LP data lane transition timing diagram
Clock
Lane
TLPX
THS-PREPARE THS-ZERO
Data
Lane
VIL
TREOT
LP-11
LP-01 LP-00
TEOT
THS-TRAIL
THS-EXIT
MS38283V1
6.3.11
MIPI D-PHY PLL characteristics
The parameters given in Table 66 are derived from tests performed under temperature and
V
supply voltage conditions summarized in Table 21.
DD
(1)
Table 66. DSI-PLL characteristics
Symbol
Parameter
Conditions
Min Typ
Max Unit
fPLL_IN PLL input clock
-
-
-
-
-
4
4
-
-
-
-
-
100
fPLL_INFIN PFD input clock
25
MHz
500
fPLL_OUT PLL multiplier output clock
fVCO_OUT PLL VCO output
31.25
500
-
1000
tLOCK
PLL lock time
200
µs
200/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)
Table 66. DSI-PLL characteristics (continued)
Symbol
Parameter
Conditions
Min Typ
Max Unit
0.55 0.70
0.65 0.80
0.95 1.20
fVCO_OUT = 500 MHz
-
-
-
IDD(PLL) PLL power consumption on VDD12
1. Guaranteed by characterization results.
f
VCO_OUT = 600 MHz
mA
fVCO_OUT = 1000 MHz
6.3.12
MIPI D-PHY regulator characteristics
The parameters given in Table 67 are derived from tests performed under temperature and
V
supply voltage conditions summarized in Table 21.
DD
(1)
Table 67. DSI regulator characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
VDD12DSI 1.2 V internal voltage on VDD12DSI
-
-
-
-
1.15 1.20 1.30
V
CEXT
ESR
External capacitor on VCAPDSI
External Serial Resistor
1.1
0
2.2
25
3.3
μF
600 mΩ
IDDDSIREG Regulator power consumption
100 120 125
µA
µA
Ultra Low Power Mode
(Reg. ON + PLL OFF)
-
-
-
-
-
-
-
-
290 600
290 600
DSI system (regulator, PLL and
IDDDSI
D-PHY) current consumption on VDDDSI
Stop State
(Reg. ON + PLL OFF)
10 MHz escape clock
(Reg. ON + PLL OFF)
4.3
4.3
8.0
5.0
5.0
8.8
DSI system current consumption on
IDDDSILP
mA
VDDDSI in LP mode communication(2)
20 MHz escape clock
(Reg. ON + PLL OFF)
300 Mbps - 1 data lane
(Reg. ON + PLL ON)
300 Mbps - 2data lane
(Reg. ON + PLL ON)
11.4 12.5
13.5 14.7
18.0 19.6
DSI system (regulator, PLL and
D-PHY) current consumption on VDDDSI
in HS mode communication(3)
IDDDSIHS
500 Mbps - 1 data lane
(Reg. ON + PLL ON)
mA
500 Mbps - 2data lane
(Reg. ON + PLL ON)
DSI system (regulator, PLL and
D-PHY) current consumption on VDDDSI
in HS mode with CLK like payload
500 Mbps - 2data lane
(Reg. ON + PLL ON)
-
21.4 23.3
C
EXT = 2.2 µF
-
-
-
110
-
-
tWAKEUP Startup delay
µs
CEXT = 3.3 µF
160
200
IINRUSH
Inrush current on VDDDSI
External capacitor load at start
60
mA
1. Guaranteed by characterization results.
2. Values based on an average traffic in LP Command Mode.
3. Values based on an average traffic (3/4 HS traffic & 1/4 LP) in Video Mode.
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6.3.13
Flash memory characteristics
(1)
Table 68. Flash memory characteristics
Parameter Conditions
Symbol
Typ
Max Unit
tprog
64-bit programming time
-
81.7
5.2
90.8
5.5
4
µs
Normal programming
Fast programming
Normal programming
Fast programming
One row (64 double
word) programming time
tprog_row
3.8
41.8
30.4
43
One page (4 Kbytes)
programming time
ms
tprog_page
tERASE
tprog_bank
tME
31
Page (4 Kbytes) erase
time
-
22
24.5
Normal programming
Fast programming
10.7
7.7
11
8
One bank (1 Mbyte)
programming time
s
Mass erase time
(one or two banks)
-
22.1
25
ms
Write mode
Erase mode
Write mode
Erase mode
3.4
-
-
-
-
Average consumption
from VDD
3.4
IDD
mA
7 (for 6 μs)
7 (for 67 μs)
Maximum current (peak)
1. Guaranteed by design.
Table 69. Flash memory endurance and data retention
Symbol
Parameter
Endurance
Conditions
Min(1)
Unit
NEND
TA = –40 to +105 °C
10
30
15
7
kcycles
1 kcycle(2) at TA = 85 °C
1 kcycle(2) at TA = 105 °C
1 kcycle(2) at TA = 125 °C
10 kcycles(2) at TA = 55 °C
10 kcycles(2) at TA = 85 °C
10 kcycles(2) at TA = 105 °C
tRET
Data retention
Years
30
15
10
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
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6.3.14
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 70. They are based on the EMS levels and classes
defined in application note AN1709.
Table 70. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, TA = +25 °C,
fHCLK = 120 MHz,
conforming to IEC 61000-4-2
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VFESD
3B
5A
Fast transient voltage burst limits to be
VEFTB applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 120 MHz,
conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
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Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 71. EMI characteristics
Max vs. [fHSE/fHCLK
8 MHz / 120 MHz
]
Monitored
frequency band
Symbol Parameter
Conditions
Unit
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI Level
-2
3
V
DD = 3.6 V, TA =
25 °C,
dBµV
-
SEMI
Peak level UFBGA169 package
compliant with
10
8
IEC 61967-2
3
6.3.15
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 72. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
TA = +25 °C, conforming
to ANSI/ESDA/JEDEC
JS-001
Electrostatic discharge
voltage (human body model)
VESD(HBM)
2
2000
V
Electrostatic discharge
TA = +25 °C,
VESD(CDM) voltage (charge device
model)
conforming toANSI/ESD
STM5.3.1
C3
250
1. Guaranteed by characterization results.
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Static latch-up
Electrical characteristics
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 73. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
II level A(1)
1. Negative injection is limited to -30 mA for PF0, PF1, PG6, PG7, PG8, PG12, PG13, PG14.
6.3.16
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V
(for standard, 3.3 V-capable I/O pins) should be avoided during normal
DDIOx
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 74.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
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Table 74. I/O current injection susceptibility
Functional
susceptibility
Symbol
Description
Unit
Negative Positive
injection injection
Injected current on all pins except PA4, PA5, PB0, PF13,
PE15, PC8, PA13, PH3-BOOT0, PB8, PE0,
OPAMP1_V1NM, OPAMP2_V1NM
-5
0
NA
NA
Injected current on pins PF13, PE15, PC8, PA13, PH3-
BOOT0, PB8, PE0
(1)
IINJ
mA
Injected current on pins OPAMP1_V1NM,
OPAMP2_V1NM
0
0
0
Injected current on PA4, PA5, PB0 pins
-5
1. Guaranteed by characterization.
6.3.17
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 75 are derived from tests
performed under the conditions summarized in Table 21: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant (except BOOT0).
Table 75. I/O static characteristics
Sym
Parameter
Conditions
Min
Typ
Max
Unit
bol
I/O input low
level voltage
except BOOT0
0.3xVDDIOx
1.62 V<VDDIOx<3.6 V
-
-
(2)
I/O input low
level voltage
except BOOT0
0.39xVDDIOx-0.06
1.62 V<VDDIOx<3.6 V
-
-
(3)
VIL
V
(1)
I/O input low
level voltage
except BOOT0
0.43xVDDIOx-0.1
1.08 V<VDDIOx<1.62 V
1.62 V<VDDIOx<3.6 V
-
-
-
-
(3)
BOOT0 I/O input
low level voltage
0.17xVDDIOx
(3)
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Table 75. I/O static characteristics (continued)
Sym
bol
Parameter
Conditions
Min
Typ
Max
Unit
I/O input high
level voltage
except BOOT0
(2)
1.62 V<VDDIOx<3.6 V
0.7xVDDIOx
-
-
I/O input high
level voltage
except BOOT0
0.49xVDDIOX+0.26
1.62 V<VDDIOx<3.6 V
1.08 V<VDDIOx<1.62 V
1.62 V<VDDIOx<3.6 V
-
-
-
-
-
(3)
VIH
V
(1)
I/O input high
level voltage
except BOOT0
0.61xVDDIOX+0.05
-
-
(3)
BOOT0 I/O input
high level
voltage
(3)
0.77xVDDIOX
TT_xx, FT_xxx
and NRST I/O
input hysteresis
1.62 V<VDDIOx<3.6 V
1.08 V<VDDIOx<1.62 V
-
200
Vhys
mV
(3)
FT_sx
-
-
-
-
150
-
-
BOOT0 I/O input
hysteresis
1.62 V<VDDIOx<3.6 V
200
(4)
VIN ≤ Max(VDDXXX
)
-
-
±100
650(3)(6)
FT_xx input
leakage
Max(VDDXXX) ≤ VIN ≤
Max(VDDXXX)+1 V(4)(5)
current(3)
Max(VDDXXX)+1 V <
VIN ≤ 5.5 V(3)(5)
-
-
-
-
-
-
200(6)
±150
(4)
VIN ≤ Max(VDDXXX
)
Max(VDDXXX) ≤ VIN
≤
FT_lu, FT_u,
PB2 and PC3 IO
2500(3)(7)
Max(VDDXXX)+1 V(4)
Ilkg
nA
Max(VDDXXX)+1 V <
VIN ≤ 5.5 V(4)(5)(7)
-
-
-
-
-
-
250(7)
±150
(6)
VIN ≤ Max(VDDXXX)
TT_xx input
leakage current
Max(VDDXXX) ≤ VIN
3.6 V(6)
<
2000(3)
OPAMPx_VINM
(x=1,2)
dedicated input
leakage current
(8)
-
-
-
Weak pull-up
RPU equivalent
VIN = VSS
25
40
55
kΩ
resistor (9)
Weak pull-down
RPD equivalent
VIN = VDDIOx
25
-
40
5
55
-
kΩ
pF
resistor(9)
I/O pin
CIO
-
capacitance
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1. Refer to Figure 37: I/O input characteristics.
2. Tested in production.
3. Guaranteed by design.
4. Max(VDDXXX) is the maximum value of all the I/O supplies.
5. All TX_xx IO except FT_lu, FT_u, PB2 and PC3.
6. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this
formula:
ITotal_Ileak_max = 10 µA + [number of IOs where VIN is applied on the pad] ₓ Ilkg(Max).
7. To sustain a voltage higher than MIN(VDD, VDDA, VDDUSB, VLCD) +0.3 V, the internal Pull-up and Pull-Down
resistors must be disabled.
8. Refer to Ibias in Table 91: OPAMP characteristics for the values of the OPAMP dedicated input leakage
current.
9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable
PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 37 for standard I/Os, and in Figure 37 for
5 V tolerant I/Os.
Figure 37. I/O input characteristics
TTL requirement Vih min = 2V
TTL requirement Vil max = 0.8V
MSv37613V1
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed V /V ).
OL OH
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Electrical characteristics
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum
DDIOx,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 18: Voltage characteristics).
VDD
•
The sum of the currents sunk by all the I/Os on V , plus the maximum consumption of
SS
the MCU sunk on V , cannot exceed the absolute maximum rating ΣI
(see
SS
VSS
Table 18: Voltage characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).
(1)
Table 76. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for
an I/O pin
CMOS port(2)
|IIO| = 8 mA
VDDIOx ≥ 2.7 V
VOL
-
0.4
Output high level voltage for
an I/O pin
VOH
VDDIOx-0.4
-
0.4
-
Output low level voltage for
an I/O pin
(3)
TTL port(2)
|IIO| = 8 mA
VDDIOx ≥ 2.7 V
VOL
-
2.4
-
Output high level voltage for
an I/O pin
(3)
VOH
Output low level voltage for
an I/O pin
(3)
VOL
1.3
-
|IIO| = 20 mA
VDDIOx ≥ 2.7 V
Output high level voltage for
an I/O pin
(3)
VOH
V
DDIOx-1.3
Output low level voltage for
an I/O pin
(3)
VOL
-
0.45
-
V
|IIO| = 4 mA
VDDIOx ≥ 1.62 V
Output high level voltage for
an I/O pin
(3)
VOH
VDDIOx-0.45
Output low level voltage for
an I/O pin
0.35 ₓ
VDDIOx
(3)
VOL
-
|IIO| = 2 mA
1.62 V ≥ VDDIOx
1.08 V
≥
Output high level voltage for
an I/O pin
(3)
VOH
0.65ₓVDDIOx
-
|IIO| = 20 mA
VDDIOx ≥ 2.7 V
-
-
0.4
0.4
Output low level voltage for |IIO| = 10 mA
an FT I/O pin in FM+ mode VDDIOx ≥ 1.62 V
VOLFM+
(3)
(FT I/O with "f" option)
|IIO| = 2 mA
1.62 V ≥ VDDIOx
1.08 V
≥
-
0.4
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified
in Table 18: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports
and control pins) must always respect the absolute maximum ratings ΣIIO
.
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2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 38 and
Table 77, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
(1)(2)
Table 77. I/O AC characteristics
Speed Symbol
Parameter
Conditions
Min
Max
Unit
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
1
0.1
10
1.5
0.1
25
52
140
17
37
110
25
10
1
Maximum
frequency
Fmax
MHz
00
Output rise and
fall time
Tr/Tf
ns
MHz
ns
Maximum
frequency
Fmax
50
15
1
01
9
16
40
4.5
9
Output rise and
fall time
Tr/Tf
21
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(1)(2)
Table 77. I/O AC characteristics
(continued)
Min
Speed Symbol
Parameter
Conditions
Max
Unit
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=30 pF, 2.7 V≤VDDIOx≤3.6 V
C=30 pF, 1.62 V≤VDDIOx≤2.7 V
C=30 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=30 pF, 2.7 V≤VDDIOx≤3.6 V
C=30 pF, 1.62 V≤VDDIOx≤2.7 V
C=30 pF, 1.08 V≤VDDIOx≤1.62 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
50
25
5
Maximum
frequency
Fmax
MHz
100(3)
37.5
5
10
5.8
11
28
Output rise and
fall time
Tr/Tf
ns
2.5
5
12
120(3)
50
10
Maximum
frequency
Fmax
MHz
180(3)
11
75
10
3.3
6
Output rise and
fall time
Tr/Tf
ns
16
Maximum
frequency
Fmax
-
-
1
5
MHz
ns
Fm+
Tf
C=50 pF, 1.6 V≤VDDIOx≤3.6 V
Output fall
time(4)
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the
SYSCFG_CFGR1 register. Refer to the RM0432 reference manual for a description of GPIO Port
configuration register.
2. Guaranteed by design.
3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.
4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.
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(1)
Figure 38. I/O AC characteristics definition
10%
90%
50%
50%
10%
90%
t
t
r(IO)out
f(IO)out
T
Maximum frequency is achieved if (t + t (≤ 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by the specified capacitance.
MS32132V2
1. Refer to Table 77: I/O AC characteristics.
6.3.18
NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, R
.
PU
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions.
(1)
Table 78. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
NRST input low level
voltage
VIL(NRST)
-
-
-
0.3ₓVDDIOx
V
NRST input high level
voltage
VIH(NRST)
Vhys(NRST)
RPU
-
0.7ₓVDDIOx
-
200
40
-
-
-
NRST Schmitt trigger
voltage hysteresis
-
-
25
-
mV
kΩ
ns
Weak pull-up equivalent
resistor(2)
VIN = VSS
-
55
70
-
NRST input filtered
pulse
VF(NRST)
VNF(NRST)
NRST input not filtered
pulse
1.71 V ≤ VDD
≤ 3.6 V
350
-
ns
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10% order).
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Figure 39. Recommended NRST pin protection
External
reset circuit(1)
VDD
RPU
NRST(2)
Internal reset
Filter
0.1 μF
MS19878V3
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 78: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
6.3.19
Extended interrupt and event controller input (EXTI) characteristics
The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
(1)
Table 79. EXTI input characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Pulse length to event
controller
PLEC
-
20
-
-
ns
1. Guaranteed by design.
6.3.20
Analog switches booster
(1)
Table 80. Analog switches booster characteristics
Symbol
Parameter
Supply voltage
Min
Typ
Max
Unit
VDD
1.62
-
-
-
3.6
V
tSU(BOOST)
Booster startup time
240
µs
Booster consumption for
1.62 V ≤ VDD ≤ 2.0 V
-
-
-
-
-
-
250
500
900
Booster consumption for
2.0 V ≤ VDD ≤ 2.7 V
IDD(BOOST)
µA
Booster consumption for
2.7 V ≤ VDD ≤ 3.6 V
1. Guaranteed by design.
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
6.3.21
Analog-to-digital converter characteristics
Unless otherwise specified, the parameters given in Table 81 are preliminary values derived
from tests performed under ambient temperature, f
frequency and V
supply voltage
PCLK
DDA
conditions summarized in Table 21: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
(1) (2)
Table 81. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
3.6
Unit
Analog supply
voltage
VDDA
-
1.62
2
-
V
Positive
reference
voltage
V
DDA ≥ 2 V
-
VDDA
V
V
VREF+
VDDA < 2 V
VDDA
Negative
reference
voltage
VREF-
-
VSSA
V
Range 1
Range 2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
80
ADC clock
frequency
fADC
MHz
26
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 6 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 6 bits
5.33
6.15
7.27
8.88
4.21
4.71
5.33
6.15
Sampling rate
for FAST
channels
fs
Msps
Sampling rate
for SLOW
channels
fADC = 80 MHz
Resolution = 12 bits
-
-
-
-
-
5.33
15
MHz
1/fADC
V
External trigger
frequency
fTRIG
Resolution = 12 bits
-
Conversion
voltage range(2)
(3)
VAIN
0
VREF+
External input
impedance
RAIN
-
-
-
-
-
-
5
1
50
-
kΩ
pF
Internal sample
and hold
capacitor
CADC
conversi
on cycle
tSTAB
Power-up time
Calibration time
f
ADC = 80 MHz
1.45
116
µs
tCAL
-
1/fADC
214/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1) (2)
Table 81. ADC characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Trigger
CKMODE = 00
CKMODE = 01
CKMODE = 10
1.5
2
-
2.5
2.0
conversion
latency Regular
and injected
channels
-
-
-
2.25
tLATR
1/fADC
without
conversion
abort
CKMODE = 11
-
-
2.125
Trigger
CKMODE = 00
CKMODE = 01
CKMODE = 10
2.5
3
-
3.5
3.0
conversion
latency Injected
channels
-
-
tLATRINJ
1/fADC
-
3.25
aborting a
regular
conversion
CKMODE = 11
-
-
3.125
fADC = 80 MHz
-
0.03125
2.5
-
-
8.00625
640.5
µs
ts
Sampling time
1/fADC
ADC voltage
regulator start-
up time
tADCVREG_STU
-
-
-
-
20
µs
P
fADC = 80 MHz
Resolution = 12 bits
0.1875
8.1625
µs
Total conversion
time
(including
tCONV
ts + 12.5 cycles for
successive approximation
= 15 to 653
Resolution = 12 bits
1/fADC
sampling time)
fs = 5 Msps
fs = 1 Msps
fs = 10 ksps
fs = 5 Msps
fs = 1 Msps
-
-
-
-
-
730
160
16
830
220
50
ADC
consumption
from the VDDA
supply
IDDA(ADC)
µA
ADC
consumption
DDV_S(ADC) from the VREF+
130
30
160
40
I
µA
µA
single ended
mode
fs = 10 ksps
-
0.6
2
fs = 5 Msps
fs = 1 Msps
fs = 10 ksps
-
-
-
260
60
310
70
3
ADC
consumption
from the VREF+
differential mode
I
DDV_D(ADC)
1.3
1. Guaranteed by design
2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the
SYSCFG_CFGR1 when VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on
the package.
Refer to Section 4: Pinouts and pin description for further details.
DS12023 Rev 5
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
The maximum value of R
can be found in Table 82: Maximum ADC RAIN.
AIN
(1)(2)
Table 82. Maximum ADC R
AIN
RAIN max (Ω)
Fast channels(3) Slow channels(4)
Sampling cycle
Sampling time
[ns] @80 MHz
Resolution
@80 MHz
2.5
6.5
31.25
81.25
100
330
N/A
100
12.5
24.5
47.5
92.5
247.5
640.5
2.5
156.25
306.25
593.75
1156.25
3093.75
8006.75
31.25
680
470
1500
2200
4700
12000
39000
120
1200
1800
3900
10000
33000
N/A
12 bits
6.5
81.25
390
180
12.5
24.5
47.5
92.5
247.5
640.5
2.5
156.25
306.25
593.75
1156.25
3093.75
8006.75
31.25
820
560
1500
2200
5600
12000
47000
180
1200
1800
4700
10000
39000
N/A
10 bits
8 bits
6 bits
6.5
81.25
470
270
12.5
24.5
47.5
92.5
247.5
640.5
2.5
156.25
306.25
593.75
1156.25
3093.75
8006.75
31.25
1000
1800
2700
6800
15000
50000
220
680
1500
2200
5600
12000
50000
N/A
6.5
81.25
560
330
12.5
24.5
47.5
92.5
247.5
640.5
156.25
306.25
593.75
1156.25
3093.75
8006.75
1200
2700
3900
8200
18000
50000
1000
2200
3300
6800
15000
50000
216/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
1. Guaranteed by design.
2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the
SYSCFG_CFGR1 when VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. Fast channels are: PC0, PC1, PC2, PC3, PA0.
4. Slow channels are: all ADC inputs except the fast channels.
DS12023 Rev 5
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)(2)(3)
Table 83. ADC accuracy - limited test conditions 1
Conditions(4)
Sym-
bol
Parameter
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
4
5
5
Single
ended
Total
unadjusted
error
ET
EO
EG
ED
EL
3.5 4.5
3.5 4.5
Differential
1
1
2.5
2.5
Single
ended
Offset
error
1.5 2.5
1.5 2.5
2.5 4.5
2.5 4.5
2.5 3.5
2.5 3.5
Differential
Single
ended
Gain error
LSB
Differential
1
1
1
1
1.5
1.5
1.2
1.2
Single
ended
Differential
linearity
error
ADC clock frequency ≤
80 MHz,
Differential
Sampling rate ≤ 5.33 Msps,
VDDA = VREF+ = 3 V,
TA = 25 °C
1.5 2.5
1.5 2.5
Single
ended
Integral
linearity
error
1
1
2
2
-
-
-
-
-
-
-
-
-
-
-
-
Differential
Fast channel (max speed) 10.4 10.5
Slow channel (max speed) 10.4 10.5
Fast channel (max speed) 10.8 10.9
Slow channel (max speed) 10.8 10.9
Fast channel (max speed) 64.4 65
Slow channel (max speed) 64.4 65
Fast channel (max speed) 66.8 67.4
Slow channel (max speed) 66.8 67.4
Single
ended
Effective
ENOB number of
bits
bits
Differential
Single
ended
Signal-to-
noise and
distortion
ratio
SINAD
Differential
dB
Fast channel (max speed) 65
Slow channel (max speed) 65
Fast channel (max speed) 67
Slow channel (max speed) 67
66
66
68
68
Single
ended
Signal-to-
SNR
noise ratio
Differential
218/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)(2)(3)
Table 83. ADC accuracy - limited test conditions 1
(continued)
Sym-
bol
Parameter
Conditions(4)
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-74 -73
-74 -73
-79 -76
-79 -76
ADC clock frequency ≤
80 MHz,
Single
ended
Total
THD harmonic
distortion
Sampling rate ≤ 5.33 Msps,
VDDA = VREF+ = 3 V,
TA = 25 °C
dB
Differential
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
V
DDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.
DS12023 Rev 5
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)(2)(3)
Table 84. ADC accuracy - limited test conditions 2
Conditions(4)
Sym-
bol
Parameter
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
4
6.5
6.5
Single
ended
Total
unadjusted
error
ET
EO
EG
ED
EL
3.5 5.5
3.5 5.5
Differential
1
4.5
5
Single
ended
1
Offset
error
1.5
1.5
2.5
2.5
3
Differential
3
6
Single
ended
6
Gain error
LSB
2.5 3.5
2.5 3.5
Differential
1
1
1
1
1.5
1.5
1.2
1.2
Single
ended
Differential
linearity
error
ADC clock frequency ≤
80 MHz,
Differential
Sampling rate ≤ 5.33 Msps,
2 V ≤ VDDA
1.5 3.5
1.5 3.5
Single
ended
Integral
linearity
error
1
1
3
Differential
2.5
Fast channel (max speed) 10 10.5
Slow channel (max speed) 10 10.5
Fast channel (max speed) 10.7 10.9
Slow channel (max speed) 10.7 10.9
-
-
-
-
-
-
-
-
-
-
-
-
Single
ended
Effective
ENOB number of
bits
bits
Differential
Fast channel (max speed) 62
Slow channel (max speed) 62
65
65
Single
ended
Signal-to-
noise and
distortion
ratio
SINAD
Fast channel (max speed) 66 67.4
Slow channel (max speed) 66 67.4
Differential
dB
Fast channel (max speed) 64
Slow channel (max speed) 64
66
66
Single
ended
Signal-to-
SNR
noise ratio
Fast channel (max speed) 66.5 68
Slow channel (max speed) 66.5 68
Differential
220/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)(2)(3)
Table 84. ADC accuracy - limited test conditions 2
(continued)
Sym-
bol
Parameter
Conditions(4)
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-74 -65
-74 -67
-79 -70
-79 -71
Single
ended
ADC clock frequency ≤
80 MHz,
Total
THD harmonic
distortion
dB
Sampling rate ≤ 5.33 Msps,
2 V ≤ VDDA
Differential
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
V
DDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)(2)(3)
Table 85. ADC accuracy - limited test conditions 3
Conditions(4)
Sym-
bol
Parameter
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5.5 7.5
4.5 6.5
4.5 7.5
4.5 5.5
Single
ended
Total
unadjusted
error
ET
EO
EG
ED
EL
Differential
2
5
5
Single
ended
2.5
2
Offset
error
3.5
3
Differential
2.5
4.5
3.5
3.5
3.5
7
Single
ended
6
Gain error
LSB
4
Differential
5
1.2 1.5
1.2 1.5
Single
ended
Differential
linearity
error
ADC clock frequency ≤
80 MHz,
1
1
3
1.2
1.2
3.5
Differential
Sampling rate ≤ 5.33 Msps,
1.65 V ≤ VDDA = VREF+
3.6 V,
≤
Single
ended
Integral
linearity
error
2.5 3.5
Voltage scaling Range 1
2
2
2.5
Differential
2.5
Fast channel (max speed) 10 10.4
Slow channel (max speed) 10 10.4
Fast channel (max speed) 10.6 10.7
Slow channel (max speed) 10.6 10.7
-
-
-
-
-
-
-
-
-
-
-
-
Single
ended
Effective
ENOB number of
bits
bits
Differential
Fast channel (max speed) 62
Slow channel (max speed) 62
Fast channel (max speed) 65
Slow channel (max speed) 65
Fast channel (max speed) 63
Slow channel (max speed) 63
Fast channel (max speed) 66
Slow channel (max speed) 66
64
64
66
66
65
65
67
67
Single
ended
Signal-to-
noise and
distortion
ratio
SINAD
Differential
dB
Single
ended
Signal-to-
SNR
noise ratio
Differential
222/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)(2)(3)
Table 85. ADC accuracy - limited test conditions 3
(continued)
Sym-
bol
Parameter
Conditions(4)
Min Typ Max Unit
ADC clock frequency ≤
80 MHz,
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
-
-
-
-69 -67
-71 -67
-72 -71
Single
ended
Total
THD harmonic
distortion
Sampling rate ≤ 5.33 Msps,
dB
1.65 V ≤ VDDA = VREF+
3.6 V,
≤
Differential
Slow channel (max speed)
-
-72 -71
Voltage scaling Range 1
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.
DS12023 Rev 5
223/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)(2)(3)
Table 86. ADC accuracy - limited test conditions 4
Conditions(4)
Sym-
bol
Parameter
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
4
4
5.4
5
Single
ended
Total
unadjusted
error
ET
EO
EG
ED
EL
5
Differential
3.5 4.5
2
2
4
4
Single
ended
Offset
error
2
3.5
3.5
4.5
4.5
4
Differential
2
4
Single
ended
4
Gain error
LSB
3
Differential
3
4
1
1.5
1.5
1.2
1.2
3
Single
ended
Differential
linearity
error
1
1
ADC clock frequency ≤
26 MHz,
Differential
1
1.65 V ≤ VDDA = VREF+ ≤
3.6 V,
2.5
2.5
2
Single
ended
Integral
linearity
error
Voltage scaling Range 2
3
2.5
2.5
-
Differential
2
Fast channel (max speed) 10.2 10.5
Slow channel (max speed) 10.2 10.5
Fast channel (max speed) 10.6 10.7
Slow channel (max speed) 10.6 10.7
Single
ended
Effective
ENOB number of
bits
-
bits
-
Differential
-
Fast channel (max speed) 63
Slow channel (max speed) 63
Fast channel (max speed) 65
Slow channel (max speed) 65
Fast channel (max speed) 64
Slow channel (max speed) 64
Fast channel (max speed) 66
Slow channel (max speed) 66
65
65
66
66
65
65
67
67
-
Single
ended
Signal-to-
noise and
distortion
ratio
-
SINAD
-
Differential
-
dB
-
Single
ended
-
Signal-to-
SNR
noise ratio
-
Differential
-
224/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)(2)(3)
Table 86. ADC accuracy - limited test conditions 4
(continued)
Sym-
bol
Parameter
Conditions(4)
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-71 -69
-71 -69
-73 -72
-73 -72
ADC clock frequency ≤
26 MHz,
Single
ended
Total
THD harmonic 1.65 V ≤ VDDA = VREF+ ≤
dB
distortion
3.6 V,
Differential
Voltage scaling Range 2
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
V
DDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Figure 40. ADC accuracy characteristics
VSSA
4095
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4094
4093
ET = total unajusted error: maximum deviation
between the actual and ideal transfer curves.
EO = offset error: maximum deviation
between the first actual transition and
the first ideal one.
(2)
ET
(3)
7
6
(1)
EG = gain error: deviation between the last
ideal transition and the last actual one.
ED = differential linearity error: maximum
deviation between actual steps and the ideal ones.
EL = integral linearity error: maximum deviation
between any actual transition and the end point
correlation line.
5
EO
EL
4
3
2
1
ED
1 LSB IDEAL
0
4096
VDDA
4094 4095
7
4093
2
3
4
5
6
1
MS19880V2
Figure 41. Typical connection diagram using the ADC
VDDA
VT
VT
Sample and hold ADC converter
(1)
RAIN
RADC
AINx
12-bit
converter
(2)
(3)
Cparasitic
CADC
Ilkg
VAIN
MS33900V5
1. Refer to Table 81: ADC characteristics for the values of RAIN and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 75: I/O static characteristics for the value of the pad capacitance). A high
C
parasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 75: I/O static characteristics for the values of Ilkg
.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 25: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
226/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
6.3.22
Digital-to-Analog converter characteristics
(1)
Table 87. DAC characteristics
Conditions
Symbol
Parameter
Min
1.71
1.80
1.71
1.80
Typ
Max
Unit
DAC output buffer OFF, DAC_OUT
pin not connected (internal
connection only)
-
-
-
-
Analog supply voltage for
DAC ON
VDDA
3.6
Other modes
DAC output buffer OFF, DAC_OUT
pin not connected (internal
connection only)
V
VREF+
Positive reference voltage
Negative reference voltage
VDDA
Other modes
-
VREF-
VSSA
connected to VSSA
DAC output
5
25
9.6
-
-
-
-
RL
Resistive load
kΩ
kΩ
buffer ON
connected to VDDA
-
11.7
-
RO
Output Impedance
DAC output buffer OFF
13.8
2
Output impedance sample VDD = 2.7 V
and hold mode, output
RBON
kΩ
kΩ
VDD = 2.0 V
-
-
-
-
-
-
3.5
buffer ON
Output impedance sample VDD = 2.7 V
and hold mode, output
16.5
18.0
RBOFF
VDD = 2.0 V
buffer OFF
CL
DAC output buffer ON
Sample and hold mode
-
-
-
50
1
pF
µF
Capacitive load
CSH
0.1
VREF+
– 0.2
DAC output buffer ON
0.2
-
Voltage on DAC_OUT
output
VDAC_OUT
V
DAC output buffer OFF
±0.5 LSB
0
-
-
VREF+
3
1.7
Normal mode
DAC output
buffer ON
CL ≤ 50 pF,
RL ≥ 5 kΩ
Settling time (full scale: for
a 12-bit code transition
between the lowest and the
±1 LSB
-
1.6
2.9
±2 LSB
±4 LSB
±8 LSB
-
1.55
1.48
1.4
2.85
2.8
tSETTLING highest input codes when
DAC_OUT reaches final
µs
-
-
2.75
value ±0.5LSB, ±1 LSB,
±2 LSB, ±4 LSB, ±8 LSB)
Normal mode DAC output buffer
OFF, ±1LSB, CL = 10 pF
-
-
-
-
2
2.5
7.5
5
Normal mode DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
Wakeup time from off state
4.2
2
(setting the ENx bit in the
DAC Control register) until
final value ±1 LSB
(2)
tWAKEUP
µs
Normal mode DAC output buffer
OFF, CL ≤ 10 pF
Normal mode DAC output buffer ON
CL ≤ 50 pF, RL = 5 kΩ, DC
PSRR
VDDA supply rejection ratio
-80
-28
dB
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
Table 87. DAC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Minimal time between two
consecutive writes into the
DAC_DORx register to
guarantee a correct
DAC_OUT for a small
variation of the input code
(1 LSB)
TW_to_W
-
-
µs
DAC_MCR:MODEx[2:0] =
000 or 001
DAC_MCR:MODEx[2:0] =
010 or 011
CL ≤ 50 pF, RL ≥ 5 kΩ
CL ≤ 10 pF
1
1.4
-
DAC output buffer
0.7
3.5
18
ON, CSH = 100 nF
DAC_OUT
ms
Sampling time in sample
and hold mode (code
transition between the
lowest input code and the
highest input code when
DACOUT reaches final
value ±1LSB)
pin connected
DAC output buffer
OFF, CSH = 100 nF
-
10.5
tSAMP
DAC_OUT
pin not
connected
(internal
connection
only)
DAC output buffer
OFF
-
2
3.5
µs
Sample and hold mode,
DAC_OUT pin connected
(3)
Ileak
Output leakage current
-
-
-
nA
Internal sample and hold
capacitor
CIint
-
5.2
7
8.8
pF
µs
tTRIM
Middle code offset trim time DAC output buffer ON
50
-
-
-
-
-
VREF+ = 3.6 V
1500
750
Middle code offset for 1 trim
code step
Voffset
µV
µA
VREF+ = 1.8 V
-
No load, middle
code (0x800)
-
-
-
315
450
500
670
DAC output
buffer ON
No load, worst code
(0xF1C)
DAC consumption from
VDDA
DAC output
buffer OFF
No load, middle
code (0x800)
I
DDA(DAC)
-
0.2
315 ₓ
670 ₓ
Sample and hold mode, CSH
100 nF
=
Ton/(Ton Ton/(Ton
+Toff) +Toff)
-
(4)
(4)
228/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)
Table 87. DAC characteristics (continued)
Parameter Conditions Min
No load, middle
Symbol
Typ
Max
Unit
-
-
-
185
240
code (0x800)
DAC output
buffer ON
No load, worst code
(0xF1C)
340
400
DAC output
buffer OFF
No load, middle
code (0x800)
155
205
DAC consumption from
VREF+
IDDV(DAC)
µA
185 ₓ
Ton/(Ton Ton/(Ton
400 ₓ
Sample and hold mode, buffer ON,
CSH = 100 nF, worst case
-
-
+Toff)
+Toff)
(4)
(4)
155 ₓ
205 ₓ
Sample and hold mode, buffer OFF,
CSH = 100 nF, worst case
Ton/(Ton Ton/(Ton
+Toff) +Toff)
(4)
(4)
1. Guaranteed by design.
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Refer to Table 75: I/O static characteristics.
4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0432 reference manual for more details.
Figure 42. 12-bit buffered / non-buffered DAC
Buffered/non-buffered DAC
Buffer(1)
RLOAD
12-bit
DACx_OUT
digital to
analog
converter
CLOAD
ai17157d
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
.
(1)
Table 88. DAC accuracy
Conditions
DAC output buffer ON
Symbol
Parameter
Min
Typ
Max
Unit
-
-
-
±2
±2
Differential non
linearity (2)
DNL
-
DAC output buffer OFF
10 bits
-
monotonicity
guaranteed
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±4
±4
Integral non
linearity(3)
INL
DAC output buffer OFF
CL ≤ 50 pF, no RL
VREF+ = 3.6 V
VREF+ = 1.8 V
±12
±25
±8
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
LSB
Offset error at
code 0x800(3)
Offset
DAC output buffer OFF
CL ≤ 50 pF, no RL
Offset error at
code 0x001(4)
DAC output buffer OFF
CL ≤ 50 pF, no RL
Offset1
±5
VREF+ = 3.6 V
VREF+ = 1.8 V
±5
Offset Error at
OffsetCal code 0x800
after calibration
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
±7
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
±0.5
±0.5
±30
±12
Gain
Gain error(5)
%
DAC output buffer OFF
CL ≤ 50 pF, no RL
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
Total
unadjusted
error
TUE
LSB
LSB
DAC output buffer OFF
CL ≤ 50 pF, no RL
Total
unadjusted
error after
calibration
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
TUECal
-
-
±23
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
1 kHz, BW 500 kHz
-
-
71.2
71.6
-
-
Signal-to-noise
ratio
SNR
THD
dB
dB
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
BW 500 kHz
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
-
-
-78
-79
-
-
Total harmonic
distortion
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
230/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)
Table 88. DAC accuracy (continued)
Conditions Min
DAC output buffer ON
Symbol
Parameter
Typ
Max
Unit
-
-
-
-
70.4
-
Signal-to-noise
and distortion
ratio
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
SINAD
dB
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
71
-
-
-
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
11.4
11.5
Effective
number of bits
ENOB
bits
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
1. Guaranteed by design.
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON.
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
6.3.23
Voltage reference buffer characteristics
(1)
Table 89. VREFBUF characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
RS = 0
2.4
2.8
-
3.6
3.6
Normal mode
VRS = 1
VRS = 0
-
Analog supply
voltage
VDDA
1.65
-
2.4
Degraded mode(2)
Normal mode
V
RS = 1
RS = 0
1.65
-
2.8
V
V
2.037
2.042
2.047
2.506
VDDA
VDDA
Voltage
reference
output
VRS = 1
VRS = 0
VRS = 1
2.494
2.5
VREFBUF_
OUT
VDDA-150 mV
VDDA-150 mV
-
-
Degraded mode(2)
Trim step
resolution
TRIM
CL
-
-
-
-
±0.05
1
±0.1
1.5
%
Load capacitor
-
-
0.5
µF
Equivalent
Serial Resistor
of Cload
esr
-
-
-
-
-
-
2
4
Ω
Static load
current
Iload
-
mA
I
load = 500 µA
-
-
200
100
1000
500
Iline_reg
Line regulation 2.8 V ≤ VDDA ≤ 3.6 V
Load
ppm/V
ppm/mA
Iload = 4 mA
Iload_reg
500 μA ≤ Iload ≤4 mA Normal mode
-
-
50
-
500
regulation
Tcoeff_
-40 °C < TJ < +125 °C
vrefint +
50
Temperature
coefficient
TCoeff
ppm/ °C
Tcoeff_
0 °C < TJ < +50 °C
-
-
+
vrefint
50
DC
40
25
-
60
40
-
Power supply
rejection
PSRR
tSTART
dB
µs
100 kHz
-
CL = 0.5 µF(3)
CL = 1.1 µF(3)
CL = 1.5 µF(3)
300
500
650
350
650
800
Start-up time
-
-
Control of
maximum DC
current drive
on VREFBUF_
OUT during
IINRUSH
-
-
-
8
-
mA
start-up phase
(4)
232/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)
Table 89. VREFBUF characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Iload = 0 µA
load = 500 µA
Iload = 4 mA
-
-
-
16
18
35
25
30
50
VREFBUF
consumption
from VDDA
IDDA(VREF
BUF)
I
µA
1. Guaranteed by design, unless otherwise specified.
2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA
drop voltage).
-
3. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.
4. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in
the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1.
DS12023 Rev 5
233/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
6.3.24
Comparator characteristics
(1)
Table 90. COMP characteristics
Conditions
Symbol
VDDA
Parameter
Min
Typ
Max
Unit
Analog supply voltage
-
-
1.62
-
3.6
Comparator input voltage
range
VIN
0
-
VDDA
V
(2)
VBG
Scaler input voltage
Scaler offset voltage
-
VREFINT
VSC
-
BRG_EN=0 (bridge disable)
BRG_EN=1 (bridge enable)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±5
200
0.8
100
-
±10
300
1
mV
nA
µA
µs
Scaler static consumption
from VDDA
I
DDA(SCALER)
tSTART_SCALER Scaler startup time
200
5
VDDA ≥ 2.7 V
High-speed
mode
V
V
V
DDA < 2.7 V
DDA ≥ 2.7 V
DDA < 2.7 V
-
7
Comparator startup time to
reach propagation delay
specification
tSTART
-
15
25
80
80
100
0.9
1
µs
ns
Medium mode
-
Ultra-low-power mode
-
VDDA ≥ 2.7 V
VDDA < 2.7 V
DDA ≥ 2.7 V
VDDA < 2.7 V
55
65
0.55
0.65
5
High-speed
mode
Propagation delay for
200 mV step
with 100 mV overdrive
(3)
tD
V
Medium mode
µs
Ultra-low-power mode
12
Full common
mode range
Voffset
Comparator offset error
Comparator hysteresis
-
-
±5
±20
mV
No hysteresis
-
-
-
-
0
8
-
-
-
-
Low hysteresis
Medium hysteresis
High hysteresis
Vhys
mV
15
27
234/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)
Table 90. COMP characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static
-
400
600
Ultra-low-
power mode
With 50 kHz
±100 mV overdrive
square signal
nA
-
-
-
-
-
1200
5
-
Static
7
Comparator consumption
from VDDA
With 50 kHz
±100 mV overdrive
square signal
IDDA(COMP)
Medium mode
6
-
100
-
µA
nA
Static
70
75
High-speed
mode
With 50 kHz
±100 mV overdrive
square signal
Comparator input bias
current
(4)
-
-
-
-
I
bias
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 24: Embedded internal voltage reference.
3. Guaranteed by characterization results.
4. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 75: I/O static characteristics.
6.3.25
Operational amplifiers characteristics
(1)
Table 91. OPAMP characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply
voltage
VDDA
CMIR
-
1.8
-
3.6
V
Common mode
input range
-
0
-
VDDA
V
25 °C, No Load on output.
All voltage/Temp.
Normal mode
-
-
-
-
-
-
±1.5
Input offset
voltage
VIOFFSET
mV
±3
-
±5
±10
Input offset
voltage drift
∆VIOFFSET
μV/°C
mV
Low-power mode
-
Offset trim step
TRIMOFFSETP at low common
TRIMLPOFFSETP input voltage
-
-
-
-
0.8
1
1.1
(0.1 ₓ VDDA
)
Offset trim step
TRIMOFFSETN at high common
TRIMLPOFFSETN input voltage
1.35
(0.9 ₓ VDDA
)
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
Table 91. OPAMP characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Normal mode
-
-
-
-
-
-
-
-
500
100
450
50
ILOAD
Drive current
VDDA ≥ 2 V
VDDA ≥ 2 V
Low-power mode
Normal mode
µA
Drive current in
PGA mode
ILOAD_PGA
Low-power mode
Resistive load
(connected to
VSSA or to
VDDA)
Normal mode
4
-
-
-
-
-
-
-
-
RLOAD
V
DDA < 2 V
Low-power mode
Normal mode
20
4.5
40
kΩ
Resistive load
in PGA mode
(connected to
VSSA or to
RLOAD_PGA
VDDA < 2 V
Low-power mode
V
)
DDA
CLOAD
CMRR
Capacitive load
-
-
-
-
-
50
-
pF
dB
Normal mode
-85
-90
Common mode
rejection ratio
Low-power mode
-
CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ DC
Normal mode
70
72
85
90
-
-
Power supply
rejection ratio
PSRR
GBW
dB
CLOAD ≤ 50 pf,
RLOAD ≥ 20 kΩ DC
Low-power mode
Normal mode
550
100
250
40
-
1600 2200
VDDA ≥ 2.4 V
(OPA_RANGE = 1)
Low-power mode
Normal mode
420
700
180
700
180
300
80
600
Gain Bandwidth
Product
kHz
950
VDDA < 2.4 V
(OPA_RANGE = 0)
Low-power mode
Normal mode
280
-
-
-
-
-
-
VDDA ≥ 2.4 V
Slew rate
Low-power mode
Normal mode
-
(from 10 and
90% of output
voltage)
SR(2)
V/ms
dB
-
VDDA < 2.4 V
Low-power mode
Normal mode
-
55
45
110
110
AO
Open loop gain
Low-power mode
VDDA
100
-
-
Normal mode
-
-
-
-
High saturation
voltage
Iload = max or Rload
=
=
(2)
VOHSAT
min Input at VDDA
.
VDDA
50
Low-power mode
mV
Normal mode
-
-
-
-
-
100
Low saturation
voltage
Iload = max or Rload
min Input at 0.
(2)
VOLSAT
Low-power mode
Normal mode
-
50
-
74
66
φm
Phase margin
°
Low-power mode
-
236/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)
Table 91. OPAMP characteristics (continued)
Parameter Conditions Min
Symbol
Typ
Max
Unit
Normal mode
-
-
13
20
-
-
GM
Gain margin
dB
Low-power mode
CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ
follower
Normal mode
-
5
10
configuration
Wake up time
from OFF state.
tWAKEUP
µs
CLOAD ≤ 50 pf,
RLOAD ≥ 20 kΩ
follower
Low-power mode
-
-
10
-
30
configuration
General purpose input (all packages
except UFBGA132 and UFBGA169 only)
(3)
TJ ≤ 75 °C
-
-
-
-
-
-
-
-
-
-
1
3
8
15
-
OPAMP input
bias current
Ibias
nA
Dedicated input
TJ ≤ 85 °C
-
(UFBGA132 and
UFBGA169 only)
TJ ≤ 105 °C
TJ ≤ 125 °C
-
-
2
4
-
Non inverting
gain value
PGA gain(2)
-
-
8
-
16
80/80
-
PGA Gain = 2
PGA Gain = 4
-
120/
40
-
-
-
-
-
-
R2/R1 internal
resistance
Rnetwork
kΩ/kΩ
140/
20
values in PGA
PGA Gain = 8
PGA Gain = 16
mode(4)
150/
10
Resistance
variation (R1 or
R2)
Delta R
-
-
-15
-
15
%
%
PGA gain error
PGA gain error
-1
-
-
1
-
GBW/
2
Gain = 2
Gain = 4
Gain = 8
Gain = 16
-
GBW/
4
-
-
-
-
-
-
-
-
-
PGA bandwidth
for different non
inverting gain
PGA BW
MHz
GBW/
8
GBW/
16
DS12023 Rev 5
237/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
Table 91. OPAMP characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
at 1 kHz, Output
loaded with 4 kΩ
Normal mode
-
500
-
at 1 kHz, Output
loaded with 20 kΩ
Low-power mode
Normal mode
-
-
-
600
180
290
-
-
-
Voltage noise
density
en
nV/√Hz
at 10 kHz, Output
loaded with 4 kΩ
at 10 kHz, Output
loaded with 20 kΩ
Low-power mode
OPAMP
Normal mode
-
-
120
45
260
100
no Load, quiescent
mode
IDDA(OPAMP)(2) consumption
from VDDA
µA
Low-power mode
1. Guaranteed by design, unless otherwise specified.
2. Guaranteed by characterization results.
3. Mostly I/O leakage, when used in analog mode. Refer to Ilkg parameter in Table 75: I/O static characteristics.
4. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between
OPAMP inverting input and ground. The PGA gain =1+R2/R1
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Electrical characteristics
6.3.26
Temperature sensor characteristics
Table 92. TS characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
TL
VTS linearity with temperature
-
±1
2.5
±2
2.7
°C
mV/°C
V
Avg_Slope(2) Average slope
2.3
V30
Voltage at 30°C (±5 °C)(3)
0.742
0.76
0.785
tSTART
Sensor Buffer Start-up time in continuous
-
-
8
70
-
15
120
-
µs
µs
µs
µA
(TS_BUF)(1) mode(4)
Start-up time when entering in continuous
(1)
tSTART
mode(4)
ADC sampling time when reading the
temperature
(1)
tS_temp
5
-
Temperature sensor consumption from VDD
when selected by ADC
,
IDD(TS)(1)
4.7
7
1. Guaranteed by design.
2. Guaranteed by characterization results.
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to
Table 8: Temperature sensor calibration values.
4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
6.3.27
V
monitoring characteristics
BAT
Table 93. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
39
3
-
-
-
kΩ
-
Ratio on VBAT measurement
Error on Q
Er(1)
-10
12
10
-
%
µs
(1)
tS_vbat
ADC sampling time when reading the VBAT
-
1. Guaranteed by design.
Table 94. V
charging characteristics
BAT
Symbol
Parameter Conditions
Min
Typ
5
Max
Unit
Battery
charging
resistor
VBRS = 0
VBRS = 1
-
-
-
-
RBC
kΩ
1.5
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
6.3.28
DFSDM characteristics
Unless otherwise specified, the parameters given in Table 95 for DFSDM are derived from
tests performed under the ambient temperature, f
frequency and V supply voltage
APB2
DD
conditions summarized in Table 21: General operating conditions.
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 x V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDM1_CKINy, DFSDM1_DATINy, DFSDM1_CKOUT for
DFSDM).
(1)
Table 95. DFSDM characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DFSDM
clock
fDFSDMCLK
-
-
-
fSYSCLK
MHz
fCKIN
(1/TCKIN
Input clock
frequency
SPI mode (SITP[1:0] =
01)
-
-
-
-
20
20
)
Output clock
frequency
fCKOUT
-
-
MHz
%
Output clock
DuCyCKOUT frequency
duty cycle
45
50
55
-
SPI mode (SITP[1:0] =
01),
External clock mode
(SPICKSEL[1:0] = 0)
Input clock
twh(CKIN)
TCKIN/2-
0.5
high and low
twl(CKIN)
T
CKIN/2
time
SPI mode
Data input
tsu
(SITP[1:0]=01),
External clock mode
(SPICKSEL[1:0] = 0)
1.5
0
-
-
-
-
-
setup time
ns
SPI mode
Data input
hold time
(SITP[1:0]=01),
External clock mode
(SPICKSEL[1:0] = 0)
th
Manchester Manchester mode
(CKOUT
DIV+1) ₓ
TDFSDMCLK
(2 ₓ
CKOUTDIV)ₓ
TDFSDMCLK
data period
(recovered
(SITP[1:0] = 10 or 11),
Internal clock mode
TManchester
clock period) (SPICKSEL[1:0] ≠ 0)
1. Data based on characterization results, not tested in production.
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DS12023 Rev 5
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Electrical characteristics
Figure 16: DFSDM timing diagram
WZO
WZK
WU
WI
63,&.6(/ꢍ ꢍꢅ
6,73ꢍ ꢍꢅꢅ
WVX WK
WVX WK
6,73ꢍ ꢍꢅꢄ
63,&.6(/ꢍ ꢍꢆ
63,&.6(/ꢍ ꢍꢂ
63,&.6(/ꢍ ꢍꢄ
6,73ꢍ ꢍꢅꢅ
WU
WI
WZO
WZK
WVX WK
WVX WK
6,73ꢍ ꢍꢅꢄ
6,73ꢍ ꢍꢂ
6,73ꢍ ꢍꢆ
5HFRYHUHGꢍFORFN
5HFRYHUHGꢍGDWD
ꢅ
ꢅ
ꢄ
ꢄ
ꢅ
06Yꢆꢉꢂꢉꢇ9ꢄ
6.3.29
Timer characteristics
The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
Table 96. TIMx characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
-
1
-
tTIMxCLK
ns
tres(TIM)
Timer resolution time
fTIMxCLK = 120 MHz
-
8.33
0
-
Timer external clock
frequency on CH1 to
CH4
f
TIMxCLK/2
MHz
fEXT
fTIMxCLK = 120 MHz
0
-
60
16
MHz
TIMx (except TIM2
and TIM5)
ResTIM
Timer resolution
bit
TIM2 and TIM5
-
-
32
1
65536
546.13
tTIMxCLK
µs
16-bit counter clock
period
tCOUNTER
fTIMxCLK = 120 MHz 0.00833
-
-
65536 × 65536
35.77
tTIMxCLK
Maximum possible
tMAX_COUNT count with 32-bit
counter
fTIMxCLK = 120 MHz
-
s
1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.
(1)
Table 97. IWDG min/max timeout period at 32 kHz (LSI)
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
Prescaler divider PR[2:0] bits
Unit
/4
/8
0
0.125
0.250
0.500
1.0
512
1024
2048
4096
8192
16384
32768
1
/16
/32
/64
/128
/256
2
3
4
ms
2.0
5
4.0
6 or 7
8.0
1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there
is always a full RC period of uncertainty.
Table 98. WWDG min/max timeout value at 120 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
Unit
1
2
4
8
0
1
2
3
0.0341
0.0683
0.1356
0.2731
2.1845
4.3691
8.7381
17.4763
ms
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DS12023 Rev 5
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Electrical characteristics
6.3.30
Communication interfaces characteristics
I2C interface characteristics
2
The I2C interface meets the timings requirements of the I C-bus specification and user
manual rev. 03 for:
•
•
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0432 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
is disabled, but is still present. Only FT_f I/O pins
DDIOx
support Fm+ low level output current maximum requirement. Refer to Section 6.3.17: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 99 below for the analog
filter characteristics:
(1)
Table 99. I2C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Maximum pulse width of spikes that
are suppressed by the analog filter
tAF
50(2)
260(3)
ns
1. Guaranteed by design.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
SPI characteristics
Unless otherwise specified, the parameters given in Table 100 for SPI are derived from tests
performed under the ambient temperature, f frequency and supply voltage conditions
PCLKx
summarized in Table 21: General operating conditions.
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 x V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)
Table 100. SPI characteristics
Symbol
Parameter
Conditions
Min
Typ
Max(2) Unit
Master mode
2.7 V < VDD < 3.6 V
Voltage Range V1
60
Master mode
1.71 V < VDD < 3.6 V
Voltage Range V1
46
60
Master transmitter mode
1.71 V < VDD < 3.6 V
Voltage Range V1
Slave receiver mode
1.71 V < VDD < 3.6 V
Voltage Range V1
fSCK
1/tc(SCK)
60
33
SPI clock frequency
-
-
MHz
Slave mode transmitter/full duplex
2.7 V < VDD < 3.6 V
Voltage Range V1
Slave mode transmitter/full duplex
1.71 V < VDD < 3.6 V
21
13
Voltage Range V1
1.71 V < VDD < 3.6 V
Voltage Range V2
1.08 V < VDD < 1.32 V(3)
12
-
tsu(NSS) NSS setup time
th(NSS) NSS hold time
tw(SCKH)
Slave mode, SPI prescaler = 2
Slave mode, SPI prescaler = 2
4ₓTPCLK
2ₓTPCLK
-
-
ns
ns
-
SCK high and low time Master mode
TPCLK-1
TPCLK
TPCLK+1 ns
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
Master mode
Slave mode
Master mode
Slave mode
1
2.5
6
-
-
-
-
-
-
Data input setup time
Data input hold time
ns
-
-
ns
ns
th(SI)
5.5
9
-
34
ta(SO) Data output access time Slave mode
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Electrical characteristics
(1)
Table 100. SPI characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max(2) Unit
tdis(SO) Data output disable time Slave mode
Slave mode
9
-
16
ns
2.7 V < VDD < 3.6 V
Voltage Range V1
-
-
13
10
15
Slave mode
1.71 V < VDD < 3.6 V
Voltage Range V1
23
tv(SO)
Data output valid time
Slave mode
1.71 V < VDD < 3.6 V
Voltage Range V2
-
-
13
29
25
39
ns
Slave mode
1.08 V < VDD < 1.32 V(3)
tv(MO)
th(SO)
th(MO)
Master mode
-
7
2
-
4
-
Slave mode 1.71 V < VDD < 3.6 V
Slave mode 1.08 < VDD < 1.32 V(3)
Master mode
Data output hold time
26
1
-
-
-
-
1. Guaranteed by characterization results.
2. The maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into
SCK low or high-phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a
master having tsu(MI) = 0 while Duty(SCK) = 50%.
3. SPI mapped on Port G.
Figure 43. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Figure 44. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
tf(SCK)
th(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
First bit OUT
tsu(SI) th(SI)
First bit IN
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
MISO output
MOSI input
Last bit OUT
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD
.
Figure 45. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD
.
SAI characteristics
Unless otherwise specified, the parameters given in Table 101 for SAI are derived from
tests performed under the ambient temperature, f
frequency and V supply voltage
DD
PCLKx
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DS12023 Rev 5
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Electrical characteristics
conditions summarized inTable 21: General operating conditions, with the following configu-
ration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 x V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (CK,SD,FS).
DS12023 Rev 5
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
Table 101. SAI characteristics
Parameter Conditions
SAI Main clock output
Symbol
Min
Max Unit
fMCLK
-
-
50
MHz
Master transmitter
2.7 V ≤ VDD ≤ 3.6 V
Voltage Range 1
-
23.5
Master transmitter
1.71 V ≤ VDD ≤ 3.6 V
Voltage Range 1
-
-
-
16
16
26
Master receiver
Voltage Range 1
Slave transmitter
2.7 V ≤ VDD ≤ 3.6 V
Voltage Range 1
fCK
SAI clock frequency(2)
MHz
Slave transmitter
1.71 V ≤ VDD ≤ 3.6 V
Voltage Range 1
-
-
20
25
Slave receiver
Voltage Range 1
Voltage Range 2
-
-
13
9
1.08 V ≤ VDD ≤ 1.32 V
Master mode
2.7 V ≤ VDD ≤ 3.6 V
-
-
21
30
tv(FS)
FS valid time
ns
Master mode
1.71 V ≤ VDD ≤ 3.6 V
th(FS)
tsu(FS)
FS hold time
FS setup time
FS hold time
Master mode
Slave mode
10
1.5
2.5
1
-
-
-
-
-
-
-
ns
ns
ns
th(FS)
Slave mode
tsu(SD_A_MR)
tsu(SD_B_SR)
th(SD_A_MR)
th(SD_B_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
Data input setup time
Data input hold time
ns
ns
1.5
6.5
2.5
Slave transmitter (after enable edge)
2.7 V ≤ VDD ≤ 3.6 V
-
-
19
25
Slave transmitter (after enable edge)
1.71 V ≤ VDD ≤ 3.6 V
tv(SD_B_ST) Data output valid time
ns
ns
Slave transmitter (after enable edge)
1.08 V < VDD <1.32 V
-
50
-
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge)
10
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Electrical characteristics
(1)
Table 101. SAI characteristics (continued)
Symbol
Parameter
Conditions
Min
Max Unit
Master transmitter (after enable edge)
2.7 V ≤ VDD ≤ 3.6 V
-
17
Master transmitter (after enable edge)
1.71 V ≤ VDD ≤ 3.6 V
tv(SD_A_MT) Data output valid time
-
25
ns
ns
Master transmitter (after enable edge)
1.08 V ≤ VDD ≤ 1.32 V
-
52
-
th(SD_A_MT) Data output hold time Master transmitter (after enable edge)
10
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
Figure 46. SAI master timing waveforms
1/f
SCK
SAI_SCK_X
t
h(FS)
SAI_FS_X
(output)
t
t
t
h(SD_MT)
v(FS)
v(SD_MT)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_MR)
su(SD_MR)
SAI_SD_X
(receive)
Slot n
MS32771V1
Figure 47. SAI slave timing waveforms
1/f
SCK
SAI_SCK_X
t
t
t
h(FS)
w(CKH_X)
w(CKL_X)
SAI_FS_X
(input)
t
t
t
h(SD_ST)
su(FS)
v(SD_ST)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_SR)
su(SD_SR)
SAI_SD_X
(receive)
Slot n
MS32772V1
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
USB OTG full speed (FS) characteristics
The device’s USB interface is fully compliant with the USB specification version 2.0 and is
USB-IF certified (for Full-speed device operation).
Table 102. USB electrical characteristics
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
Unit
USB OTG full speed
VDDUSB transceiver operating
voltage
-
3.0(2)
-
3.6
Over VCM
range
(3)
VDI
Differential input sensitivity
0.2
0.8
0.8
-
-
-
-
-
-
-
-
Differential input common
mode range
Includes VDI
range
(3)
VCM
2.5
2.0
0.3
3.6
24.8
Single ended receiver input
threshold
V
(3)
VSE
VOL
VOH
-
RL of 1.5 kΩ to
3.6 V(4)
Static output level low
Static output level high
RL of 15 kΩ to
3.6 V(4)
2.8
14.25
Pull down resistor on PA11,
PA12 (USB_FS_DP/DM)
(3)
RPD
VIN = VDD
Pull Up Resistor on PA12
(USB_FS_DP)
VIN = VSS
during idle
0.9
1.425
-
1.25
2.25
-
1.575
3.09
14.5
kΩ
Pull Up Resistor on PA12
(USB_FS_DP)
VIN = VSS
(3)
RPU
during reception
Pull Up Resistor on PA10
(OTG_FS_ID)
-
1. All the voltages are measured from the local ground potential.
2. The STM32L4R5xx USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full
USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
3. Guaranteed by design.
4. RL is the load connected on the USB OTG full speed drivers.
Note:
When VBUS sensing feature is enabled, PA9 should be left at its default state (floating
input), not as alternate function. A typical 200 μA current consumption of the sensing block
(current to voltage conversion to determine the different sessions) can be observed on PA9
when the feature is enabled.
250/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
Figure 48. USB OTG timings – definition of data signal rise and fall time
Cross over
points
Differential
data lines
VCRS
VSS
tf
tr
ai14137b
(1)
Table 103. USB OTG electrical characteristics
Driver characteristics
Symbol
Parameter
Conditions
Min Max Unit
trLS
Rise time in LS(2)
CL = 200 to 600 pF
75
80
4
300
125
20
ns
%
tfLS
Fall time in LS(2)
trfmLS
trFS
Rise/ fall time matching in LS
Rise time in FS(2)
tr / tf
CL = 50 pF
CL = 50 pF
tr / tf
ns
tfFS
Fall time in FS(2)
trfmFS
Rise/ fall time matching in FS
90
1.3
28
111
2.0
44
%
V
Output signal crossover voltage
(LS/FS)
VCRS
ZDRV
-
Output driver impedance(3)
Driving high or low
Ω
1. Guaranteed by design
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.
(1)
Table 104. USB BCD DC electrical characteristics
Driver characteristics
Symbol
Parameter
Conditions Min
Typ
Max
Unit
Primary detection mode
consumption
-
-
-
-
-
IDD(USBBCD)
300
μA
Secondary detection mode
consumption
-
RDAT_LKG
VDAT_LKG
Data line leakage resistance
Data line leakage voltage
300
0.0
-
-
-
kΩ
V
-
-
3.6
Dedicated charging port
resistance across D+/D-
RDCP_DAT
-
-
-
200
Ω
VLGC_HI
Logic high
Logic low
2.0
-
-
-
3.6
0.8
V
V
-
VLGC_LOW
-
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
Table 104. USB BCD DC electrical characteristics (continued)
Driver characteristics
Symbol
VLGC
Parameter
Logic threshold
Conditions Min
Typ
Max
Unit
-
-
-
-
-
-
0.8
0.25
0.5
0.5
25
-
-
-
-
-
-
2.0
0.4
0.7
0.7
175
175
V
V
VDAT_REF
VDP_SRC
VDM_SRC
IDP_SINK
IDM_SINK
Data detect voltage
D+ source voltage
D- source voltage
D+ sink current
V
V
μA
μA
D- sink current
25
1. Guaranteed by design
CAN (controller area network) interface
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
6.3.31
FSMC characteristics
Unless otherwise specified, the parameters given in Table 105 to Table 118 for the FMC
interface are derived from tests performed under the ambient temperature, f
frequency
HCLK
and V supply voltage conditions summarized in Table 21, with the following configuration:
DD
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 x V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 49 through Figure 52 represent asynchronous waveforms and Table 105 through
Table 112 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•
•
•
•
•
•
AddressSetupTime = 0x1
AddressHoldTime = 0x1
DataHoldTime = 0x1
ByteLaneSetup = 0x1
DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
BusTurnAroundDuration = 0x0
In all timing tables, the THCLK is the HCLK clock period.
252/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
Figure 49. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
t
w(NE)
FMC_NE
t
t
t
h(NE_NOE)
w(NOE)
v(NOE_NE)
FMC_NOE
FMC_NWE
tv(A_NE)
t
h(A_NOE)
FMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NOE)
FMC_NBL[1:0]
t
h(Data_NE)
t
t
su(Data_NOE)
h(Data_NOE)
t
su(Data_NE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
DS12023 Rev 5
253/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)(2)
Table 105. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol
Parameter
FMC_NE low time
Min
Max
Unit
tw(NE)
tv(NOE_NE)
tw(NOE)
3THCLK-0.5
3THCLK+1
FMC_NEx low to FMC_NOE low
FMC_NOE low time
0
1
2THCLK-0.5
2THCLK+1
th(NE_NOE)
tv(A_NE)
th(A_NOE)
tsu(Data_NE)
FMC_NOE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
Address hold time after FMC_NOE high
Data to FMC_NEx high setup time
THCLK
-
-
1
2THCLK-1
-
ns
THCLK+14
-
tsu(Data_NOE) Data to FMC_NOEx high setup time
14
0
0
-
-
th(Data_NOE)
th(Data_NE)
tv(NADV_NE)
tw(NADV)
Data hold time after FMC_NOE high
Data hold time after FMC_NEx high
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
-
0
-
THCLK+1.5
1. CL = 30 pF.
2. Guaranteed by characterization results.
Table 106. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT
(1)(2)
timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
8THCLK-0.5
8THCLK+1
tw(NOE)
FMC_NWE low time
FMC_NWAIT low time
7THCLK-0.5
THCLK
7THCLK+0.5
ns
tw(NWAIT)
-
-
-
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
5THCLK+12.5
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+12
1. CL = 30 pF.
2. Guaranteed by characterization results.
254/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
Figure 50. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FMC_NEx
FMC_NOE
FMC_NWE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
t
th(A_NWE)
v(A_NE)
FMC_A[25:0]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_NBL[1:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
(1)(2)
Table 107. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
Parameter
FMC_NE low time
Min
Max
Unit
tw(NE)
4THCLK-0.5
4THCLK+1
tv(NWE_NE) FMC_NEx low to FMC_NWE low
tw(NWE) FMC_NWE low time
th(NE_NWE) FMC_NWE high to FMC_NE high hold time
tv(A_NE) FMC_NEx low to FMC_A valid
th(A_NWE) Address hold time after FMC_NWE high
tv(BL_NE) FMC_NEx low to FMC_BL valid
THCLK-0.5
THCLK+1
THCLK-0.5
THCLK+1
2THCLK-0.5
-
-
0
2THCLK-1
-
ns
-
THCLK
th(BL_NWE) FMC_BL hold time after FMC_NWE high
tv(Data_NE) Data to FMC_NEx low to Data valid
th(Data_NWE) Data hold time after FMC_NWE high
tv(NADV_NE) FMC_NEx low to FMC_NADV low
2THCLK-0.5
-
-
THCLK+3
2THCLK+1
-
1
-
-
tw(NADV)
FMC_NADV low time
THCLK+1.5
1. CL = 30 pF.
2. Guaranteed by characterization results.
DS12023 Rev 5
255/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Table 108. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT
(1)(2)
timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
FMC_NWE low time
9THCLK-0.5 9THCLK+1.5
tw(NWE)
6THCLK-0.5
7THCLK-13
5THCLK+13
6THCLK+1
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid
-
-
1. CL = 30 pF.
2. Guaranteed by characterization results.
Figure 51. Asynchronous multiplexed PSRAM/NOR read waveforms
t
w(NE)
FMC_ NE
FMC_NOE
t
t
h(NE_NOE)
v(NOE_NE)
t
w(NOE)
t
FMC_NWE
t
h(A_NOE)
v(A_NE)
FMC_ A[25:16]
Address
NBL
t
t
v(BL_NE)
h(BL_NOE)
FMC_ NBL[1:0]
t
h(Data_NE)
t
su(Data_NE)
t
t
t
h(Data_NOE)
v(A_NE)
Address
su(Data_NOE)
Data
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
256/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)(2)
Table 109. Asynchronous multiplexed PSRAM/NOR read timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
4THCLK-0.5
2THCLK-0.5
THCLK-0.5
THCLK-1
-
4THCLK+1
tv(NOE_NE) FMC_NEx low to FMC_NOE low
tw(NOE) FMC_NOE low time
th(NE_NOE) FMC_NOE high to FMC_NE high hold time
tv(A_NE) FMC_NEx low to FMC_A valid
tv(NADV_NE) FMC_NEx low to FMC_NADV low
2THCLK+1
THCLK+0.5
-
3
0.5
1.5
tw(NADV)
FMC_NADV low time
THCLK
THCLK+1.5
ns
FMC_AD(address) valid hold time after
FMC_NADV high
th(AD_NADV)
T
HCLK-3
0
-
th(A_NOE) Address hold time after FMC_NOE high
tsu(Data_NE) Data to FMC_NEx high setup time
tsu(Data_NOE) Data to FMC_NOE high setup time
th(Data_NE) Data hold time after FMC_NEx high
th(Data_NOE) Data hold time after FMC_NOE high
-
-
-
-
-
THCLK+14
14
0
0
1. CL = 30 pF.
2. Guaranteed by characterization results.
(1)(2)
Table 110. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
9THCLK-0.5 9THCLK+ 1
6THCLK-0.5 6THCLK+1
tw(NOE)
FMC_NWE low time
ns
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
5THCLK+12
-
-
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+11
1. CL = 30 pF.
2. Guaranteed by characterization results.
DS12023 Rev 5
257/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Figure 52. Asynchronous multiplexed PSRAM/NOR write waveforms
t
w(NE)
FMC_ NEx
FMC_NOE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
FMC_NWE
t
t
h(A_NWE)
v(A_NE)
FMC_ A[25:16]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_ NBL[1:0]
NBL
v(Data_NADV)
Data
t
t
h(Data_NWE)
t
v(A_NE)
Address
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32756V1
(1)(2)
Table 111. Asynchronous multiplexed PSRAM/NOR write timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
5THCLK-0.5
THCLK-0.5
2THCLK-0.5
2THCLK-0.5
-
5THCLK+1
tv(NWE_NE) FMC_NEx low to FMC_NWE low
tw(NWE) FMC_NWE low time
th(NE_NWE) FMC_NWE high to FMC_NE high hold time
tv(A_NE) FMC_NEx low to FMC_A valid
tv(NADV_NE) FMC_NEx low to FMC_NADV low
THCLK+1
2THCLK+0.5
-
3
1
0
tw(NADV)
FMC_NADV low time
THCLK+0.5
THCLK+1.5
ns
FMC_AD(adress) valid hold time after
FMC_NADV high
th(AD_NADV)
THCLK-3
-
th(A_NWE) Address hold time after FMC_NWE high
th(BL_NWE) FMC_BL hold time after FMC_NWE high
0
-
2THCLK-0.5
-
THCLK
THCLK+2
-
tv(BL_NE)
FMC_NEx low to FMC_BL valid
-
tv(Data_NADV) FMC_NADV high to Data valid
-
th(Data_NWE) Data hold time after FMC_NWE high
2THCLK+0.5
258/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
1. CL = 30 pF.
2. Guaranteed by characterization results.
(1)(2)
Table 112. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
FMC_NWE low time
10THCLK-0.5 10THCLK+1
7THCLK-0.5 7THCLK+0.5
tw(NWE)
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid
7THCLK+12.5
5THCLK+13
-
-
1. CL = 30 pF.
2. Guaranteed by characterization results.
Synchronous waveforms and timings
Figure 53 through Figure 56 represent synchronous waveforms and Table 113
through Table 116 provide the corresponding timings. The results shown in these
tables are obtained with the following FMC configuration:
•
•
•
•
•
BurstAccessMode = FMC_BurstAccessMode_Enable
MemoryType = FMC_MemoryType_CRAM
WriteBurst = FMC_WriteBurst_Enable
CLKDivision = 1
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all timing tables, the THCLK is the HCLK clock period.
•
For 2.7 V ≤ V ≤ 3.6 V, maximum FMC_CLK = 60 MHz for CLKDIV = 0x1 and 54 MHz
for CLKDIV = 0x0 at CL = 30 pF (on FMC_CLK).
DD
•
For 1.71 V ≤ V ≤ 2.7 V, maximum FMC_CLK = 60 MHz for CLKDIV = 0x1 and
32 MHz for CLKDIV = 0x0 at CL= 20 pF (on FMC_CLK).
DD
DS12023 Rev 5
259/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Figure 53. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
td(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
td(CLKH-AIV)
d(CLKL-AV)
FMC_A[25:16]
t
td(CLKH-NOEH)
d(CLKL-NOEL)
FMC_NOE
t
t
t
h(CLKH-ADV)
su(ADV-CLKH)
d(CLKL-ADIV)
t
t
t
su(ADV-CLKH)
d(CLKL-ADV)
h(CLKH-ADV)
FMC_AD[15:0]
AD[15:0]
t
D1
D2
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
MS32757V1
260/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)(2)(3)
Table 113. Synchronous multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max Unit
tw(CLK)
FMC_CLK period
RxTHCLK-0.5
-
2.5
-
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
RxTHCLK/2 +1
-
2.5
-
2
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
5.5
-
RxTHCLK/2 +1
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low
-
2
-
ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high
RxTHCLK/2 +1
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
-
0
3
-
2
-
4
-
1.5
4
-
-
1. CL = 30 pF.
2. Guaranteed by characterization results.
3. Clock ratio R = (HCLK period /FMC_CLK period).
DS12023 Rev 5
261/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Figure 54. Synchronous multiplexed PSRAM write timings
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262/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)(2)(3)
Table 114. Synchronous multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
RxTHCLK- 0.5
-
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
2.5
RxTHCLK/2 +1
-
-
2.5
2
-
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
5.5
RxTHCLK/2 +1
-
2
-
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high
-
ns
RxTHCLK/2 +1
td(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid
-
3
-
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low
0
-
3.5
-
1
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high
RxTHCLK/2 +1.5
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
1.5
4
-
-
1. CL = 30 pF.
2. Guaranteed by characterization results.
3. Clock ratio R = (HCLK period /FMC_CLK period).
DS12023 Rev 5
263/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Figure 55. Synchronous non-multiplexed NOR/PSRAM read timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKH-NExH)
d(CLKL-NExL)
Data latency = 0
d(CLKL-NADVH)
FMC_NEx
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
t
t
d(CLKH-AIV)
d(CLKL-AV)
t
t
d(CLKL-NOEL)
d(CLKH-NOEH)
FMC_NOE
t
t
su(DV-CLKH)
h(CLKH-DV)
su(DV-CLKH)
t
t
h(CLKH-DV)
FMC_D[15:0]
FMC_NWAIT
D1
D2
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
MS32759V1
Table 115. Synchronous non-multiplexed NOR/PSRAM
(1)(2)(3)
read timings
Symbol
Parameter
Min
Max Unit
tw(CLK)
FMC_CLK period
FMC_CLK low to FMC_NEx low (x=0..2)
RxTHCLK -0.5
-
2.5
-
td(CLKL-NExL)
-
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
RxTHCLK/2 +1
-
2.5
-
2
td(CLKL-AV)
td(CLKH-AIV)
td(CLKL-NOEL)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK low to FMC_NOE low
-
5.5
ns
RxTHCLK/2 +0.5
-
2
-
-
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high
RxTHCLK/2 +1
2
4
-
-
264/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
Table 115. Synchronous non-multiplexed NOR/PSRAM
(1)(2)(3)
read timings
(continued)
Symbol
Parameter
Min
Max Unit
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
1.5
4
-
ns
-
1. CL = 30 pF.
2. Guaranteed by characterization results.
3. Clock ratio R = (HCLK period /FMC_CLK period).
Figure 56. Synchronous non-multiplexed PSRAM write timings
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DS12023 Rev 5
265/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)(2)(3)
Table 116. Synchronous non-multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
RxTHCLK-0.5
-
td(CLKL-NExL)
td(CLKH-NExH)
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
-
2.5
RxTHCLK/2 +1
-
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
2
-
2.5
-
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
5.5
FMC_CLK high to FMC_Ax invalid (x=16…25) RxTHCLK/2 +0.5
-
ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high
-
2
RxTHCLK/2 +1
-
td(CLKL-Data)
td(CLKL-NBLL)
FMC_D[15:0] valid data after FMC_CLK low
FMC_CLK low to FMC_NBL low
-
3.5
1
-
-
-
-
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
RxTHCLK/2 +1.5
1.5
4
1. CL = 30 pF.
2. Guaranteed by characterization results.
3. Clock ratio R = (HCLK period /FMC_CLK period).
NAND controller waveforms and timings
Figure 57 through Figure 60 represent synchronous waveforms, and Table 117 and
Table 118 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
COM.FMC_SetupTime = 0x01
COM.FMC_WaitSetupTime = 0x03
COM.FMC_HoldSetupTime = 0x02
COM.FMC_HiZSetupTime = 0x01
ATT.FMC_SetupTime = 0x01
ATT.FMC_WaitSetupTime = 0x03
ATT.FMC_HoldSetupTime = 0x02
ATT.FMC_HiZSetupTime = 0x01
Bank = FMC_Bank_NAND
MemoryDataWidth = FMC_MemoryDataWidth_16b
ECC = FMC_ECC_Enable
ECCPageSize = FMC_ECCPageSize_512Bytes
TCLRSetupTime = 0
TARSetupTime = 0
In all timing tables, the T
is the HCLK clock period.
DS12023 Rev 5
HCLK
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STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
Figure 57. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
th(NOE-ALE)
td(NCE-NOE)
FMC_NOE (NRE)
FMC_D[15:0]
tsu(D-NOE)
th(NOE-D)
MSv38003V1
Figure 58. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
th(NWE-ALE)
td(NCE-NWE)
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
th(NWE-D)
tv(NWE-D)
MSv38004V1
Figure 59. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
th(NOE-ALE)
td(NCE-NOE)
FMC_NWE
tw(NOE)
FMC_NOE
tsu(D-NOE)
th(NOE-D)
FMC_D[15:0]
MSv38005V1
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Figure 60. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NWE)
tw(NWE)
th(NOE-ALE)
FMC_NWE
FMC_NOE
td(D-NWE)
tv(NWE-D)
th(NWE-D)
FMC_D[15:0]
MSv38006V1
(1)(2)
Table 117. Switching characteristics for NAND Flash read cycles
Symbol
Parameter
FMC_NOE low width
Min
Max
Unit
Tw(N0E)
Tsu(D-NOE)
Th(NOE-D)
4THCLK-0.5 4THCLK+0.5
FMC_D[15-0] valid data before FMC_NOE high
FMC_D[15-0] valid data after FMC_NOE high
14
-
0
-
ns
Td(NCE-NOE) FMC_NCE valid before FMC_NOE low
Th(NOE-ALE) FMC_NOE high to FMC_ALE invalid
-
3THCLK+1
-
3THCLK-0.5
1. CL = 30 pF.
2. Guaranteed by characterization results.
(1)(2)
Table 118. Switching characteristics for NAND Flash write cycles
Symbol
Parameter
FMC_NWE low width
Min
Max
Unit
Tw(NWE)
Tv(NWE-D)
Th(NWE-D)
Td(D-NWE)
2THCLK-0.5 4THCLK+0.5
FMC_NWE low to FMC_D[15-0] valid
FMC_NWE high to FMC_D[15-0] invalid
FMC_D[15-0] valid before FMC_NWE high
5
-
2THCLK-1
5THCLK-1
-
-
ns
-
Td(NCE_NWE) FMC_NCE valid before FMC_NWE low
3THCLK-1
-
Th(NWE-ALE)
FMC_NWE high to FMC_ALE invalid
3THCLK-0.5
1. CL = 30 pF.
2. Guaranteed by characterization results.
268/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
6.3.32
OctoSPI characteristics
Unless otherwise specified, the parameters given in Table 119, Table 120 and Table 121 for
OctoSPI are derived from tests performed under the ambient temperature, f frequency
AHB
and V supply voltage conditions summarized in Table 21: General operating conditions,
DD
with the following configuration:
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Measurement points are done at CMOS levels: 0.5 x V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics.
(1)
(2)
Table 119. OctoSPI characteristics in SDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.71 V < VDD< 3.6 V
Voltage Range 1
CLOAD = 20 pF
-
-
58
2.7 V < VDD< 3.6 V
Voltage Range 1
CLOAD = 20 pF
-
-
86
OctoSPI clock
frequency
F(QCK)
MHz
1.71 V < VDD< 3.6 V
Voltage Range 1
CLOAD = 15 pF
-
-
-
-
66
26
1.71 V < VDD< 3.6 V
Voltage Range 2
CLOAD = 20 pF
tw(CKH)
tw(CKL)
OctoSPI clock
high and low Prescaler = 0
time
t(CK)/2-1
t(CK)/2-1
-
-
t(CK)/2
t(CK)/2
Voltage Range 1
Data input
0.5
-
-
-
ts(IN)
setup time
Voltage Range 2
0
-
Voltage Range 1
Data input
7.75
-
-
-
ns
th(IN)
hold time
Voltage Range 2
10.5
-
Voltage Range 1
Data output
-
-
2
4
-
3.5
5.5
-
tv(OUT)
valid time
Voltage Range 2
Voltage Range 1
Data output
0
0
th(OUT)
hold time
Voltage Range 2
-
-
1. Values in the table applies to Octal and Quad SPI mode.
2. Guaranteed by characterization results.
DS12023 Rev 5
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Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
(2)
Table 120. OctoSPI characteristics in DTR mode (no DQS)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.71 V < VDD < 3.6 V
Voltage Range 1
CLOAD = 20 pF
-
-
58
2.7 V < VDD < 3.6 V
Voltage Range 1
CLOAD = 20 pF
-
-
-
-
-
-
60
60
26
FCK
OctoSPI clock
frequency
MHz
1/t(CK)
1.71 V < VDD < 3.6 V
Voltage Range 1
CLOAD = 15 pF
1.71 V < VDD < 3.6 V
Voltage Range 2
CLOAD = 20 pF
tw(CKH)
tw(CKL)
t(CK)/2-1
t(CK)/2-1
0.5
-
t(CK)/2+0.5
OctoSPI clock high
and low time
-
-
t(CK)/2+0.5
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
-
-
-
-
tsf(IN)
tsr(IN)
Data input
setup time
1
7.75
-
-
thf(IN)
thr(IN)
Data input
hold time
10.75
-
-
DHQC = 0
4.5
6
ns
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
tvr(OUT)
tvf(OUT)
DHQC = 1
Data output
valid time
-
tpclk/4+1
tpclk/4+3
Pres=1,2 ...
DHQC = 0
DHQC = 0
8.5
-
12
-
1
DHQC = 1
thr(OUT) Data output
thf(OUT) hold time
tpclk/4-2
3.5
-
-
-
-
Pres=1,2 ...
DHQC = 0
1. Values in the table applies to Octal and Quad SPI mode.
2. Guaranteed by characterization results.
270/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)
Table 121. OctoSPI characteristics in DTR mode (with DQS) /Octal and HyperBus™
Symbol
Parameter
Conditions
Min
Typ
Max(2)
Unit
1.71 V < VDD < 3.6 V
Voltage Range 1
CLOAD = 20 pF
-
-
60
2.7 V < VDD < 3.6 V
Voltage Range 1
CLOAD = 20 pF
-
-
-
-
-
-
64
60
26
OctoSPI clock
frequency
(Octal Flash and
HyperFlash™)
1.71 V < VDD < 3.6 V
Voltage Range 1
CLOAD = 15 pF
1.71 V < VDD < 3.6 V
Voltage Range 2
CLOAD = 20 pF
FCK
MHz
1/t(CK)
Prescaler =
0,1,3,5...
1.71 < VDD < 3.6 V
Voltage Range V1
-
-
-
-
-
-
-
-
18
25
22
29
CLOAD = 20 pF
tCKDS = 9ns
Prescaler =
2,4,6...
2.7 < VDD < 3.6 V Prescaler =
OctoSPI clock
frequency
(HyperRAM™)
0,1,3,5...
Voltage Range V1
CLOAD = 20 pF
tCKDS = 9ns
Prescaler =
2,4,6...
1.71 < VDD < 3.6 V
Voltage Range V2
CLOAD = 20 pF
tCKDS = 9ns
-
-
-
17
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
(1)
Table 121. OctoSPI characteristics in DTR mode (with DQS) /Octal and HyperBus™ (continued)
Symbol
Parameter
Conditions
Min
Typ
Max(2)
Unit
tw(CKH)
t(CK)/2-1
t(CK)/2-0.5
-
-
-
-
-
t(CK)/2+0.5
t(CK)/2+0.5
t(CK)+1
-
OctoSPI clock high
and low time
-
tw(CKL)
tv(CK) Clock valid time
th(CK) Clock hold time
-
-
t(CK)/2-0.5
Chip select high
tw(CS)
time
-
-
-
-
-
3 x t(CK)
-
-
-
-
-
-
Data input vallid
tv(DQ)
time
0
0
0
-
-
Data storbe input
tv(DS)
-
ns
valid time
Data storbe input
hold time
th(DS)
-
Data storbe output
tv(RWDS)
3 x t(CK)
valid time
Voltage Range 1
-3.5
-5.5
5.75
9
-
t(CK)/2-5.75(3)
tsr(IN) Data input
tsf(IN) setup time
Voltage Range 2
Voltage Range 1
Voltage Range 2
-
-
t(CK)/2-9(3)
-
-
thr(IN) Data input
thf(IN) hold time
-
DHQC = 0
4.5
6
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
tvr(OUT)
DHQC = 1
Data output
valid time
tpclk/4+1.
5
-
tpclk/4+2.25
tvf(OUT)
Pres=1,2 ...
DHQC = 0
DHQC = 0
8
-
11
-
ns
0.5
tpclk/4-1.75
0.75
thr(OUT)
DHQC = 1
Data output
hold time
-
-
-
-
thf(OUT)
Pres=1,2 ...
DHQC = 0
1. Guaranteed by characterization results.
2. Maximum frequency values are given for a RWDS to DQ skew of maximum +/-1.0 ns.
3. Data input setup time maximum does not take into account Data level switching duration.
272/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
Figure 61. OctoSPI timing diagram - SDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tv(OUT)
th(OUT)
Data output
D0
D1
D2
ts(IN)
th(IN)
Data input
D0
D1
D2
MSv36878V1
Figure 62. OctoSPI timing diagram - DDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tvf(OUT) thr(OUT)
D0
tvr(OUT)
thf(OUT)
D3
Data output
D1
D2
D4
tsr(IN)thr(IN)
D5
tsf(IN) thf(IN)
Data input
D0
D1
D2
D3
D4
D5
MSv36879V1
Figure 63. OctoSPI HyperBus™ clock
tr(CK)
tw(CKH)
tw(CKL)
t(CK)
tf(CK)
VOD(CK)
CK
MSv47732V2
DS12023 Rev 5
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280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Figure 64. OctoSPI HyperBus™ read
tw(CS)
CS#
th(CK)
tv(CK)
tACC= Initial Access
CK
tv(RWDS)
tv(DS)
th(DS)
RWDS
tv(OUT)
th(OUT)
tv(DQ)
ts(DQ)
th(DQ)
Latency Count
Dn
Dn
Dn+1
A
Dn+1
47:40 39:32 31:24 23:16 15:8
7:0
DQ[7:0]
A
B
B
Command-Address
Memory drives DQ[7:0] and RWDS
MSv47733V2
Host drives DQ[7:0] and Memory drives RWDS
Figure 65. OctoSPI HyperBus™ read with double latency
CS#
tRWR=Read Write Recovery
Additional Latency
tACC = Access
CK
tCKDS
RWDS
High = 2x Latency Count
Low = 1x Latency Count
RWDS and Data
are edge aligned
Dn
A
Dn Dn+1 Dn+1
47:40 39:32 31:24 23:16 15:8 7:0
DQ[7:0]
B
A
B
Command-Address
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
MSv49351V2
274/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
Figure 66. OctoSPI HyperBus™ write
tw(CS)
CS#
Read Write Recovery
tv(CK)
Access Latency
th(CK)
CK
th(OUT)
tv(OUT)
tv(RWDS)
High = 2x Latency Count
Low = 1x Latency Count
RWDS
Latency Count
th(OUT)
th(OUT)
tv(OUT)
tv(OUT)
Dn
A
Dn
B
Dn+1
A
Dn+1
B
47:40 39:32 31:24 23:16 15:8
7:0
DQ[7:0]
Command-Address
Host drives DQ[7:0] and RWDS
Host drives DQ[7:0] and Memory drives RWDS
MSv47734V2
DS12023 Rev 5
275/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
6.3.33
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 122 for DCMI are derived from
tests performed under the ambient temperature, f
frequency and V supply voltage
HCLK
DD
summarized in Table 20, with the following configuration:
•
•
•
•
•
•
DCMI_PIXCLK polarity: falling
DCMI_VSYNC and DCMI_HSYNC polarity: high
Data format: 14 bits
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 x V
DD
Figure 67. DCMI timing diagram
1/DCMI_PIXCLK
DCMI_PIXCLK
DCMI_HSYNC
DCMI_VSYNC
DATA[0:13]
th(HSYNC)
tsu(HSYNC)
th(HSYNC)
tsu(VSYNC)
tsu(DATA) th(DATA)
MS32414V2
(1)
Table 122. DCMI characteristics
Symbol
Parameter
Condition
Min
Max
Unit
Frequency ratio
DCMI_PIXCLK/fHCLK
-
-
-
0.4
-
1.71 < VDD < 3.6
Voltage range V1
-
48
DCMI_PIXCLK Pixel clock input
MHz
%
1.71 < VDD < 3.6
Voltage range V2
-
10
70
Dpixel
Pixel clock input duty cycle
-
30
276/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
(1)
Table 122. DCMI characteristics (continued)
Symbol
Parameter
Condition
Min
Max
Unit
1.71 < VDD < 3.6
Voltage range V1
5.5
-
tsu(DATA)
Data input setup time
1.71 < VDD < 3.6
Voltage range V2
8
0
0
-
-
-
1.71 < VDD < 3.6
Voltage range V1
th(DATA)
Data hold time
1.71 < VDD < 3.6
Voltage range V2
ns
1.71 < VDD < 3.6
Voltage range V1
6
9
-
-
tsu(HSYNC)
tsu(VSYNC)
,
DCMI_HSYNC/DCMI_VSYNC
input setup time
1.71 < VDD < 3.6
Voltage range V2
1.71 < VDD < 3.6
Voltage range V1
0
0
-
-
th(HSYNC)
th(VSYNC)
,
DCMI_HSYNC/DCMI_VSYNC
input hold time
1.71 < VDD < 3.6
Voltage range V2
1. Data based on characterization results, not tested in production.
6.3.34
LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 123 for LCD-TFT are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 21, with the following configuration:
•
•
•
•
•
•
•
LCD_CLK polarity: high
LCD_DE polarity: low
LCD_VSYNC and LCD_HSYNC polarity: high
Pixel formats: 24 bits
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 x V
DD
DS12023 Rev 5
277/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics.
(1)
Table 123. LTDC characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
2.7 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
-
-
83
50
LTDC clock output
frequency
MHz
fCLK
DCLK
LTDC clock output duty
cycle
-
-
45
55
%
tw(CLKH)
tw(CLKL)
Clock high time
Clock low time
tw(CLK)/2-0.5 tw(CLK)/2+0.5
tv(DATA)
th(DATA)
Data output valid time
Data output hold time
-
-
-
6
-
0
tv(HSYNC)
tv(VSYNC)
tv(DE)
-
HSYNC/VSYNC/DE
output valid time
-
-
-
3
-
th(HSYNC)
th(VSYNC)
th(DE)
HSYNC/VSYNC/DE
output hold time
0
1. Guaranteed by characterization results.
6.3.35
SD/SDIO/MMC card host interfaces (SDMMC)
Unless otherwise specified, the parameters given in Table xx for SDIO are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 21: General operating conditions with the following
configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 x V Refer to Section 6.3.17: I/O
port characteristics for more details on the input/output characteristics.
DD
Table 124. Dynamics characteristics:
SD / eMMC characteristics at VDD = 2.7 V to 3.6 V
(1)
Symbol
fPP
Parameter
Conditions
Min Typ Max Unit
Clock frequency in data transfer
mode
-
0
-
-
-
66
MHz
-
SDIO_CK/fPCLK2 frequency
ratio
-
-
8/3
tW(CKL)
tW(CKH)
Clock low time
Clock high time
fpp = 52 MHz
fpp = 52 MHz
8.5
8.5
9.5
9.5
-
-
ns
278/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Electrical characteristics
Table 124. Dynamics characteristics:
(1)
SD / eMMC characteristics at VDD = 2.7 V to 3.6 V
(continued)
Symbol
Parameter Conditions
Min Typ Max Unit
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(2)/DDR(2) mode
tISU
tIHD
Input setup time HS
Input hold time HS
-
-
1.5
2
-
-
-
-
ns
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(2)/DDR(2) mode
tOV
tOH
Output valid time HS
Output hold time HS
-
-
-
5
-
6.5
-
ns
ns
ns
4
CMD, D inputs (referenced to CK) in SD default mode
tISUD
tIHD
Input setup time SD
Input hold time SD
-
-
1.5
2
-
-
-
-
CMD, D outputs (referenced to CK) in SD default mode
tOVD
tOHD
Output valid default time SD
Output hold default time SD
-
-
-
1
-
2.5
-
0
1. Guaranteed by characterization results.
2. For SD 1.8 V support, an external voltage converter is needed.
Table 125. Dynamics characteristics:
eMMC characteristics at VDD = 1.71 V to 1.9 V
(1)(2)
Symbol
fPP
Parameter
Conditions
Min
Typ Max Unit
Clock frequency in data transfer
mode
-
0
-
-
52
MHz
-
SDIO_CK/fPCLK2 frequency
ratio
-
-
-
8/3
tW(CKL)
tW(CKH)
Clock low time
Clock high time
fpp = 52 MHz
fpp = 52 MHz
8.5
8.5
9.5
9.5
-
-
ns
ns
ns
CMD, D inputs (referenced to CK) in eMMC mode
tISU
tIH
Input setup time HS
Input hold time HS
-
-
0.5
4.5
-
-
-
-
CMD, D outputs (referenced to CK) in eMMC mode
tOV
tOH
Output valid time HS
Output hold time HS
-
-
-
6
-
7.4
-
4
1. Guaranteed by characterization results.
2. Cload = 20 pF.
DS12023 Rev 5
279/307
280
Electrical characteristics
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
See the different SDMMC diagrams in Figure 68, Figure 69 and Figure 70 below.
Figure 68. SDIO high-speed mode
Figure 69. SD default mode
CK
t
t
OVD
OHD
D, CMD
(output)
ai14888
Figure 70. DDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tvf(OUT) thr(OUT)
D0
tvr(OUT)
thf(OUT)
D3
Data output
D1
D2
D4
tsr(IN)thr(IN)
D5
tsf(IN) thf(IN)
Data input
D0
D1
D2
D3
D4
D5
MSv36879V1
280/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
DS12023 Rev 5
281/307
303
Package information
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
7.1
UFBGA169 package information
UFBGA169 is a 169-ball, 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package.
Figure 71. UFBGA169 outline
Z
Seating plane
A4
A2
ddd
Z
A
A3
A1
b
SIDE VIEW
A1 ball
A1 ball
X
index area
identifier
E
E1
e
F
A
F
D
D1
e
Y
N
13
1
Øb (169 balls)
BOTTOM VIEW
TOP VIEW
Øeee M
Øfff
Z
Z
X Y
M
A0YV_ME_V2
1. Drawing is not to scale.
Table 126. UFBGA169 mechanical data
millimeters
inches(1)
Typ.
Symbol
Min.
Typ.
Max.
Min.
Max.
A
A1
A2
A3
A4
b
0.460
0.050
0.400
-
0.530
0.080
0.450
0.130
0.320
0.280
7.000
6.000
7.000
6.000
0.500
0.500
0.600
0.110
0.500
-
0.0181
0.0020
0.0157
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0110
0.2756
0.2362
0.2756
0.2362
0.0197
0.0197
0.0236
0.0043
0.0197
-
0.270
0.230
6.950
5.950
6.950
5.950
-
0.370
0.330
7.050
6.050
7.050
6.050
-
0.0106
0.0091
0.2736
0.2343
0.2736
0.2343
-
0.0146
0.0130
0.2776
0.2382
0.2776
0.2382
-
D
D1
E
E1
e
F
0.450
0.550
0.0177
0.0217
282/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Package information
inches(1)
Table 126. UFBGA169 mechanical data (continued)
millimeters
Typ.
Symbol
Min.
Max.
Min.
Typ.
Max.
ddd
eee
fff
-
-
-
-
-
-
0.100
0.150
0.050
-
-
-
-
-
-
0.0039
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 72. UFBGA169 recommended footprint
Dpad
Dsm
MS18965V2
Table 127. UFBGA169 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.5 mm
0.27 mm
0.35 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Solder paste
0.27 mm aperture diameter.
Note:
Note:
Non-solder mask defined (NSMD) pads are recommended.
4 to 6 mils solder paste screen printing process.
DS12023 Rev 5
283/307
303
Package information
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
UFBGA169 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 73. UFBGA169 marking (package top view)
STM32L
Product
identification (1)
4R5AII6
Date code
Y WW
Aditional information
Y
MSv47753V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
284/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Package information
7.2
UFBGA144 package information
UFBGA144 is a 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package.
Figure 74. UFBGA144 outline
C Seating plane
ddd Z
A4
A2
A
A3
A1
A
E1
A
A1 ball
A1 ball
E
identifier index area
e
F
F
D1
D
e
B
M
12
1
Øb (144 balls)
BOTTOM VIEW
TOP VIEW
Øeee M C A B
Øfff M C
A02Y_ME_V2
1. Drawing is not to scale.
Table 128. UFBGA144 mechanical data
millimeters
inches(1)
Typ.
Symbol
Min.
Typ.
Max.
Min.
Max.
A
A1
A2
A3
A4
b
0.460
0.050
0.400
-
0.530
0.080
0.450
0.130
0.320
0.400
10.000
8.800
10.000
8.800
0.800
0.600
0.600
0.110
0.500
-
0.0181
0.0020
0.0157
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0110
0.2756
0.2362
0.2756
0.2362
0.0197
0.0197
0.0236
0.0043
0.0197
-
-
-
-
-
0.360
9.950
8.750
9.950
8.750
0.750
0.550
0.440
10.050
8.850
10.050
8.850
0.850
0.650
0.0091
0.2736
0.2343
0.2736
0.2343
-
0.0130
0.2776
0.2382
0.2776
0.2382
-
D
D1
E
E1
e
F
0.0177
0.0217
DS12023 Rev 5
285/307
303
Package information
Symbol
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Table 128. UFBGA144 mechanical data (continued)
millimeters
Typ.
inches(1)
Min.
Max.
Min.
Typ.
Max.
ddd
eee
fff
-
-
-
-
-
-
0.080
0.150
0.080
-
-
-
-
-
-
0.0039
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 75. UFBGA144 recommended footprint
Dpad
Dsm
A02Y_FP_V1
Table 129. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.80 mm
0.400 mm
0.550 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
0.400 mm
Between 0.100 mm and 0.125 mm
0.120 mm
286/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
UFBGA144 device marking
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 76. UFBGA144 marking (package top view)
Product
identification(1)
STM32L4R9
ZIJ6
Additional
information
Y
Date code
Y WW
Ball A1
indentifier
MSv47754V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12023 Rev 5
287/307
303
Package information
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
7.3
LQFP144 package information
LQFP144 is a 144-pin, 20 x 20 mm, low-profile quad flat package.
Figure 77. LQFP144 outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
L
D1
D3
L1
108
73
109
72
37
144
1
36
PIN 1
IDENTIFICATION
e
1A_ME_V4
1. Drawing is not to scale.
288/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Package information
inches(1)
Table 130. LQFP144 mechanical data
millimeters
Typ
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
21.800
19.800
-
-
1.600
0.150
1.450
0.270
0.200
22.200
20.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.8740
0.7953
-
-
0.0020
0.0531
0.0067
0.0035
0.8583
0.7795
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
22.000
20.000
17.500
22.000
20.000
17.500
0.500
0.600
1.000
3.5°
0.8661
0.7874
0.6890
0.8661
0.7874
0.6890
0.0197
0.0236
0.0394
3.5°
D1
D3
E
21.800
19.800
-
22.200
20.200
-
0.8583
0.7795
-
0.8740
0.7953
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DS12023 Rev 5
289/307
303
Package information
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Figure 78. LQFP144 recommended footprint
1.35
108
73
109
72
0.35
0.5
19.9
17.85
22.6
144
37
1
36
19.9
22.6
ai14905e
1. Dimensions are expressed in millimeters.
LQFP144 device marking
The following figures gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
290/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Package information
Figure 79. LQFP144 marking (package top view)
Aditional information
Product identification (1)
Y
STM32L4R5ZIT6
Date code
Pin 1
identifier
YWW
MSv47755V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
(2)
Figure 80. LQFP144 external SMPS device marking (package top view)
Aditional information
Product identification (1)
Y
STM32L4R5
ZIT6P
Date code
Pin 1
identifier
YWW
MSv47760V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
2. SMPS package version only available for 2 M Flash devices STM32L4R5xI.
DS12023 Rev 5
291/307
303
Package information
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
7.4
WLCSP144 package information
WLCSP144 is a 144-bump, 5.24x 5.24 mm, 0.40 mm pitch, wafer level chip scale package.
Figure 81. WLCSP144 outline
A1 BALL LOCATION
e1
A1
DETAIL A
E
e2
E
e
e
D
A
D
A2
SIDE VIEW
TOP VIEW
BOTTOM VIEW
A3
BUMP
FRONT VIEW
A1
SEATING PLANE
DETAIL A
ROTATED 90
A085_WLCSP144_ME_V1
1. Drawing is not to scale.
292/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Package information
inches(1)
Table 131. WLCSP144 mechanical data
millimeters
Typ
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
A3
b
-
-
0.18
0.38
0.025(2)
0.25
5.24
5.24
0.40
4.40
4.40
0.420(3)
0.420(4)
-
0.59
-
-
0.023
-
-
-
0.007
0.015
0.0010
0.010
0.206
0.206
0.016
0.173
0.173
0.0165
0.0165
-
-
-
-
-
-
-
-
-
-
0.22
0.28
5.26
5.26
-
0.009
0.011
0.207
0.207
-
D
5.22
0.205
E
5.22
0.205
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
e1
e2
F
-
-
-
-
-
-
G
-
-
aaa
bbb
ccc
ddd
eee
0.10
0.10
0.10
0.05
0.05
0.004
0.004
0.004
0.002
0.002
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 3 decimal digits.
2. A3 value is guaranteed by technology design value.
3. This value is calculated from over value D and e1.
4. This value is calculated from over value E and e2.
Figure 82. WLCSP144 recommended footprint
Dpad
Dsm
A085_WLCSP144_FP_V1
1. Dimensions are expressed in millimeters.
DS12023 Rev 5
293/307
303
Package information
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Table 132. WLCSP144 recommended PCB design rules
Dimension Recommended values
Pitch
Dpad
0.4 mm
0.225 mm
0.290 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
0.250 mm
0.100 mm
WLCSP144 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 83. WLCSP144 marking (package top view)
Product identification (1)
32L4R5ZIY6
Aditional information
YWW Y
Date code
MSv47756V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
294/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Package information
7.5
UFBGA132 package information
UFBGA132 is a 132-ball, 7 x 7 mm, ultra thin fine pitch ball grid array package.
Figure 84. UFBGA132 outline
A1 ball identifier
B
A
D
E1
E
e
Z
A
Z
e
D1
M
1
12
Øb (132 balls)
BOTTOM VIEW
TOP VIEW
M
Øeee C A B
M
C
Ø fff
A4
ddd C
A2
A3
A1
A
b
SEATING
PLANE
UFBGA132_A0G8_ME_V2
1. Drawing is not to scale.
Table 133. UFBGA132 mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
A3
A4
b
-
-
0.600
-
-
0.0236
-
-
0.110
-
-
0.0043
-
0.450
0.130
0.320
0.290
7.000
5.500
7.000
5.500
-
-
0.0177
0.0051
0.0126
0.0114
0.2756
0.2165
0.2756
0.2165
-
-
-
-
0.0094
-
-
-
-
0.240
6.850
-
0.340
7.150
-
0.0094
0.2697
-
0.0134
0.2815
-
D
D1
E
6.850
-
7.150
-
0.2697
-
0.2815
-
E1
DS12023 Rev 5
295/307
303
Package information
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Table 133. UFBGA132 mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
e
Z
-
-
-
-
-
0.500
0.750
0.080
0.150
0.050
-
-
-
-
-
-
-
-
-
-
0.0197
0.0295
0.0031
0.0059
0.0020
-
-
-
-
-
ddd
eee
fff
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 85. UFBGA132 recommended footprint
Dpad
Dsm
UFBGA132_A0G8_FP_V1
Table 134. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.5 mm
0.280 mm
0.370 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
Ball diameter
0.280 mm
Between 0.100 mm and 0.125 mm
0.100 mm
0.280 mm
296/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
UFBGA132 device marking
Package information
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 86. UFBGA132 marking (package top view)
STM32L
Product
identification (1)
4R5QII6
Date code
Y WW
Aditional information
Y
MSv47757V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12023 Rev 5
297/307
303
Package information
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
7.6
LQFP100 package information
LQFP100 is a 100-pin, 14 x 14 mm, low-profile quad flat package.
Figure 87. LQFP100 outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
75
C
D
D1
D3
L
L1
51
50
76
100
26
PIN 1
IDENTIFICATION
25
e
1
1L_ME_V5
1. Drawing is not to scale.
Table 135. LQPF100 mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
16.200
14.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
-
0.050
1.350
0.170
0.090
15.800
13.800
-
-
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
16.000
14.000
12.000
16.000
0.6299
0.5512
0.4724
0.6299
D1
D3
E
15.800
16.200
0.6220
0.6378
298/307
DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Package information
inches(1)
Table 135. LQPF100 mechanical data (continued)
millimeters
Typ
Symbol
Min
Max
Min
Typ
Max
E1
E3
e
13.800
14.000
12.000
0.500
0.600
1.000
3.5°
14.200
0.5433
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
0.5591
-
-
-
-
-
-
-
-
L
0.450
0.750
-
0.0177
0.0295
-
L1
k
-
0.0°
-
-
0.0°
-
7.0°
0.080
7.0°
0.0031
ccc
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 88. LQFP100 recommended footprint
75
51
76
50
0.5
0.3
16.7 14.3
100
26
1.2
1
25
12.3
16.7
ai14906c
1. Dimensions are expressed in millimeters.
DS12023 Rev 5
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303
Package information
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
LQFP100 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 89. LQFP100 marking (package top view)
STM32L4R5
Product
identification (1)
VIT6
Y
Date code
YWW
Pin 1 identifier
MSv47758V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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Package information
7.7
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
D
INT
I/O
D
INT I/O
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ ((V
– V ) × I ),
I/O
OL
OL
DDIOx OH OH
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 136. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP100 - 14 × 14mm
42
55
Thermal resistance junction-ambient
UFBGA132 - 7 × 7 mm
Thermal resistance junction-ambient
LQFP144 - 20 × 20 mm
32
ΘJA
°C/W
Thermal resistance junction-ambient
UFBGA144 -10 x 10 mm
53
Thermal resistance junction-ambient
UFBGA169 - 7 × 7 mm
52
Thermal resistance junction-ambient
WLCSP144
30.1
7.7.1
7.7.2
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32L4Rxxx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
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Package information
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T
= 82 °C (measured according to JESD51-2),
Amax
I
= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output
OL
OL
at low level with I = 20 mA, V = 1.3 V
OL
OL
P
P
= 50 mA × 3.5 V= 175 mW
INTmax
= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IOmax
This gives: P
= 175 mW and P
= 272 mW:
IOmax
INTmax
P
= 175 + 272 = 447 mW
Dmax
Using the values obtained in Table 136 T
is calculated as follows:
Jmax
–
T
For LQFP100, 42 °C/W
= 82 °C + (42 °C/W × 447 mW) = 82 °C + 18.774 °C = 100.774 °C
Jmax
This is within the range of the suffix 6 version parts (–40 < T < 105 °C) see Section 8:
J
Ordering information.
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Ordering information).
Note:
With this given P
we can find the T
allowed for a given device temperature range
Amax
Dmax
(order code suffix 6 or 7).
Suffix 6: T
Suffix 3: T
= T
= T
- (42°C/W × 447 mW) = 105-18.774 = 86.226 °C
- (42°C/W × 447 mW) = 130-18.774 = 111.226 °C
Amax
Amax
Jmax
Jmax
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature T remains within the
J
specified range.
Assuming the following application conditions:
Maximum ambient temperature T
= 100 °C (measured according to JESD51-2),
Amax
I
= 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V
OL
OL
P
P
= 20 mA × 3.5 V= 70 mW
INTmax
= 20 × 8 mA × 0.4 V = 64 mW
IOmax
This gives: P
= 70 mW and P
= 64 mW:
IOmax
INTmax
P
= 70 + 64 = 134 mW
Dmax
Thus: P
= 134 mW
Dmax
Using the values obtained in Table 136 T
is calculated as follows:
Jmax
–
T
For LQFP100, 42 °C/W
= 100 °C + (42 °C/W × 134 mW) = 100 °C + 5.628 °C = 105.628 °C
Jmax
This is above the range of the suffix 6 version parts (–40 < T < 105 °C).
J
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DS12023 Rev 5
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Package information
In this case, parts must be ordered at least with the temperature range suffix 3 (see
Section 8: Ordering information) unless we reduce the power dissipation in order to be able
to use suffix 6 parts.
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Ordering information
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
8
Ordering information
Table 137. STM32L4Rxxx ordering information scheme
STM32 4Rx
Example:
L
V
I
T
6 P TR
Device family
®
STM32 = Arm based 32-bit microcontroller
Product type
L = ultra-low-power
Device subfamily
4R5 = STM32L4R5xx
4R7 = STM32L4R7xx, LCD-TFT, Chrom-GRC
4R9 = STM32L4R9xx, LCD-TFT Chrom-GRC and DSI Host
Pin count
V = 100 pins
Q = 132 balls
Z = 144 pins/balls
A = 169 balls
Flash memory size
I = 2 Mbytes of Flash memory
G = 1 Mbyte of Flash memory
Package
T = LQFP
I = UFBGA (7 x 7 mm)
J = UFBGA (10 x 10 mm)
Y = WLCSP
Temperature range
6 = Industrial temperature range, -40 to 85 °C (105 °C junction)
3 = Industrial temperature range, -40 to 125 °C (130°C junction)
Option
P = Dedicated pinout supporting external SMPS
S = new sawing
Packing
TR = tape and reel
xxx = programmed parts
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Revision history
9
Revision history
Table 138. Document revision history
Date
Revision
Changes
10-Oct-2017
1
Initial release.
Added:
– Section 6.3.10: MIPI D-PHY characteristics
– Section 6.3.11: MIPI D-PHY PLL characteristics
– Section 6.3.12: MIPI D-PHY regulator characteristics
Updated:
– Cover page Features (Performance benchmark and Energy
benchmark)
24-Nov-2017
2
– Table 4: STM32L4R5xx modes overview
– Section 3.12: Clocks and startup
– Figure 18: STM32L4R5xx WLCSP144 ballout(1)
– Figure 19: STM32L4R5xx UFBGA132 ballout(1)
– Table 21: General operating conditions
Added:
– Figure 4: STM32L4R5xxxP and STM32L4R7xxxP with external
SMPS power supply overview
– Figure 11: STM32L4R5xxxP UFBGA169 external SMPS ballout(1)
– Figure 14: STM32L4R5ZxxxP external SMPS LQFP144 pinout(1)
– Figure 17: STM32L4R9ZxxxP WLCSP144 external SMPS
ballout(1)
– Figure 20: STM32L4R5xxxP UFBGA132 external SMPS ballout(1)
Updated:
19-Jan-2018
3
– Footnotes of Table 2: STM32L4R5xx, STM32L4R7xx and
STM32L4R9xx features and peripheral counts
– Table 15: STM32L4Rxxx pin definitions
– Figure 1: STM32L4R5xx, STM32L4R7xx and STM32L4R9xx block
diagram
– Figure 3: STM32L4R5xx and STM32L4R7xx power supply
overview
– Figure 5: STM32L4R9xx power supply overview
– Section 3.10.1: Power supply schemes
– Section 3.12: Clocks and startup
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Revision history
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
Table 138. Document revision history (continued)
Date
Revision
Changes
Added:
– Figure 6: Power-up/down sequence
– Figure 65: OctoSPI HyperBus™ read with double latency
Updated:
– Section 1: Introduction
– Section 3.10.1: Power supply schemes
– Table 8: Temperature sensor calibration values
– Updated maximum value for VDD12-VSS on Table 18: Voltage
characteristics
– Updated maximum value for VDD12 on Table 21: General operating
conditions
24-Apr-2018
4
– Title of Table 40: Typical consumption in Run and Low-power run
modes, with different codes running from SRAM1 and power
supplied by external SMPS
– Values on column “Parameter”’ on Table 41: Current consumption
in Sleep and Low-power sleep mode, Flash ON
– Values on column “Parameter”’ on Table 42: Current consumption
in Sleep and Low-power sleep modes, Flash ON and power
supplied by external SMPS
– Title of Table 43: Current consumption in Low-power sleep mode,
Flash in power-down
– FCK 1/t(CK) rows on Table 121: OctoSPI characteristics in DTR
mode (with DQS)/Octal and HyperBus™
Updated:
– Table 2: STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
features and peripheral counts.
– Figure 1: STM32L4R5xx, STM32L4R7xx and STM32L4R9xx block
diagram.
– Figure 11: STM32L4R5xxxP UFBGA169 external SMPS ballout(1)
– Figure 20: STM32L4R5xxxP UFBGA132 external SMPS ballout(1)
.
.
– Section 5: Memory mapping removing tables and figure, which are
put in the reference manual.
– Table 15: STM32L4Rxxx pin definitions replacing ‘BGA132_SMPS’
by ‘UFBGA132_SMPS’.
23-Jan-2020
5
– Table 18: Voltage characteristics.
– Table 75: I/O static characteristics note 4.
– Table 89: VREFBUF characteristics.
– Table 121: OctoSPI characteristics in DTR mode (with DQS)/Octal
and HyperBus™.
– Figure 63: OctoSPI HyperBus™ clock., Figure 64: OctoSPI
HyperBus™ read, Figure 65: OctoSPI HyperBus™ read with
double latency, Figure 66: OctoSPI HyperBus™ write removing
any reference to CK#.
– Table 137: STM32L4Rxxx ordering information scheme.
– Section 7: Package information.
– Section 8: Ordering information.
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS12023 Rev 5
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