STM32F723ZCK7TR [STMICROELECTRONICS]
Arm Cortex-M7 32b MCUFPU, 462DMIPS, up to 512KB Flash;型号: | STM32F723ZCK7TR |
厂家: | ST |
描述: | Arm Cortex-M7 32b MCUFPU, 462DMIPS, up to 512KB Flash |
文件: | 总229页 (文件大小:3297K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
STM32F722xx
STM32F723xx
Arm® Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 512KB Flash
/256+16+4KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com IF
Datasheet - production data
Features
FBGA
®
®
• Core: Arm 32-bit Cortex -M7 CPU with FPU,
adaptive real-time accelerator (ART
Accelerator) and L1-cache: 8 Kbytes of data
cache and 8 Kbytes of instruction cache,
allowing 0-wait state execution from embedded
Flash memory and external memories,
frequency up to 216 MHz, MPU,
LQFP64 (10 × 10 mm)
LQFP100 (14 × 14 mm)
LQFP144 (20 × 20 mm)
UFBGA144 (7 x 7 mm)
WLCSP100
(0.4 mm pitch)
UFBGA176 (10 x 10 mm)
LQFP176 (24 x 24 mm)
462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1)
and DSP instructions.
– V
supply for RTC, 32×32 bit backup
BAT
registers + 4 Kbytes of backup SRAM
• Memories
– Up to 512 Kbytes of Flash memory with
protection mechanisms (read and write
protections, proprietary code readout
protection (PCROP))
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels
and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• Up to 18 timers: up to thirteen 16-bit (1x low-
power 16-bit timer available in Stop mode) and
two 32-bit timers, each with up to 4
IC/OC/PWMs or pulse counter and quadrature
(incremental) encoder inputs. All 15 timers
running up to 216 MHz. 2x watchdogs, SysTick
timer
– 528 bytes of OTP memory
– SRAM: 256 Kbytes (including 64 Kbytes of
data TCM RAM for critical real-time data) +
16 Kbytes of instruction TCM RAM (for
critical real-time routines) + 4 Kbytes of
backup SRAM (available in the lowest
power modes)
• General-purpose DMA: 16-stream DMA
– Flexible external memory controller with up
to 32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND
memories
controller with FIFOs and burst support
• Debug mode
– SWD and JTAG interfaces
®
– Cortex -M7 Trace Macrocell™
• Dual mode Quad-SPI
• Up to 140 I/O ports with interrupt capability
– Up to 136 fast I/Os up to 108 MHz
– Up to 138 5 V-tolerant I/Os
• Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– Dedicated USB power
• Up to 21 communication interfaces
2
– 4-to-26 MHz crystal oscillator
– Up to 3× I C interfaces (SMBus/PMBus)
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– Up to 4 USARTs/4 UARTs (27 Mbit/s,
ISO7816 interface, LIN, IrDA, modem
control)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
– Up to 5 SPIs (up to 54 Mbit/s), 3 with
2
muxed simplex I Ss for audio class
• Low-power
accuracy via internal audio PLL or external
clock
– Sleep, Stop and Standby modes
– 2 x SAIs (serial audio interface)
April 2020
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This is information on a product in full production.
www.st.com
STM32F722xx STM32F723xx
– 1 x CAN (2.0B active)
– 2 x SDMMCs
• CRC calculation unit
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID
• Advanced connectivity
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and on-chip
Hi-speed PHY or ULPI depending on the
part number
• True random number generator
Table 1. Device summary
Reference
STM32F722xx
STM32F723xx
Part number
STM32F722IC, STM32F722IE, STM32F722RC, STM32F722RE, STM32F722VC,
STM32F722VE, STM32F722ZC, STM32F722ZE
STM32F723IC, STM32F723IE, STM32F723VC, STM32F723VE, STM32F723ZC,
STM32F723ZE
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Contents
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1
2.2
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STM32F723xx versus STM32F722xx LQFP100/ LQFP144/
LQFP176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 23
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 27
3.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.15.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.15.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.16.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.16.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.16.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 36
3.17 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 36
3.18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.19
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.20.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.20.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.20.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.20.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.20.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.20.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.20.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.21 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.22 Universal synchronous/asynchronous receiver transmitters (USART) . . 43
3.23 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 44
3.24 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.25 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.26 Audio PLL (PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.27 SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . 45
3.28 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.29 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 46
3.30 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 46
3.31 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.32 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.33 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.34 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.35 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.36 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.37 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4
5
6
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1.1
6.1.2
6.1.3
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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6.1.4
6.1.5
6.1.6
6.1.7
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Operating conditions at power-up / power-down (regulator ON) . . . . . 110
Operating conditions at power-up / power-down (regulator OFF) . . . . 110
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . 110
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 130
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 140
6.3.13 USB OTG HS PHY PLLs characteristics (on STM32F723xx devices) 142
6.3.14 USB OTG HS PHY regulator characteristics . . . . . . . . . . . . . . . . . . . 142
6.3.15 USB HS PHY external resistor characteristics
(on STM32F723xx devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 146
6.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.23 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.3.26
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
BAT
6.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.3.29 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3.30 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
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6.3.31 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
6.3.32 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . 199
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
7.1
7.2
7.3
7.4
7.5
7.6
LQFP64 – 10 x 10 mm, low-profile quad flat package information . . . . . 202
LQFP100, 14 x 14 mm low-profile quad flat package information . . . . . 205
LQFP144, 20 x 20 mm low-profile quad flat package information . . . . . 208
LQFP176 24 x 24 mm low-profile quad flat package information . . . . . . .211
UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
UFBGA176+25, 10 x 10, 0.65 mm ultra thin-pitch ball grid
array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
7.7
7.8
WLCSP100 - 0.4 mm pitch wafer level chip scale package information 221
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 227
A.1
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32F722xx and STM32F723xx features and peripheral counts . . . . . . . . . . . . . . . . . . 15
Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 33
Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 36
Voltage regulator modes in stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
STM32F722xx and STM32F723xx pin and ball definition . . . . . . . . . . . . . . . . . . . . . . . . . 62
FMC pin definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
STM32F722xx and STM32F723xx alternate function mapping. . . . . . . . . . . . . . . . . . . . . 89
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 108
VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
VCAP1 operating conditions in the LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 110
Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . 110
reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM RAM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
Table 25.
or SRAM on AXI (L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory or SRAM on AXI (L1-cache disabled), regulator ON . . . . . 115
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory on ITCM interface (ART disabled), regulator ON . . . . . . . . 116
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
Table 26.
Table 27.
Table 28.
or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 118
Typical and maximum current consumption in Sleep mode, regulator OFF. . . . . . . . . . . 118
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 119
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 120
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Typical and maximum current consumptions in V
mode. . . . . . . . . . . . . . . . . . . . . . . 121
BAT
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
USB OTG HS and USB OTG PHY HS current consumption . . . . . . . . . . . . . . . . . . . . . . 130
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
LSE
DS11853 Rev 6
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9
List of tables
STM32F722xx STM32F723xx
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
PLLI2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
USB OTG HS PLL1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
USB OTG HS PLL2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
USB OTG HS PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
USB HS PHY external resistor characteristics (on STM32F723xx devices). . . . . . . . . . . 143
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
ADC static accuracy at f
ADC static accuracy at f
ADC static accuracy at f
= 18 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
= 30 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
= 36 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
ADC
ADC
ADC
ADC dynamic accuracy at f
ADC dynamic accuracy at f
= 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 158
= 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 158
ADC
ADC
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
BAT
internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
2
I S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
USB OTG high speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
USB OTG high speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
USB FS PHY BCD electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 179
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Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 179
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 180
Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 181
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 182
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 100. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 184
Table 101. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 102. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 103. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 104. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 105. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 106. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 107. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 108. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 109. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 110. LPSDR SDRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 111. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 112. Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 113. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 200
Table 114. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 201
Table 115. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 116. LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 117. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 118. LQFP176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 119. UFBGA144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 120. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) . . . . . . . . . . . . . . . . 216
Table 121. UFBGA176+25 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 122. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 219
Table 123. WLCSP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 124. WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 223
Table 125. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 126. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 127. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 227
Table 128. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
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9
List of figures
STM32F722xx STM32F723xx
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Compatible board design for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STM32F722xx and STM32F723xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
(1)
STM32F722xx and STM32F723xx AXI-AHB bus matrix architecture
. . . . . . . . . . . . . . 24
VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 31
Figure 11. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. Startup in regulator OFF: slow V slope
DD
- power-down reset risen after V
/V
stabilization . . . . . . . . . . . . . . . . . . . . . . . . 35
CAP_1 CAP_2
Figure 14. Startup in regulator OFF mode: fast V slope
DD
- power-down reset risen before V
/V
stabilization . . . . . . . . . . . . . . . . . . . . . . 35
CAP_1 CAP_2
Figure 15. STM32F722xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 16. STM32F722xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 17. STM32F723xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 18. STM32F723xx WLCSP100 ballout (with OTG PHY HS) . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 19. STM32F722xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 20. STM32F723xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 21. STM32F723xx UFBGA144 ballout (with OTG PHY HS). . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 22. STM32F722xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 23. STM32F723xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 24. STM32F723xx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 25. STM32F723xx UFBGA176 ballout (with OTG PHY HS). . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 26. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 27. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 28. STM32F722xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 29. STM32F723xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 30. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 31. External capacitor C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
EXT
Figure 32. Typical V
current consumption (RTC ON/BKP SRAM OFF and
BAT
LSE in low drive mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 33. Typical V current consumption (RTC ON/BKP SRAM OFF and
BAT
LSE in medium low drive mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 34. Typical V current consumption (RTC ON/BKP SRAM OFF and
BAT
LSE in medium high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 35. Typical V current consumption (RTC ON/BKP SRAM OFF and
BAT
LSE in high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 36. Typical V current consumption (RTC ON/BKP SRAM OFF and
BAT
LSE in high medium drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 37. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 38. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 39. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 40. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 41. ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
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Figure 42. LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 43. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 44. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 45. FT I/O input characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 46. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 47. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 48. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 49. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 50. Power supply and reference decoupling (V
Figure 51. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . 160
). . . . . . . . . . . . . . . . 160
REF+
DDA
connected to V
REF+
DDA
Figure 52. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 53. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 54. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 55. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
2
(1)
Figure 56. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
2
(1)
Figure 57. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 58. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 59. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 60. USB OTG full speed timings: definition of data signal rise and fall time. . . . . . . . . . . . . . 174
Figure 61. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 178
Figure 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 180
Figure 64. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 65. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 66. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 67. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 68. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 69. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 70. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 71. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 72. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 192
Figure 73. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 193
Figure 74. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 75. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 76. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 77. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 78. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 79. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 80. LQFP64 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 81. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 82. LQFP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 83. LQFP100 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 84. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 85. LQFP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 86. LQFP144 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 87. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 88. LQFP144 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 89. LQFP176 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 90. LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 91. LQFP176 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 92. UFBGA144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 93. UFBGA144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
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12
List of figures
STM32F722xx STM32F723xx
Figure 94. UFBGA144 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 95. UFBGA176 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 96. UFBGA176+25 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 97. UFBGA176 top view example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 98. WLCSP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 99. WLCSP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 100. WLCSP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
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Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F722xx and STM32F723xx microcontrollers.
This document should be ready in conjunction with the STM32F72xxx and STM32F73xxx
®
advanced Arm -based 32-bit MCUs reference manual (RM0431). The reference manual is
available from the STMicroelectronics website www.st.com.
®(a)
®
®
For information on the Arm
Cortex -M7 core, refer to the Cortex -M7 technical
reference manual available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS11853 Rev 6
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49
Description
STM32F722xx STM32F723xx
2
Description
®
The STM32F722xx and STM32F723xx devices are based on the high-performance Arm
®
®
Cortex -M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex -M7 core
features a single floating point unit (SFPU) precision which supports Arm single-precision
®
data-processing instructions and data types. It also implements a full set of DSP instructions
and a memory protection unit (MPU) which enhances the application security.
The STM32F722xx and STM32F723xx devices incorporate high-speed embedded
memories with a Flash memory up to 512 Kbytes, 256 Kbytes of SRAM (including
64 Kbytes of data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM
(for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power
modes, and an extensive range of enhanced I/Os and peripherals connected to two APB
buses, two AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect
supporting internal and external memories access.
All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, thirteen general-
purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-
bit timers, a true random number generator (RNG). They also feature standard and
advanced communication interfaces.
2
•
•
Up to three I Cs
2
2
Five SPIs, three I Ss in half duplex mode. To achieve the audio class accuracy, the I S
peripherals can be clocked via a dedicated internal audio PLL or via an external clock
to allow synchronization.
•
•
Four USARTs plus four UARTs
An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI only for the LQFP64 and LQFP100 packages and with the integrated HS PHY for
the LQFP144 and UFBGA176 packages)
•
•
•
One CAN
Two SAI serial audio interfaces
Two SDMMC host interfaces
Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC)
interface, a Quad-SPI Flash memory interface.
The STM32F722xx and STM32F723xx devices operate in the –40 to +105 °C temperature
range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for the USB (OTG_FS and
OTG_HS) and the SDMMC2 (clock, command and 4-bit data) are available on all the
packages except LQFP100 and LQFP64 for a greater power supply choice.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A
comprehensive set of power-saving mode allows the design of low-power applications.
The STM32F722xx and STM32F723xx devices offer devices in 7 packages ranging from 64
pins to 176 pins. The set of included peripherals changes with the device chosen.
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STM32F722xx STM32F723xx
Description
These features make the STM32F722xx and STM32F723xx microcontrollers suitable for a
wide range of applications:
•
•
•
•
•
•
•
•
Motor drive and application control,
Medical equipment,
Industrial applications: PLC, inverters, circuit breakers,
Printers, and scanners,
Alarm systems, video intercom, and HVAC,
Home audio appliances,
Mobile applications, Internet of Things,
Wearable devices: smartwatches.
The following table lists the peripherals available on each part number.
Table 2. STM32F722xx and STM32F723xx features and peripheral counts
Peripherals
STM32F72xRx
STM32F72xVx
STM32F72xZx
STM32F72xIx
Flash memory in Kbytes
256 512
256 512
256 512
256 512
System
Instruction
Backup
256(176+16+64)
SRAM in Kbytes
16
4
(1)
FMC memory controller
Quad-SPI
No
Yes
Yes
(2)
General-purpose
Advanced-control
Basic
10
2
2
Timers
Low-power
No
1
Random number generator
Yes
(3)
2
(3)
(3)
SPI / I S
3/3 (simplex)
4/2
4/3 (simplex)
5/3 (simplex)
2
I C
3
USART/UART
USB OTG FS
4/4
Yes
Yes
(4)
USB OTG HS
Communication
interfaces
USB OTG PHY HS
controller (USBPHYC)
(10)
No
Yes
CAN
1
2
SAI
SDMMC1
SDMMC2
Yes
(5)(6)
No
50
Yes
82 in STM32F722xx
79 in STM32F723xx
114 in STM32F722xx 140 in STM32F722xx
112 in STM32F723xx 138 in STM32F723xx
GPIOs
12-bit ADC
3
16
24
Number of channels
12-bit DAC
Number of channels
Yes
2
(7)
Maximum CPU frequency
216 MHz
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49
Description
STM32F722xx STM32F723xx
Table 2. STM32F722xx and STM32F723xx features and peripheral counts (continued)
Peripherals
STM32F72xRx
STM32F72xVx
STM32F72xZx
STM32F72xIx
(8)
Operating voltage
1.7 to 3.6 V
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to + 125 °C
LQFP100
Operating temperatures
Package
LQFP144
UFBGA176
LQFP176
(9)
(10)
LQFP64
WLCSP100
(10)
UFBGA144
1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory
using the NE1 Chip Select.
2. On the STM32F723xx device packages, except the 176-pin ones, the TIM12 is not available, so there are 9 general-
purpose timers.
3. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio
mode.
4. USB OTG HS with the ULPI on the STM32F722xx devices and with integrated HS PHY on the STM32F723xx devices.
5. The SDMMC2 supports a dedicated power rail for clock, command and data 0..4 lines, feature available starting from 144
pin package.
6. The SDMMC2 is not available on the STM32F723Vx devices.
7. 216 MHz maximum frequency for - 40°C to + 85°C ambient temperature range (200 MHz maximum frequency for - 40°C to
+ 105°C ambient temperature range).
8. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 3.15.2: Internal reset OFF).
9. Available only on the STM32F722xx devices.
10. Available only on the STM32F723xx devices.
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Description
2.1
Full compatibility throughout the family
The STM32F722xx devices are fully pin-to-pin, compatible with the STM32F7x5xx,
STM32F7x6xx, STM32F7x7xx devices.
The STM32F722xx devices are fully pin-to-pin, compatible with the STM32F4xxxx devices,
allowing the user to try different peripherals, and reaching higher performances (higher
frequency) for a greater degree of freedom during the development cycle.
Figure 1 and Figure 2 give compatible board designs between the STM32F722xx, with
LQFP64 and LQFP100 packages, and STM32F4xx families.
Figure 1. Compatible board design for LQFP100 package
STM32F427xx / STM32F437xx
STM32F429xx / STM32F439xx
STM32F415xx / STM32F417xx
PC3
VDD
18
19
20
21
22
23
24
25
STM32F405xx / STM32F407xx
VSSA
VREF+
VDDA
PA0-WKUP
PA1
PA2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PC3
VSSA
VREF+
VDDA
PA0-WKUP
PA1
18
19
20
21
22
23
24
25
STM32F72xxx
Pins 19 to 49 are not compatible
PA2
PA3
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MSv41001V2
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49
Description
STM32F722xx STM32F723xx
Figure 2. Compatible board design for LQFP64 package
53 52 51 50 49
48
53 52 51 50 49
48 VDD
VDD
VSS
PA13
PA12
PA11
PA10
PA9
VDD
VDD
47
VCAP_2
47
46
45
44
43
42
41
46 PA13
45 PA12
44 PA11
43 PA10
42 PA9
41 PA8
40 PC9
39 PC8
38 PC7
37 PC6
VSS
VSS
PA8
STM32F405/
STM32F415 line
STM32F4x1
40 PC9
39 PC8
38 PC7
37 PC6
36 PB15
35 PB14
34 PB13
33 PB12
PB11 not available anymore
36
35
34
33
PB15
PB14
PB13
PB12
Replaced by V
CAP_1
28 29 30 3132
31
28 29 30
32
V
increased to 4.7 μf
CAP
ESR 1 ohm or below 1 ohm
VDD
VSS
VSS
VDD
VDD
57 56 55 54 53 52 51 50 49
48
VDD
VSS
PA13
PA12
PA11
47
46
45
44
43
42
PA10
PA9
VSS
STM32F722xx
41 PA8
PC9
40
39
38
37
36
35
34
PC8
PC7
PC6
PC5 not available anymore
PB15
PB14
PB13
Replaced by V
CAP_1
33 PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Not compatible STM32F722xx pins with either
STM32F4x1 or STM32F405/F415 or both
V
increased to 4.7 μf
CAP
ESR between 0.1 ohm and 0.2 ohm
VSS
VDD
MSv41007V3
The STM32F722xx LQFP144, UFBGA176 and LQFP176 packages are fully pin to pin
compatible with the STM32F4xx devices.
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STM32F722xx STM32F723xx
Description
2.2
STM32F723xx versus STM32F722xx LQFP100/ LQFP144/
LQFP176 packages
Figure 3. Compatible board design for LQFP100 package
58 PD11
57 PB15
56
58 PD11
57 PD10
56 PD9
55 PD8
54 PB15
STM32F722xx
STM32F723xx
PB14
55 VDD12OTGHS
VDDPHYHS
OTG_HS_REXT
PB13
PB12
54
53
52
51
53
52
51
PB14
PB13
PB12
50
50
Not compatible pins
MSv63473V1
Figure 4. Compatible board design for LQFP144 package
93
92
91
90 PG3
89 PG2
PG8
PG5
PG4
93
92
91
90
PG8
PG7
PG6
PG5
89 PG4
88 PG3
87 PG2
86 PD15
85 PD14
84 VDD
83
82
81
80 PD11
79 PD10
78 PD9
77 PD8
76 PB15
75
74
73
88
PD15
87 PD14
86 VDD
85 VSS
84 PD13
83
82
81
80 PD9
79 PD8
78
PD12
PD11
PD10
VSS
PD13
PD12
STM32F722xx
STM32F723xx
PB15
77 PB14
VDD12OTGHS
OTG_HS_REXT
PB13
PB12
76
75
74
73
PB14
PB13
PB12
72
72
PG6, PG7 removed on the STM32F723xx
Not compatible pins
MSv41098V1
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49
Description
STM32F722xx STM32F723xx
Figure 5. Compatible board design for LQFP176 package
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
PG8
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
VDD12OTGHS
OTG_HS_REXT
PB13
112
111
110
109
108
107
106
105
104
103
102
101
100
99
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
98
97
96 PD8
95 PB15
94 PB14
93 PB13
92 PB12
91
90
89
STM32F722xx
STM32F723xx
PB12
91 VDD
90
89
VDD
VSS
PH12
VSS
PH12
88
88
PG6, PG7 removed on the STM32F723xx
Not compatible pins
MSv41099V1
Figure 6 shows the general block diagram of the device family.
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STM32F722xx STM32F723xx
Description
Figure 6. STM32F722xx and STM32F723xx block diagram
JTAG & SW
ETM
JTRST, JTDI,
JTCK/SWCLK
MPU FPU
NVIC
DTCM RAM 64KB
ITCM RAM 16KB
JTDO/SWD, JTDO
DTCM
ICTM
TRACECK
TRACED[3:0]
Arm CPU
Cortex-M7
AXIM
I-Cache
ACCEL/
CACHE
FLASH 512KB
8KB
RNG
D-Cache
8KB
216MHz
AHBP
AHBS
DP
SRAM1 176KB
SRAM2 16KB
USB
DM
SCL, SDA, INT, ID, VBUS
OTG FS
CLK, NE [3:0], A[23:0],
D[31:0], NOEN, NWEN,
NBL[3:0], SDCLKE[1:0]
SDNE[1:0], SDNWE, NL
NRAS, NCAS, NADV
NWAIT, INTN
LDO
BGR
(2)
PLL1
PLL2
AHB2 216 MHz
USB HS
PHY
EXT MEM CTL (FMC)
SRAM, SDRAM, NOR-Flash,
NAND-Flash, SDRAM
USB OTG HS
DP, DM
ULPI:CK, D[7:0], DIR, STP, NXT
SCL/SDA, INT, ID, VBUS
Quad-SPI
DMA/
FIFO
CLK, CS,D[7:0]
@VDDA
PLL
LDO
AHB1 216 MHz
POR
reset
SUPPLY
SUPERVISION
POR/PDR
Int
8 Streams
FIFO
GP-DMA2
BOR
PVD
VDDA, VSSA
NRESET
@VDDA
RC HS
8 Streams
FIFO
WKUP[4:0]
GP-DMA1
(3)
@VDD33
BBgen + POWER MNGT
VDDPHYHS = 3.0 to 3.6V
VDD12
RC LS
VDDMMC33 = 3.0 to 3.6V
VDDUSB33 = 3.0 to 3.6 V
VDD = 1.8 to 3.6 V
VSS
PA[15:0]
PB[15:0]
GPIO PORT A
GPIO PORT B
VOLT. REG
3.3V TO 1.2V
PLL1+PLL2+PLL3
VCAP1
@VDD33
PC[15:0]
GPIO PORT C
XTAL OSC
4- 16MHz
OSC_IN
PD[15:0]
PE[15:0]
GPIO PORT D
GPIO PORT E
GPIO PORT F
OSC_OUT
RCC
WDG32K
Reset & control
Standby
interface
VBAT = 1.8 to 3.6 V
PF[15:0]
PG[15:0]
@VSW
GPIO PORT G
GPIO PORT H
OSC32_IN
OSC32_OUT
XTAL 32 kHz
PH[15:0]
PI[11:0]
RTC
RTC_TS
RTC_TAMPx
RTC_OUT
AWU
GPIO PORT I
EXT IT. WKUP
Backup register
CRC
4 KB BKPRAM
168 AF
TIM2
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
D[7:0]
32b
16b
SDMMC1
SDMMC2
CMD, CK as AF
TIM3
TIM4
D[7:0]
CMD, CK as AF
GPDMA1
GPDMA2
AHB/APB2
16b
32b
16b
16b
16b
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF
4 compl. chan.(TIM8_CH1[1:4]N),
16b
AHB/
APB1
TIM1 / PWM
TIM5
TIM12
TIM13
TIM14
4 channels
TIM8 / PWM 16b
4 chan. (TIM8_CH1[1:4], ETR, BKIN as AF
2 channels as AF
1 channel as AF
1 channel as AF
16b
16b
16b
TIM9
2 channels as AF
1 channel as AF
1 channel as AF
TIM10
TIM11
smcard
irDA
RX, TX, SCK
RX, TX, SCK,
smcard
irDA
smcard
irDA
USART1
USART2
USART3
CTS, RTS as AF
CTS, RTS as AF
WWDG
RX, TX, SCK,
smcard
irDA
RX, TX, SCK
CTS, RTS as AF
USART6
CTS, RTS as AF
RX, TX as AF
RX, TX as AF
RX, TX as AF
UART4
UART5
UART7
UART8
SPI2/I2S2
MOSI, MISO,
SPI1/I2S1
SPI4
SCK, NSS as AF
16b
LPTIM1
MOSI, MISO,
SCK, NSS as AF
MOSI, MISO,
SCK, NSS as AF
RX, TX as AF
SPI5
TIM6
TIM7
16b
16b
MOSI, MISO, SCK
NSS as AF
MOSI, MISO, SCK
NSS as AF
SCL, SDA, SMBAL as AF
SD, SCK, FS, MCLK as AF
SD, SCK, FS, MCLK as AF
SAI1
SAI2
SPI3/I2S3
I2C1/SMBUS
I2C2/SMBUS
I2C3/SMBUS
(2)
SCL, SDA, SMBAL as AF
SCL, SDA, SMBAL as AF
ULPI:CK, D[7:0], DIR, STP, NXT
SCL, SDA, INT, ID, VBUS
OTG HS PHY
CONTROLLER
SYSCFG
@VDDA
VDDREF_ADC
Temperature sensor
bxCAN1
TX, RX
8 analog inputs common
to the 3 ADCs
8 analog inputs common
to the ADC1 & 2
ADC1
@VDDA
DAC1
ADC2
IF
ITF
ADC3
DAC2
8 analog inputs for ADC3
DAC1 DAC2
as AF as AF
MSv41012V4
1. The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked
from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
2. Available only on the STM32F723xx devices.
3. Available only on the STM32F723xx LQFP100 package.
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STM32F722xx STM32F723xx
3
Functional overview
3.1
Arm® Cortex®-M7 with FPU
®
®
The Arm Cortex -M7 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and low interrupt latency.
®
The Cortex -M7 processor is a highly efficient high-performance featuring:
–
–
–
–
–
–
Six-stage dual-issue pipeline
Dynamic branch prediction
Harvard caches (8 Kbytes of I-cache and 8 Kbytes of D-cache)
64-bit AXI4 interface
64-bit ITCM interface
2x32-bit DTCM interfaces
The processor supports the following memory interfaces:
•
•
•
Tightly Coupled Memory (TCM) interface.
Harvard instruction and data caches and AXI master (AXIM) interface.
Dedicated low-latency AHB-Lite peripheral (AHBP) interface.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It supports single precision FPU (floating point unit), speeds up software development by
using metalanguage development tools, while avoiding saturation.
Figure 6 shows the general block diagram of the STM32F722xx and STM32F723xx family.
®
®
Note:
Cortex -M7 with FPU core is binary compatible with the Cortex -M4 core.
3.2
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
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3.3
Embedded Flash memory
The STM32F722xx and STM32F723xx devices embed a Flash memory of up to 512 Kbytes
available for storing programs and data.
The flexible protections can be configured thanks to option bytes:
•
Readout protection (RDP) to protect the whole memory. Three levels are available:
–
–
Level 0: no readout protection
Level 1: No access (read, erase, program) to the Flash memory or backup SRAM
can be performed while the debug feature is connected or while booting from RAM
or system memory bootloader
–
Level 2: debug/chip read protection disabled.
•
•
Write protection (WRP): the protected area is protected against erasing and
programming.
Proprietary code readout protection (PCROP): Flash memory user sectors (0 to 7) can
be protected against D-bus read accesses by using the proprietary readout protection
(PCROP). The protected area is execute-only.
3.4
3.5
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
Embedded SRAM
All the devices feature:
•
System SRAM up to 256 Kbytes:
–
–
–
SRAM1 on AHB bus Matrix: 176 Kbytes
SRAM2 on AHB bus Matrix: 16 Kbytes
DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 64 Kbytes for
critical real-time data.
•
Instruction RAM (ITCM-RAM) 16 Kbytes:
–
It is mapped on TCM interface and reserved only for CPU Execution/Instruction
useful for critical real-time routines.
The Data TCM RAM is accessible by the GP-DMAs and peripheral DMAs through the
specific AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is
accessed at CPU clock speed with 0 wait states.
•
4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
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3.6
AXI-AHB bus matrix
The STM32F722xx and STM32F723xx system architecture is based on 2 sub-systems:
•
An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:
–
–
3x AXI to 32-bit AHB bridges connected to AHB bus matrix
1x AXI to 64-bit AHB bridge connected to the embedded Flash memory
•
A multi-AHB Bus-Matrix
–
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, USB
HS) and the slaves (Flash memory, RAM, FMC, Quad-SPI, AHB and APB
peripherals) and ensures a seamless and efficient operation even when several
high-speed peripherals work simultaneously.
(1)
Figure 7. STM32F722xx and STM32F723xx AXI-AHB bus matrix architecture
GP
USB OTG
HS
GP
DMA1
DMA2
Arm Cortex-M7
8KB
DTCM RAM
64KB
I/D Cache
ITCM RAM
16KB
AXI to
multi-AHB
ITCM
FLASH
512KB
64-bit AHB
64-bit BuS Matrix
SRAM1
176KB
SRAM2
16KB
AHB
Periph1
APB1
APB2
AHB
periph2
FMC external
MemCtl
Quad-SPI
32-bit Bus Matrix - S
MSv41005V1
1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus.
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3.7
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support a circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. The configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
2
•
•
•
•
•
•
•
•
•
SPI and I S
2
I C
USART
General-purpose, basic and advanced-control timers TIMx
DAC
SDMMC
ADC
SAI
Quad-SPI
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3.8
Flexible memory controller (FMC)
The Flexible memory controller (FMC) includes three memory controllers:
•
•
•
The NOR/PSRAM memory controller
The NAND/memory controller
The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
The main features of the FMC controller are the following:
•
Interface with static-memory mapped devices including:
–
–
–
–
Static random access memory (SRAM)
NOR Flash memory/OneNAND Flash memory
PSRAM (4 memory banks)
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•
•
•
•
•
•
•
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
8-, 16-, 32-bit data bus width
Independent Chip Select control for each memory bank
Independent configuration for each memory bank
Write FIFO
Read FIFO for SDRAM controller
The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is
HCLK/2
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.9
Quad-SPI memory interface (QUADSPI)
All the devices embed a Quad-SPI memory interface, which is a specialized communication
interface targetting Single, Dual or Quad-SPI Flash memories. It can work in:
•
•
•
Direct mode through registers
External Flash status register polling mode
Memory mapped mode.
Up to 256 Mbytes of external Flash are memory mapped, supporting 8, 16 and 32-bit
access. The code execution is supported.
The opcode and the frame format are fully programmable. The communication can be either
in Single Data Rate or Dual Data Rate.
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3.10
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
®
and handle up to 110 maskable interrupt channels plus the 16 interrupt lines of the Cortex -
M7 with FPU core.
•
•
•
•
•
•
•
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with a minimum
interrupt latency.
3.11
3.12
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs in the
STM32F722xx devices (138 GPIOs in the STM32F723xx devices) can be connected to the
16 external interrupt lines.
Clocks and startup
On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can
then select as system clock either the RC oscillator or an external 4-26 MHz clock source.
This clock can be monitored for failure. If a failure is detected, the system automatically
switches back to the internal RC oscillator and a software interrupt is generated (if enabled).
This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz.
Similarly, a full interrupt management of the PLL clock entry is available when necessary
(for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 216 MHz while the maximum frequency of the high-speed APB domains is
108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz.
The devices embed two dedicated PLLs (PLLI2S and PLLSAI) which allow to achieve audio
2
class performance. In this case, the I S and SAI master clock can generate all standard
sampling frequencies from 8 kHz to 192 kHz.
The STM32F723xx devices embed two PLLs inside the PHY HS controller: PLL1 and PLL2.
The PLL1 allows to output 60 MHz used as an input for PLL2 which itself allows to generate
the 480 Mbps in the USB OTG High Speed mode.
The PLL1 has as input HSE clock.
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3.13
Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
•
•
•
All Flash address space mapped on ITCM or AXIM interface
All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface
The System memory bootloader
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface.
3.14
Power supply schemes
•
•
•
V
= 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
DD
enabled), provided externally through V pins.
DD
V
, V
= 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
DDA
SSA
blocks, RCs and PLL. V
and V
must be connected to V and V , respectively.
DDA
SSA DD SS
V
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
BAT
backup registers (through power switch) when V is not present.
DD
Note:
The V /V
minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
DD DDA
Section 3.15.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode
versus device operating mode to identify the packages supporting this option.
•
The V
can be connected either to V or an external independent power
DDSDMMC DD
supply (1.8 to 3.6V) for the SDMMC2 pins (clock, command, and 4-bit data). For
example, when the device is powered at 1.8V, an independent power supply 2.7V can
be connected to V
.When the V
is connected to a separated power
DDSDMMC
DDSDMMC
supply, it is independent from V or V
but it must be the last supply to be provided
DD
DDA
and the first to disappear. The following conditions V
must be respected:
DDSDMMC
–
During the power-on phase (V < V
), V
DD_MIN
should be always lower
DD
DDSDMMC
than V
DD
–
During the power-down phase (V < V
), V
should be always
DDSDMMC
DD
DD_MIN
lower than V
DD
–
–
The V
rising and falling time rate specifications must be respected
DDSDMMC
In the operating mode phase, V
could be lower or higher than V
DD:
DDSDMMC
All associated GPIOs powered by V
are operating between
DDSDMMC
and V
DDSDMMC_MAX.
V
DDSDMMC_MIN
•
The V
can be connected either to V or an external independent power supply
DDUSB DD
(3.0 to 3.6V) for USB transceivers (refer to Figure 8 and Figure 9). For example, when
the device is powered at 1.8V, an independent power supply 3.3V can be connected to
the V
. When the V
is connected to a separated power supply, it is
DDUSB
DDUSB
independent from V or V
but it must be the last supply to be provided and the first
DDA
DD
to disappear. The following conditions V
must be respected:
DDUSB
–
During the power-on phase (V < V
), V
should be always lower
DD
DD_MIN
DDUSB
than V
DD
–
During the power-down phase (V < V
), V
should be always lower
DDUSB
DD
DD_MIN
than V
DD
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Functional overview
–
–
The V
rising and falling time rate specifications must be respected
DDUSB
In the operating mode phase, V
could be lower or higher than V
DD:
DDUSB
- If the USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
are operating between V and V
V
.
DDUSB_MAX
DDUSB
DDUSB_MIN
- The V
supplies both USB transceiver (USB OTG_HS and USB OTG_FS).
DDUSB
If only one USB transceiver is used in the application, the GPIOs associated to the
other USB transceiver are still supplied by V
.
DDUSB
- If the USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered
by V
are operating between V
and V
.
DDUSB
DD_MIN
DD_MAX
Figure 8. V
connected to V power supply
DDUSB
DD
VDD
VDD_MAX
VDD= VDDA = VDDUSB
VDD_MIN
time
Power-down
Operating mode
Power-on
MS37591V1
Figure 9. V
connected to external power supply
DDUSB
VDDUSB_MAX
USB functional area
VDDUSB
VDDUSB_MIN
USB non
functional
area
USB non
functional
area
VDD = VDDA
VDD_MIN
time
Power-down
Operating mode
Power-on
MS37590V1
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STM32F722xx STM32F723xx
On the STM32F7x3xx devices, the USB OTG HS sub-system uses one or two additional
power supply pins depending on the package:
•
The VDD12OTGHS pin is the output of PHY HS regulator (1.2V). An external capacitor
of 2.2 µF must be connected on the VDD12OTGHS pin.
•
On the LQFP100 only, a second power pin VDDPHYHS is used to supply the USB
OTG PHY HS and associated GPIOs.The VDDPHYHS follows the same rules provided
for the VDDUSB power pin.
3.15
Power supply supervisor
3.15.1
Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when V is below a specified threshold,
DD
V
or V
, without the need for an external reset circuit.
POR/PDR
BOR
The device also features an embedded programmable voltage detector (PVD) that monitors
the V /V power supply and compares it to the V threshold. An interrupt can be
DD DDA
PVD
generated when V /V
drops below the V
threshold and/or when V /V
is
DD DDA
PVD
DD DDA
higher than the V
threshold. The interrupt service routine can then generate a warning
PVD
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.15.2
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor V and NRST and should maintain
DD
the device in reset mode as long as V is below a specified threshold. PDR_ON should be
DD
connected to V . Refer to Figure 10: Power supply supervisor interconnection with internal
SS
reset OFF.
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Figure 10. Power supply supervisor interconnection with internal reset OFF
VDD
External VDD power supply supervisor
Ext. reset controller active when
VDD < 1.7 V
Application reset
NRST
signal
PDR_ON
VDD
VSS
MS31383V4
The V specified threshold, below which the device must be maintained under reset, is
DD
1.7 V (see Figure 11).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
•
•
•
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
The brownout reset (BOR) circuitry must be disabled
The embedded programmable voltage detector (PVD) is disabled
V
functionality is no more available and V
pin should be connected to V
.
BAT
BAT
DD
All packages, except for the LQFP100, allow to disable the internal reset through the
PDR_ON signal when connected to V
.
SS
Figure 11. PDR_ON control with internal reset OFF
V
DD
PDR = 1.7 V
time
Reset by other source than
power supply supervisor
NRST
time
PDR_ON
PDR_ON
MS19009V7
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3.16
Voltage regulator
The regulator has four operating modes:
•
Regulator ON
–
–
–
Main regulator mode (MR)
Low power regulator (LPR)
Power-down
•
Regulator OFF
3.16.1
Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
•
MR mode used in Run/sleep modes or in Stop modes
–
In Run/Sleep modes
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). A different voltage scaling is provided to reach the
best compromise between maximum frequency and dynamic power consumption.
The over-drive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
–
In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).
•
•
LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
–
–
LPR operates in normal mode (default mode when LPR is ON)
LPR operates in under-drive mode (reduced leakage mode).
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
The V and V pins must be connected to 2*2.2 µF, ESR < 2 Ω (or 1*4.7 µF, ESR
CAP_1
CAP_2
between 0.1 Ω and 0.2 Ω if only the V
pin is provided (on LQFP64 package)).
CAP_1
All the packages have the regulator ON feature.
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(1)
Table 3. Voltage regulator configuration mode versus device operating mode
Voltage regulator
configuration
Run mode
Sleep mode
Stop mode
Standby mode
Normal mode
MR
MR
-
MR
MR
-
MR or LPR
-
Over-drive
mode(2)
-
-
-
Under-drive mode
MR or LPR
-
Power-down
mode
-
-
Yes
1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.
3.16.2
Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V voltage source through V
and V
pins.
12
CAP_1
CAP_2
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency.The two 2.2 µF ceramic capacitors should
be replaced by two 100 nF decoupling capacitors.
When the regulator is OFF, there is no more internal monitoring on V . An external power
12
supply supervisor should be used to monitor the V of the logic power domain. The PA0 pin
12
should be used for this purpose, and act as power-on reset on V power domain.
12
In regulator OFF mode, the following features are no more supported:
•
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V logic power
domain which is not reset by the NRST pin.
12
•
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
•
•
The over-drive and under-drive modes are not available.
The Standby mode is not available.
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STM32F722xx STM32F723xx
Figure 12. Regulator OFF
V12
External VCAP_1/2 power
Application reset
signal (optional)
supply supervisor
Ext. reset controller active
when VCAP_1/2 < Min V12
VDD
PA0
NRST
VDD
BYPASS_REG
V12
VCAP_1
VCAP_2
ai18498V3
The following conditions must be respected:
•
V
should always be higher than V
and V
to avoid current injection
CAP_2
DD
CAP_1
between power domains.
•
If the time for V and V
to reach V minimum value is faster than the time for
CAP_1
CAP_2
12
V
to reach 1.7 V, then PA0 should be kept low to cover both conditions: until V
DD
CAP_1
and V
reach V minimum value and until V reaches 1.7 V (see Figure 13).
12 DD
CAP_2
•
•
Otherwise, if the time for V
and V
to reach V minimum value is slower
CAP_2 12
CAP_1
than the time for V to reach 1.7 V, then PA0 could be asserted low externally (see
DD
Figure 14).
If V
and V
go below V minimum value and V is higher than 1.7 V, then a
CAP_2 12 DD
CAP_1
reset must be asserted on PA0 pin.
Note:
Note:
The minimum value of V depends on the maximum frequency targeted in the application.
12
On the LQFP64 pin package, the V
is not available.
CAP_2
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Figure 13. Startup in regulator OFF: slow V slope
DD
- power-down reset risen after V
/V
stabilization
CAP_1 CAP_2
VDD
PDR = 1.7 V or 1.8 V
VCAP_1 / VCAP_2
V12
Min V12
time
NRST
time
ai18491f
1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 14. Startup in regulator OFF mode: fast V slope
DD
- power-down reset risen before V
/V
stabilization
CAP_1 CAP_2
VDD
PDR = 1.7 V or 1.8 V
VCAP_1 / VCAP_2
V12
Min V12
time
time
NRST
PA0 asserted externally
ai18492e
1. This figure is valid whatever the internal reset mode (ON or OFF).
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3.16.3
Regulator ON/OFF and internal reset ON/OFF availability
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
Package
Regulator ON
Regulator OFF
Internal reset ON Internal reset OFF
LQFP64,
Yes
No
LQFP100
LQFP144
Yes
Yes
No
Yes
Yes
Yes
LQFP176,
UFBGA144,
UFBGA176
PDR_ON set to VDD PDR_ON set to VSS
BYPASS_REG set BYPASS_REG set
to VSS to VDD
3.17
Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
•
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
Two programmable alarms.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
•
Three anti-tamper detection pins with programmable filter.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
V
mode.
BAT
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
•
•
•
•
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator(LSE)
The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE) divided by 32
The RTC is functional in V
mode and in all low-power modes when it is clocked by the
BAT
LSE. When clocked by the LSI, the RTC is not functional in V
all low-power modes.
mode, but is functional in
BAT
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All the RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wakeup the device from the low-power modes.
3.18
Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
•
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator
modes in stop mode):
–
–
Normal mode (default mode when MR or LPR is enabled)
Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup and the LPTIM1
asynchronous interrupt).
Table 5. Voltage regulator modes in stop mode
Voltage regulator
Main regulator (MR)
Low-power regulator (LPR)
configuration
Normal mode
MR ON
LPR ON
Under-drive mode
MR in under-drive mode
LPR in under-drive mode
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising or falling edge on one of the 6 WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11),
or an RTC alarm / wakeup / tamper /time stamp event occurs.
The Standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.
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3.19
VBAT operation
The V
pin allows to power the device V
domain from an external battery, an external
BAT
BAT
supercapacitor, or from V when no external battery and an external supercapacitor are
DD
present.
The V
The V
operation is activated when V is not present.
BAT
BAT
DD
pin supplies the RTC, the backup registers and the backup SRAM.
Note:
When the microcontroller is supplied from V
, external interrupts and RTC alarm/events
BAT
do not exit it from V
operation.
BAT
When the PDR_ON pin is connected to V (Internal Reset OFF), the V
functionality is
BAT
SS
no more available and the V
pin should be connected to VDD.
BAT
3.20
Timers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
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Table 6. Timer feature comparison
Max
Max
DMA
request
generation channels
Capture/ Complem
Timer
type
Counter Counter Prescaler
interface timer
clock
(MHz)
Timer
compare
entary
output
resolution
type
factor
clock
(MHz)(1)
Any
integer
between 1
and 65536
Up,
Down,
Up/down
Advanced TIM1,
16-bit
Yes
Yes
Yes
No
4
4
4
2
1
2
1
0
Yes
No
No
No
No
No
No
No
108
54
216
-control
TIM8
Any
integer
between 1
and 65536
Up,
Down,
Up/down
TIM2,
TIM5
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
108/216
108/216
216
Any
integer
between 1
and 65536
Up,
Down,
Up/down
TIM3,
TIM4
54
Any
integer
between 1
and 65536
TIM9
Up
Up
Up
Up
Up
108
108
54
General
purpose
Any
integer
between 1
and 65536
TIM10,
TIM11
No
216
Any
integer
between 1
and 65536
TIM12
No
108/216
108/216
108/216
Any
integer
between 1
and 65536
TIM13,
TIM14
No
54
Any
integer
between 1
and 65536
TIM6,
TIM7
Basic
Yes
54
1. The maximum timer clock is either 108 or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR
register.
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3.20.1
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
•
•
•
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
The TIM1 and TIM8 support independent DMA request generation.
3.20.2
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F722xx and
STM32F723xx devices (see Table 6 for differences).
•
TIM2, TIM3, TIM4, TIM5
The STM32F722xx and STM32F723xx include 4 full-featured general-purpose timers:
TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-
reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on
a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4
independent channels for input capture/output compare, PWM or one-pulse mode
output. This gives up to 16 input capture/output compare/PWMs on the largest
packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•
TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
3.20.3
Basic timers TIM6 and TIM7
These timers are mainly used for the DAC trigger and waveform generation. They can also
be used as a generic 16-bit time base.
The TIM6 and TIM7 support independent DMA request generation.
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3.20.4
Low-power timer (LPTIM1)
The low-power timer has an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
•
•
•
•
•
•
•
•
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous / one-shot mode
Selectable software / hardware input trigger
Selectable clock source:
Internal clock source: LSE, LSI, HSI or APB clock
External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
•
•
Programmable digital glitch filter
Encoder mode
3.20.5
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.20.6
3.20.7
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
•
•
•
•
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
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3.21
Inter-integrated circuit interface (I2C)
2
The devices embed 3 I Cs. Refer to Table 7: I2C implementation for the features
implementation.
2
The I C bus interface handles communications between the microcontroller and the serial
2
2
I C bus. It controls all I C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
I2C-bus specification and user manual rev. 5 compatibility:
–
–
–
–
–
–
–
Slave and master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
•
System Management Bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
–
–
Address resolution protocol (ARP) support
SMBus alert
TM
•
•
Power System Management Protocol (PMBus ) specification rev 1.1 compatibility
2
Independent clock: a choice of independent clock sources allowing the I C
communication speed to be independent from the PCLK reprogramming.
•
•
Programmable analog and digital noise filters
1-byte buffer with DMA capability
2
Table 7. I C implementation
I2C features(1)
I2C1
I2C2
I2C3
Standard-mode (up to 100 kbit/s)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Fast-mode (up to 400 kbit/s)
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)
Programmable analog and digital noise filters
SMBus/PMBus hardware support
Independent clock
1. X: supported.
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3.22
Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed USARTs. Refer to Table 8: USART implementation for the features
implementation.
The universal synchronous asynchronous receiver transmitter (USART) offers a flexible
means of full-duplex data exchange with external equipment requiring an industry standard
NRZ asynchronous serial data format.
The USART peripheral supports:
•
•
Full-duplex asynchronous communications
Configurable oversampling method by 16 or 8 to give flexibility between speed and
clock tolerance
•
•
Dual clock domain allowing convenient baud rate programming independent from the
PCLK reprogramming
A common programmable transmit and receive baud rate of up to 27 Mbit/s when
USART clock source is system clock frequency (max is 216 MHz) and oversampling by
8 is used.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Auto baud rate detection
Programmable data word length (7 or 8 or 9 bits) word length
Programmable data order with MSB-first or LSB-first shifting
Progarmmable parity (odd, even, no parity)
Configurable stop bits (1 or 1.5 or 2 stop bits)
Synchronous mode and clock output for synchronous communications
Single-wire half-duplex communications
Separate signal polarity control for transmission and reception
Swappable Tx/Rx pin configuration
Hardware flow control for modem and RS-485 transceiver
Multiprocessor communications
LIN master synchronous break send capability and LIN slave break detection capability
IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode
Smartcard mode ( T=0 and T=1 asynchronous protocols for Smartcards as defined in
the ISO/IEC 7816-3 standard)
•
Support for Modbus communication
Table 8 summarizes the implementation of all U(S)ARTs instances
Table 8. USART implementation
features(1)
USART1/2/3/6
UART4/5/7/8
Data Length
7, 8 and 9 bits
Hardware flow control for modem
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
X
X
X
X
X
X
X
-
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Table 8. USART implementation (continued)
features(1)
USART1/2/3/6
UART4/5/7/8
Smartcard mode
X
X
X
X
X
X
X
X
X
-
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
X
X
X
X
X
X
X
Dual clock domain
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
1. X: supported.
3.23
Serial peripheral interface (SPI)/inter- integrated sound
interfaces (I2S)
The devices feature up to five SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4, and SPI5 can communicate at up to 50 Mbit/s, SPI2
and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable from 4 to 16 bits. The SPI interfaces support the
NSS pulse mode, TI mode and Hardware CRC calculation. All the SPIs can be served by
the DMA controller.
2
Three standard I S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in master or slave mode, in simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
2
I S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
2
All I Sx can be served by the DMA controller.
3.24
Serial audio interface (SAI)
The devices embed two serial audio interfaces.
The serial audio interface is based on two independent audio subblocks which can operate
as transmitter or receiver with their FIFO. Many audio protocols are supported by each
2
block: I S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output,
supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be
configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.
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SAI1 and SAI2 can be served by the DMA controller
3.25
Audio PLL (PLLI2S)
2
The devices feature an additional dedicated PLL for audio I S and SAI applications. It allows
2
to achieve an error-free I S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
2
The PLLI2S configuration can be modified to manage an I S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU and USB interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
2
I S/SAI flow with an external PLL (or Codec output).
3.26
3.27
Audio PLL (PLLSAI)
An additional PLL dedicated to audio is used for the SAI1 peripheral in case the PLLI2S is
programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz)
and the audio application requires both sampling frequencies simultaneously.
SD/SDIO/MMC card host interface (SDMMC)
SDMMC host interfaces are available, that support MultiMediaCard System Specification
Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDMMC Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a
stack of MMC4.1 or previous.
The SDMMC can be served by the DMA controller
3.28
Controller area network (bxCAN)
The CAN is compliant with the 2.0A and B (active) specifications with a bit rate up to 1
Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. The CAN has three transmit mailboxes, two receive
FIFOs with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated to the CAN.
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3.29
Universal serial bus on-the-go full-speed (OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
•
•
•
•
•
•
•
•
•
Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
12 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
Internal FS OTG PHY support
HNP/SNP/IP inside (no need for any external resistor)
BCD support
For the OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.30
Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. The USB OTG HS supports both full-speed and high-speed operations. It
integrates the transceivers for full-speed operation (12 Mbit/s).
The STM32F722xx devices feature a UTMI low-pin interface (ULPI) for high-speed
operation (480 Mbit/s). When using the USB OTG HS in HS mode, an external PHY device
connected to the ULPI is required.
The STM32F723xx devices feature an integrated PHY HS.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It has a software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
•
•
•
•
•
•
•
Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
8 bidirectional endpoints
16 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
For the STM32F722xx devices: External HS or HS OTG operation supporting ULPI in
SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12
signals. It can be clocked using the 60 MHz output.
•
For the STM32F723xx devices: Internal HS OTG PHY support.
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•
•
•
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Universal Serial Bus controller on-the-go High-Speed PHY controller
(USBPHYC) only on STM32F723xx devices.
The USB HS PHY controller:
–
–
–
Sets the PHYPLL1/2 values for the PHY HS
Sets the other controls on the PHY HS
Controls and monitors the USB PHY’s LDO
3.31
3.32
Random number generator (RNG)
All the devices embed an RNG that delivers 32-bit random numbers generated by an
integrated analog circuit.
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
A Fast I/O handling allows a maximum I/O toggling up to 108 MHz.
3.33
Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In the scan
mode, an automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
•
Simultaneous sample and hold
Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
DS11853 Rev 6
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49
Functional overview
STM32F722xx STM32F723xx
3.34
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with the temperature.
The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as V
, ADC1_IN18, which is used to convert the
BAT
sensor output voltage into a digital value. When the temperature sensor and V
BAT
conversion are enabled at the same time, only V
conversion is performed.
BAT
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
3.35
Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•
•
•
•
•
•
•
•
•
•
Two DAC converters: one for each output channel
8-bit or 12-bit monotonic output
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
Input voltage reference V
REF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
3.36
Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins
could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared
with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
48/229
DS11853 Rev 6
STM32F722xx STM32F723xx
Functional overview
3.37
Embedded Trace Macrocell™
The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F722xx and STM32F723xx device through a small number of ETM pins to an
external hardware trace port analyzer (TPA) device. The TPA is connected to a host
computer using the USB or any other high-speed channel. The real-time instruction and
data flow activity can be recorded and then formatted for display on the host computer that
runs the debugger software. The TPA hardware is commercially available from common
development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
DS11853 Rev 6
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49
Pinouts and pin description
STM32F722xx STM32F723xx
4
Pinouts and pin description
Figure 15. STM32F722xx LQFP64 pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
VDD
VSS
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
1
2
3
4
5
6
7
8
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PC0
PC1
PC2
PC3
LQFP64
9
10
11
12
13
14
15
16
VSSA
VDDA
PA0-WKUP
PA1
PA2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MS40455V3
1. The above figure shows the package top view.
50/229
DS11853 Rev 6
STM32F722xx STM32F723xx
Pinouts and pin description
Figure 16. STM32F722xx LQFP100 pinout
PE2
PE3
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
VDD
2
VSS
PE4
3
VCAP_2
PA13
PE5
4
PE6
5
PA12
PA11
PA10
PA9
PA8
PC9
VBAT
6
PC13
7
PC14-OSC32_IN
8
PC15-OSC32_OUT
9
VSS
VDD
10
11
12
13
14
15
16
17
18
19
PC8
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC7
PC6
LQFP100
PD15
PC0
PD14
PD13
PD12
PD11
PC1
PC2
PC3
VSSA
PD10
VREF+ 20
PD9
VDDA
PA0-WKUP
PA1
21
22
23
24
25
PD8
PB15
53 PB14
52
51
PB13
PB12
PA2
PA3
MSv40457V1
1. The above figure shows the package top view.
DS11853 Rev 6
51/229
99
Pinouts and pin description
STM32F722xx STM32F723xx
Figure 17. STM32F723xx LQFP100 pinout
PE2
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
VDD
PE3
2
VSS
PE4
3
VCAP_2
PA13
PA12
PE5
PE6
4
5
VBAT
6
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC13
7
PC14-OSC32_IN
PC15-OSC32_OUT
VSS
8
9
10
VDD 11
12
13
14
15
16
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC6
LQFP100
PD15
PC0
PC1
PD14
PD13
PD12
PD11
PB15
PB14
PC2 17
PC3
18
19
V SSA
VREF+ 20
VDDA
PA0-WKUP
PA1
21
22
23
24
25
VDD12OTGHS
VDDPHYHS
53 OTG_HS_REXT
52
51
PB13
PB12
PA2
PA3
MSv63474V1
1. The above figure shows the package top view.
52/229
DS11853 Rev 6
STM32F722xx STM32F723xx
Pinouts and pin description
Figure 18. STM32F723xx WLCSP100 ballout (with OTG PHY HS)
1
2
6
4
3
10
5
7
8
9
A
VDD
VSS
PB3
PE3
PD1
PC10
PD5
BOOT0 VSS
VDD
B
C
PA13
PA11
PA12
PA10
PC8
PD4
PD3
PE6
PA15
PA14
VCAP_2
PA9
PD0
PB4
PB5
PB7
PB8
PE1
PE2
PC11
VBAT
PC13
PC15
VDD
PH0
D
E
F
PC9
PC6
PD14
PA8
PD6
PD7
PC7
PC12
PD2
PB6
PE0
PC3
PA4
PB9
PE5
PC0
PA0
PE4
PC14
VSS
PD15
PD12
PE10
PD13
PD11
PB10
PB11
VCAP_1
VSS
PA5
PA6
PC4
PC5
PB2
PE15
PE11
PE12
PE13
PE14
PB0
PB1
PE8
PE7
PE9
VDD12
OTGHS
OTG_HS
_REXT
G
H
NRST
PC1
PB15
PB14
PB13
PB12
VDD
PH1
PA3
PA2
PA1
VSS
J
VDD
VREF+
VDDA
PC2
VDD
USB
K
PA7
VSSA
MSv42002V2
1. The above figure shows the package top view.
DS11853 Rev 6
53/229
99
Pinouts and pin description
STM32F722xx STM32F723xx
Figure 19. STM32F722xx LQFP144 pinout
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14
PC15
PF0
1
108
107
106
105
104
103
102
101
100
99
VDD
2
VSS
3
VCAP_2
PA13
PA12
PA11
PA10
PA9
4
5
6
7
8
9
PA8
10
11
12
13
14
15
16
PC9
PF1
98
PC8
PF2
97
PC7
PF3
96
PC6
PF4
95
VDDUSB
VSS
PF5
94
VSS
93
PG8
VDD 17
92
PG7
PF6
PF7
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
91
PG6
LQFP144
90
PG5
PF8
89
PG4
PF9
88
PG3
PF10
PH0
87
PG2
86
PD15
PD14
VDD
85
PH1
NRST
PC0
84
83
82
81
80
79
78
77
76
75
74
73
VSS
PC1
PD13
PD12
PD11
PD10
PD9
PC2
PC3
VDD
VSSA
VREF+
VDDA
PA0
PA1
PA2
PD8
PB15
PB14
PB13
PB12
MS39132V1
1. The above figure shows the package top view.
54/229
DS11853 Rev 6
STM32F722xx STM32F723xx
Pinouts and pin description
Figure 20. STM32F723xx LQFP144 pinout
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14
PC15
PF0
1
108
107
106
105
104
103
102
101
100
99
VDD
2
VSS
3
VCAP_2
PA13
PA12
PA11
PA10
PA9
4
5
6
7
8
9
PA8
10
11
12
13
14
15
16
PC9
PF1
98
PC8
PF2
97
PC7
PF3
96
PC6
PF4
95
VDDUSB
VSS
PF5
94
VSS
93
PG8
PG5
PG4
PG3
PG2
PD15
VDD 17
92
PF6
PF7
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
91
LQFP144
with HS PHY
90
PF8
89
PF9
88
PF10
PH0
87
PD14
86
VDD
85
PH1
NRST
PC0
VSS
84
PD13
83 PD12
PC1
82
81
80
79
78
77
PD11
PD10
PD9
PD8
PB15
PB14
PC2
PC3
VDD
VSSA
VREF+
VDDA
PA0
PA1
PA2
76 VDD12OTGHS
75 OTG_HS_REXT
74
73
PB13
PB12
MS41014V1
1. The above figure shows the package top view.
DS11853 Rev 6
55/229
99
Pinouts and pin description
STM32F722xx STM32F723xx
Figure 21. STM32F723xx UFBGA144 ballout (with OTG PHY HS)
1
2
3
4
5
PE0
6
7
PB3
8
9
PD7
10
11
PA14
PC10
VDDUSB
PA10
PC9
12
PC13
PE3
PE4
VBAT
VSS
PF3
PF7
PF9
PC1
PA0
PA1
PA2
PA3
PE2
PE5
PF0
VDD
PF4
PF6
PF8
PC2
PA4
PA5
PA6
PA7
PE1
PE6
PF1
PF2
PF5
VDD
VSS
PC3
PC4
PC5
PB0
PB1
PB4
PB5
PB6
PB7
VSS
VDD
VDD
VSS
PG1
PG0
PF15
PF14
PD6
PA15
PC11
PC12
PD1
PA13
PA12
PA11
PA9
A
B
C
D
E
F
PC14-
OSC32_IN
PB9
PG15
PG14
PG13
VSS
PG12
PG11
PG10
PG9
PD5
PC15-
OSC32_OUT
PB8
PD4
PH0 -
OSC_IN
BOOT0
PDR_ON
VDD
PD3
PH1 -
OSC_OUT
PD2
PD0
PA8
NRST
PF10
VDD
VDD
VCAP_1
PE10
PE9
VDD
VSS
VDD
VCAP_2
PD11
PD10
PD9
VDD
VSS
PC8
PC7
VDD
PG8
PC6
G
H
J
BYPASS_
REG
VDD12OTG
HS
OTG_HS
_REXT
PC0
PE11
PE12
PE13
PE14
PE15
PG5
PG2
PD15
PB15
PB13
VSSA
VREF-
VREF+
VDDA
PB2
PF13
PF12
PF11
PG4
PD13
PD12
PB11
PG3
PD14
PB14
PB12
K
L
PE8
PD8
PE7
PB10
M
MSv42000V1
1. The above figure shows the package top view.
56/229
DS11853 Rev 6
STM32F722xx STM32F723xx
Pinouts and pin description
Figure 22. STM32F722xx LQFP176 pinout
PE2
PE3
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
PI1
2
PI0
PE4
3
PH15
PH14
PH13
VDD
VSS
VCAP_2
PE5
PE6
VBAT
PI8
PC13
PC14
PC15
PI9
PI10
PI11
VSS
VDD
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0
PH1
NRST
PC0
PC1
PC2
PC3
VDD
4
5
6
7
8
9
PA13
PA12
PA11
PA10
PA9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PA8
PC9
PC8
PC7
PC6
VDDUSB
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
LQFP176
107
106
105
104
103 VDD
102
101
100
VSS
PD13
PD12
99 PD11
98 PD10
97 PD9
37
38
39
40
41
42
43
44
PD8
96
VSSA
VREF+
PB15
PB14
PB13
PB12
VDD
95
94
93
92
91
90
VDDA
PA0
PA1
PA2
PH2
PH3
VSS
89 PH12
MS41015V1
1. The above figure shows the package top view.
DS11853 Rev 6
57/229
99
Pinouts and pin description
STM32F722xx STM32F723xx
Figure 23. STM32F723xx LQFP176 pinout
PE2
PE3
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99 PD9
98 PD8
97 PB15
PB14
96
PI1
2
PI0
PE4
3
PH15
PH14
PH13
VDD
VSS
VCAP_2
PE5
PE6
VBAT
PI8
PC13
PC14
PC15
PI9
PI10
PI11
VSS
VDD
PF0
PF1
PF2
PF3
PF4
PF5
4
5
6
7
8
9
PA13
PA12
PA11
PA10
PA9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PA8
PC9
PC8
PC7
PC6
VDDUSB
VSS
PG8
LQFP176
with HS PHY
VSS
VDD
PF6
PG5
PG4
PG3
PF7
PG2
PD15
PD14
VDD
PF8
PF9
PF10
PH0
PH1
NRST
PC0
PC1
PC2
PC3
VDD
VSS
PD13
PD12
PD11
PD10
37
38
39
40
41
42
43
44
VSSA
VREF+
VDD12OTGHS
OTG_HS_REXT
95
94
93
92
91
90
VDDA
PA0
PA1
PA2
PH2
PH3
PB13
PB12
VDD
VSS
89 PH12
MS41082V1
1. The above figure shows the package top view.
58/229
DS11853 Rev 6
STM32F722xx STM32F723xx
Pinouts and pin description
Figure 24. STM32F723xx UFBGA176 ballout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
B
PE3
PE2
PE1
PE0
PB9
PB8
PB7
PB5
PG14
PG15
PG13
PG12
PB4
PG11
PB3
PG10
PD7
PD6
PC12
PD0
PA15
PC11
PA14
PC10
PA13
PA12
PE6
PI6
PB6
PE4
VBAT
PC13
PE5
PI7
VDD
SDMMC
VDD
VSS
PI5
PDR_ON
BOOT0
VDD
VSS
VDD
VSS
PG9
PD4
PD5
PD3
PD1
PD2
PI3
PI2
PI1
PA11
PA10
C
D
VSS
PH15
PI8
PI9
PI4
PF0
PI10
PI11
PH13
PH14
PI0
PA9
PA8
PC14
PC15
PH0
E
F
VSS
VSS
PF2
PF3
PF6
PF9
PC0
PH2
PH3
PH4
PH5
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VCAP2 PC9
VDD
VDD
PF1
VSS
VSS
VSS
VDD
PC8
PC7
PC6
PG6
G
H
VSS
VSS
VSS
VSS VDDUSB PG8
PH1
NRST
PF4
PF5
J
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
PG7
K
PF7
PH12
PH11
PH8
PG5
PH10
PH9
PG4
PD15
PD14
PG3
PG2
BYPASS_
REG
L
PF8
PC1
PF10
VSSA
VREF-
PB2
PG1
PG0
VSS
VDD
PE8
VSS
VDD
PE9
VCAP_1 PH6
PD13
M
N
PC2
PA4
PA5
PC3
PC4
PC5
VDD
PE13
PE14
PH7
PD12
PB13
PD11
PD9
PD10
PD8
PF13
PF12
PA1
PA2
PA0
PA6
PF15
PE11
PB12
P
R
VREF+
VDDA
PF14
PE7
PE10
PE12
PE15
PB10
PB11
PB14
PB15
PA3
PA7
PB1
PB0
PF11
MS39130V1
1. The above figure shows the package top view.
DS11853 Rev 6
59/229
99
Pinouts and pin description
STM32F722xx STM32F723xx
Figure 25. STM32F723xx UFBGA176 ballout (with OTG PHY HS)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
B
PE3
PE2
PE1
PE0
PB9
PB8
PB7
PB5
PG14
PG15
PG13
PG12
PB4
PG11
PB3
PG10
PD7
PD6
PC12
PD0
PA15
PC11
PA14
PC10
PA13
PA12
PE6
PI6
PB6
PE4
VBAT
PC13
PE5
PI7
VDD
SDMMC
VDD
VSS
PI5
PDR_ON
BOOT0
VDD
VSS
VDD
VSS
PG9
PD4
PD5
PD3
PD1
PD2
PI3
PI2
PI1
PA11
PA10
C
D
VSS
PH15
PI8
PI9
PI4
PF0
PI10
PI11
PH13
PH14
PI0
PA9
PA8
PC14
PC15
PH0
E
F
VSS
VSS
PF2
PF3
PF6
PF9
PC0
PH2
PH3
PH4
PH5
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VCAP2 PC9
VDD
VDD
PF1
VSS
VSS
VSS
VDD
PC8
PC7
PC6
G
H
VSS
VSS
VSS
VSS VDDUSB PG8
PH1
VDD12 OTG_HS
OTGHS _REXT
NRST
PF4
PF5
J
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
K
PF7
PH12
PH11
PH8
PG5
PH10
PH9
PG4
PD15
PD14
PG3
PG2
BYPASS_
REG
L
PF8
PC1
PF10
VSSA
VREF-
PB2
PG1
PG0
VSS
VDD
PE8
VSS
VDD
PE9
VCAP_1 PH6
PD13
M
N
PC2
PA4
PA5
PC3
PC4
PC5
VDD
PE13
PE14
PH7
PD12
PB13
PD11
PD9
PD10
PD8
PF13
PF12
PA1
PA2
PA0
PA6
PF15
PE11
PB12
P
R
VREF+
VDDA
PF14
PE7
PE10
PE12
PE15
PB10
PB11
PB14
PB15
PA3
PA7
PB1
PB0
PF11
MS42001V1
1. The above figure shows the package top view.
60/229
DS11853 Rev 6
STM32F722xx STM32F723xx
Pinouts and pin description
Table 9. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
FT
FTf
TTa
B
Input / output pin
5 V tolerant I/O
5V tolerant I/O, I2C Fm+ option.
3.3 V tolerant I/O directly connected to ADC
Dedicated BOOT pin
I/O structure
Notes
RST
Bidirectional reset pin with weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Functions selected through GPIOx_AFR registers
Alternate
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
DS11853 Rev 6
61/229
99
Table 10. STM32F722xx and STM32F723xx pin and ball definition
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
TRACECLK, SPI4_SCK,
SAI1_MCLK_A,
QUADSPI_BK1_IO2, FMC_A23,
EVENTOUT
-
1
1
A2
1
1
C9
A2
A3
1
1
PE2
I/O FT
-
-
TRACED0, SAI1_SD_B,
FMC_A19, EVENTOUT
-
-
2
3
2
3
A1
B1
2
3
2
3
A10 A1
A2
B2
2
3
2
3
PE3
PE4
I/O FT
I/O FT
-
-
-
-
TRACED1, SPI4_NSS,
SAI1_FS_A, FMC_A20,
EVENTOUT
D9
E8
B1
B2
TRACED2, TIM9_CH1,
SPI4_MISO, SAI1_SCK_A,
FMC_A21, EVENTOUT
-
4
4
B2
4
4
B3
4
4
PE5
I/O FT
I/O FT
-
-
TRACED3, TIM1_BKIN2,
TIM9_CH2, SPI4_MOSI,
SAI1_SD_A, SAI2_MCK_B,
FMC_A22, EVENTOUT
-
5
6
5
6
B3
C1
5
6
5
6
B10 B3
C10 C1
B4
C2
5
6
5
6
PE6
-
-
-
-
1
VBAT
S
-
-
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
RTC_TAMP2/
(2)
(3)
-
-
-
D2
D1
E1
7
8
9
-
-
D2
-
-
7
8
9
PI8
I/O FT
I/O FT
EVENTOUT
EVENTOUT
RTC_TS,
WKUP5
RTC_TAMP1/
(2)
(3)
RTC_TS/
RTC_OUT,
WKUP4
2
3
7
8
7
8
7
8
D10 D1
A1
B1
7
8
PC13
(2)
(3)
(5)
PC14-
E9
E1
OSC32_IN(PC1 I/O FT
4)
EVENTOUT
EVENTOUT
OSC32_IN
(2)
(3)
(5)
PC15-
4
-
9
-
9
-
F1
D3
10
11
9
-
E10 F1
C1
-
9
-
10 OSC32_OUT(P I/O FT
C15)
OSC32_OUT
-
UART4_RX, CAN1_RX,
FMC_D30, EVENTOUT
-
D3
11
PI9
I/O FT
-
-
-
-
-
-
-
E3
E4
12
13
-
-
-
-
E3
E4
-
-
-
-
12
13
PI10
PI11
I/O FT
I/O FT
-
FMC_D31, EVENTOUT
-
OTG_HS_ULPI_DIR,
EVENTOUT
(4)
WKUP6
-
-
-
-
-
-
F2
F3
14
15
-
-
-
-
F2
F3
-
-
-
-
14
15
VSS
VDD
S
S
-
-
-
-
-
-
-
-
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
I2C2_SDA, FMC_A0,
EVENTOUT
-
-
-
-
-
-
10
11
12
E2
H3
H2
16
17
18
-
-
-
-
-
-
E2
H3
H2
C3
C4
D4
10
11
12
16
17
18
PF0
PF1
PF2
I/O FTf
I/O FTf
I/O FT
-
-
-
-
-
-
I2C2_SCL, FMC_A1,
EVENTOUT
I2C2_SMBA, FMC_A2,
EVENTOUT
-
-
-
-
-
-
-
-
13
14
15
J2
J3
K3
19
20
21
22
23
-
-
-
-
J2
J3
K3
E2
E3
E4
13
14
15
16
17
19
20
21
22
23
PF3
PF4
PF5
VSS
VDD
I/O FT
I/O FT
I/O FT
-
-
-
-
-
FMC_A3, EVENTOUT
ADC3_IN9
FMC_A4, EVENTOUT
ADC3_IN14
-
-
FMC_A5, EVENTOUT
ADC3_IN15
10 16 G2
10
11
F9
G2 D2
S
S
-
-
-
-
-
-
11
17 G3
F10 G3 D3
TIM10_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
QUADSPI_BK1_IO3,
EVENTOUT
-
-
-
18
19
K2
K1
24
25
-
-
-
-
K2
K1
F3
F2
18
19
24
25
PF6
PF7
I/O FT
-
-
ADC3_IN4
ADC3_IN5
TIM11_CH1, SPI5_SCK,
SAI1_MCLK_B, UART7_TX,
QUADSPI_BK1_IO2,
EVENTOUT
-
I/O FT
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
SPI5_MISO, SAI1_SCK_B,
UART7_RTS, TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
-
-
-
20
L3
26
27
-
-
-
L3
G3
20
21
26
27
PF8
PF9
I/O FT
-
-
ADC3_IN6
ADC3_IN7
SPI5_MOSI, SAI1_FS_B,
UART7_CTS, TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
-
-
21
22
L2
L1
-
-
L2
L1
G2
G1
I/O FT
-
28
29
30
-
22
23
24
28
29
PF10
I/O FT
I/O FT
-
EVENTOUT
EVENTOUT
EVENTOUT
ADC3_IN8
OSC_IN
(5)
5
6
12 23 G1
12
13
G10 G1 D1
PH0-OSC_IN
(5)
13 24
14 25
H1
J1
H10 H1
E1
F1
30 PH1-OSC_OUT I/O FT
RS
OSC_OUT
7
8
31
14
15
G9
F8
J1
25
26
31
NRST
I/O
-
-
-
T
SAI2_FS_B,
OTG_HS_ULPI_STP,
FMC_SDNWE, EVENTOUT
ADC1_IN10,
ADC2_IN10,
ADC3_IN10
(4)
15 26 M2 32
M2 H1
M3 H2
32
PC0
I/O FT
I/O FT
ADC1_IN11,
ADC2_IN11,
ADC3_IN11,
RTC_TAMP3,
WKUP3
TRACED0,
SPI2_MOSI/I2S2_SD,
SAI1_SD_A, EVENTOUT
9
16 27 M3 33
16
H9
27
33
PC1
-
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
SPI2_MISO,
OTG_HS_ULPI_DIR,
FMC_SDNE0, EVENTOUT
ADC1_IN12,
ADC2_IN12,
ADC3_IN12
(4)
(4)
10 17 28 M4 34
17
18
J10 M4 H3
28
29
34
35
PC2
PC3
I/O FT
SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
FMC_SDCKE0, EVENTOUT
ADC1_IN13,
ADC2_IN13,
ADC3_IN13
11 18 29 M5 35
F7
J7
M5 H4
I/O FT
-
-
30
-
36
-
-
F10 30
36
37
-
VDD
VSSA
VREF-
VREF+
VDDA
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12 19 31 M1 37
19
-
K10 M1
J1
K1
L1
31
-
-
-
-
N1
P1
R1
-
-
N1
P1
13 20 32
21 33
38
39
20
21
J9
K9
32
33
38
39
-
R1 M1
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS, UART4_TX,
SAI2_SD_B, EVENTOUT
ADC1_IN0,
ADC2_IN0,
ADC3_IN0,
WKUP1
(5)
14 22 34
N3
40
22
G8
N3
J2
34
40
PA0-WKUP
I/O FT
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
TIM2_CH2, TIM5_CH2,
USART2_RTS, UART4_RX,
QUADSPI_BK1_IO3,
ADC1_IN1,
ADC2_IN1,
ADC3_IN1
15 23 35
N2
P2
41
42
23
24
J8
N2
P2
K2
L2
35
36
41
42
PA1
PA2
I/O FT
I/O FT
-
SAI2_MCK_B, EVENTOUT
ADC1_IN2,
ADC2_IN2,
ADC3_IN2,
WKUP2
TIM2_CH3, TIM5_CH3,
TIM9_CH1, USART2_TX,
SAI2_SCK_B, EVENTOUT
16 24 36
H8
-
-
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B, FMC_SDCKE0,
EVENTOUT
-
-
-
-
-
-
F4
43
44
-
-
-
-
F4
-
-
-
-
43
44
PH2
PH3
I/O FT
I/O FT
-
-
QUADSPI_BK2_IO1,
SAI2_MCK_B, FMC_SDNE0,
EVENTOUT
G4
G4
-
I2C2_SCL, OTG_HS_ULPI_NXT,
EVENTOUT
(4)
-
-
-
-
-
-
H4
J4
45
46
-
-
-
-
H4
J4
-
-
-
-
45
46
PH4
PH5
I/O FTf
I/O FTf
-
-
I2C2_SDA, SPI5_NSS,
FMC_SDNWE, EVENTOUT
-
TIM2_CH4, TIM5_CH4,
TIM9_CH2, USART2_RX,
OTG_HS_ULPI_D0, EVENTOUT
ADC1_IN3,
ADC2_IN3,
ADC3_IN3
(4)
17 25 37
18 26 38
R2
47
25
H7
R2 M2
37
47
PA3
I/O FT
-
-
26
-
K8
-
-
G4
H5
38
-
-
VSS
S
I
-
-
-
-
-
-
-
-
-
-
L4
48
L4
48
BYPASS_REG
FT
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
19 27 39
K4
N4
49
50
27
28
-
K4
N4
F4
J3
39
40
49
50
VDD
PA4
S
-
-
-
-
-
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK, OTG_HS_SOF,
EVENTOUT
ADC1_IN4,
ADC2_IN4,
DAC_OUT1
20 28 40
G7
I/O TTa
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
ADC1_IN5,
ADC2_IN5,
DAC_OUT2
(4)
21 29 41
P4
P3
51
52
29
30
F6
P4
P3
K3
L3
41
42
51
52
PA5
PA6
I/O TTa
I/O FT
OTG_HS_ULPI_CK, EVENTOUT
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
TIM13_CH1, EVENTOUT
ADC1_IN6,
ADC2_IN6
22 30 42
G6
-
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SD,
TIM14_CH1, FMC_SDNWE,
EVENTOUT
ADC1_IN7,
ADC2_IN7
23 31 43
R3
53
31
K7
R3 M3
43
53
PA7
I/O FT
-
I2S1_MCK, FMC_SDNE0,
EVENTOUT
ADC1_IN14,
ADC2_IN14
24 32 44
N5
P5
54
55
32
33
H6
J6
N5
P5
J4
44
45
54
55
PC4
PC5
I/O FT
I/O FT
-
-
ADC1_IN15,
ADC2_IN15
-
33 45
K4
FMC_SDCKE0, EVENTOUT
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, UART4_CTS,
OTG_HS_ULPI_D1, EVENTOUT
ADC1_IN8,
ADC2_IN8
(4)
(4)
25 34 46
R5
R4
56
57
34
F5
R5
L4
46
56
PB0
I/O FT
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
OTG_HS_ULPI_D2, EVENTOUT
ADC1_IN9,
ADC2_IN9
26 35 47
35
36
-
G5
K6
-
R4 M4
47
48
49
57
58
59
PB1
PB2
I/O FT
I/O FT
SAI1_SD_A,
SPI3_MOSI/I2S3_SD,
QUADSPI_CLK, EVENTOUT
27 36 48 M6 58
M6
J5
-
-
-
-
SPI5_MOSI, SAI2_SD_B,
FMC_SDNRAS, EVENTOUT
-
-
49
50
R6
P6
59
60
R6 M5
PF11
I/O FT
I/O FT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P6
L5
-
50
51
52
53
54
55
56
57
60
61
62
63
64
65
66
67
PF12
VSS
-
-
-
-
-
-
-
-
FMC_A6, EVENTOUT
-
-
-
-
-
-
-
-
-
51 M8 61
M8
S
S
-
-
52
53
54
55
56
N8
N6
R7
P7
N7
62
63
64
65
66
N8 G5
N6 K5
R7 M6
VDD
PF13
PF14
PF15
PG0
-
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
FMC_A7, EVENTOUT
FMC_A8, EVENTOUT
FMC_A9, EVENTOUT
FMC_A10, EVENTOUT
FMC_A11, EVENTOUT
P7
N7
M7
L6
K6
J6
57 M7 67
PG1
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
TIM1_ETR, UART7_Rx,
QUADSPI_BK2_IO0, FMC_D4,
EVENTOUT
-
-
-
37 58
38 59
39 60
R8
P8
P9
68
69
70
37
38
39
J5
H5
K5
R8 M7
58
59
60
68
69
70
PE7
PE8
PE9
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
TIM1_CH1N, UART7_Tx,
QUADSPI_BK2_IO1, FMC_D5,
EVENTOUT
P8
P9
L7
TIM1_CH1, UART7_RTS,
QUADSPI_BK2_IO2, FMC_D6,
EVENTOUT
K7
-
-
-
-
61 M9 71
-
-
-
-
M9 H6
N9 G6
61
62
71
72
VSS
VDD
S
S
-
-
-
-
-
-
-
-
62
N9
72
TIM1_CH2N, UART7_CTS,
QUADSPI_BK2_IO3, FMC_D7,
EVENTOUT
-
-
-
-
40 63
R9
73
40
41
42
43
E4
R9
J7
63
64
65
66
73
74
75
76
PE10
PE11
PE12
PE13
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
-
-
TIM1_CH2, SPI4_NSS,
SAI2_SD_B, FMC_D8,
EVENTOUT
41 64 P10 74
42 65 R10 75
43 66 N11 76
G4 P10 H8
H4 R10 J8
TIM1_CH3N, SPI4_SCK,
SAI2_SCK_B, FMC_D9,
EVENTOUT
TIM1_CH3, SPI4_MISO,
SAI2_FS_B, FMC_D10,
EVENTOUT
J4
N11 K8
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
TIM1_CH4, SPI4_MOSI,
SAI2_MCK_B, FMC_D11,,
EVENTOUT
-
-
44 67 P11 77
45 68 R11 78
44
45
K4 P11 L8
F4 R11 M8
67
68
77
78
PE14
PE15
I/O FT
I/O FT
-
-
-
-
TIM1_BKIN, FMC_D12,
EVENTOUT
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
USART3_TX,
OTG_HS_ULPI_D3, EVENTOUT
(4)
(4)
28 46 69 R12 79
46
47
G3 R12 M9
69
79
80
PB10
PB11
I/O FTf
I/O FTf
-
-
TIM2_CH4, I2C2_SDA,
USART3_RX,
OTG_HS_ULPI_D4, EVENTOUT
29 47 70 R13 80
30 48 71 M10 81
H3 R13 M10 70
48
49
50
J3 M10 H7
K3
K2 N10 G7
71
-
81
-
VCAP_1
VSS
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
31 49
-
-
-
-
-
32 50 72 N10 82
72
82
VDD
I2C2_SMBA, SPI5_SCK,
TIM12_CH1, FMC_SDNE1,
EVENTOUT
-
-
-
M11 83
-
-
M11
-
-
83
PH6
I/O FT
-
-
I2C3_SCL, SPI5_MISO,
FMC_SDCKE1, EVENTOUT
-
-
-
-
-
-
N12 84
M12 85
-
-
-
-
N12
M12
-
-
-
-
84
85
PH7
PH8
I/O FTf
I/O FTf
-
-
-
-
I2C3_SDA, FMC_D16,
EVENTOUT
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
I2C3_SMBA, TIM12_CH2,
FMC_D17, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
M13 86
L13 87
L12 88
K12 89
-
-
-
-
-
-
-
M13
L13
L12
-
-
-
-
-
-
-
-
86
87
88
89
PH9
PH10
PH11
PH12
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
-
-
TIM5_CH1, FMC_D18,
EVENTOUT
TIM5_CH2, FMC_D19,
EVENTOUT
TIM5_CH3, FMC_D20,
EVENTOUT
-
-
K12
H12
-
-
-
-
-
-
H12 90
J12 91
-
-
-
-
-
-
90
91
VSS
VDD
S
S
-
-
-
-
-
-
-
-
K2 J12
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
USART3_CK,
OTG_HS_ULPI_D5,
OTG_HS_ID, EVENTOUT
(4)
33 51 73 P12 92
51
52
J2 P12 M11 73
92
93
PB12
PB13
I/O FT
-
TIM1_CH1N,
SPI2_SCK/I2S2_CK,
USART3_CTS,
(4)
34 52 74 P13 93
H2 P13 M12 74
G2 J15 H11 75
I/O FT
OTG_HS_VBUS
OTG_HS_ULPI_D6, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
53
54
55
94 OTG_HS_REXT
-
-
-
-
-
-
-
-
-
USB HS OTG PHY calibration resistor
-
-
-
-
-
VDDPHYHS
-
-
-
-
G1 J14 H10 76
95
VDD12OTGHS
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
TIM1_CH2N, TIM8_CH2N,
SPI2_MISO, USART3_RTS,
TIM12_CH1, SDMMC2_D0,
OTG_HS_DM, EVENTOUT
35 53 75 R14 94
-
-
-
-
-
-
PB14
PB14
I/O FT
I/O FT
-
-
-
-
-
-
-
-
-
56
J1 R14 L11 77
96
OTG_HS_DM
RTC_REFIN, TIM1_CH3N,
TIM8_CH3N,
36 54 76 R15 95
-
-
-
-
-
-
PB15
PB15
I/O FT
I/O FT
-
-
SPI2_MOSI/I2S2_SD,
TIM12_CH2, SDMMC2_D1,
OTG_HS_DP, EVENTOUT
-
-
-
-
-
-
-
57
H1 R15 L12 78
97
OTG_HS_DP
USART3_TX, FMC_D13,
EVENTOUT
-
-
-
55 77 P15 96
56 78 P14 97
57 79 N15 98
-
-
-
-
-
-
P15 L9
P14 K9
N15 J9
79
80
98
99
PD8
PD9
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
USART3_RX, FMC_D14,
EVENTOUT
USART3_CK, FMC_D15,
EVENTOUT
81 100
PD10
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
USART3_CTS,
QUADSPI_BK1_IO0,
SAI2_SD_A,
-
58 80 N14 99
58
F3 N14 H9
82 101
PD11
I/O FT
-
-
FMC_A16/FMC_CLE,
EVENTOUT
TIM4_CH1, LPTIM1_IN1,
USART3_RTS,
QUADSPI_BK1_IO1,
SAI2_FS_A,
FMC_A17/FMC_ALE,
EVENTOUT
-
-
59 81 N13 100 59
F2 N13 L10 83 102
PD12
PD13
I/O FT
-
-
-
-
TIM4_CH2, LPTIM1_OUT,
QUADSPI_BK1_IO3,
SAI2_SCK_A, FMC_A18,
EVENTOUT
60 82 M15 101 60
E3 M15 K10 84 103
I/O FT
-
-
-
-
83
-
102
-
-
-
-
-
G8
85 104
86 105
VSS
VDD
S
S
-
-
-
-
-
-
-
-
84 J13 103
J13 F8
TIM4_CH3, UART8_CTS,
FMC_D0, EVENTOUT
-
-
61 85 M14 104 61
62 86 L14 105 62
F1 M14 K11 87 106
E2 L14 K12 88 107
PD14
PD15
I/O FT
I/O FT
-
-
-
-
TIM4_CH4, UART8_RTS,
FMC_D1, EVENTOUT
-
-
-
-
87 L15 106
88 K15 107
-
-
-
-
L15 J12 89 108
K15 J11 90 109
PG2
PG3
I/O FT
I/O FT
-
-
FMC_A12, EVENTOUT
FMC_A13, EVENTOUT
-
-
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
FMC_A14/FMC_BA0,
EVENTOUT
-
-
89 K14 108
-
-
K14 J10 91 110
K13 H12 92 111
PG4
I/O FT
-
-
FMC_A15/FMC_BA1,
EVENTOUT
-
-
-
-
-
-
90 K13 109
91 J15 110
92 J14 111
-
-
-
-
-
-
PG5
PG6
PG7
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
USART6_CK, FMC_INT,
EVENTOUT
USART6_RTS, FMC_SDCLK,
EVENTOUT
-
-
93 H14 112
94 G12 113
-
-
H14 G11 93 112
PG8
I/O FT
-
-
-
-
-
-
-
-
-
-
-
-
-
G12
-
-
94 113
VSS
VDD
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F10
-
-
95 H13 114
K1 H13 C11 95 114
VDDUSB
S
TIM3_CH1, TIM8_CH1,
I2S2_MCK, USART6_TX,
SDMMC2_D6, SDMMC1_D6,
EVENTOUT
37 63 96 H15 115
63
64
E1 H15 G12 96 115
PC6
PC7
I/O FT
I/O FT
-
-
-
-
TIM3_CH2, TIM8_CH2,
I2S3_MCK, USART6_RX,
SDMMC2_D7, SDMMC1_D7,
EVENTOUT
38 64 97 G15 116
D4 G15 F12 97 116
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
TRACED1, TIM3_CH3,
TIM8_CH3, UART5_RTS,
USART6_CK, SDMMC1_D0,
EVENTOUT
39 65 98 G14 117
65
D2 G14 F11 98 117
PC8
I/O FT
-
-
MCO2, TIM3_CH4, TIM8_CH4,
I2C3_SDA, I2S_CKIN,
UART5_CTS,
QUADSPI_BK1_IO0,
SDMMC1_D1, EVENTOUT
40 66 99 F14 118
66
67
D1 F14 E11 99 118
D3 F15 E12 100 119
PC9
PA8
I/O FTf
I/O FTf
-
-
-
-
MCO1, TIM1_CH1, TIM8_BKIN2,
I2C3_SCL, USART1_CK,
41 67 100 F15 119
OTG_FS_SOF, EVENTOUT
TIM1_CH2, I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX, EVENTOUT
42 68 101 E15 120 68
43 69 102 D15 121 69
44 70 103 C15 122 70
C3 E15 D12 101 120
C2 D15 D11 102 121
C1 C15 C12 103 122
PA9
PA10
PA11
I/O FT
I/O FT
I/O FT
-
-
-
OTG_FS_VBUS
TIM1_CH3, USART1_RX,
OTG_FS_ID, EVENTOUT
-
-
TIM1_CH4, USART1_CTS,
CAN1_RX, OTG_FS_DM,
EVENTOUT
TIM1_ETR, USART1_RTS,
SAI2_FS_B, CAN1_TX,
OTG_FS_DP, EVENTOUT
45 71 104 B15 123 71
46 72 105 A15 124 72
B2 B15 B12 104 123
B1 A15 A12 105 124
PA12
I/O FT
I/O FT
-
-
-
-
PA13(JTMS-
SWDIO)
JTMS-SWDIO, EVENTOUT
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
-
73 106 F13 125 73
B3 F13 G9 106 125
A2 F12 G10 107 126
A1 G13 F9 108 127
VCAP_2
VSS
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
47 74 107 F12 126 74
48 75 108 G13 127 75
VDD
TIM8_CH1N, UART4_TX,
CAN1_TX, FMC_D21,
EVENTOUT
-
-
-
E12 128
-
-
E12
-
-
128
PH13
I/O FT
-
-
TIM8_CH2N, UART4_RX,
CAN1_RX, FMC_D22,
EVENTOUT
-
-
-
-
-
-
-
-
-
E13 129
D13 130
E14 131
-
-
-
-
-
-
E13
D13
E14
-
-
-
-
-
-
129
130
131
PH14
PH15
PI0
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
TIM8_CH3N, FMC_D23,
EVENTOUT
TIM5_CH4,SPI2_NSS/I2S2_WS,
FMC_D24, EVENTOUT
TIM8_BKIN2,
SPI2_SCK/I2S2_CK, FMC_D25,
EVENTOUT
-
-
-
-
-
-
D14 132
C14 133
-
-
-
-
D14
C14
-
-
-
-
132
133
PI1
PI2
I/O FT
I/O FT
I/O FT
-
-
-
-
TIM8_CH4, SPI2_MISO,
FMC_D26, EVENTOUT
TIM8_ETR,
SPI2_MOSI/I2S2_SD,FMC_D27,
EVENTOUT
-
-
-
-
-
-
C13 134
D9 135
-
-
-
-
C13
D9
-
-
-
-
134
135
PI3
-
-
-
-
VSS
S
-
-
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
-
-
-
C9 136
-
-
C9
-
-
136
VDD
S
-
-
-
-
-
-
PA14(JTCK-
SWCLK)
49 76 109 A14 137 76
C4 A14 A11 109 137
I/O FT
JTCK-SWCLK, EVENTOUT
JTDI, TIM2_CH1/TIM2_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
UART4_RTS, EVENTOUT
50 77 110 A13 138 77
B4 A13 A10 110 138
PA15(JTDI)
PC10
I/O FT
-
-
-
-
-
-
-
-
SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
QUADSPI_BK1_IO1,
51 78 111 B14 139 78
52 79 112 B13 140 79
53 80 113 A12 141 80
A3 B14 B11 111 139
C5 B13 B10 112 140
D5 A12 C10 113 141
I/O FT
I/O FT
I/O FT
SDMMC1_D2, EVENTOUT
SPI3_MISO, USART3_RX,
UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3, EVENTOUT
PC11
TRACED3,
SPI3_MOSI/I2S3_SD,
USART3_CK, UART5_TX,
SDMMC1_CK, EVENTOUT
PC12
CAN1_RX, FMC_D2,
EVENTOUT
-
-
81 114 B12 142 81
82 115 C12 143 82
B5 B12 E10 114 142
A4 C12 D10 115 143
PD0
PD1
I/O FT
I/O FT
-
-
-
-
CAN1_TX, FMC_D3,
EVENTOUT
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
TRACED2, TIM3_ETR,
UART5_RX, SDMMC1_CMD,
EVENTOUT
54 83 116 D12 144 83
E5 D12 E9 116 144
C6 D11 D9 117 145
PD2
PD3
I/O FT
I/O FT
-
-
-
-
SPI2_SCK/I2S2_CK,
USART2_CTS, FMC_CLK,
EVENTOUT
-
84 117 D11 145 84
USART2_RTS, FMC_NOE,
EVENTOUT
-
-
85 118 D10 146 85
86 119 C11 147 86
B6 D10 C9 118 146
A5 C11 B9 119 147
PD4
PD5
I/O FT
I/O FT
-
-
-
-
USART2_TX, FMC_NWE,
EVENTOUT
-
-
-
-
120 D8 148
121 C8 149
-
-
-
-
D8
C8
E7 120 148
F7 121 149
VSS
S
S
-
-
-
-
-
-
-
-
VDDSDMMC
SPI3_MOSI/I2S3_SD,
SAI1_SD_A, USART2_RX,
SDMMC2_CK, FMC_NWAIT,
EVENTOUT
-
-
87 122 B11 150 87
88 123 A11 151 88
D6 B11 A8 122 150
E6 A11 A9 123 151
PD6
PD7
I/O FT
I/O FT
-
-
-
-
USART2_CK SDMMC2_CMD,
FMC_NE1, EVENTOUT
USART6_RX,
QUADSPI_BK2_IO2,
SAI2_FS_B, SDMMC2_D0,
FMC_NE2/FMC_NCE,
EVENTOUT
-
-
124 C10 152
-
-
C10 E8 124 152
PG9
I/O FT
-
-
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
SAI2_SD_B, SDMMC2_D1,
FMC_NE3, EVENTOUT
-
-
-
-
125 B10 153
-
-
-
-
B10 D8 125 153
PG10
PG11
I/O FT
I/O FT
-
-
-
-
SDMMC2_D2, FMC_INT,
EVENTOUT
126 B9 154
B9
C8 126 154
LPTIM1_IN1, USART6_RTS,
SDMMC2_D3, FMC_NE4,
EVENTOUT
-
-
-
-
127 B8 155
-
-
-
-
B8
A8
B8 127 155
PG12
PG13
I/O FT
-
-
-
-
TRACED0, LPTIM1_OUT,
USART6_CTS, FMC_A24,
EVENTOUT
128 A8 156
D7 128 156
I/O FT
TRACED1, LPTIM1_ETR,
USART6_TX,
QUADSPI_BK2_IO3, FMC_A25,
EVENTOUT
-
-
-
-
129 A7 157
130 D7 158
-
-
-
-
A7
D7
C7 129 157
PG14
VSS
I/O FT
-
-
-
-
-
130 158
S
-
-
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
-
-
-
-
131 C7 159
132 B7 160
-
-
-
-
C7
B7
F6 131 159
B7 132 160
VDD
S
-
-
-
-
-
-
USART6_CTS, FMC_SDNCAS,
EVENTOUT
PG15
I/O FT
JTDO/TRACESWO, TIM2_CH2,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
SDMMC2_D2, EVENTOUT
PB3(JTDO/TRA
CESWO)
55 89 133 A10 161 89
A6 A10 A7 133 161
I/O FT
-
-
-
-
NJTRST, TIM3_CH1,
SPI1_MISO, SPI3_MISO,
SPI2_NSS/I2S2_WS,
56 90 134 A9 162 90
B7
C7
A9
A6
A6 134 162 PB4(NJTRST) I/O FT
SDMMC2_D3, EVENTOUT
TIM3_CH2, I2C1_SMBA,
SPI1_MOSI/I2S1_SD,
SPI3_MOSI/I2S3_SD,
OTG_HS_ULPI_D7,
(4)
57 91 135 A6 163 91
B6 135 163
PB5
PB6
I/O FT
-
-
FMC_SDCKE1, EVENTOUT
TIM4_CH1, I2C1_SCL,
USART1_TX,
QUAD SPI_BK1_NCS,
FMC_SDNE1, EVENTOUT
58 92 136 B6 164 92
D7
B6
C6 136 164
I/O FTf
-
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
TIM4_CH2, I2C1_SDA,
USART1_RX, FMC_NL,
EVENTOUT
59 93 137 B5 165 93
60 94 138 D6 166 94
B8
A7
B5
D6
D6 137 165
PB7
I/O FTf
-
-
-
D5 138 166
C5 139 167
BOOT
I
B
-
VPP
TIM4_CH3, TIM10_CH1,
I2C1_SCL, CAN1_RX,
SDMMC2_D4, SDMMC1_D4,
EVENTOUT
61 95 139 A5 167 95
C8
D8
E7
A5
B4
A4
PB8
PB9
PE0
I/O FTf
-
-
-
-
-
-
TIM4_CH4, TIM11_CH1,
I2C1_SDA, SPI2_NSS/I2S2_WS,
CAN1_TX, SDMMC2_D5,
62 96 140 B4 168 96
B5 140 168
I/O FTf
SDMMC1_D5, EVENTOUT
TIM4_ETR, LPTIM1_ETR,
UART8_Rx, SAI2_MCK_A,
FMC_NBL0, EVENTOUT
-
-
97 141 A4 169 97
A5 141 169
A4 142 170
I/O FT
I/O FT
LPTIM1_IN2, UART8_Tx,
FMC_NBL1, EVENTOUT
98 142 A3 170 98
B9
A8
A3
D5
PE1
VSS
-
-
-
-
63 99
-
D5
-
99
E6
-
-
S
-
-
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
-
-
143 C6 171
-
-
C6
C5
E5 143 171
F5 144 172
PDR_ON
VDD
S
S
-
-
-
-
-
-
-
-
64 100 144 C5 172 100
A9
TIM8_BKIN, SAI2_MCK_A,
FMC_NBL2, EVENTOUT
-
-
-
-
-
-
D4 173
C4 174
-
-
-
-
D4
-
-
173
PI4
I/O FT
-
-
TIM8_CH1, SAI2_SCK_A,
FMC_NBL3, EVENTOUT
C4
-
-
174
PI5
I/O FT
-
-
TIM8_CH2, SAI2_SD_A,
FMC_D28, EVENTOUT
-
-
-
-
-
-
C3 175
C2 176
-
-
-
-
C3
C2
-
-
-
-
175
176
PI6
PI7
I/O FT
I/O FT
-
-
-
-
TIM8_CH3, SAI2_FS_A,
FMC_D29, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F6
F7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F6
F7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VSS
VSS
VSS
VSS
VSS
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F8
F8
F9
F9
F10
F10
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G6
G7
G8
G9
G10
H6
H7
H8
H9
H10
J6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G6
G7
G8
G9
G10
H6
H7
H8
H9
H10
J6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J7
J7
J8
J8
J9
J9
J10
K6
K7
K8
J10
K6
K7
K8
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
STM32F722xx
STM32F723xx
Pin name
(function after
reset)(1)
Additional
functions
Alternate functions
-
-
-
-
-
-
K9
-
-
-
-
-
-
K9
-
-
-
-
-
-
VSS
VSS
S
S
-
-
-
-
-
-
-
-
K10
K10
1. Function availability depends on the chosen device.
2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and
PI8 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by
the main reset).
4. ULPI signals not available on the STM32F723xx devices.
5. If the device is in regulator OFF/internal reset ON mode (BYPASS_REG pin is set to VDD), then PA0 is used as an internal reset (active low).
Pinouts and pin description
STM32F722xx STM32F723xx
Table 11. FMC pin definition
NOR/PSRAM/SR
NOR/PSRAM
Mux
Pin name
NAND16
SDRAM
AM
PF0
PF1
A0
A1
-
-
-
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
-
-
PF2
A2
-
-
PF3
A3
-
-
PF4
A4
-
-
PF5
A5
-
-
PF12
PF13
PF14
PF15
PG0
PG1
PG2
PG3
PG4
PG5
PD11
PD12
PD13
PE3
A6
-
-
A7
-
-
A8
-
-
A9
-
-
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
D0
-
-
-
-
-
-
-
-
-
-
BA0
BA1
-
-
-
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
CLE
ALE
-
-
-
-
-
PE4
-
-
PE5
-
-
PE6
-
-
PE2
-
-
PG13
PG14
PD14
PD15
PD0
PD1
PE7
-
-
-
-
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D1
D2
D3
D4
PE8
D5
PE9
D6
PE10
D7
86/229
DS11853 Rev 6
STM32F722xx STM32F723xx
Pin name
Pinouts and pin description
Table 11. FMC pin definition (continued)
NOR/PSRAM/SR
AM
NOR/PSRAM
Mux
NAND16
SDRAM
PE11
PE12
PE13
PE14
PE15
PD8
PD9
PD10
PH8
PH9
PH10
PH11
PH12
PH13
PH14
PH15
PI0
D8
D9
DA8
D8
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
-
DA9
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
NE1
NE2
NE3
-
DA10
D10
DA11
D11
DA12
D12
DA13
D13
DA14
D14
DA15
D15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PI1
-
-
PI2
-
-
-
PI3
-
PI6
-
-
PI7
-
-
PI9
-
-
PI10
PD7
PG9
PG10
PG11
PG12
PD3
PD4
PD5
PD6
PB7
-
-
NE1
NE2
NE3
-
-
NCE
-
-
-
-
-
NE4
CLK
NOE
NWE
NWAIT
NADV
NE4
CLK
NOE
NWE
NWAIT
NADV
-
-
-
-
NOE
NWE
NWAIT
-
-
-
-
-
DS11853 Rev 6
87/229
99
Pinouts and pin description
Pin name
STM32F722xx STM32F723xx
Table 11. FMC pin definition (continued)
NOR/PSRAM/SR
AM
NOR/PSRAM
Mux
NAND16
SDRAM
PF6
PF7
PF8
PF9
PF10
PG6
PG7
PE0
PE1
PI4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
INT
-
NBL0
NBL0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
NBL0
NBL1
NBL2
NBL3
SDCLK
SDNWE
SDNRAS
SDNCAS
SDCKE0
SDNE0
SDNE1
SDCKE1
SDNWE
SDNE0
SDCKE0
SDCKE1
SDNE1
NBL1
NBL1
NBL2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PI5
NBL3
PG8
PC0
PF11
PG15
PH2
PH3
PH6
PH7
PH5
PC2
PC3
PB5
PB6
-
-
-
-
-
-
-
-
-
-
-
-
-
88/229
DS11853 Rev 6
Table 12. STM32F722xx and STM32F723xx alternate function mapping
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF15
SYS
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
CAN1/TIM1 SAI2/QUAD
SAI2/USART 2/13/14/QU SPI/SDMM
6/UART4/5/7/
8/OTG1_FS
SPI1/I2S1/
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
UART7/F
MC/SDM
MC1/
Port
TIM8/9/10/1 I2C1/2/3/U SPI2/I2S2/
1/LPTIM1
TIM1/2
TIM3/4/5
ADSPI/
FMC/
OTG2_HS
C2/OTG2_ SDMMC2
HS/OTG1_
FS
SART1
SPI3/I2S3/
SPI4/5
OTG2_FS
UART4
TIM2_CH1
/TIM2_ET TIM5_CH1 TIM8_ETR
R
USART2_CT
S
EVEN
TOUT
PA0
PA1
-
-
-
-
-
-
-
-
UART4_ TX
UART4_RX
-
SAI2_SD_B
-
-
-
-
USART2_RT
S
QUADSPI_ SAI2_MCK
BK1_IO3
EVEN
TOUT
TIM2_CH2 TIM5_CH2
-
_B
EVEN
TOUT
PA2
PA3
PA4
-
-
-
TIM2_CH3 TIM5_CH3 TIM9_CH1
TIM2_CH4 TIM5_CH4 TIM9_CH2
-
-
-
-
-
-
-
USART2_TX SAI2_SCK_B
-
-
-
-
-
-
-
-
-
OTG_HS_U
LPI_D0
EVEN
TOUT
USART2_RX
USART2_CK
-
-
SPI1_NSS SPI3_NSS
/I2S1_WS /I2S3_WS
OTG_HS_ EVEN
-
-
-
-
-
SOF
TOUT
TIM2_CH1
/TIM2_ET
R
TIM8_CH1
N
SPI1_SCK
-
OTG_HS_U
LPI_CK
EVEN
TOUT
PA5
PA6
-
-
-
-
-
-
-
-
-
-
-
-
/I2S1_CK
Port A
TIM1_BKI
N
SPI1_MIS
EVEN
TOUT
TIM3_CH1 TIM8_BKIN
-
TIM13_CH1
-
-
-
O
SPI1_MO
SI/I2S1_S
D
TIM1_CH1
N
TIM8_CH1
FMC_SDN EVEN
PA7
-
TIM3_CH2
N
-
-
-
-
TIM14_CH1
-
WE
TOUT
TIM8_BKIN
OTG_FS_S
OF
EVEN
TOUT
PA8
PA9
MCO1
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH4
-
I2C3_SCL
-
-
-
-
-
USART1_CK
USART1_TX
USART1_RX
-
-
-
-
-
-
-
-
-
-
-
-
-
2
I2C3_SMB SPI2_SCK
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
A
/I2S2_CK
OTG_FS_I
D
EVEN
TOUT
PA10
PA11
-
-
-
USART1_CT
S
OTG_FS_D
M
EVEN
TOUT
-
-
CAN1_RX
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF15
SYS
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
CAN1/TIM1 SAI2/QUAD
SAI2/USART 2/13/14/QU SPI/SDMM
6/UART4/5/7/
8/OTG1_FS
SPI1/I2S1/
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
UART7/F
MC/SDM
MC1/
Port
TIM8/9/10/1 I2C1/2/3/U SPI2/I2S2/
1/LPTIM1
TIM1/2
TIM3/4/5
ADSPI/
FMC/
OTG2_HS
C2/OTG2_ SDMMC2
HS/OTG1_
FS
SART1
SPI3/I2S3/
SPI4/5
OTG2_FS
UART4
USART1_RT
S
OTG_FS_D
EVEN
TOUT
PA12
-
TIM1_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI2_FS_B
CAN1_TX
-
-
-
-
P
JTMS-
SWDIO
EVEN
TOUT
PA13
PA14
-
-
-
-
-
-
-
-
-
-
-
-
Port A
JTCK-
SWCLK
EVEN
TOUT
TIM2_CH1
/TIM2_ET
R
SPI1_NSS SPI3_NSS
/I2S1_WS /I2S3_WS
EVEN
TOUT
PA15
JTDI
-
-
-
-
UART4_RTS
-
-
-
-
TIM1_CH2
N
TIM8_CH2
N
OTG_HS_U
LPI_D1
EVEN
TOUT
PB0
PB1
PB2
PB3
PB4
-
-
-
TIM3_CH3
-
-
-
-
-
-
-
-
-
-
-
-
UART4_CTS
-
-
-
-
-
-
-
-
-
-
-
-
TIM1_CH3
N
TIM8_CH3
N
OTG_HS_U
LPI_D2
EVEN
TOUT
TIM3_CH4
-
-
-
SAI1_SD_ SPI3_MOSI/I
QUADSPI_
CLK
EVEN
TOUT
-
-
-
-
-
-
A
2S3_SD
JTDO/TR
ACESWO
SPI1_SCK SPI3_SCK
/I2S1_CK /I2S3_CK
SDMMC2_
D2
EVEN
TOUT
TIM2_CH2
-
-
-
-
-
SPI1_MIS SPI3_MIS SPI2_NSS/I2
SDMMC2_
D3
EVEN
TOUT
NJTRST
-
TIM3_CH1
-
Port B
O
O
S2_WS
SPI1_MO SPI3_MO
SI/I2S1_S SI/I2S3_S
I2C1_SMB
A
OTG_HS_U
LPI_D7
FMC_SDC EVEN
KE1 TOUT
PB5
-
TIM3_CH2
-
-
-
-
-
D
D
QUADSPI_
BK1_NCS
FMC_SDN EVEN
PB6
PB7
PB8
-
-
-
-
-
-
TIM4_CH1
TIM4_CH2
TIM4_CH3
-
-
I2C1_SCL
I2C1_SDA
I2C1_SCL
-
-
USART1_TX
USART1_RX
-
-
-
-
-
-
-
-
E1
TOUT
EVEN
TOUT
-
-
-
-
-
-
FMC_NL
TIM10_CH
1
SDMMC2_
D4
SDMMC1 EVEN
_D4 TOUT
CAN1_RX
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF15
SYS
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
CAN1/TIM1 SAI2/QUAD
SAI2/USART 2/13/14/QU SPI/SDMM
6/UART4/5/7/
8/OTG1_FS
SPI1/I2S1/
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
UART7/F
MC/SDM
MC1/
Port
TIM8/9/10/1 I2C1/2/3/U SPI2/I2S2/
1/LPTIM1
TIM1/2
TIM3/4/5
ADSPI/
FMC/
OTG2_HS
C2/OTG2_ SDMMC2
HS/OTG1_
FS
SART1
SPI3/I2S3/
SPI4/5
OTG2_FS
UART4
SPI2_NSS
/I2S2_WS
SDMMC2_
SDMMC1 EVEN
PB9
-
-
-
TIM4_CH4 TIM11_CH1 I2C1_SDA
-
-
-
-
-
CAN1_TX
-
-
D5
_D5
TOUT
SPI2_SCK
/I2S2_CK
OTG_HS_U
LPI_D3
EVEN
TOUT
PB10
PB11
TIM2_CH3
-
-
-
-
I2C2_SCL
I2C2_SDA
USART3_TX
-
-
OTG_HS_U
LPI_D4
EVEN
TOUT
-
TIM2_CH4
-
-
USART3_RX
USART3_CK
-
-
-
-
TIM1_BKI
N
I2C2_SMB SPI2_NSS
OTG_HS_U
LPI_D5
OTG_HS_ EVEN
Port B
PB12
PB13
PB14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A
/I2S2_WS
ID
TOUT
TIM1_CH1
N
SPI2_SCK
/I2S2_CK
USART3_CT
S
OTG_HS_U
LPI_D6
EVEN
TOUT
-
-
-
-
TIM1_CH2
N
TIM8_CH2
N
SPI2_MIS
O
USART3_RT
S
SDMMC2_
OTG_HS_ EVEN
DM TOUT
-
-
-
-
-
-
TIM12_CH1
-
D0
SPI2_MO
SI/I2S2_S
D
RTC_REF TIM1_CH3
TIM8_CH3
N
SDMMC2_
OTG_HS_ EVEN
DP TOUT
PB15
PC0
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM12_CH2
-
IN
N
D1
OTG_HS_U
LPI_STP
FMC_SDN EVEN
-
-
-
-
-
-
-
SAI2_FS_B
-
-
-
-
-
WE
TOUT
SPI2_MO
SI/I2S2_S
D
SAI1_SD_
A
EVEN
TOUT
PC1 TRACED0
-
-
-
-
-
-
-
-
-
-
-
Port C
SPI2_MIS
O
OTG_HS_U
LPI_DIR
FMC_SDN EVEN
E0 TOUT
PC2
PC3
-
-
-
-
SPI2_MO
SI/I2S2_S
D
OTG_HS_U
LPI_NXT
FMC_SDC EVEN
KE0 TOUT
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF15
SYS
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
CAN1/TIM1 SAI2/QUAD
SAI2/USART 2/13/14/QU SPI/SDMM
6/UART4/5/7/
8/OTG1_FS
SPI1/I2S1/
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
UART7/F
MC/SDM
MC1/
Port
TIM8/9/10/1 I2C1/2/3/U SPI2/I2S2/
1/LPTIM1
TIM1/2
TIM3/4/5
ADSPI/
FMC/
OTG2_HS
C2/OTG2_ SDMMC2
HS/OTG1_
FS
SART1
SPI3/I2S3/
SPI4/5
OTG2_FS
UART4
FMC_SDN EVEN
E0 TOUT
PC4
-
-
-
-
-
-
-
I2S1_MCK
-
-
-
-
-
-
-
FMC_SDC EVEN
KE0 TOUT
PC5
PC6
PC7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SDMMC2_
D6
SDMMC1 EVEN
_D6 TOUT
TIM3_CH1 TIM8_CH1
TIM3_CH2 TIM8_CH2
TIM3_CH3 TIM8_CH3
I2S2_MCK
-
USART6_TX
USART6_RX
SDMMC2_
D7
SDMMC1 EVEN
_D7 TOUT
-
-
I2S3_MCK
SDMMC1 EVEN
_D0 TOUT
PC8 TRACED1
-
-
UART5_RTS USART6_CK
-
-
-
-
QUADSPI_
BK1_IO0
SDMMC1 EVEN
_D1 TOUT
PC9
MCO2
TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN
UART5_CTS
USART3_TX
-
Port C
SPI3_SCK
/I2S3_CK
QUADSPI_
BK1_IO1
SDMMC1 EVEN
_D2 TOUT
PC10
PC11
-
-
-
-
-
-
-
-
-
-
UART4_TX
SPI3_MIS
O
QUADSPI_
BK2_NCS
SDMMC1 EVEN
_D3 TOUT
USART3_RX UART4_RX
SPI3_MO
SI/I2S3_S USART3_CK
D
SDMMC1 EVEN
PC12 TRACED3
-
-
-
-
-
UART5_TX
-
-
-
_CK
TOUT
EVEN
TOUT
PC13
PC14
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
EVEN
TOUT
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF15
SYS
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
CAN1/TIM1 SAI2/QUAD
SAI2/USART 2/13/14/QU SPI/SDMM
6/UART4/5/7/
8/OTG1_FS
SPI1/I2S1/
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
UART7/F
MC/SDM
MC1/
Port
TIM8/9/10/1 I2C1/2/3/U SPI2/I2S2/
1/LPTIM1
TIM1/2
TIM3/4/5
ADSPI/
FMC/
OTG2_HS
C2/OTG2_ SDMMC2
HS/OTG1_
FS
SART1
SPI3/I2S3/
SPI4/5
OTG2_FS
UART4
EVEN
TOUT
PD0
PD1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CAN1_RX
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D2
FMC_D3
EVEN
TOUT
-
-
CAN1_TX
SDMMC1 EVEN
PD2 TRACED2
TIM3_ETR
UART5_RX
-
-
-
-
_CMD
TOUT
SPI2_SCK
/I2S2_CK
USART2_CT
S
EVEN
TOUT
PD3
PD4
PD5
-
-
-
-
-
-
-
-
-
FMC_CLK
USART2_RT
S
FMC_NO EVEN
TOUT
-
-
E
FMC_NW EVEN
TOUT
USART2_TX
USART2_RX
E
SPI3_MO
SI/I2S3_S
D
SAI1_SD_
A
SDMMC2 FMC_NW EVEN
PD6
-
-
-
-
-
-
-
-
_CK
AIT
TOUT
Port D
SDMMC2
_CMD
EVEN
TOUT
PD7
PD8
PD9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART2_CK
USART3_TX
USART3_RX
USART3_CK
-
-
-
-
-
-
FMC_NE1
FMC_D13
FMC_D14
FMC_D15
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
-
-
-
EVEN
TOUT
PD10
PD11
PD12
PD13
PD14
PD15
-
-
-
USART3_CT
S
QUADSPI_
BK1_IO0
FMC_A16/ EVEN
FMC_CLE TOUT
-
-
SAI2_SD_A
SAI2_FS_A
LPTIM1_IN
1
USART3_RT
S
QUADSPI_
BK1_IO1
FMC_A17/ EVEN
FMC_ALE TOUT
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
-
LPTIM1_O
UT
QUADSPI_ SAI2_SCK_
BK1_IO3
EVEN
FMC_A18
-
-
-
-
A
TOUT
EVEN
FMC_D0
-
-
UART8_CTS
UART8_RTS
-
-
TOUT
Port D
EVEN
FMC_D1
-
-
TOUT
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF15
SYS
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
CAN1/TIM1 SAI2/QUAD
SAI2/USART 2/13/14/QU SPI/SDMM
6/UART4/5/7/
8/OTG1_FS
SPI1/I2S1/
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
UART7/F
MC/SDM
MC1/
Port
TIM8/9/10/1 I2C1/2/3/U SPI2/I2S2/
1/LPTIM1
TIM1/2
TIM3/4/5
ADSPI/
FMC/
OTG2_HS
C2/OTG2_ SDMMC2
HS/OTG1_
FS
SART1
SPI3/I2S3/
SPI4/5
OTG2_FS
UART4
LPTIM1_ET
R
SAI2_MCK
FMC_NBL EVEN
TOUT
PE0
PE1
PE2
-
-
-
-
-
-
-
-
TIM4_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UART8_Rx
-
-
-
_A
0
LPTIM1_IN
2
FMC_NBL EVEN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UART8_Tx
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
TOUT
TRACECL
K
SAI1_MCL
K_A
QUADSPI_
BK1_IO2
EVEN
TOUT
-
SPI4_SCK
-
-
FMC_A23
SAI1_SD_
B
EVEN
TOUT
PE3 TRACED0
PE4 TRACED1
PE5 TRACED2
PE6 TRACED3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A19
FMC_A20
FMC_A21
FMC_A22
FMC_D4
FMC_D5
FMC_D6
FMC_D7
FMC_D8
FMC_D9
FMC_D10
FMC_D11
FMC_D12
SAI1_FS_
A
EVEN
TOUT
-
SPI4_NSS
-
SPI4_MIS SAI1_SCK
_A
EVEN
TOUT
TIM9_CH1
-
O
TIM1_BKI
N2
SPI4_MO SAI1_SD_
SAI2_MCK
_B
EVEN
TOUT
TIM9_CH2
-
SI
A
Port E
QUADSPI_
BK2_IO0
EVEN
TOUT
PE7
PE8
PE9
-
-
-
-
-
-
-
-
-
TIM1_ETR
-
-
-
-
-
-
-
-
-
-
-
UART7_Rx
TIM1_CH1
N
QUADSPI_
BK2_IO1
EVEN
TOUT
-
-
-
-
-
-
-
-
-
UART7_Tx
QUADSPI_
BK2_IO2
EVEN
TOUT
TIM1_CH1
-
UART7_RTS
TIM1_CH2
N
QUADSPI_
BK2_IO3
EVEN
TOUT
PE10
PE11
PE12
PE13
PE14
PE15
-
UART7_CTS
EVEN
TOUT
TIM1_CH2
SPI4_NSS
SPI4_SCK
-
-
-
-
-
SAI2_SD_B
TIM1_CH3
N
SAI2_SCK_
B
EVEN
TOUT
SPI4_MIS
O
EVEN
TOUT
TIM1_CH3
TIM1_CH4
SAI2_FS_B
SPI4_MO
SI
SAI2_MCK
_B
EVEN
TOUT
Port E
TIM1_BKI
N
EVEN
TOUT
-
-
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF15
SYS
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
CAN1/TIM1 SAI2/QUAD
SAI2/USART 2/13/14/QU SPI/SDMM
6/UART4/5/7/
8/OTG1_FS
SPI1/I2S1/
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
UART7/F
MC/SDM
MC1/
Port
TIM8/9/10/1 I2C1/2/3/U SPI2/I2S2/
1/LPTIM1
TIM1/2
TIM3/4/5
ADSPI/
FMC/
OTG2_HS
C2/OTG2_ SDMMC2
HS/OTG1_
FS
SART1
SPI3/I2S3/
SPI4/5
OTG2_FS
UART4
EVEN
TOUT
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C2_SDA
I2C2_SCL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A0
EVEN
TOUT
-
-
FMC_A1
I2C2_SMB
A
EVEN
TOUT
-
-
FMC_A2
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A3
EVEN
TOUT
-
-
FMC_A4
EVEN
TOUT
-
-
FMC_A5
TIM10_CH
1
SAI1_SD_
B
QUADSPI_
BK1_IO3
EVEN
TOUT
Port F
SPI5_NSS
SPI5_SCK
UART7_Rx
UART7_Tx
-
-
-
-
-
SAI1_MCL
K_B
QUADSPI_
BK1_IO2
EVEN
TOUT
TIM11_CH1
SPI5_MIS SAI1_SCK
_B
QUADSPI_
BK1_IO0
EVEN
TOUT
-
-
-
-
-
-
-
-
UART7_RTS TIM13_CH1
UART7_CTS TIM14_CH1
O
SPI5_MO SAI1_FS_
QUADSPI_
BK1_IO1
EVEN
TOUT
SI
B
EVEN
TOUT
PF10
PF11
PF12
PF13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI5_MO
SI
FMC_SDN EVEN
-
-
-
-
-
SAI2_SD_B
RAS
TOUT
EVEN
TOUT
-
-
-
-
-
-
-
-
FMC_A6
EVEN
TOUT
FMC_A7
FMC_A8
FMC_A9
EVEN
TOUT
Port F PF14
PF15
EVEN
TOUT
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF15
SYS
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
CAN1/TIM1 SAI2/QUAD
SAI2/USART 2/13/14/QU SPI/SDMM
6/UART4/5/7/
8/OTG1_FS
SPI1/I2S1/
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
UART7/F
MC/SDM
MC1/
Port
TIM8/9/10/1 I2C1/2/3/U SPI2/I2S2/
1/LPTIM1
TIM1/2
TIM3/4/5
ADSPI/
FMC/
OTG2_HS
C2/OTG2_ SDMMC2
HS/OTG1_
FS
SART1
SPI3/I2S3/
SPI4/5
OTG2_FS
UART4
EVEN
TOUT
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A10
FMC_A11
FMC_A12
FMC_A13
EVEN
TOUT
-
EVEN
TOUT
-
EVEN
TOUT
-
FMC_A14/ EVEN
FMC_BA0 TOUT
-
FMC_A15/ EVEN
FMC_BA1 TOUT
-
Port G
EVEN
TOUT
-
-
EVEN
FMC_INT
USART6_CK
TOUT
USART6_RT
S
FMC_SDC EVEN
LK
TOUT
FMC_NE2
/FMC_NC
E
QUADSPI_
BK2_IO2
SDMMC2
_D0
EVEN
TOUT
PG9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART6_RX
-
SAI2_FS_B
SAI2_SD_B
SDMMC2
_D1
EVEN
TOUT
PG10
-
FMC_NE3
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF15
SYS
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
CAN1/TIM1 SAI2/QUAD
SAI2/USART 2/13/14/QU SPI/SDMM
6/UART4/5/7/
8/OTG1_FS
SPI1/I2S1/
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
UART7/F
MC/SDM
MC1/
Port
TIM8/9/10/1 I2C1/2/3/U SPI2/I2S2/
1/LPTIM1
TIM1/2
TIM3/4/5
ADSPI/
FMC/
OTG2_HS
C2/OTG2_ SDMMC2
HS/OTG1_
FS
SART1
SPI3/I2S3/
SPI4/5
OTG2_FS
UART4
SDMMC2_
EVEN
TOUT
PG11
-
-
-
-
-
-
-
-
-
-
-
-
-
D2
LPTIM1_IN
1
USART6_RT
S
SDMMC2
_D3
EVEN
TOUT
PG12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_NE4
FMC_A24
FMC_A25
Port G
LPTIM1_O
UT
USART6_CT
S
EVEN
TOUT
PG13 TRACED0
PG14 TRACED1
-
-
LPTIM1_ET
R
QUADSPI_
BK2_IO3
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART6_TX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART6_CT
S
FMC_SDN EVEN
PG15
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CAS
TOUT
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
-
-
LPTIM1_IN
2
QUADSPI_ SAI2_SCK_
BK2_IO0
FMC_SDC EVEN
KE0 TOUT
-
B
QUADSPI_ SAI2_MCK
FMC_SDN EVEN
-
-
-
-
-
-
BK2_IO1
_B
E0
TOUT
Port H
OTG_HS_U
LPI_NXT
EVEN
TOUT
I2C2_SCL
-
-
FMC_SDN EVEN
WE TOUT
I2C2_SDA SPI5_NSS
-
-
-
-
I2C2_SMB
SPI5_SCK
A
FMC_SDN EVEN
E1 TOUT
TIM12_CH1
-
SPI5_MIS
FMC_SDC EVEN
KE1 TOUT
I2C3_SCL
O
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF15
SYS
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
CAN1/TIM1 SAI2/QUAD
SAI2/USART 2/13/14/QU SPI/SDMM
6/UART4/5/7/
8/OTG1_FS
SPI1/I2S1/
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
UART7/F
MC/SDM
MC1/
Port
TIM8/9/10/1 I2C1/2/3/U SPI2/I2S2/
1/LPTIM1
TIM1/2
TIM3/4/5
ADSPI/
FMC/
OTG2_HS
C2/OTG2_ SDMMC2
HS/OTG1_
FS
SART1
SPI3/I2S3/
SPI4/5
OTG2_FS
UART4
EVEN
TOUT
PH8
PH9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C3_SDA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D16
FMC_D17
FMC_D18
FMC_D19
FMC_D20
FMC_D21
FMC_D22
FMC_D23
FMC_D24
FMC_D25
FMC_D26
I2C3_SMB
A
EVEN
TOUT
-
-
TIM12_CH2
EVEN
TOUT
PH10
PH11
PH12
PH13
PH14
PH15
PI0
TIM5_CH1
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
TIM5_CH2
-
-
Port H
EVEN
TOUT
TIM5_CH3
-
-
TIM8_CH1
N
EVEN
TOUT
-
UART4_TX
CAN1_TX
TIM8_CH2
N
EVEN
TOUT
-
UART4_RX
CAN1_RX
TIM8_CH3
N
EVEN
TOUT
-
-
-
-
-
-
-
-
-
SPI2_NSS
/I2S2_WS
EVEN
TOUT
TIM5_CH4
-
TIM8_BKIN
2
SPI2_SCK
/I2S2_CK
EVEN
TOUT
PI1
-
-
SPI2_MIS
O
EVEN
TOUT
PI2
TIM8_CH4
TIM8_ETR
SPI2_MO
SI/I2S2_S
D
EVEN
TOUT
Port I
PI3
-
-
-
-
-
-
-
-
-
-
FMC_D27
SAI2_MCK
_A
FMC_NBL EVEN
TOUT
PI4
PI5
PI6
-
-
-
-
-
-
-
-
-
TIM8_BKIN
TIM8_CH1
TIM8_CH2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
SAI2_SCK_
A
FMC_NBL EVEN
3
TOUT
EVEN
TOUT
SAI2_SD_A
FMC_D28
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF15
SYS
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
CAN1/TIM1 SAI2/QUAD
SAI2/USART 2/13/14/QU SPI/SDMM
6/UART4/5/7/
8/OTG1_FS
SPI1/I2S1/
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
UART7/F
MC/SDM
MC1/
Port
TIM8/9/10/1 I2C1/2/3/U SPI2/I2S2/
1/LPTIM1
TIM1/2
TIM3/4/5
ADSPI/
FMC/
OTG2_HS
C2/OTG2_ SDMMC2
HS/OTG1_
FS
SART1
SPI3/I2S3/
SPI4/5
OTG2_FS
UART4
EVEN
TOUT
PI7
PI8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_CH3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI2_FS_A
-
-
-
-
-
-
-
-
-
FMC_D29
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
PI9
UART4_RX
CAN1_RX
FMC_D30
EVEN
TOUT
PI10
PI11
PI12
PI13
PI14
PI15
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D31
OTG_HS_U
LPI_DIR
EVEN
TOUT
Port I
-
-
-
-
-
EVEN
TOUT
-
-
-
-
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
Memory mapping
STM32F722xx STM32F723xx
5
Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
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6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
A
DD
1.7 V ≤ V ≤ 3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 26.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 27.
Figure 26. Pin loading conditions
Figure 27. Pin input voltage
MCU pin
MCU pin
V
C =50 pF
IN
MS19011V2
MS19010V2
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6.1.6
Power supply scheme
Figure 28. STM32F722xx power supply scheme
V
BAT
Backup circuitry
(OSC32K,RTC,
Wakeup logic
Power switch
VBAT =
1.65 to 3.6V
Backup registers,
backup RAM)
OUT
IN
IO
Logic
GP I/Os
V
DDSDMMC
V
DDSDMMC
100 nF
+ 1 μF
OUT
IN
PG[9..12], PD[6,7]
IO
Logic
Kernel logic
(CPU,
V
CAP_1
digital
V
CAP_2
2 × 2.2 μF
& RAM)
V
DD
V
DD
Voltage
1/2/...11/12
regulator
12 × 100 nF
+ 1 × 4.7 μF
V
SS
1/2/...11/12
Flash memory
BYPASS_REG
V
DDUSB
V
DDUSB
OTG FS
PHY
100 nF
+ 1 μF
Reset
controller
PDR_ON
V
DD
V
DDA
V
REF
V
REF+
Analog:
RCs, PLL,
...
100 nF
+ 1 μF
100 nF
+ 1 μF
V
ADC
REF-
V
SSA
MSv42076V2
1. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the
voltage regulator is OFF.
2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
3. VDDA=VDD and VSSA=VSS
.
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Figure 29. STM32F723xx power supply scheme
V
BAT
Backup circuitry
Power switch
(OSC32K,RTC,
Wakeup logic
VBAT =
1.65 to 3.6V
Backup registers,
backup RAM)
OUT
IN
IO
Logic
GP I/Os
V
DDSDMMC
V
DDSDMMC
100 nF
+ 1 μF
OUT
IN
PG[9..12], PD[6,7]
IO
Logic
OUT
IN
PA[11,12], PB[14,15]
IO
Logic
V
DDUSB
V
DDUSB
100 nF
+ 1 μF
OTG FS
PHY
Kernel logic
(CPU,
digital
& RAM)
V
V
CAP_1
CAP_2
2 × 2.2 μF
V
DD
V
DD
1/2/...11/12
Voltage
regulator
12 × 100 nF
+ 1 × 4.7 μF
V
SS
1/2/...11/12
Flash memory
BYPASS_REG
OTG HS PHY
voltage
regulator
V
DD12OTGHS
OTG HS PHY
2.2 μF
OTG_HS_REXT
3 Kohm +/-1%
PDR_ON
Reset
controller
V
DD
V
DDA
V
REF
V
REF+
Analog:
RCs, PLL,
...
100 nF
+ 1 μF
100 nF
+ 1 μF
V
ADC
REF-
V
SSA
MSv42069V1
1. In all the packages (except LQFP100), the VDDUSB allows supplying the PHY FS in PA11/PA12 and the
PHY HS on PB14/PB15. In the LQFP100, the PHY HS on PB14/PB15 is supplied by VDDPHYHS
.
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2. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the
voltage regulator is OFF.
3. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
4. VDDA=VDD and VSSA=VSS
.
Caution:
Each power supply pair (V /V , V
/V
...) must be decoupled with filtering ceramic
DD SS
DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
6.1.7
Current consumption measurement
Figure 30. Current consumption measurement scheme
I
_V
DD BAT
V
BAT
I
DD
V
DD
V
DDA
ai14126
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 13: Voltage characteristics,
Table 14: Current characteristics, and Table 15: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. The device mission profile (application
conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission
profiles are available on demand.
Table 13. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage (including VDDA, VDD,
VDD–VSS
− 0.3
4.0
, V
(1)
VBAT, VDDUSB DDPHYHS and VDDSDMMC
)
Input voltage on FT pins(2)
Input voltage on TTa pins
Input voltage on any other pin
Input voltage on BOOT pin
VSS − 0.3 VDD+4.0
V
VSS − 0.3
VSS − 0.3
VSS
4.0
4.0
9.0
VIN
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Symbol
Electrical characteristics
Table 13. Voltage characteristics (continued)
Ratings
Min
Max
Unit
|ΔVDDx
|
Variations between different VDD power pins
-
-
50
50
mV
|VSSX −VSS
|
Variations between all the different ground pins(3)
see Section 6.3.18:
Absolute maximum
ratings (electrical
sensitivity)
VESD(HBM)
Electrostatic discharge voltage (human body model)
-
1. All main power (VDD, VDDA, VDDSDMMC, VDDPHYHS, VDDUSB) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Table 14 for the values of the maximum allowed
injected current.
3. Include VREF- pin.
Table 14. Current characteristics
Symbol
Ratings
Max.
Unit
ΣIVDD
Σ IVSS
Total current into sum of all VDD_x power lines (source)(1)
Total current out of sum of all VSS_x ground lines (sink)(1)
Total current into VDDUSB power line (source)
300
− 300
25
Σ IVDDUSB
Σ IVDDSDMMC Total current into VDDSDMMC power line (source)
60
IVDD
IVDDSDMMC
IVSS
Maximum current into each VDD_x power line (source)(1)
Maximum current into VDDSDMMC power line (source): PG[12:9], PD[7:6]
Maximum current out of each VSS_x ground line (sink)(1)
Output current sunk by any I/O and control pin
100
100
− 100
25
mA
IIO
Output current sourced by any I/Os and control pin
Total output current sunk by sum of all I/O and control pins (2)
Total output current sunk by sum of all USB I/Os
− 25
120
25
ΣIIO
Total output current sourced by sum of all I/Os and control pins(2)
Injected current on FT, FTf, RST and B pins (3)
− 120
− 5/+0
±5
IINJ(PIN)
Injected current on TTa pins(4)
(4)
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(5)
±25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer to Table 13: Voltage characteristics for the values of the maximum allowed input voltage.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
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Symbol
STM32F722xx STM32F723xx
Table 15. Thermal characteristics
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
− 65 to +150
°C
Maximum junction temperature
125
6.3
Operating conditions
6.3.1
General operating conditions
Table 16. General operating conditions
Symbol
Parameter
Conditions(1)
Min Typ
Max Unit
Power Scale 3 (VOS[1:0] bits in
PWR_CR register = 0x01), Regulator
ON, over-drive OFF
0
-
-
-
-
-
144
Over-
drive
OFF
168
Power Scale 2 (VOS[1:0] bits
in PWR_CR register = 0x10),
Regulator ON
0
Over-
drive
ON
fHCLK
Internal AHB clock frequency
180
Over-
drive
OFF
MH
z
180
Power Scale 1 (VOS[1:0] bits
in PWR_CR register= 0x11),
Regulator ON
0
Over-
drive
ON
216(2)
Over-drive OFF
Over-drive ON
Over-drive OFF
Over-drive ON
0
0
0
0
-
-
-
-
45
54
fPCLK1
Internal APB1 clock frequency
Internal APB2 clock frequency
90
fPCLK2
108
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Electrical characteristics
Table 16. General operating conditions (continued)
Symbol
Parameter
Conditions(1)
Min Typ
Max Unit
VDD
Standard operating voltage
-
1.7(3)
1.7(3)
-
-
3.6
Analog operating voltage
2.4
(ADC limited to 1.2 M samples)
(4)(5)
(6)
VDDA
Must be the same potential as VDD
Analog operating voltage
2.4
-
3.6
3.6
(ADC limited to 2.4 M samples)
USB supply voltage (supply
USB not used
USB used
1.7
3.0
3.3
VDDUSB voltage for PA11,PA12, PB14 and
PB15 pins)
-
3.3
-
3.6
3.6
3.6
3.6
V
USB PHY HS supply voltage in
VDDSPHYHS the STM32F723 LQFP100 (supply
voltage for PB14 and PB15)
USB PHY HS not used
USB PHY HS used
-
1.7
3.0
VBAT
Backup operating voltage
1.65
-
SDMMC2 supply voltage (supply
VDDSDMMC voltage for PG[12:9] and PD6
pins)
It can be different from VDD
1.7
-
3.6
Power Scale 3 ((VOS[1:0] bits in
PWR_CR register = 0x01), 144 MHz 1.08 1.14 1.20
HCLK max frequency
Power Scale 2 ((VOS[1:0] bits in
PWR_CR register = 0x10), 168 MHz
HCLK max frequency with over-drive
OFF or 180 MHz with over-drive ON
Regulator ON: 1.2 V internal
voltage on VCAP_1/VCAP_2 pins
1.20 1.26 1.32
V12
Power Scale 1 ((VOS[1:0] bits in
PWR_CR register = 0x11), 180 MHz
1.26 1.32 1.40
HCLK max frequency with over-drive
OFF or 216 MHz with over-drive ON
V
Max frequency 144 MHz
Max frequency 168MHz
Max frequency 180 MHz
2 V ≤ VDD ≤ 3.6 V
1.10 1.14 1.20
1.20 1.26 1.32
1.26 1.32 1.38
Regulator OFF: 1.2 V external
voltage must be supplied from
external regulator on
VCAP_1/VCAP_2 pins(7)
− 0.3
− 0.3
-
-
5.5
5.2
Input voltage on RST and FT
pins(8)
VDD ≤ 2 V
VIN
VDDA
0.3
+
Input voltage on TTa pins
-
-
− 0.3
-
-
Input voltage on BOOT pin
0
9
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STM32F722xx STM32F723xx
Table 16. General operating conditions (continued)
Symbol
Parameter
Conditions(1)
Min Typ
Max Unit
LQFP64
-
-
-
-
-
-
-
-
-
-
-
-
-
-
881
LQFP100
WLCSP100
LQFP144
LQFP176
UFBGA144
UFBGA176
-
-
1117
558
Power dissipation at TA = 85 °C for
suffix 6 or TA = 105 °C for suffix
7(9)
PD
-
1587 mW
1869
476
-
-
-
485
Maximum power dissipation
Low power dissipation(10)
Maximum power dissipation
Low power dissipation(10)
6 suffix version
− 40
− 40
− 40
− 40
− 40
− 40
85
°C
105
Ambient temperature for 6 suffix
version
TA
TJ
105
°C
125
Ambient temperature for 7 suffix
version
105
°C
125
Junction temperature range
7 suffix version
1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.
2. 216 MHz maximum frequency for 6 suffix version (200 MHz maximum frequency for 7 suffix version).
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:
Internal reset OFF).
4. When the ADC is used, refer to Table 67: ADC characteristics.
5. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
6. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA
can be tolerated during power-up and power-down operation.
7. The over-drive mode is not supported when the internal regulator is OFF.
8. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
9. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax
.
10. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax
.
Table 17. Limitations depending on the operating power supply range
Maximum Flash
Maximum HCLK
memory access
frequency vs Flash
Operating
Possible Flash
memory
operations
powersupply ADC operation frequency with
I/O operation
memory wait states
range
no wait states
(1)(2)
(fFlashmax
)
180 MHz with 8 wait
states and over-drive
OFF
8-bit erase and
program
operations only
VDD =1.7 to Conversion time
No I/O
compensation
20 MHz
2.1 V(3)
up to 1.2 Msps
216 MHz with 9 wait
states and over-drive
ON
16-bit erase and
program
operations
VDD = 2.1 to Conversion time
2.4 V up to 1.2 Msps
No I/O
compensation
22 MHz
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Electrical characteristics
Table 17. Limitations depending on the operating power supply range (continued)
Maximum Flash
memory access
powersupply ADC operation frequency with
Maximum HCLK
frequency vs Flash
Operating
Possible Flash
memory
operations
I/O operation
memory wait states
range
no wait states
(1)(2)
(fFlashmax
)
216 MHz with 8 wait
states and over-drive
ON
16-bit erase and
program
operations
VDD = 2.4 to Conversion time
I/O compensation
works
24 MHz
2.7 V
up to 2.4 Msps
216 MHz with 7 wait
states and over-drive
ON
32-bit erase and
program
operations
VDD = 2.7 to Conversion time
3.6 V(4)
up to 2.4 Msps
I/O compensation
works
30 MHz
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states given here
does not impact the execution speed from Flash memory since the ART accelerator or L1-cache allows to achieve a
performance equivalent to 0-wait state program execution.
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:
Internal reset OFF).
4. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+
pins will be degraded between 2.7 and 3 V.
6.3.2
VCAP1/VCAP2 external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor C
to
EXT
the VCAP1/VCAP2 pins. C
is specified in Table 18.
EXT
Note:
The VCAP2 pin is not available on the LQFP64 package.
Figure 31. External capacitor C
EXT
C
ESR
R Leak
MS19044V2
1. Legend: ESR is the equivalent series resistance.
(1)
Table 18. VCAP1/VCAP2 operating conditions
Symbol
Parameter
Conditions
CEXT
ESR
Capacitance of external capacitor
ESR of external capacitor
2.2 µF
< 2 Ω
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
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STM32F722xx STM32F723xx
(1)
Table 19. VCAP1 operating conditions in the LQFP64 package
Symbol
Parameter
Conditions
CEXT
ESR
Capacitance of external capacitor
ESR of external capacitor
4.7 µF
between 0.1 Ω and 0.2 Ω
1. When bypassing the voltage regulator, the 4.7 µF VCAP capacitor is not required and should be replaced
by two 100 nF decoupling capacitors.
6.3.3
Operating conditions at power-up / power-down (regulator ON)
Subject to general operating conditions for T .
A
Table 20. Operating conditions at power-up / power-down (regulator ON)
Symbol
Parameter
VDD rise time rate
VDD fall time rate
Min
Max
Unit
20
20
∞
∞
tVDD
µs/V
6.3.4
Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for T .
A
(1)
Table 21. Operating conditions at power-up / power-down (regulator OFF)
Symbol
Parameter
VDD rise time rate
DD fall time rate
Conditions
Power-up
Power-down
Min
Max
Unit
20
20
20
20
∞
∞
∞
∞
tVDD
V
µs/V
VCAP_1 and VCAP_2 rise time rate Power-up
VCAP_1 and VCAP_2 fall time rate Power-down
tVCAP
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
1.08 V.
6.3.5
Reset and power control block characteristics
The parameters given in Table 22 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 16.
DD
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Electrical characteristics
Table 22. reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
PLS[2:0]=000 (rising edge)
PLS[2:0]=000 (falling edge)
PLS[2:0]=001 (rising edge)
PLS[2:0]=001 (falling edge)
PLS[2:0]=010 (rising edge)
PLS[2:0]=010 (falling edge)
PLS[2:0]=011 (rising edge)
PLS[2:0]=011 (falling edge)
PLS[2:0]=100 (rising edge)
PLS[2:0]=100 (falling edge)
PLS[2:0]=101 (rising edge)
PLS[2:0]=101 (falling edge)
PLS[2:0]=110 (rising edge)
PLS[2:0]=110 (falling edge)
PLS[2:0]=111 (rising edge)
PLS[2:0]=111 (falling edge)
-
2.09
1.98
2.23
2.13
2.39
2.29
2.54
2.44
2.70
2.59
2.86
2.65
2.96
2.85
3.07
2.95
-
2.14 2.19
2.04 2.08
2.30 2.37
2.19 2.25
2.45 2.51
2.35 2.39
2.60 2.65
2.51 2.56
2.76 2.82
2.66 2.71
2.93 2.99
2.84 2.92
3.03 3.10
2.93 2.99
3.14 3.21
3.03 3.09
V
V
V
V
V
V
V
V
Programmable voltage
detector level selection
VPVD
V
V
V
V
V
V
V
V
(1)
VPVDhyst
PVD hysteresis
100
-
mV
V
Falling edge
1.60
1.64
-
1.68 1.76
1.72 1.80
Power-on/power-down
reset threshold
VPOR/PDR
Rising edge
V
(1)
VPDRhyst
PDR hysteresis
-
40
-
mV
V
Falling edge
2.13
2.23
2.44
2.53
2.75
2.85
-
2.19 2.24
2.29 2.33
2.50 2.56
2.59 2.63
2.83 2.88
2.92 2.97
Brownout level 1
threshold
VBOR1
VBOR2
VBOR3
Rising edge
V
Falling edge
V
Brownout level 2
threshold
Rising edge
V
Falling edge
V
Brownout level 3
threshold
Rising edge
V
(1)
VBORhyst
BOR hysteresis
-
100
1.5
-
mV
TRSTTEMPO
POR reset temporization
-
0.5
3.0
ms
(1)(2)
InRush current on
voltage regulator power-
on (POR or wakeup
from Standby)
(1)
IRUSH
-
-
160
-
250
5.4
mA
InRush energy on
voltage regulator power-
on (POR or wakeup
from Standby)
VDD = 1.7 V, TA = 105 °C,
IRUSH = 171 mA for 31 µs
(1)
ERUSH
-
µC
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STM32F722xx STM32F723xx
1. Guaranteed by design.
2. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant
when first instruction is read by the user application code.
6.3.6
6.3.7
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Over-drive switching characteristics
When the over-drive mode switches from enabled to disabled or disabled to enabled, the
system clock is stalled during the internal voltage set-up.
The over-drive switching characteristics are given in Table 23. They are sbject to general
operating conditions for T .
A
(1)
Table 23. Over-drive switching characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
HSI
-
45
-
HSE max for 4 MHz
and min for 26 MHz
Over_drive switch
enable time
45
-
100
Tod_swen
External HSE
50 MHz
-
-
40
20
-
-
-
µs
HSI
HSE max for 4 MHz
and min for 26 MHz.
Over_drive switch
disable time
20
80
Tod_swdis
External HSE
50 MHz
-
15
-
1. Guaranteed by design.
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 30: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark code.
DS11853 Rev 6
STM32F722xx STM32F723xx
Electrical characteristics
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in input mode with a static value at V or V (no load).
DD SS
All peripherals are disabled except if it is explicitly mentioned.
The Flash memory access time is adjusted both to f frequency and V range
HCLK
DD
(see Table 17: Limitations depending on the operating power supply range).
•
When the regulator is ON, the voltage scaling and over-drive mode are adjusted to
f
frequency as follows:
HCLK
–
–
–
Scale 3 for f
≤ 144 MHz
HCLK
Scale 2 for 144 MHz < f
Scale 1 for 168 MHz < f
≤ 168 MHz
HCLK
≤ 216 MHz. The over-drive is only ON at 216 MHz.
HCLK
•
When the regulator is OFF, the V12 is provided externally as described in Table 16:
General operating conditions:
•
•
•
The system clock is HCLK, f
= f
/4, and f
= f
/2.
PCLK1
HCLK
PCLK2
HCLK
External clock frequency is 25 MHz and PLL is ON when f
is higher than 25 MHz.
HCLK
The typical current consumption values are obtained for 1.7 V ≤ V ≤ 3.6 V voltage
DD
range and for T = 25 °C unless otherwise specified.
A
•
•
The maximum values are obtained for 1.7 V ≤ V ≤ 3.6 V voltage range and a
DD
maximum ambient temperature (T ) unless otherwise specified.
A
For the voltage range 1.7 V ≤ V ≤ 3.6 V, the maximum frequency is 180 MHz.
DD
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM RAM, regulator ON
Max(1)
Symbol Parameter
Conditions
fHCLK (MHz)
Typ
Unit
TA = 25 °C TA = 85 °C TA = 105 °C
216
200
180
168
144
60
156
144
127
113
86
170(4)
154
134(4)
119
96
180(4)
164.6
143(4)
127.4
112.6
52.8
200
183
158(4)
All peripherals
enabled(2)(3)
141
126
41
44
65
Supply cur-
rent in RUN
mode
25
22
24
33.5
45
IDD
mA
216
200
180
168
144
60
99
110(4)
102
90(4)
78
119.6(4)
113.1
96.7(4)
86.5
138.5
92
132
81
125(4)
100.1
90.8
50.3
38.1
All peripherals
disabled(3)
72
55
61
77.1
24
25
38.5
25
12
13
26.3
1. Guaranteed by characterization results.
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STM32F722xx STM32F723xx
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
4. Guaranteed by test in production.
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator ON
Max(1)
Symbol Parameter
Conditions
fHCLK (MHz)
Typ
Unit
TA = 25 °C TA = 85 °C TA = 105 °C
216
200
180
168
144
60
155.3
144.7
127.3
113.1
86.9
41.2
21.7
90
164
153.6
135
119.1
91.6
43.6
24
175.8
165.2
143.5
127.8
99.5
53.1
33.6
120.4
113.8
97.3
87
185
176
154
138
110
64
All peripherals
enabled(2)(3)
Supply cur-
25
43.8
130
124
107
97
IDD
rent in RUN
mode
mA
216
200
180
168
144
60
106
99
84
74
86.6
76
All peripherals
disabled(3)
66
51
59
68.2
38.8
26.4
78
23
27
49
25
11
13.6
36.8
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
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Table 26. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory or SRAM on AXI (L1-cache disabled), regulator ON
Max(1)
Symbol Parameter
Conditions
fHCLK (MHz)
Typ
Unit
TA= 25 °C TA=85 °C TA=105 °C
216
200
180
168
144
60
129.3
122
108
99
137.6
128
117
104.5
84.7
45
162.8
153.2
136.4
122.3
99.3
173
163.3
146
132
109.2
70
All peripherals
enabled(2)(3)
80
42
59.5
Supply cur-
rent in RUN
mode
25
23
23.4
82.3
77
37.8
48
IDD
mA
216
200
180
168
144
60
73.3
70
107.4
101.8
90.2
119
113.5
101
92.1
79
62
71
All peripherals
disabled(3)
59
63.6
53.3
31
81.4
49
67.9
26
45.1
56
25
14
16
30.6
41.2
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
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STM32F722xx STM32F723xx
Table 27. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory on ITCM interface (ART disabled), regulator ON
Max(1)
Symbol Parameter
Conditions
fHCLK (MHz)
Typ
Unit
TA= 25 °C TA=85 °C TA=105 °C
216
200
180
168
144
60
138
133
110
99
151
141
131
117
98
174.7
164.3
149.2
134
184
174
159
144
121
75
All peripherals
enabled(2)(3)
79
111.7
64
49
53
Supply cur-
rent in
RUN mode
25
27
30
38.3
119.5
113.1
103.1
93.2
80.4
49.7
31.1
48
IDD
mA
216
200
180
168
144
60
82
96
131
124
114
104
91
81
89
65
85
All peripherals
disabled(3)
58
76
48
67
33
36
60
25
18
21
41
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
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Table 28. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator OFF
Max(1)
TA= 85 °C
IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD
Typ
Unit
fHCLK
(MHz)
Symbol Parameter Conditions
TA= 25 °C
TA= 105 °C
180
168
144
60
112
110
78
37
19
74
64
51
22
10
1.4
1.4
1.3
1.1
1.1
1.4
1.4
1.3
1.1
1.2
120
106.4
82.5
37.6
18.5
78
2
2
2
2
2
2
2
2
2
2
132.7
118.7
93.6
49.3
30.4
89.3
80.1
63.5
35.2
23.2
2
2
2
2
2
2
2
2
2
2
142
130
103
60
2
2
2
2
2
2
2
2
2
2
All Peripher-
als
Enabled(2)(3)
Supply cur-
rent in RUN
25
40
IDD12/
mode from
IDD
mA
180
168
144
60
99
V12 and
VDD supply
All Peripher-
68
90
als Dis-
54
74
abled(3)
24
45
25
12
35
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
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STM32F722xx STM32F723xx
Table 29. Typical and maximum current consumption in Sleep mode, regulator ON
Max(1)
Symbol Parameter
Conditions
fHCLK (MHz)
Typ
Unit
TA= 25 °C TA=85 °C TA=105 °C
216
200
180
168
144
60
82
77
67
60
46
24
14
24
22
19
17
13
7
96(3)
109.3(3)
103.4
88.3(3)
78.9
128.3
122.6
120(3)
92.7
73.6
49
84
72(3)
64
All peripherals
enabled(2)
49
61.8
26
37.2
Supply cur-
rent in
SLEEP
25
16
27
38.8
62.2
61.2
48(3)
43.9
36.3
32.3
30.6
IDD
mA
216
200
180
168
144
60
28(3)
42.9(3)
mode
26
41.9
21(3)
19
33.2(3)
30.1
All peripherals
disabled
15
24.6
9
20.5
25
5
7
18.8
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. Guaranteed by test in production.
Table 30. Typical and maximum current consumption in Sleep mode, regulator OFF
Max(1)
Typ
Unit
fHCLK
(MHz)
Symbol Parameter Conditions
TA= 25 °C
TA= 85 °C
TA= 105 °C
IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD
180
168
144
60
62
55
43
22
13
17
15
12
5
1.3
1.3
1.3
1
67.5
59.8
46.3
24
2
2
2
2
2
2
2
2
2
2
84.4
75.4
59.6
35.8
25.8
31.4
28.4
23.2
19.3
17.6
2
2
2
2
2
2
2
2
2
2
95
86
70
46
36
42
40
33
29
28
2
2
2
2
2
2
2
2
2
2
All Periph-
erals
Enabled(2)
Supply cur-
rent in RUN
25
1
15
IDD12/
mode from
IDD
mA
180
168
144
60
1.3
1.3
1.2
1
19
V12 and VDD
supply
17
All Periph-
erals Dis-
abled
14
6
25
3
1
4
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Electrical characteristics
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
Table 31. Typical and maximum current consumptions in Stop mode
Max(1)
Typ
VDD = 3.6 V
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA =
TA =
25 °C
25 °C 85 °C 105 °C
Flash memory in Stop mode,
all oscillators OFF, no IWDG
0.45
0.4
2
2
12
12
10
22
22
18
Supply current in Stop
mode, main regulator in
Run mode
Flash memory in Deep power
down mode, all oscillators OFF
IDD_STOP_NM
(normal mode)
Flash memory in Stop mode, all
oscillators OFF, no IWDG
0.32
1.5
Supply current in Stop
mode, main regulator in
Low-power mode
Flash memory in Deep power
down mode, all oscillators OFF, no
IWDG
0.27
0.15
1.5
0.8
10
5
18
7
mA
Regulator in Run mode, Flash
memory in Deep power down
mode, all oscillators OFF, no
IWDG
Supply current in Stop
mode, main regulator in
Low voltage and under-
drive modes
IDD_STOP_UDM
(under-drive
mode)
Regulator in Low-power mode,
Flash memory in Deep power
down mode, all oscillators OFF, no
IWDG
0.1
0.7
4
7
1. Data based on characterization, tested in production.
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STM32F722xx STM32F723xx
Table 32. Typical and maximum current consumptions in Standby mode
Typ(1)
Max(2)
TA =
TA =
TA =
TA = 25 °C
Symbol
Parameter
Conditions
25 °C 85 °C 105 °C Unit
VDD
= VDD= VDD =
VDD = 3.3 V
1.7 V 2.4 V 3.3 V
Backup SRAM OFF, RTC and
LSE OFF
1.09
1.85
1.65
1.13
1.88
1.86
1.4
4
5
7
27
30
47
55
60
Backup SRAM ON, RTC and
LSE OFF
2.17
2.43
Backup SRAM OFF, RTC ON
and LSE in low drive mode
95.5
Backup SRAM OFF, RTC ON
and LSE in medium low drive 1.67
mode
1.88
2.01
2.46
2.61
7
47.5
50.5
97
Backup SRAM OFF, RTC ON
and LSE in medium high drive 1.8
mode
7.5
102.5
Supply current
in Standby
mode
IDD_STBY
µA
Backup SRAM OFF, RTC ON
1.92
2.13
2.6
2.73
3.23
8
9
53
62
107
127
and LSE in high drive mode
Backup SRAM ON, RTC ON
2.39
and LSE in low drive mode
Backup SRAM ON, RTC ON
and LSE in Medium low drive 2.41
mode
2.64
3.25
9
63
128
Backup SRAM ON, RTC ON
and LSE in Medium high drive 2.67
mode
2.89
2.9
2.53
3.51
10
10
68
68
139
138
Backup SRAM ON, RTC ON
2.68
and LSE in High drive mode
1. PDR is OFF for VDD=1.7V. When the PDR is OFF (internal reset OFF), the typical current consumption is reduced by
additional 1.2 µA.
2. Guaranteed by characterization results.
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Electrical characteristics
Table 33. Typical and maximum current consumptions in V
mode
Max(2)
BAT
Typ
TA =25 °C
TA =85 °C TA =105 °C
Symbol Parameter
Conditions(1)
Unit
VBAT = VBAT
1.7 V 2.4 V 3.3 V
= VBAT=
VBAT = 3.6 V
Backup SRAM OFF, RTC and
LSE OFF
0.035 0.037 0.043
4
9
10
Backup SRAM ON, RTC and
LSE OFF
0.69
0.57
0.71
0.74
0.73
1.05
20
Backup SRAM OFF, RTC ON
and LSE in low drive mode
98
244
Backup SRAM OFF, RTC ON
and LSE in medium low drive
mode
0.59
0.69
0.76
0.86
1.08
1.19
101
111
251
277
Backup SRAM OFF, RTC ON
and LSE in medium high drive
mode
Supplycurrent
I
µA
DD_VBAT in VBAT mode
Backup SRAM OFF, RTC ON
and LSE in high drive mode
0.8
0.98
1.41
1.43
1.65
1.65
1.31
1.74
1.78
2.01
2.01
122
162
166
187
187
305
405
414
468
468
Backup SRAM ON, RTC ON and
LSE in low drive mode
1.22
1.25
1.46
1.46
Backup SRAM ON, RTC ON and
LSE in Medium low drive mode
Backup SRAM ON, RTC ON and
LSE in Medium high drive mode
Backup SRAM ON, RTC ON and
LSE in High drive mode
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Guaranteed by characterization results.
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STM32F722xx STM32F723xx
Figure 32. Typical V
current consumption (RTC ON/BKP SRAM OFF and
BAT
LSE in low drive mode)
4
3.5
3
1.65 V
1.7 V
1.8 V
2 V
2.5
2
2.4 V
2.7 V
3 V
1.5
1
3.3 V
3.6 V
0.5
0
0
20
40
60
80
100
120
Temperature °C
MS37585V1
Figure 33. Typical V
current consumption (RTC ON/BKP SRAM OFF and
BAT
LSE in medium low drive mode)
4.5
4
3.5
3
1.65 V
1.7 V
1.8 V
2 V
2.5
2
2.4 V
2.7 V
3 V
1.5
1
3.3 V
3.6 V
0.5
0
0
20
40
60
80
100
120
MS37586V1
Temperature °C
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Figure 34. Typical V
Electrical characteristics
current consumption (RTC ON/BKP SRAM OFF and
BAT
LSE in medium high drive mode)
4.5
4
3.5
3
1.65 V
1.7 V
1.8 V
2 V
2.5
2
2.4 V
2.7 V
3 V
1.5
1
3.3 V
3.6 V
0.5
0
0
20
40
60
80
100
120
Temperature °C
MS37587V1
Figure 35. Typical V
current consumption (RTC ON/BKP SRAM OFF and
LSE in high drive mode)
BAT
4.5
4
3.5
3
1.65 V
1.7 V
1.8 V
2 V
2.5
2
2.4 V
2.7 V
3 V
1.5
1
3.3 V
3.6 V
0.5
0
0
20
40
60
80
100
120
Temperature °C
MS37588V1
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STM32F722xx STM32F723xx
Figure 36. Typical V
current consumption (RTC ON/BKP SRAM OFF and
BAT
LSE in high medium drive mode)
9
8
7
6
5
4
3
2
1
0
1.65 V
1.7 V
1.8 V
2 V
2.4 V
2.7 V
3 V
3.3 V
3.6 V
0
20
40
60
80
100
120
Temperature( °C)
MS37589V1
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 61: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 35: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
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pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
ISW = VDD × fSW × C
Where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
is the MCU supply voltage
SW
V
DD
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
INT
EXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
(1)
Table 34. Switching output I/O current consumption
I/O toggling
Typ
Typ
Symbol
Parameter
Conditions
Unit
frequency (fsw)
MHz
V
DD = 3.3 V VDD = 1.8 V
2
8
0.1
0.4
0.1
0.2
0.7
1.3
1.6
2.4
2.6
2.8
-
25
50
60
84
90
100
108
2
1.1
2.4
CEXT = 0 pF
3.1
C = CINT + CS + CEXT
4.3
4.9
5.4
5.6
I/O switching
Current
IDDIO
mA
0.2
0.1
0.3
1.1
2.3
3.4
3.6
5.2
5.4
-
8
0.6
25
50
60
84
90
100
108
1.8
3.1
CEXT = 10 pF
C = CINT + CS + CEXT
4.6
9.7
10.12
14.92
18.11
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Electrical characteristics
STM32F722xx STM32F723xx
(1)
Table 34. Switching output I/O current consumption (continued)
I/O toggling
Typ
Typ
Symbol
Parameter
Conditions
Unit
frequency (fsw)
MHz
VDD = 3.3 V VDD = 1.8 V
2
0.3
1.0
0.1
0.5
1.6
4.2
4.4
5.8
-
8
25
50
60
84
90
2
3.5
CEXT = 22 pF
5.9
C = CINT + CS + CEXT
10.0
19.12
19.6
0.3
I/O switching
Current
IDDIO
mA
0.2
0.7
2.3
5.19
-
8
1.3
CEXT = 33 pF
25
50
60
3.5
C = CINT + CS + CEXT
10.26
16.53
1. CINT + CS, PCB board capacitance including the pad pin is estimated to15 pF.
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
•
•
•
•
•
At startup, all I/O pins are in analog input configuration.
All peripherals are disabled unless otherwise mentioned.
I/O compensation cell enabled.
The ART/L1-cache is ON.
Scale 1 mode selected, internal digital voltage V12 = 1.32 V.
HCLK is the system clock. f = f /4, and f = f /2.
HCLK
PCLK1
HCLK
PCLK2
The given value is calculated by measuring the difference of current consumption
–
–
–
with all peripherals clocked off
with only one peripheral clocked on
f
f
= 216 MHz (Scale 1 + over-drive ON), f
= 144 MHz (Scale 3)
= 168 MHz (Scale 2),
HCLK
HCLK
HCLK
•
Ambient operating temperature is 25 °C and V =3.3 V.
DD
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Electrical characteristics
Table 35. Peripheral current consumption
I
DD(Typ)(1)
Peripheral
Unit
Scale 1
Scale 2
Scale 3
GPIOA
3.6
3.4
3.6
3.4
3.6
3.4
3.4
3.3
3.4
3.3
1.1
0.7
2.9
3.1
3.0
3.0
2.9
2.9
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
3.7
3.7
3.7
3.6
3.5
AHB1
GPIOG
GPIOH
GPIOI
3.5
2.8
µA/MHz
2.9
(up to
216 MHz)
3.5
3.5
1.2
2.9
CRC
0.9
0.6
BKPSRAM
DMA1
0.8
3.07 x N + 8.7
2.98 x N + 8.4
2.52 x N + 7.02
DMA2
3.01 x N + 7.98 2.95 x N + 7.95 2.48 x N + 6.69
OTG_HS+ULPI
RNG
54.4
1.9
53.2
1.8
44.6
1.6
AHB2
(up to
216 MHz)
USB_OTG_FS
28.7
27.9
23.5
µA/MHz
16.2
15.8
13.3
FMC
QSPI
AHB3
µA/MHz
µA/MHz
(up to
216 MHz)
16.9
16.3
13.8
Bus matrix(2)
15.8
12.8
8.5
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Electrical characteristics
STM32F722xx STM32F723xx
Table 35. Peripheral current consumption (continued)
I
DD(Typ)(1)
Peripheral
Unit
Scale 1
Scale 2
Scale 3
TIM2
19.3
15
18.2
14
15.6
12.2
12.8
14.4
2.8
TIM3
TIM4
15.7
18
15.1
16.9
3.1
2.9
7.8
5.1
5.6
9.8
1.3
6
TIM5
TIM6
3.7
TIM7
3.5
2.5
TIM12
TIM13
TIM14
LPTIM1
WWDG
SPI2/I2S2(3)
SPI3/I2S3(3)
USART2
USART3
UART4
UART5
I2C1
8.1
6.4
6.1
4.7
6.3
4.7
9.4
8.3
2.4
1.4
6.7
5.3
APB1
4.8
3.8
12
3.3
10.6
10.3
9.2
µA/MHz
(up to
54 MHz)
13.3
12.8
11.7
11.7
10.6
10.6
10.7
8.9
12
10.7
10.2
9.6
9.6
9.8
8
8.9
8.3
I2C2
8.3
I2C3
8.3
CAN1
6.9
PWR
11.3
6.1
11.3
5.1
12
8.9
DAC(4)
UART7
UART8
4.4
13.3
12.6
10.3
9.7
11.6
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Electrical characteristics
Table 35. Peripheral current consumption (continued)
I
DD(Typ)(1)
Peripheral
Unit
Scale 1
Scale 2
Scale 3
TIM1
24.9
24.5
12.4
12.3
6.3
6.3
6.4
9.1
7
23.8
23.7
11.6
11.7
5.8
5.6
5.8
8.3
7.2
3.2
2.9
1
20
20
10
10
4.9
4.9
5
TIM8
USART1
USART6
ADC1(5)
ADC2(5)
ADC3(5)
SDMMC1
SDMMC2
SPI1/I2S1(3)
SPI4
7.1
6
APB2
3.2
2.9
1
2.6
µA/MHz
(up to
2.2
0.7
7.8
5.6
5.7
3.6
4.2
4
108 MHz)
SYSCFG
TIM9
9.9
7
9.1
6.4
6.8
4.1
4.9
4.7
TIM10
TIM11
7.2
4.8
5.6
5.4
SPI5
SAI1
SAI2
USB PHY HS
Controller
8.3
7.9
6.7
1. When the I/O compensation cell is ON, IDD typical value increases by 0.22 mA.
2. The BusMatrix is automatically active when at least one master is ON.
3. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.
4. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of
0.75 mA per DAC channel for the analog part.
5. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of
1.73 mA per ADC for the analog part.
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Electrical characteristics
STM32F722xx STM32F723xx
USB OTG HS and USB OTG HS PHY current consumption (on STM32F723xx
devices)
The MCU is placed under the following conditions:
•
•
STM32 MCU is enumerated as a HID device.
f
f
= 216 MHz (Scale 1 + over-drive ON), f
= 144 MHz (Scale 3)
= 168 MHz (Scale 2),
HCLK
HCLK
HCLK
The given value is calculated by measuring the difference of current consumption in
case:
–
–
USB is configured but no transfer is done.
USB is configured and there is a transmission on going.
•
Ambient operating temperature is 25 °C, V = V
= 3.3 V.
DDUSB
DD
Table 36. USB OTG HS and USB OTG PHY HS current consumption
IDD (Typ)
-
Unit
Scale 1
Scale 2
Scale 3
USB OTG HS and USB OTG HS PHY
current consumption
50.16
44.92
38.98
mA
6.3.8
Wakeup time from low-power modes
The wakeup times given in Table 37 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•
•
For Stop or Sleep modes: the wakeup event is WFE.
WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and V =3.3 V.
DD
Table 37. Low-power mode wakeup timings
Typ(1)
Max(1)
Symbol
Parameter
Conditions
Unit
CPU
clock
cycles
(2)
tWUSLEEP
Wakeup from Sleep
-
13
14
13
Main regulator is ON
14.9
Main regulator is ON and Flash
memory in Deep power down mode
104.1
107.6
Wakeup from Stop mode
with MR/LP regulator in
normal mode
(2)
tWUSTOP
µs
Low power regulator is ON
21.4
24.2
Low power regulator is ON and Flash
memory in Deep power down mode
111.5
116.5
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Electrical characteristics
Table 37. Low-power mode wakeup timings (continued)
Typ(1)
Max(1)
Symbol
Parameter
Conditions
Unit
Main regulator in under-drive mode
(Flash memory in Deep power-down
mode)
107.4
113.2
Wakeup from Stop mode
with MR/LP regulator in
Under-drive mode
(2)
µs
tWUSTOP
Low power regulator in under-drive
mode
112.7
120
(Flash memory in Deep power-down
mode)
Exit Standby mode on rising edge
Exit Standby mode on falling edge
308
307
313
313
Wakeup from Standby
mode
tWUSTDBY(2)
µs
1. Guaranteed by characterization results.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
6.3.9
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 61: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 37.
The characteristics given in Table 38 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 16.
Table 38. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
External user clock source
frequency(1)
fHSE_ext
1
-
50
MHz
VHSEH
VHSEL
tw(HSE)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
0.7VDD
VSS
-
-
VDD
V
0.3VDD
-
OSC_IN high or low time(1)
OSC_IN rise or fall time(1)
5
-
-
-
-
tw(HSE)
ns
tr(HSE)
tf(HSE)
10
Cin(HSE) OSC_IN input capacitance(1)
-
-
45
-
5
-
-
pF
%
DuCy(HSE) Duty cycle
-
55
±1
IL
OSC_IN Input leakage current
VSS ≤ VIN ≤ VDD
-
µA
1. Guaranteed by design.
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Electrical characteristics
STM32F722xx STM32F723xx
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 61: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 38.
The characteristics given in Table 39 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 16.
Table 39. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User External clock source
frequency(1)
fLSE_ext
-
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
tw(LSE)
0.7VDD
VSS
-
-
-
VDD
0.3VDD
-
V
OSC32_IN input pin low level voltage
OSC32_IN high or low time(1)
-
450
tf(LSE)
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1)
-
-
50
Cin(LSE)
OSC32_IN input capacitance(1)
-
-
30
-
5
-
-
pF
%
DuCy(LSE) Duty cycle
-
70
±1
IL
OSC32_IN Input leakage current
VSS ≤ VIN ≤ VDD
-
µA
1. Guaranteed by design.
Figure 37. High-speed external clock source AC timing diagram
V
HSEH
90%
10 %
HSEL
V
t
t
t
W(HSE)
t
t
W(HSE)
r(HSE)
f(HSE)
T
HSE
f
HSE_ext
External
I
L
OSC _I N
clock source
STM32F
ai17528
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Electrical characteristics
Figure 38. Low-speed external clock source AC timing diagram
V
LSEH
90%
10%
V
LSEL
t
t
t
W(LSE)
t
t
W(LSE)
r(LSE)
f(LSE)
T
LSE
f
LSE_ext
External
I
L
OSC32_IN
clock source
STM32F
ai17529
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 40. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 40. HSE 4-26 MHz oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fOSC_IN
RF
Oscillator frequency
Feedback resistor
-
-
4
-
-
26
-
MHz
200
kΩ
VDD=3.3 V,
ESR= 30 Ω,
CL=5 pF@25 MHz
-
-
450
530
-
-
IDD
HSE current consumption
HSE accuracy
µA
VDD=3.3 V,
ESR= 30 Ω,
CL=10 pF@25 MHz
(2)
ACCHSE
-
− 500
-
-
500
ppm
mA/V
ms
Gm_crit_max Maximum critical crystal gm
Startup
-
-
1
-
(3)
tSU(HSE
Startup time
VDD is stabilized
2
1. Guaranteed by design.
2. This parameter depends on the crystal used in the application. The minimum and maximum values must
be respected to comply with USB standard specifications.
3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is based on characterization results. It is measured for a standard crystal
resonator and it can vary significantly with the crystal manufacturer.
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STM32F722xx STM32F723xx
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 39). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 39. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC_IN
HSE
Bias
controlled
gain
8 MHz
resonator
R
F
OSC_OUT
(1)
STM32F
R
EXT
C
L2
ai17530
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 41. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions
Min Typ Max Unit
LSEDRV[1:0]=00
-
-
-
-
250
300
370
480
-
-
-
-
Low drive capability
LSEDRV[1:0]=10
Medium low drive capability
IDD
LSE current consumption
nA
LSEDRV[1:0]=01
Medium high drive capability
LSEDRV[1:0]=11
High drive capability
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Symbol
Electrical characteristics
(1)
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz)
(continued)
Parameter
Conditions
Min Typ Max Unit
LSEDRV[1:0]=00
-
-
-
-
-
-
0.48
0.75
1.7
Low drive capability
LSEDRV[1:0]=10
Medium low drive capability
Gm_crit_max Maximum critical crystal gm
µA/V
LSEDRV[1:0]=01
Medium high drive capability
LSEDRV[1:0]=11
-
-
-
2.7
-
High drive capability
(2)
tSU
start-up time
VDD is stabilized
2
s
1. Guaranteed by design.
2. Guaranteed by characterization results. tSU is the start-up time measured from the moment it is enabled
(by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard
crystal resonator and it can vary significantly with the crystal manufacturer.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST Microelectronics website
www.st.com.
Figure 40. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC32_ IN
LSE
Bias
controlled
gain
32.768 kHz
resonator
R
F
OSC32_ OU T
STM32F
C
L2
ai17531a
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STM32F722xx STM32F723xx
6.3.10
Internal clock source characteristics
The parameters given in Table 42 and Table 43 are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 16.
DD
High-speed internal (HSI) RC oscillator
(1)
Table 42. HSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fHSI
Frequency
-
-
-
-
16
-
-
1
MHz
%
HSI user trimming step(2)
TA = –40 to 105 °C(3) − 8
-
4.5
4
%
ACCHSI
Accuracy of the HSI oscillator
TA = –10 to 85 °C(3)
− 4
− 1
-
-
%
TA = 25 °C(4)
-
1
%
(2)
tsu(HSI)
HSI oscillator startup time
-
-
2.2
60
4
µs
µA
(2)
IDD(HSI)
HSI oscillator power consumption
-
80
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Factory calibrated, parts not soldered.
Figure 41. ACCHSI versus temperature
6
4
2
0
-40
0
25
55
85
105
125
°
TA ( C)
-2
-4
-6
-8
Min
Max
Typical
MSv41055V1
1. Guaranteed by characterization results.
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Electrical characteristics
Low-speed internal (LSI) RC oscillator
(1)
Table 43. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(2)
fLSI
Frequency
17
-
32
15
47
40
kHz
µs
(3)
tsu(LSI)
LSI oscillator startup time
LSI oscillator power consumption
(3)
IDD(LSI)
-
0.4
0.6
µA
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by characterization results.
3. Guaranteed by design.
Figure 42. LSI deviation versus temperature
8.0%
6.0%
4.0%
2.0%
0.0%
-2.0%
-4.0%
-6.0%
-8.0%
Min
Max
-40°C
0°C
25°C
85°C
105°C
125°C
Typical
Temperature (°C)
MS37554V1
6.3.11
PLL characteristics
The parameters given in Table 44 and Table 45 are derived from tests performed under
temperature and V supply voltage conditions summarized in Table 16.
DD
Table 44. Main PLL characteristics
Symbol
Parameter
PLL input clock(1)
Conditions
Min
Typ
Max
Unit
fPLL_IN
-
-
0.95(2)
24
1
-
2.10
216
fPLL_OUT
PLL multiplier output clock
MHz
48 MHz PLL multiplier output
clock
fPLL48_OUT
fVCO_OUT
-
-
-
48
-
75
PLL VCO output
100
432
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STM32F722xx STM32F723xx
Table 44. Main PLL characteristics (continued)
Symbol
tLOCK
Parameter
Conditions
Min
Typ
Max
Unit
VCO freq = 100 MHz
VCO freq = 432 MHz
75
100
-
-
-
200
300
-
PLL lock time
µs
RMS
25
peak
to
peak
Cycle-to-cycle jitter
-
-
-
150
15
-
-
-
System clock
216 MHz
RMS
peak
to
Period Jitter
200
Jitter(3)
ps
peak
Main clock output (MCO) for
RMII Ethernet
Cycle to cycle at 50 MHz
on 1000 samples
-
-
-
32
40
330
-
-
-
-
Main clock output (MCO) for MII Cycle to cycle at 25 MHz
Ethernet
on 1000 samples
Cycle to cycle at 1 MHz
on 1000 samples
Bit Time CAN jitter
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
0.40
0.75
(4)
IDD(PLL)
PLL power consumption on VDD
PLL power consumption on VDDA
mA
mA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
0.40
0.85
(4)
IDDA(PLL)
-
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Guaranteed by characterization results.
Table 45. PLLI2S characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLI2S_IN
PLLI2S input clock(1)
-
0.95(2)
1
2.10
PLLI2S multiplier output clock for
SAI
fPLLI2SQ_OUT
-
-
-
-
-
-
216
216
MHz
PLLI2S multiplier output clock for
I2S
fPLLI2SR_OUT
fVCO_OUT
PLLI2S VCO output
-
100
75
-
-
-
432
200
300
VCO freq = 100 MHz
VCO freq = 432 MHz
tLOCK
PLLI2S lock time
µs
100
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Electrical characteristics
Table 45. PLLI2S characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RMS
-
90
-
ps
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
peak
to
peak
-
280
-
ps
Master I2S clock jitter
Average frequency of
12.288 MHz
Jitter(3)
-
-
90
-
-
ps
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 KHz
on 1000 samples
WS I2S clock jitter
400
ps
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
0.40
0.75
PLLI2S power consumption on
VDD
(4)
IDD(PLLI2S)
-
-
mA
mA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
0.40
0.85
PLLI2S power consumption on
VDDA
(4)
IDDA(PLLI2S)
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
Table 46. PLLISAI characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLSAI_IN
PLLSAI input clock(1)
-
0.95(2)
1
2.10
PLLSAI multiplier output clock
for 48 MHz
fPLLSAIP_OUT
-
-
-
-
48
-
75
MHz
PLLSAI multiplier output clock
for SAI
fPLLSAIQ_OUT
fVCO_OUT
216
PLLSAI VCO output
-
100
75
100
-
-
-
432
200
300
-
VCO freq = 100 MHz
VCO freq = 432 MHz
tLOCK
PLLSAI lock time
µs
ps
-
RMS
90
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
peak
to
peak
-
280
-
ps
Master SAI clock jitter
Average frequency of
12.288 MHz
Jitter(3)
-
-
90
-
-
ps
ps
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 KHz
on 1000 samples
FS clock jitter
400
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Table 46. PLLISAI characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
0.40
0.75
PLLSAI power consumption on
VDD
(4)
IDD(PLLSAI)
-
mA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
0.40
0.85
PLLSAI power consumption on
VDDA
(4)
IDDA(PLLSAI)
-
mA
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
6.3.12
PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 57: EMI characteristics). It is available only on the main PLL.
Table 47. SSCG parameters constraint
Symbol
Parameter
Min
Typ
Max(1)
Unit
fMod
md
Modulation frequency
-
0.25
-
-
-
-
10
2
KHz
%
Peak modulation depth
-
MODEPER * INCSTEP
1. Guaranteed by design.
2
15 − 1
-
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round[fPLL_IN ⁄ (4 × fMod)]
f
and f
must be expressed in Hz.
PLL_IN
Mod
As an example:
If f = 1 MHz, and f
= 1 kHz, the modulation depth (MODEPER) is given by
MOD
PLL_IN
equation 1:
MODEPER = round[106 ⁄ (4 × 103)] = 250
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
INCSTEP = round[((215 – 1) × md × PLLN) ⁄ (100 × 5 × MODEPER)]
f
must be expressed in MHz.
VCO_OUT
With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
INCSTEP = round[((215 – 1) × 2 × 240) ⁄ (100 × 5 × 250)] = 126md(quantitazed)%
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An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
mdquantized% = (MODEPER × INCSTEP × 100 × 5) ⁄ ((215 – 1) × PLLN)
As a result:
mdquantized% = (250 × 126 × 100 × 5) ⁄ ((215 – 1) × 240) = 2.002%(peak)
Figure 43 and Figure 44 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is f
nominal.
PLL_OUT
T
is the modulation period.
mode
md is the modulation depth.
Figure 43. PLL output clock waveforms in center spread mode
Frequency (PLL_OUT)
md
F0
md
Time
tmode
2xtmode
ai17291
Figure 44. PLL output clock waveforms in down spread mode
Frequency (PLL_OUT)
F0
2xmd
Time
tmode
2xtmode
ai17292b
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6.3.13
USB OTG HS PHY PLLs characteristics (on STM32F723xx devices)
The parameters given in Table 48 are derived from tests performed under temperature and
V
supply voltage conditions summarized in Table 16.
DD
(1)
Table 48. USB OTG HS PLL1 characteristics
Symbol
fPLL1_IN
Parameter
Conditions
Min
Typ
Max Unit
PLL1 input clock
-
-
-
-
-
-
12, 12.5, 16, 24, 25
fPLL1_OUT PLL1 output clock(2)
-
60
-
-
MHz
fVCO_OUT PLL1 VCO output
600
720
22
tLOCK
PLL1 lock time(2)
-
-
-
-
µs
IDD(PLL1) PLL1 digital power consumption
IDDA(PLL1) PLL1 analog power consumption
-
1.8
2.75
mA
-
1. Guaranteed by design.
2. Based on test during characterization.
(1)
Table 49. USB OTG HS PLL2 characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fPLL2_IN
PLL2 input clock
-
-
-
-
-
-
-
-
-
-
-
-
60
-
fPLL2_OUT PLL2 output clock(2)
480
-
MHz
fVCO_OUT PLL2 VCO output
480
-
tLOCK
PLL2 lock time(2)
-
-
-
91
2.1
1.5
µs
IDD(PLL2) PLL2 digital power consumption
IDDA(PLL2) PLL2 analog power consumption
mA
1. Guaranteed by design.
2. Based on test during characterization.
6.3.14
USB OTG HS PHY regulator characteristics
The parameters given in Table 50 are derived from tests performed under temperature and
V
supply voltage conditions summarized in Table 16.
DD
(1)
Table 50. USB OTG HS PHY regulator characteristics
Symbol
Parameter
Conditions Min Typ Max Unit
VDD12OTGHS
CEXT
1.2 V internal voltage on VDD12OTGHS
External capacitor on VDD12OTGHS
Regulator power consumption
-
-
-
1.18 1.2 1.24
1.1 2.2 3.3
100 120 125
V
µF
µA
IDDPHYHSREG
1. Based on test during characterization.
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6.3.15
USB HS PHY external resistor characteristics
(on STM32F723xx devices)
Table 51. USB HS PHY external resistor characteristics (on STM32F723xx devices)
Symbol
Parameter
Conditions
Min Typ Max Unit
External calibration resistor connected Required if using
(to GND) from OTG_HS_REXT USB HS PHY
REXT
2.97 3.00 3.03 kΩ
6.3.16
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Table 52. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Write / Erase 8-bit mode, VDD = 1.7 V
-
-
-
6.7
9.2
-
IDD
Supply current Write / Erase 16-bit mode, VDD = 2.1 V
Write / Erase 32-bit mode, VDD = 3.3 V
-
-
mA
12.6
Table 53. Flash memory programming
Symbol
Parameter
Conditions
Min(1) Typ Max(1) Unit
Program/eraseparallelism
(PSIZE) = x 8/16/32
tprog
Word programming time
-
-
-
-
-
-
-
-
-
-
16
100(2) µs
418
Program/eraseparallelism
(PSIZE) = x 8
346
252
208
Program/eraseparallelism
(PSIZE) = x 16
tERASE16KB Sector (16 KB) erase time
tERASE128KB Sector (128 KB) erase time
tERASE64KB Sector (64 KB) erase time
312
265
ms
ms
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
1953 2500
1252 1639
Program/eraseparallelism
(PSIZE) = x 16
Program/eraseparallelism
(PSIZE) = x 32
927
1322
Program/eraseparallelism
(PSIZE) = x 8
1027 1298
Program/eraseparallelism
(PSIZE) = x 16
675
505
840
682
ms
Program/eraseparallelism
(PSIZE) = x 32
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Symbol
STM32F722xx STM32F723xx
Table 53. Flash memory programming (continued)
Parameter
Conditions
Min(1) Typ Max(1) Unit
Program/eraseparallelism
(PSIZE) = x 8
-
-
-
7718 9883
4869 6379
3503 5180
Program/eraseparallelism
(PSIZE) = x 16
tME
Mass erase time
ms
Program/eraseparallelism
(PSIZE) = x 32
32-bit program operation
16-bit program operation
8-bit program operation
2.7
2.1
1.7
-
-
-
3.6
3.6
3.6
V
V
V
Vprog
Programming voltage
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 10 K erase operations.
Table 54. Flash memory programming with V
PP
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
tprog
Double word programming
-
-
16
180
900
450
6.9
-
100(2)
µs
tERASE16KB Sector (16 KB) erase time
tERASE128KB Sector (128 KB) erase time
tERASE64KB Sector (64 KB) erase time
-
-
TA = 0 to +40 °C
VDD = 3.3 V
-
ms
VPP = 8.5 V
-
-
tME
Vprog
VPP
Mass erase time
-
-
s
V
V
Programming voltage
VPP voltage range
-
-
2.7
7
3.6
9
-
Minimum current sunk on
the VPP pin
IPP
-
-
10
-
-
-
-
mA
Cumulative time during
which VPP is applied
(3)
tVPP
1
hour
1. Guaranteed by design.
2. The maximum programming time is measured after 10 K erase operations.
3. VPP should only be connected during programming/erasing.
Table 55. Flash memory endurance and data retention
Value
Symbol
Parameter
Conditions(1)
Unit
Min(2)
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
NEND
Endurance
10
kcycles
Years
1 kcycle(3) at TA = 85 °C
30
10
20
tRET
Data retention 1 kcycle(3) at TA = 105 °C
10 kcycles(3) at TA = 55 °C
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1. Tj can not go above 125°C (current consumption limitation).
2. Guaranteed by characterization results.
3. Cycling performed over the whole temperature range.
6.3.17
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
DD
SS
A device reset allows normal operations to be resumed.
The test results are given in Table 56. They are based on the EMS levels and classes
defined in application note AN1709.
Table 56. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, TA = +25 °C,
fHCLK = 216 MHz,
Voltage limits to be applied on any I/O
pin to induce a functional disturbance
VFESD
2B
5A
conforms to IEC 61000-4-2
VDD = 3.3 V, TA =+25 °C,
Fast transient voltage burst limits to be
VEFTB
applied through 100 pF on VDD and VSS fHCLK = 216 MHz,
pins to induce a functional disturbance
conforms to IEC 61000-4-2
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as
possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
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The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 57. EMI characteristics
Max vs.
Monitored
frequency band
[fHSE/fCPU
]
Symbol Parameter
Conditions
Unit
25/200 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI Level
23
20
34
24
4
VDD = 3.6 V, TA = 25 °C, conforming to
IEC61967-2 ART/L1-cache OFF, over-drive ON,
all peripheral clocks enabled, clock dithering
disabled.
dBµV
-
SEMI
Peak level
6.3.18
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/ESDA/JEDEC JS-001-2012 and ANSI/ESD S5.3.1-2009 standards.
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Maximum
Table 58. ESD absolute maximum ratings
Conditions
Symbol
Ratings
Class
Unit
value(1)
Electrostatic discharge
voltage (human body model) ANSI/ESDA/JEDEC JS-001-2012
TA = +25 °C conforming to
VESD(HBM)
2
2000
V
TA = +25 °C conforming to ANSI/ESD
Electrostatic discharge
VESD(CDM)
STM5.3.1-2009, all the packages
voltage (charge device model)
3
250
excepted WLCSP100
1. Guaranteed by characterization results.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
•
•
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.
Table 59. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
II level A
6.3.19
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3 V-capable I/O pins) should be avoided during normal product
DD
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –
5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 60.
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Table 60. I/O current injection susceptibility
Functionalsusceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on BOOT0, PDR_ON, BYPASS_REG,
OTG_HS_REXT
-0
-0
-0
0
Injected current on NRST
NA(1)
NA(1)
IINJ
Injected current on PF9, PF10, PH0_OSCIN, PH1_OSCOUT, PC0,
PC1, PC2, PC3, PB14(2), PB15(2)
mA
Injected current on any other FT or FTf pins
Injected current on any other pins
-5
-5
NA(1)
+5
1. Injection is not possible.
2. PB14 and PB15 in the STM32F723xx devices.
Note:
It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
6.3.20
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 61: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 16. All I/Os are
CMOS and TTL compliant.
Table 61. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.35VDD−0.04(1)
FT, TTa and NRST I/O input
low level voltage
1.7 V≤ VDD≤ 3.6 V
-
-
(2)
0.3VDD
1.75 V≤ VDD ≤ 3.6 V,
–40 °C≤ TA ≤ 105 °C
VIL
V
-
-
-
BOOT I/O input low level
voltage
0.1VDD+0.1(1)
1.7 V≤ VDD ≤ 3.6 V,
0 °C≤ TA ≤ 105 °C
-
0.45VDD+0.3(1)
FT, TTa and NRST I/O input
high level voltage(5)
1.7 V≤ VDD≤ 3.6 V
-
-
-
-
(2)
0.7VDD
1.75 V≤ VDD ≤ 3.6 V,
–40 °C≤ TA ≤ 105 °C
VIH
V
BOOT I/O input high level
voltage
0.17VDD+0.7(1)
1.7 V≤ VDD ≤ 3.6 V,
0 °C≤ TA ≤ 105 °C
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Table 61. I/O static characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
FT, TTa and NRST I/O input
hysteresis
(3)
1.7 V≤ VDD≤ 3.6 V
10%VDD
-
-
1.75 V≤ VDD ≤ 3.6 V,
–40 °C≤ TA ≤ 105 °C
VHYS
V
BOOT I/O input hysteresis
0.1
-
-
1.7 V≤ VDD ≤ 3.6 V,
0 °C≤ TA ≤ 105 °C
I/O input leakage current (4)
VSS ≤ VIN ≤ VDD
VIN = 5 V
-
-
-
-
1
3
Ilkg
µA
I/O FT input leakage current (5)
All pins
except for
PA10/PB12
(OTG_FS_ID
,OTG_HS_ID
)
30
7
40
10
40
50
14
50
Weak pull-up
equivalent
resistor(6)
RPU
VIN = VSS
PA10/PB12
(OTG_FS_ID
,OTG_HS_ID
)
kΩ
All pins
except for
PA10/PB12
(OTG_FS_ID
,OTG_HS_ID
)
30
Weak pull-
down
RPD
VIN = VDD
equivalent
resistor(7)
PA10/PB12
(OTG_FS_ID
,OTG_HS_ID
)
7
-
10
5
14
-
(8)
CIO
I/O pin capacitance
-
pF
1. Guaranteed by design.
2. Tested in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 60: I/O
current injection susceptibility
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 60: I/O current injection
susceptibility
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the
series resistance is minimum (~10% order).
7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 45.
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Figure 45. FT I/O input characteristics
VIL/VIH (V)
2.52
TTL requirement
VIHmin = 2V
2.0
1.92
1.7
1.22
1.19
Area not determined
1.065
0.8
TTL requirement
VILmax = 0.8V
Tested in production - CMOS requirement VILmax = 0.3VDD
0.55
0.51
VDD (V)
1.7
2.0
2.4
3.3
3.6
2.7
MS33746V2
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or
source up to 20 mA (with a relaxed V /V ) except PC13, PC14, PC15 and PI8 which
OL OH
can sink or source up to 3mA. When using the PC13 to PC15 and PI8 GPIOs in output
mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 14).
VDD
•
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
ΣI
(see Table 14).
VSS
Output voltage levels
Unless otherwise specified, the parameters given in Table 62 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 16. All I/Os are CMOS and TTL compliant.
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Table 62. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max Unit
CMOS port(2)
IIO = +8 mA
(1)
VOL
Output low level voltage for an I/O pin
-
0.4
2.7 V ≤ VDD ≤ 3.6 V
CMOS port(2)
Output high level voltage for an I/O pin
except PC14
(3)
VOH
VDD − 0.4
VDD − 0.4
-
-
IIO = -8 mA
V
2.7 V ≤ VDD ≤ 3.6 V
CMOS port(2)
(3)
VOH
Output high level voltage for PC14
Output low level voltage for an I/O pin
IIO = -2 mA
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2)
IIO =+8mA
(1)
(3)
VOL
-
0.4
-
2.7 V ≤ VDD ≤ 3.6 V
V
TTL port(2)
IIO =-8mA
Output high level voltage for an I/O pin
except PC14
VOH
2.4
2.7 V ≤ VDD ≤ 3.6 V
I
IO = +20 mA
(1)
(3)
VOL
Output low level voltage for an I/O pin
-
1.3(4)
2.7 V ≤ VDD ≤ 3.6 V
V
V
IIO = -20 mA
Output high level voltage for an I/O pin
except PC14
VOH
VDD−1.3(4)
-
2.7 V ≤ VDD ≤ 3.6 V
I
IO = +6 mA
(1)
VOL
Output low level voltage for an I/O pin
-
VDD−0.4(4)
0.4(4)
1.8 V ≤ VDD ≤ 3.6 V
IIO = -6 mA
Output high level voltage for an I/O pin
except PC14
(3)
VOH
-
1.8 V ≤ VDD ≤ 3.6 V
I
IO = +4 mA
(1)
VOL
Output low level voltage for an I/O pin
-
0.4(5)
1.7 V ≤ VDD ≤ 3.6V
IIO = -4 mA
Output high level voltage for an I/O pin
except PC14
(3)
VOH
VDD−0.4(5)
VDD−0.4(5)
-
-
V
1.7 V ≤ VDD ≤ 3.6V
IIO = -1 mA
(3)
VOH
Output high level voltage for PC14
1.7 V ≤ VDD ≤ 3.6V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 14.
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 14 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
4. Based on characterization data.
5. Guaranteed by design.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 46 and
Table 63, respectively.
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Unless otherwise specified, the parameters given in Table 63 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 16.
(1)(2)
Table 63. I/O AC characteristics
OSPEEDRy
[1:0] bit
Symbol
Parameter
Conditions
Min
Typ
Max Unit
value(1)
CL = 50 pF, VDD ≥ 2.7 V
CL = 50 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 10 pF, VDD ≥ 1.8 V
CL = 10 pF, VDD ≥ 1.7 V
-
-
-
-
-
-
-
-
-
-
4
2
fmax(IO)out Maximum frequency(3)
8
4
3
MHz
ns
00
Output high to low level fall
time and output low to high
level rise time
tf(IO)out
/
CL = 50 pF, VDD = 1.7 V to
3.6 V
-
-
100
tr(IO)out
CL = 50 pF, VDD≥ 2.7 V
CL = 50 pF, VDD≥ 1.8 V
CL = 50 pF, VDD≥ 1.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 10 pF, VDD≥ 1.8 V
CL = 10 pF, VDD≥ 1.7 V
CL = 50 pF, VDD ≥ 2.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 50 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 40 pF, VDD ≥ 2.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 40 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 1.8 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 40 pF, VDD ≥2.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 40 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 1.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
25
12.5
10
fmax(IO)out Maximum frequency(3)
MHz
50
20
01
12.5
10
Output high to low level fall
time and output low to high
level rise time
6
tf(IO)out
tr(IO)out
/
ns
MHz
ns
20
10
50(4)
100(4)
25
fmax(IO)out Maximum frequency(3)
50
10
42.5
6
Output high to low level fall
time and output low to high
level rise time
4
tf(IO)out
tr(IO)out
/
10
6
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DS11853 Rev 6
STM32F722xx STM32F723xx
Electrical characteristics
(1)(2)
Table 63. I/O AC characteristics
(continued)
OSPEEDRy
[1:0] bit
Symbol
Parameter
Conditions
Min
Typ
Max Unit
value(1)
CL = 30 pF, VDD ≥ 2.7 V
CL = 30 pF, VDD ≥ 1.8 V
CL = 30 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD≥ 2.7 V
CL = 10 pF, VDD ≥ 1.8 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 30 pF, VDD ≥ 2.7 V
CL = 30 pF, VDD ≥1.8 V
CL = 30 pF, VDD ≥1.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 10 pF, VDD ≥1.8 V
CL = 10 pF, VDD ≥1.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100(4)
50
42.5
MHz
fmax(IO)out Maximum frequency(3)
180(4)
100
72.5
4
11
6
Output high to low level fall
time and output low to high
level rise time
7
tf(IO)out
/
ns
2.5
tr(IO)out
3.5
4
Pulse width of external signals
-
tEXTIpw detected by the EXTI
controller
-
10
-
-
ns
1. Guaranteed by design.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F72xxx and STM32F73xxx reference
manual for a description of the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 46.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.
Figure 46. I/O AC characteristics definition
90%
10%
50%
50%
90%
t
10%
t
EXTERNAL
OUTPUT
ON CL
r(IO)out
f(IO)out
T
Maximum frequency is achieved if (t + t ) ≤ (2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by CL specified in the table “ I/O AC characteristics”.
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Electrical characteristics
STM32F722xx STM32F723xx
6.3.21
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 61: I/O static characteristics).
PU
Unless otherwise specified, the parameters given in Table 64 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 16.
Table 64. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RPU
Weak pull-up equivalent resistor(1)
NRST Input filtered pulse
VIN = VSS
-
30
-
40
-
50
kΩ
ns
ns
µs
(2)
VF(NRST)
100
(2)
VNF(NRST)
NRST Input not filtered pulse
VDD > 2.7 V
Internal Reset source
300
20
-
-
-
TNRST_OUT Generated reset pulse duration
-
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
2. Guaranteed by design.
Figure 47. Recommended NRST pin protection
V
DD
External
reset circuit
(1)
R
PU
(2)
Internal Reset
NRST
Filter
0.1 μF
STM32F
ai14132c
1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as
possible to the chip.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 64. Otherwise the reset is not taken into account by the device.
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Electrical characteristics
6.3.22
TIM timer characteristics
The parameters given in Table 65 are guaranteed by design.
Refer to Section 6.3.20: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)(2)
Table 65. TIMx characteristics
Conditions(3)
Symbol
Parameter
Min
Max
Unit
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK
=
tTIMxCLK
1
-
216 MHz
tres(TIM)
Timer resolution time
AHB/APBx
prescaler>4, fTIMxCLK
=
tTIMxCLK
1
-
108 MHz
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK/2
16/32
0
-
MHz
bit
f
TIMxCLK = 216 MHz
ResTIM
Timer resolution
Maximum possible count
with 32-bit counter
65536 ×
65536
tMAX_COUNT
tTIMxCLK
-
-
1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 216 MHz, by setting the TIMPRE bit in the
RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCLK, otherwise TIMxCLK =
4x PCLKx.
6.3.23
6.3.24
RTC characteristics
Table 66. RTC characteristics
Symbol
Parameter
Conditions
Min
Max
Any read/write operation
from/to an RTC register
-
fPCLK1/RTCCLK frequency ratio
4
-
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 67 are derived from tests
performed under the ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 16.
Table 67. ADC characteristics
Conditions
Symbol
Parameter
Power supply
Min
Typ
Max
Unit
VDDA
1.7(1)
1.7(1)
-
-
-
3.6
VDDA
-
V
V
V
VDDA − VREF+ < 1.2 V
VREF+ Positive reference voltage
VREF- Negative reference voltage
-
0
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201
Electrical characteristics
STM32F722xx STM32F723xx
Table 67. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA = 1.7(1) to 2.4 V
0.6
0.6
15
30
18
36
MHz
MHz
fADC
ADC clock frequency
VDDA = 2.4 to 3.6 V
f
ADC = 30 MHz,
-
-
-
1764
17
kHz
(2)
12-bit resolution
fTRIG
External trigger frequency
-
-
1/fADC
0
VAIN
Conversion voltage range(3)
-
-
VREF+
V
(VSSA or VREF-
tied to ground)
See Equation 1 for
(2)
RAIN
External input impedance
Sampling switch resistance
-
1.5
-
-
-
50
6
kΩ
kΩ
pF
details
(2)(4)
RADC
-
-
Internal sample and hold
capacitor
(2)
CADC
4
7
f
f
ADC = 30 MHz
-
-
-
0.100
3(5)
0.067
2(5)
16
µs
1/fADC
µs
Injection trigger conversion
latency
(2)
tlat
-
-
ADC = 30 MHz
-
-
-
Regular trigger conversion
latency
(2)
tlatr
-
-
1/fADC
µs
fADC = 30 MHz
-
0.100
-
(2)
tS
Sampling time
Power-up time
3
-
-
480
3
1/fADC
µs
(2)
tSTAB
-
2
fADC = 30 MHz
12-bit resolution
0.50
0.43
0.37
0.30
-
-
-
-
16.40
16.34
16.27
16.20
µs
µs
f
ADC = 30 MHz
10-bit resolution
ADC = 30 MHz
8-bit resolution
ADC = 30 MHz
6-bit resolution
Total conversion time (including
sampling time)
f
(2)
tCONV
µs
f
µs
9 to 492 (tS for sampling +n-bit resolution for successive
approximation)
1/fADC
Msps
12-bit resolution
-
-
-
-
2.4
4.5
Single ADC
12-bit resolution
Sampling rate
Msps
Msps
Interleave Dual ADC
mode
(2)
fS
(fADC = 36 MHz, and
tS = 3 ADC cycles)
12-bit resolution
-
-
7.2
Interleave Triple ADC
mode
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Electrical characteristics
Table 67. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ADC VREF DC current
consumption in conversion
mode
(2)
IVREF+
-
-
300
500
µA
ADC VDDA DC current
consumption in conversion
mode
(2)
IVDDA
-
-
1.6
1.8
mA
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:
Internal reset OFF).
2. Guaranteed by characterization results.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA
.
4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 67.
Equation 1: R
max formula
AIN
(k – 0.5)
RAIN = -------------------------------------------------------------- – RADC
fADC × CADC × ln(2N + 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
Table 68. ADC static accuracy at f
= 18 MHz
Typ
ADC
Symbol
Parameter
Test conditions
Max(1)
Unit
ET
Total unadjusted error
±3
±4
fADC =18 MHz
VDDA = 1.7 to 3.6 V
VREF = 1.7 to 3.6 V
VDDA − VREF < 1.2 V
EO
EG
ED
EL
Offset error
±2
±1
±1
±2
±3
±3
±2
±3
LSB
Gain error
Differential linearity error
Integral linearity error
1. Guaranteed by characterization results.
Table 69. ADC static accuracy at f
= 30 MHz
Typ
ADC
Symbol
Parameter
Test conditions
Max(1)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
±2
±5
±2.5
±4
f
ADC = 30 MHz,
±1.5
±1.5
±1
RAIN < 10 kΩ,
DDA = 2.4 to 3.6 V,
Gain error
V
LSB
VREF = 1.7 to 3.6 V,
VDDA − VREF < 1.2 V
Differential linearity error
Integral linearity error
±2
±1.5
±3
1. Guaranteed by characterization results.
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201
Electrical characteristics
Symbol
STM32F722xx STM32F723xx
= 36 MHz
Table 70. ADC static accuracy at f
ADC
Parameter
Test conditions
Typ
Max(1)
Unit
ET
Total unadjusted error
±4
±7
f
ADC =36 MHz,
EO
EG
ED
EL
Offset error
±2
±3
±2
±3
±3
±6
±3
±6
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V
VDDA − VREF < 1.2 V
LSB
Gain error
Differential linearity error
Integral linearity error
1. Guaranteed by characterization results.
(1)
Table 71. ADC dynamic accuracy at f
Parameter
= 18 MHz - limited test conditions
ADC
Symbol
Test conditions
Min
Typ
Max Unit
ENOB
SINAD
SNR
Effective number of bits
Signal-to-noise and distortion ratio
Signal-to-noise ratio
10.3
64
10.4
64.2
65
-
-
-
-
bits
fADC =18 MHz
V
DDA = VREF+= 1.7 V
Input Frequency = 20 KHz
Temperature = 25 °C
64
dB
THD
Total harmonic distortion
− 67
− 72
1. Guaranteed by characterization results.
(1)
Table 72. ADC dynamic accuracy at f
= 36 MHz - limited test conditions
ADC
Symbol
Parameter
Test conditions
Min
Typ
Max Unit
ENOB
SINAD
SNR
Effective number of bits
Signal-to noise and distortion ratio
Signal-to noise ratio
10.6
66
10.8
67
-
-
-
-
bits
fADC =36 MHz
VDDA = VREF+ = 3.3 V
Input Frequency = 20 KHz
Temperature = 25 °C
64
68
dB
THD
Total harmonic distortion
− 70
− 72
1. Guaranteed by characterization results.
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for I
Section 6.3.20 does not affect the ADC accuracy.
and ΣI
in
INJ(PIN)
INJ(PIN)
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STM32F722xx STM32F723xx
Electrical characteristics
Figure 48. ADC accuracy characteristics
V
V
DDA
4096
REF+
[1LSB
=
(or
depending on package)]
IDEAL
4096
E
G
4095
4094
4093
(2)
E
T
(3)
7
6
5
4
3
2
1
(1)
E
E
O
L
E
D
1L SB
IDEAL
7
0
V
1
2
3
456
4093 4094 4095 4096
V
DDA
SSA
ai14395c
1. See also Table 69.
2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 49. Typical connection diagram using the ADC
STM32F
V
DD
Sample and hold ADC
V
T
converter
0.6 V
(1)
AIN
(1)
R
R
ADC
AINx
12-bit
converter
V
0.6 V
T
V
AIN
C
(1)
ADC
C
parasitic
I
1 μA
L
ai17534
1. Refer to Table 67 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
f
ADC should be reduced.
DS11853 Rev 6
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201
Electrical characteristics
STM32F722xx STM32F723xx
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 50 or Figure 51,
depending on whether V is connected to V or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 50. Power supply and reference decoupling (V
not connected to V
)
DDA
REF+
STM32
(1)
VREF+
1 μF // 10 nF
V
V
DDA
1 μF // 10 nF
(1)
SSA/VREF+
ai17535c
1. VREF+ input is available on all the packages except LQFP64, whereas the VREF– is available only on
UFBGA176 and UFBGA144. When VREF- is not available, it is internally connected to VSSA
.
Figure 51. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
STM32F
(1)
VREF+/VDDA
1 μF // 10 nF
(1)
VREF-/VSSA
ai17536c
1. VREF+ input is available on all the packages except LQFP64, whereas the VREF– is available only on
UFBGA176 and UFBGA144. When VREF- is not available, it is internally connected to VSSA
.
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Electrical characteristics
6.3.25
Temperature sensor characteristics
Table 73. Temperature sensor characteristics
Parameter
Symbol
Min
Typ Max
Unit
(1)
TL
VSENSE linearity with temperature
-
-
1
2.5
0.76
6
2
°C
mV/°C
V
Avg_Slope(1) Average slope
-
(1)
V25
Voltage at 25 °C
-
-
10
-
(2)
tSTART
Startup time
-
µs
(2)
TS_temp
ADC sampling time when reading the temperature (1 °C accuracy)
10
-
µs
1. Guaranteed by characterization results.
2. Guaranteed by design.
Table 74. Temperature sensor calibration values
Symbol
Parameter
Memory address
0x1FF0 7A2C - 0x1FF0 7A2D
TS_CAL1
TS_CAL2
TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V
TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FF0 7A2E - 0x1FF0 7A2F
6.3.26
V
monitoring characteristics
BAT
Table 75. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
50
4
-
-
KΩ
-
Ratio on VBAT measurement
Error on Q
Er(1)
–1
-
+1
%
ADC sampling time when reading the VBAT
1 mV accuracy
(2)(2)
TS_vbat
5
-
-
µs
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.27
Reference voltage
The parameters given in Table 76 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 16.
DD
Table 76. internal reference voltage
Symbol
VREFINT
Parameter
Conditions
Min
Max
Unit
Typ
Internal reference voltage
–40 °C < TA < +105 °C 1.18 1.21
1.24
V
ADC sampling time when reading the
internal reference voltage
(1)
TS_vrefint
-
10
-
-
-
µs
Internal reference voltage spread over the
temperature range
(2)
VRERINT_s
VDD = 3V 10mV
3
5
mV
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Electrical characteristics
STM32F722xx STM32F723xx
Table 76. internal reference voltage (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Typ
(2)
TCoeff
Temperature coefficient
Startup time
-
-
-
-
30
6
50
10
ppm/°C
µs
(2)
tSTART
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
Table 77. Internal reference voltage calibration values
Parameter Memory address
VREFIN_CAL Raw data acquired at temperature of 30 °C VDDA = 3.3 V
Symbol
0x1FF0 7A2A - 0x1FF0 7A2B
6.3.28
DAC electrical characteristics
Table 78. DAC characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Comments
VDDA
Analog supply voltage
1.7(1)
-
3.6
V
-
VREF+
VSSA
Reference supply voltage
Ground
1.7(1)
0
-
-
3.6
0
V
V
VREF+ ≤ VDDA
-
-
Connected to
5
-
-
-
-
kΩ
kΩ
VSSA
Resistive load
(2)
RLOAD
with buffer ON
Connected to
25
-
VDDA
When the buffer is OFF, the Minimum
Impedance output with buffer
OFF
(2)
RO
-
-
-
-
15
50
kΩ resistive load between DAC_OUT and
SS to have a 1% accuracy is 1.5 MΩ
V
Maximum capacitive load at DAC_OUT
pin (when the buffer is ON).
(2)
CLOAD
Capacitive load
pF
It gives the maximum output excursion of
the DAC.
DAC_OUT Lower DAC_OUT voltage
min(2)
with buffer ON
0.2
-
-
V
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ = 3.6 V and
(0x1C7) to (0xE38) at VREF+ = 1.7 V
DAC_OUT Higher DAC_OUT voltage
max(2)
with buffer ON
VDDA
0.2
−
−
-
-
-
-
0.5
-
V
mV
V
DAC_OUT Lower DAC_OUT voltage
min(2)
with buffer OFF
-
It gives the maximum output excursion of
the DAC.
DAC_OUT Higher DAC_OUT voltage
max(2)
with buffer OFF
VREF+
1LSB
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STM32F722xx STM32F723xx
Electrical characteristics
Comments
Table 78. DAC characteristics (continued)
Symbol
Parameter
Min
Typ
Max
Unit
With no load, worst code (0x800) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
-
170
240
DAC DC VREF current
consumption in quiescent
mode (Standby mode)
(4)
IVREF+
µA
With no load, worst code (0xF1C) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
-
-
-
50
75
With no load, middle code (0x800) on the
inputs
280
475
380
625
µA
DAC DC VDDA current
consumption in quiescent
mode(3)
(4)
IDDA
With no load, worst code (0xF1C) at
µA VREF+ = 3.6 V in terms of DC
consumption on the inputs
Differential non linearity
Difference between two
consecutive code-1LSB)
-
-
±0.5
LSB Given for the DAC in 10-bit configuration.
DNL(4)
-
-
-
-
±2
±1
LSB Given for the DAC in 12-bit configuration.
LSB Given for the DAC in 10-bit configuration.
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
INL(4)
-
-
±4
LSB Given for the DAC in 12-bit configuration.
mV Given for the DAC in 12-bit configuration
-
-
-
-
±10
±3
Offset error
Given for the DAC in 10-bit at VREF+
3.6 V
=
(difference between
measured value at Code
(0x800) and the ideal value =
VREF+/2)
LSB
LSB
%
Offset(4)
Given for the DAC in 12-bit at VREF+
3.6 V
=
-
-
-
-
±12
Gain
Gain error
±0.5
Given for the DAC in 12-bit configuration
error(4)
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±4LSB
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
(4)
tSETTLING
-
3
6
µs
Total Harmonic Distortion
Buffer ON
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
THD(4)
-
-
-
-
-
dB
Max frequency for a correct
Update DAC_OUT change when
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
1
MS/s
rate(2)
small variation in the input
code (from code i to i+1LSB)
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Table 78. DAC characteristics (continued)
Symbol
Parameter
Min
Typ
Max
Unit
Comments
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
input code between lowest and highest
possible ones.
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
(4)
tWAKEUP
-
6.5
10
µs
Power supply rejection ratio
PSRR+ (2) (to VDDA) (static DC
measurement)
-
–67
–40
dB No RLOAD, CLOAD = 50 pF
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:
Internal reset OFF).
2. Guaranteed by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed by characterization results.
Figure 52. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R
L
DAC_OUTx
12-bit
digital to
analog
converter
C
L
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
6.3.29
Communications interfaces
I2C interface characteristics
2
2
The I C interface meets the timings requirements of the I C-bus specification and user
manual rev. 03 for:
•
•
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s.
Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.
2
The I C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0431 reference manual) and when the I2CCLK frequency is greater
than the minimum shown in the table below:
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Electrical characteristics
Table 79. Minimum I2CCLK frequency in all I2C modes
Symbol
Parameter
Condition
Min
Unit
Standard-mode
Fast-mode
-
2
Analog Filter ON
DNF=0
10
9
Analog Filter OFF
DNF=1
I2CCLK
frequency
f(I2CCLK)
MHz
Analog Filter ON
DNF=0
22.5
16
Fast-mode Plus
Analog Filter OFF
DNF=1
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V is disabled, but is still present.
DD
The 20mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load Cload supported in Fm+, which is given by these formulas:
•
•
Tr(SDA/SCL)=0.8473xR xC
p load
R (min)= (VDD-V (max))/I (max)
p
OL
OL
Where Rp is the I2C lines pull-up. Refer to Section 6.3.20: I/O port characteristics for the
I2C I/Os characteristics.
2
All I C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
(1)
Table 80. I2C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Maximum pulse width of spikes
that are suppressed by the analog
filter
tAF
50(2)
260(3)
ns
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
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STM32F722xx STM32F723xx
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 81 for the SPI interface are
derived from tests performed under the ambient temperature, f frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 16, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)
Table 81. SPI dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
SPI1,4,5
-
-
54(2)
2.7≤VDD≤3.6
Master mode
SPI1,4,5
-
-
-
-
-
-
-
-
-
-
-
-
27
54
1.71≤VDD≤3.6
Master transmitter mode
SPI1,4,5
1.71≤VDD≤3.6
Slave receiver mode
SPI1,4,5
fSCK
SPI clock frequency
54
MHz
1/tc(SCK)
1.71≤VDD≤3.6
Slave mode transmitter/full duplex
SPI1,4,5
50(3)
37(3)
27
2.7≤VDD≤3.6
Slave mode transmitter/full duplex
SPI1,4,5
1.71≤VDD≤3.6
Master & Slave mode
SPI2,3
1.71≤VDD≤3.6
tsu(NSS)
th(NSS)
NSS setup time
NSS hold time
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
4xTpclk
2xTpclk
-
-
-
-
ns
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
Tpclk-1
Tpclk
Tpclk+1
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(1)
Table 81. SPI dynamic characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Master mode
Slave mode
4
3.5
3
-
-
-
-
Data input setup time
Master mode
-
-
Data input hold time
Slave mode
1
-
-
ta(SO)
Data output access time
Slave mode
7
9
21
12
10
13.5
3
tdis(SO) Data output disable time
Slave mode
5
7
ns
Slave mode 2.7≤VDD≤3.6V
Slave mode 1.71≤VDD≤3.6V
Master mode
-
6.5
6.5
2
tv(SO)
Data output valid time
-
tv(MO)
-
Slave mode
4.5
0
-
-
-
-
th(SO)
th(MO)
1.71≤VDD≤3.6V
Data output hold time
Master mode
1. Guaranteed by characterization results.
2. Excepting SPI1 with SCK IO=PA5. In this configuration, the maximum achievable frequency is 40 MHz.
3. Maximum frequency of the slave transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK
level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having
Tsu(MI)=0 while signal Duty(SCK)=50%.
Figure 53. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
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Figure 54. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
tf(SCK)
th(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
First bit OUT
tsu(SI) th(SI)
First bit IN
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
MISO output
MOSI input
Last bit OUT
Next bits IN
Last bit IN
MSv41659V1
Figure 55. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
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I2S interface characteristics
2
Unless otherwise specified, the parameters given in Table 82 for the I S interface are
derived from tests performed under the ambient temperature, f
frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 16, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
2
(1)
Table 82. I S dynamic characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S Main clock output
I2S clock frequency
-
Master data: 32 bits
Slave data: 32 bits
256 x 8K 256xFs(2)
MHz
-
-
64xFs
fCK
MHz
%
64xFs
DCK
I2S clock frequency duty cycle Slave receiver
30
-
70
3
-
tv(WS)
WS valid time
WS hold time
WS setup time
WS hold time
Master mode
Master mode
Slave mode
th(WS)
0
tsu(WS)
5
-
th(WS)
Slave mode
2
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
Master receiver
Slave receiver
Master receiver
Slave receiver
2.5
2.5
3.5
2
-
Data input setup time
Data input hold time
Data output valid time
Data output hold time
-
ns
-
-
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
-
12
3
-
-
5
0
-
1. Guaranteed by characterization results.
2. 256xFs maximum is 49.152 MHz (APB1 Maximum frequency).
Note:
Refer to RM0431 reference manual I2S section for more details on the sampling frequency
(F ).
S
f
, f , and D values reflect only the digital peripheral behavior. The values of these
CK
MCK CK
parameters might be slightly impacted by the source clock precision. D depends mainly
CK
on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). F
maximum value is supported for each mode/condition.
S
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2
(1)
Figure 56. I S slave timing diagram (Philips protocol)
t
c(CK)
CPOL = 0
CPOL = 1
WS input
t
t
t
t
w(CKL)
h(WS)
w(CKH)
t
t
t
v(SD_ST)
h(SD_ST)
su(WS)
SD
SD
transmit
receive
LSB transmit(1)
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
su(SD_SR)
LSB receive(1)
h(SD_SR)
Bitn receive
LSB receive
MS46528V1
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
(1)
Figure 57. I S master timing diagram (Philips protocol)
t
t
r(CK)
f(CK)
t
c(CK)
CPOL = 0
CPOL = 1
WS output
t
w(CKH)
t
t
h(WS)
t
v(WS)
w(CKL)
t
t
v(SD_MT)
h(SD_MT)
SD
transmit
receive
LSB transmit(1)
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
t
h(SD_MR)
su(SD_MR)
LSB receive(1)
Bitn receive
LSB receive
SD
MS46529V1
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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SAI characteristics
Electrical characteristics
Unless otherwise specified, the parameters given in Table 83 for SAI are derived from tests
performed under the ambient temperature, f frequency and VDD supply voltage
PCLKx
conditions summarized in Table 16, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C=30 pF
Measurement points are performed at CMOS levels: 0.5V
DD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
(1)
Table 83. SAI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCKL
SAI Main clock output
-
256x8K
256xFs
128xFs(3)
128xFs(3)
Master data: 32 bits
Slave data: 32 bits
-
-
MHz
FCK
SAI clock frequency(2)
FS valid time
Master mode
-
-
18
20
2.7≤VDD≤3.6V
tv(FS)
Master mode
1.71≤VDD≤3.6V
tsu(FS)
th(FS)
FS setup time
FS hold time
Slave mode
Master mode
Slave mode
1
-
-
-
-
-
-
-
7
0.5
1
tsu(SD_A_MR)
tsu(SD_B_SR)
th(SD_A_MR)
th(SD_B_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
Data input setup time
Data input hold time
2.5
3.5
0.5
ns
Slave transmitter (after enable edge)
-
11
2.7≤VDD≤3.6V
tv(SD_B_MT)
th(SD_B_ST)
tv(SD_A_MT)
th(SD_A_MT)
Data output valid time
Slave transmitter (after enable edge)
-
5
-
18
-
1.71≤VDD≤3.6V
Slave transmitter (after enable edge)
Data output hold time
Data output valid time
Master transmitter (after enable edge)
16
2.7≤VDD≤3.6V
Master transmitter (after enable edge)
-
18.5
-
1.71≤VDD≤3.6V
Data output hold time Master transmitter (after enable edge)
7.5
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With Fs = 192 KHz.
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Figure 58. SAI master timing waveforms
1/f
SCK
SAI_SCK_X
t
h(FS)
SAI_FS_X
(output)
t
t
t
h(SD_MT)
v(FS)
v(SD_MT)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_MR)
su(SD_MR)
SAI_SD_X
(receive)
Slot n
MS32771V1
Figure 59. SAI slave timing waveforms
1/f
SCK
SAI_SCK_X
t
t
t
h(FS)
w(CKH_X)
w(CKL_X)
SAI_FS_X
(input)
t
t
t
h(SD_ST)
su(FS)
v(SD_ST)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_SR)
su(SD_SR)
SAI_SD_X
(receive)
Slot n
MS32772V1
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Electrical characteristics
USB OTG full speed (FS) characteristics
This interface is present in both the USB OTG HS and USB OTG FS controllers.
Table 84. USB OTG full speed startup time
Symbol
Parameter
Max
Unit
(1)
tSTARTUP
USB OTG full speed transceiver startup time
1
µs
1. Guaranteed by design.
Table 85. USB OTG full speed DC electrical characteristics
Min.
Max.(
Symbol
Parameter
Conditions
Typ.
Unit
(1)
1)
USB OTG full speed
VDDUSB transceiver operating
voltage
-
3.0(2)
-
3.6
V
I(USB_FS_DP/DM,
USB_HS_DP/DM)
(3)
VDI
Differential input sensitivity
0.2
0.8
1.3
-
-
-
-
Input
levels
Differential common mode
range
(3)
VCM
Includes VDI range
2.5
2.0
V
V
Single ended receiver
threshold
(3)
VSE
-
VOL
VOH
Static output level low
Static output level high
RL of 1.5 kΩ to 3.6 V(4)
-
-
-
0.3
3.6
Output
levels
(4)
RL of 15 kΩ to VSS
2.8
PA11, PA12
(USB_FS_DP/DM)
VIN = VDD
VIN = VDD
14.25
-
24.8
RPD
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
2.4
0.9
5.2
8
kΩ
PA12 (USB_FS_DP)
VIN = VSS, during idle
1.25 1.575
PA9, PB13
RPU
VIN = VSS, during
reception
(OTG_FS_VBUS,
OTG_HS_VBUS)
0.55 0.95 1.35
1. All the voltages are measured from the local ground potential.
2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed
electrical characteristics which are degraded in the 2.7-to-3.0 V VDDUSB voltage range.
3. Guaranteed by design.
RL is the load connected on the USB OTG full speed drivers.
4.
When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state
(floating input), not as alternate function. A typical 200 µA current consumption of the
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 and PB13 when the feature is enabled.
Note:
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Figure 60. USB OTG full speed timings: definition of data signal rise and fall time
Cross over
points
Differential
data lines
VCRS
VSS
tf
tr
ai14137b
(1)
Table 86. USB OTG full speed electrical characteristics
Driver characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tr
tf
Rise time(2)
Fall time(2)
CL = 50 pF
4
4
20
20
ns
ns
%
V
CL = 50 pF
trfm
VCRS
Rise/ fall time matching
tr/tf
-
90
1.3
111
2.0
Output signal crossover voltage
Driving high or
low
ZDRV
Output driver impedance(3)
28
44
Ω
1. Guaranteed by design.
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
2.
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.
USB high speed (HS) characteristics (through ULPI in STM32F722xx devices)
Unless otherwise specified, the parameters given in Table 89 for ULPI are derived from
tests performed under the ambient temperature, fHCLK frequency summarized in Table 88
and V supply voltage conditions summarized in Table 87, with the following configuration:
DD
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11, unless otherwise specified
Capacitive load C = 20 pF, unless otherwise specified
Measurement points are done at CMOS levels: 0.5V
.
DD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output
characteristics.
Table 87. USB HS DC electrical characteristics
Symbol
Input level
Parameter
Min.(1)
Max.(1)
Unit
VDD
USB OTG HS operating voltage
1.7
3.6
V
1. All the voltages are measured from the local ground potential.
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Symbol
Electrical characteristics
(1)
Table 88. USB HS clock timing parameters
Parameter
Min
Typ
Max
Unit
f
HCLK value to guarantee proper operation of
-
30
-
-
MHz
USB HS interface
FSTART_8BIT
FSTEADY
DSTART_8BIT
DSTEADY
Frequency (first transition)
8-bit ±10%
54
59.97
40
60
60
50
50
66
60.03
60
MHz
MHz
%
Frequency (steady state) ±500 ppm
Duty cycle (first transition)
8-bit ±10%
Duty cycle (steady state) ±500 ppm
49.975
50.025
%
Time to reach the steady state frequency and
duty cycle after the first transition
tSTEADY
-
-
1.4
ms
ms
µs
tSTART_DEV
Peripheral
-
-
-
-
5.6
-
Clock startup time after the
de-assertion of SuspendM
tSTART_HOST
Host
PHY preparation time after the first transition
of the input clock
tPREP
-
-
-
1. Guaranteed by design.
Figure 61. ULPI timing diagram
Clock
t
t
HC
SC
Control In
(ULPI_DIR,
ULPI_NXT)
t
t
HD
SD
data In
(8-bit)
t
t
DC
DC
Control out
(ULPI_STP)
t
DD
data out
(8-bit)
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Symbol
STM32F722xx STM32F723xx
(1)
Table 89. Dynamic characteristics: USB ULPI
Parameter
Conditions
Min.
Typ.
Max. Unit
tSC
tHC
tSD
tHD
Control in (ULPI_DIR, ULPI_NXT) setup time
Control in (ULPI_DIR, ULPI_NXT) hold time
Data in setup time
-
-
-
-
1.5
1
-
-
-
-
-
-
-
-
1.5
1
Data in hold time
2.7 V < VDD < 3.6 V,
CL = 20 pF and
OSPEEDRy[1:0] = 11
ns
-
-
-
6
7.5
-
t
DC/tDD Data/control output delay
1.7 V < VDD < 3.6 V,
9.5
11
CL = 15 pF and
OSPEEDRy[1:0] = 11
1. Guaranteed by characterization results.
USB high speed (HS) characteristics (embedded PHY High speed on
STM32F723xx devices)
Table 90. USB OTG high speed DC electrical characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
Vhssq
Vhsdsc
Vhsdif
High speed squelch detection threshold
High speed disconnect detection threshold
High speed differential detection threshold
-
-
-
100
525
100
-
150 mV
625 mV
-
-
-
mV
High speed data signalling common mode voltage
range
Vhscm
-
-50
-
500 mV
Vhsoi
Vhsoh
Vhsol
High speed idle level
High speed data signaling high
High speed data signaling low
Chirp J level
-
-
-
-
-
-10
360
-10
-
-
-
10
440 mV
10 mV
mV
Vchirpj
Vchirpk
700
-900
-
1100 mV
-500 mV
Chirp K level
-
Table 91. USB OTG high speed electrical characteristics
Parameter
Comments
Conditions
Min Typ Max Unit
tlr
tlf
Rise time
Fall time
-
-
0.5
0.5
-
-
-
ns
ns
-
Setup time from INHSDRIVERENABLE=1 to the
transition on INHSDATAP/INHSDATAN
tlrfm
Zdrv
-
-
10
-
-
ns
Driver output impedance
40.5
-
49.5
Ω
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Table 92. USB FS PHY BCD electrical characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
Primary detection mode consumption
Secondary detection mode consumption
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
300
300
-
IDDUSB
µA
RDAT_LKG Data line leakage resistance
300
0.0
-
kΩ
V
VDAT_LKG Data line leakage voltage
3.6
200
3.6
0.8
2.0
3.6
3.6
3.6
175
175
30
RDCP_DAT Dedicated charging port resistance across D+/D-
Ω
VLGC_HI
Logic high
2.0
-
VLGC_LOW Logic low
VLGC
Logic threshold
0.8
0.25
0.5
0.5
25
25
7
V
VDAT_REF Data detect voltage
VDP_SRC
VDM_SRC
IDM_SINK
IDP_SINK
IDP_SRC
D+ source voltage
D- source voltage
D- sink current
D+ sink current
µA
Data contact detect current source
CAN (controller area network) interface
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (CANx_TX and CANx_RX).
6.3.30
FMC characteristics
Unless otherwise specified, the parameters given in Table 93 to Table 106 for the FMC
interface are derived from tests performed under the ambient temperature, f
frequency
HCLK
and V supply voltage conditions summarized in Table 16, with the following configuration:
DD
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 62 through Figure 65 represent asynchronous waveforms and Table 93 through
Table 100 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•
•
•
•
•
AddressSetupTime = 0x1
AddressHoldTime = 0x1
DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
BusTurnAroundDuration = 0x0
Capcitive load CL = 30 pF
In all timing tables, the T
is the HCLK clock period
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Figure 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
t
w(NE)
FMC_NE
t
t
t
h(NE_NOE)
w(NOE)
v(NOE_NE)
FMC_NOE
FMC_NWE
tv(A_NE)
t
h(A_NOE)
FMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NOE)
FMC_NBL[1:0]
t
h(Data_NE)
t
t
su(Data_NOE)
h(Data_NOE)
t
su(Data_NE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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(1)
Table 93. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol
Parameter
FMC_NE low time
Min
Max
Unit
tw(NE)
tv(NOE_NE)
tw(NOE)
2Thclk -1
2Thclk +1
FMC_NEx low to FMC_NOE low
FMC_NOE low time
0
0.5
2Thclk -1
2Thclk +1
th(NE_NOE)
tv(A_NE)
FMC_NOE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
0
-
-
0.5
th(A_NOE)
Address hold time after FMC_NOE high
FMC_NEx low to FMC_BL valid
FMC_BL hold time after FMC_NOE high
Data to FMC_NEx high setup time
Data to FMC_NOEx high setup time
Data hold time after FMC_NOE high
Data hold time after FMC_NEx high
FMC_NEx low to FMC_NADV low
FMC_NADV low time
0
-
tv(BL_NE)
-
0.5
ns
th(BL_NOE)
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NOE)
th(Data_NE)
tv(NADV_NE)
tw(NADV)
0
-
Thclk -1.5
-
Thclk -1.5
-
0
0
-
-
-
0
-
Thclk -0.5
1. CL = 30 pF.
Table 94. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT
(1)
timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
7Thclk +1 7Thclk +1
tw(NOE)
FMC_NWE low time
FMC_NWAIT low time
5Thclk -1
Thclk -0.5
5Thclk +1.5
5Thclk +1
ns
tw(NWAIT)
-
-
-
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT invalid 4Thclk +1
1. Guaranteed by characterization results.
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Figure 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FMC_NEx
FMC_NOE
FMC_NWE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
t
th(A_NWE)
v(A_NE)
FMC_A[25:0]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_NBL[1:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
(1)
Table 95. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
Parameter
FMC_NE low time
Min
Max
Unit
tw(NE)
tv(NWE_NE)
tw(NWE)
3Thclk +1
3Thclk +1
FMC_NEx low to FMC_NWE low
FMC_NWE low time
Thclk - 0.5
Thclk +0.5
Thclk - 1.5
Thclk +0.5
th(NE_NWE)
tv(A_NE)
th(A_NWE)
tv(BL_NE)
FMC_NWE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
Address hold time after FMC_NWE high
FMC_NEx low to FMC_BL valid
FMC_BL hold time after FMC_NWE high
Data to FMC_NEx low to Data valid
Data hold time after FMC_NWE high
FMC_NEx low to FMC_NADV low
FMC_NADV low time
Thclk
-
-
0
Thclk - 0.5
-
ns
-
0.5
th(BL_NWE)
tv(Data_NE)
th(Data_NWE)
tv(NADV_NE)
tw(NADV)
Thclk - 0.5
-
-
Thclk +1.5
Thclk +0.5
-
-
-
0
Thclk - 0.5
1. Guaranteed by characterization results.
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Table 96. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT
(1)
timings
Symbol
Parameter
FMC_NE low time
FMC_NWE low time
Min
Max
Unit
tw(NE)
8Thclk -1
8Thclk +1
tw(NWE)
6Thclk -1.5
6Thclk -1
6Thclk +0.5
-
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT)
invalid
4Thclk + 2
-
1. Guaranteed by characterization results.
Figure 64. Asynchronous multiplexed PSRAM/NOR read waveforms
t
w(NE)
FMC_ NE
FMC_NOE
t
t
h(NE_NOE)
v(NOE_NE)
t
w(NOE)
t
FMC_NWE
t
h(A_NOE)
v(A_NE)
FMC_ A[25:16]
Address
NBL
t
t
v(BL_NE)
h(BL_NOE)
FMC_ NBL[1:0]
t
h(Data_NE)
t
su(Data_NE)
t
t
t
h(Data_NOE)
v(A_NE)
Address
su(Data_NOE)
Data
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
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(1)
Table 97. Asynchronous multiplexed PSRAM/NOR read timings
Symbol
Parameter
FMC_NE low time
Min
Max
Unit
tw(NE)
tv(NOE_NE)
ttw(NOE)
3Thclk -1
3Thclk +1
2Thclk +0.5
Thclk +1
-
FMC_NEx low to FMC_NOE low
FMC_NOE low time
2Thclk
Thclk -1
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FMC_NOE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
0
-
0
0.5
0.5
Thclk -0.5
Thclk +1
FMC_AD(address) valid hold time after
FMC_NADV high)
th(AD_NADV)
Thclk +0.5
-
ns
th(A_NOE)
th(BL_NOE)
tv(BL_NE)
Address hold time after FMC_NOE high
FMC_BL time after FMC_NOE high
FMC_NEx low to FMC_BL valid
Thclk -0.5
-
0
-
-
0.5
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NE)
th(Data_NOE)
Data to FMC_NEx high setup time
Data to FMC_NOE high setup time
Data hold time after FMC_NEx high
Data hold time after FMC_NOE high
Thclk -1.5
-
-
-
-
Thclk -1.5
0
0
1. Guaranteed by characterization results.
(1)
Table 98. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
FMC_NWE low time
8Thclk -1
8Thclk +1
tw(NOE)
5Thclk -1.5
8Thclk +0.5
-
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Thclk +1.5
FMC_NEx hold time after FMC_NWAIT
invalid
th(NE_NWAIT)
4Thclk +1
-
1. Guaranteed by characterization results.
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Figure 65. Asynchronous multiplexed PSRAM/NOR write waveforms
t
w(NE)
FMC_ NEx
FMC_NOE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
FMC_NWE
t
t
h(A_NWE)
v(A_NE)
FMC_ A[25:16]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_ NBL[1:0]
NBL
v(Data_NADV)
Data
t
t
h(Data_NWE)
t
v(A_NE)
Address
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32756V1
(1)
Table 99. Asynchronous multiplexed PSRAM/NOR write timings
Symbol
Parameter
FMC_NE low time
Min
Max
Unit
tw(NE)
tv(NWE_NE)
tw(NWE)
4Thclk -1
Thclk -0.5
4Thclk +1
FMC_NEx low to FMC_NWE low
FMC_NWE low time
Thclk +0.5
2Thclk -0.5 2Thclk +0.5
th(NE_NWE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FMC_NWE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
Thclk -0.5
-
0
-
0
0.5
Thclk
Thclk +1
ns
FMC_AD(adress) valid hold time after
FMC_NADV high)
th(AD_NADV)
Thclk +0.5
-
th(A_NWE)
th(BL_NWE)
tv(BL_NE)
Address hold time after FMC_NWE high
FMC_BL hold time after FMC_NWE high
FMC_NEx low to FMC_BL valid
Thclk +0.5
-
Thclk -0.5
-
-
0.5
tv(Data_NADV)
th(Data_NWE)
FMC_NADV high to Data valid
-
Thclk +1.5
-
Data hold time after FMC_NWE high
Thclk +0.5
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1. Guaranteed by characterization results.
(1)
Table 100. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
FMC_NWE low time
9Thclk - 1
9Thclk + 1
tw(NWE)
7Thclk -0.5 7Thclk + 0.5
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
6Thclk + 2
4Thclk - 1
-
-
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT)
invalid
1. Guaranteed by characterization results.
Synchronous waveforms and timings
Figure 66 through Figure 69 represent synchronous waveforms and Table 101 through
Table 104 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•
•
•
•
•
•
BurstAccessMode = FMC_BurstAccessMode_Enable;
MemoryType = FMC_MemoryType_CRAM;
WriteBurst = FMC_WriteBurst_Enable;
CLKDivision = 1;
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period.
–
For 2.7 V≤ VDD≤ 3.6 V, maximum FMC_CLK = 108 MHz at CL=20 pF or 90 MHz at
CL=30 pF (on FMC_CLK).
–
For 1.71 V≤ VDD<2.7 V, maximum FMC_CLK = 70 MHz at CL=10 pF (on FMC_CLK).
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Figure 66. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
td(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
td(CLKH-AIV)
d(CLKL-AV)
FMC_A[25:16]
t
td(CLKH-NOEH)
d(CLKL-NOEL)
FMC_NOE
t
t
t
h(CLKH-ADV)
d(CLKL-ADIV)
t
t
t
su(ADV-CLKH)
su(ADV-CLKH)
d(CLKL-ADV)
h(CLKH-ADV)
FMC_AD[15:0]
AD[15:0]
t
D1
D2
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
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STM32F722xx STM32F723xx
(1)
Table 101. Synchronous multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
2Thclk - 0.5
-
2
-
td(CLKL-NExL)
td(CLKH_NExH)
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
-
Thclk + 0.5
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
1
-
0
td(CLKL-AV)
td(CLKH-AIV)
td(CLKL-NOEL)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK low to FMC_NOE low
-
3
-
Thclk
-
2
-
ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high
Thclk - 0.5
td(CLKL-ADV)
td(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
-
2
-
0
FMC_A/D[15:0] valid data before FMC_CLK
high
tsu(ADV-CLKH)
th(CLKH-ADV)
0.5
-
FMC_A/D[15:0] valid data after FMC_CLK high
4
2
3
-
-
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
1. Guaranteed by characterization results.
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Electrical characteristics
Figure 67. Synchronous multiplexed PSRAM write timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
t
d(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
d(CLKH-AIV)
t
t
d(CLKL-AV)
FMC_A[25:16]
t
d(CLKH-NWEH)
d(CLKL-NWEL)
FMC_NWE
t
t
t
d(CLKL-ADIV)
t
d(CLKL-Data)
d(CLKL-Data)
d(CLKL-ADV)
FMC_AD[15:0]
AD[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
t
d(CLKH-NBLH)
FMC_NBL
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STM32F722xx STM32F723xx
(1)
Table 102. Synchronous multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
2Thclk - 0.5
-
2
-
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
Thclk +0.5
-
1
-
0
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
3
-
Thclk
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
1. Guaranteed by characterization results.
-
1.5
-
ns
Thclk +0.5
-
3
-
0
-
3
2
-
-
Thclk +0.5
2
3
-
-
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Electrical characteristics
Figure 68. Synchronous non-multiplexed NOR/PSRAM read timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKH-NExH)
d(CLKL-NExL)
Data latency = 0
d(CLKL-NADVH)
FMC_NEx
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
t
t
d(CLKH-AIV)
d(CLKL-AV)
t
t
d(CLKL-NOEL)
d(CLKH-NOEH)
FMC_NOE
t
t
su(DV-CLKH)
h(CLKH-DV)
t
t
h(CLKH-DV)
su(DV-CLKH)
FMC_D[15:0]
FMC_NWAIT
D1
D2
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
MS32759V1
(1)
Table 103. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
2Thclk - 0.5
-
2
-
t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
Thclk +0.5
-
0.5
-
0
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
3
-
Thclk
ns
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low
-
2
-
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high
Thclk -0.5
0.5
4
-
th(CLKH-DV)
FMC_D[15:0] valid data after FMC_CLK high
-
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
2
-
3
-
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1. Guaranteed by characterization results.
Figure 69. Synchronous non-multiplexed PSRAM write timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKL-NExL)
FMC_NEx
d(CLKH-NExH)
Data latency = 0
d(CLKL-NADVH)
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
FMC_NWE
t
d(CLKH-AIV)
t
t
d(CLKL-AV)
td(CLKH-NWEH)
d(CLKL-NWEL)
t
t
d(CLKL-Data)
d(CLKL-Data)
FMC_D[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FMC_NBL
t
t
d(CLKH-NBLH)
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
MS32760V1
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Electrical characteristics
(1)
Table 104. Synchronous non-multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
t(CLK)
FMC_CLK period
2Thclk - 0.5
-
2
-
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
Thclk +0.5
-
0.5
-
0
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
3
-
Thclk
ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
1. Guaranteed by characterization results.
-
1.5
-
Thclk +1
-
3
2
-
-
Thclk +1
2
-
3.5
-
NAND controller waveforms and timings
Figure 70 through Figure 73 represent synchronous waveforms, and Table 105 and
Table 106 provide the corresponding timings. The results shown in this table are obtained
with the following FMC configuration:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
COM.FMC_SetupTime = 0x01;
COM.FMC_WaitSetupTime = 0x03;
COM.FMC_HoldSetupTime = 0x02;
COM.FMC_HiZSetupTime = 0x01;
ATT.FMC_SetupTime = 0x01;
ATT.FMC_WaitSetupTime = 0x03;
ATT.FMC_HoldSetupTime = 0x02;
ATT.FMC_HiZSetupTime = 0x01;
Bank = FMC_Bank_NAND;
MemoryDataWidth = FMC_MemoryDataWidth_16b;
ECC = FMC_ECC_Enable;
ECCPageSize = FMC_ECCPageSize_512Bytes;
TCLRSetupTime = 0;
TARSetupTime = 0.
In all timing tables, the THCLK is the HCLK clock period.
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Figure 70. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
t
th(NOE-ALE)
d(ALE-NOE)
FMC_NOE (NRE)
FMC_D[15:0]
t
t
h(NOE-D)
su(D-NOE)
MS32767V1
Figure 71. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
h(NWE-ALE)
d(ALE-NWE)
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
t
t
h(NWE-D)
v(NWE-D)
MS32768V1
Figure 72. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
h(NOE-ALE)
d(ALE-NOE)
FMC_NWE
FMC_NOE
t
w(NOE)
t
t
h(NOE-D)
su(D-NOE)
FMC_D[15:0]
MS32769V1
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Figure 73. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
t
h(NOE-ALE)
d(ALE-NOE)
w(NWE)
FMC_NWE
FMC_N OE
t
d(D-NWE)
t
t
v(NWE-D)
h(NWE-D)
FMC_D[15:0]
MS32770V1
(1)
Table 105. Switching characteristics for NAND Flash read cycles
Symbol
Parameter
FMC_NOE low width
Min
Max
Unit
tw(N0E)
4Thclk -0.5 4Thclk +0.5
tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high
th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high
11
-
0
-
ns
td(ALE-NOE) FMC_ALE valid before FMC_NOE low
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid
1. Guaranteed by characterization results.
-
3Thclk +1.5
-
4Thclk - 2
(1)
Table 106. Switching characteristics for NAND Flash write cycles
Symbol
Parameter
FMC_NWE low width
Min
Max
Unit
tw(NWE)
tv(NWE-D)
th(NWE-D)
td(D-NWE)
td(ALE-NWE)
th(NWE-ALE)
4Thclk -0.5 4Thclk +0.5
FMC_NWE low to FMC_D[15-0] valid
FMC_NWE high to FMC_D[15-0] invalid
FMC_D[15-0] valid before FMC_NWE high
FMC_ALE valid before FMC_NWE low
FMC_NWE high to FMC_ALE invalid
0
-
2Thclk - 1
5Thclk - 1
-
-
ns
-
3Thclk +1.5
-
2Thclk - 2
1. Guaranteed by characterization results.
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Electrical characteristics
STM32F722xx STM32F723xx
SDRAM waveforms and timings
•
CL = 30 pF on data and address lines. CL = 10 pF on FMC_SDCLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period.
–
–
–
For 3.0 V≤ V ≤ 3.6 V, maximum FMC_SDCLK= 100 MHz at CL=20 pF (on
DD
FMC_SDCLK).
For 2.7 V≤ V ≤ 3.6 V, maximum FMC_SDCLK = 90 MHz at CL=30 pF (on
DD
FMC_SDCLK).
For 1.71 V≤ V <1.9 V, maximum FMC_SDCLK = 70 MHz at CL=10 pF (on
DD
FMC_SDCLK).
Figure 74. SDRAM read access waveforms (CL = 1)
FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR)
th(SDCLKL_AddR)
Row n
Col1
Col2
Coli
Coln
FMC_A[12:0]
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
th(SDCLKL_NCAS)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS)
th(SDCLKL_NRAS)
FMC_SDNRAS
FMC_SDNCAS
td(SDCLKL_NCAS)
FMC_SDNWE
FMC_D[31:0]
tsu(SDCLKH_Data)
th(SDCLKH_Data)
Data1 Data2 Datai
Datan
MS32751V2
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Symbol
Electrical characteristics
(1)
Table 107. SDRAM read timings
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data input setup time
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
2Thclk -0.5
2Thclk +0.5
tsu(SDCLKH _Data)
th(SDCLKH_Data)
td(SDCLKL_Add)
1.5
2
-
-
-
1.5
1.5
-
td(SDCLKL- SDNE)
th(SDCLKL_SDNE)
td(SDCLKL_SDNRAS)
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
th(SDCLKL_SDNCAS)
-
ns
0.5
-
1
0.5
-
-
1.5
-
0
1. Guaranteed by characterization results.
(1)
Table 108. LPSDR SDRAM read timings
Symbol
Parameter
Min
Max
Unit
tW(SDCLK)
FMC_SDCLK period
Data input setup time
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
2Thclk -0.5
2Thclk +0.5
tsu(SDCLKH_Data)
th(SDCLKH_Data)
td(SDCLKL_Add)
0
4.5
-
-
-
1.5
1.5
-
td(SDCLKL_SDNE)
th(SDCLKL_SDNE)
td(SDCLKL_SDNRAS
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
th(SDCLKL_SDNCAS)
-
ns
0
-
0.5
-
0
-
1.5
-
0
1. Guaranteed by characterization results.
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Figure 75. SDRAM write access waveforms
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddR)
td(SDCLKL_AddR)
Row n
Col1
Col2
Coli
Coln
FMC_A[12:0]
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS)
th(SDCLKL_NRAS)
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
th(SDCLKL_NCAS)
th(SDCLKL_NWE)
td(SDCLKL_NCAS)
td(SDCLKL_NWE)
td(SDCLKL_Data)
Data1
Data2
Datai
Datan
FMC_D[31:0]
td(SDCLKL_NBL)
FMC_NBL[3:0]
th(SDCLKL_Data)
MS32752V2
(1)
Table 109. SDRAM write timings
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
2Thclk -0.5
2Thclk +0.5
td(SDCLKL _Data
th(SDCLKL _Data)
td(SDCLKL_Add)
)
-
0
1.5
-
-
1.5
1.5
-
td(SDCLKL_SDNWE)
th(SDCLKL_SDNWE)
td(SDCLKL_ SDNE)
th(SDCLKL-_SDNE)
td(SDCLKL_SDNRAS)
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
td(SDCLKL_SDNCAS)
-
0.5
-
ns
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
1.5
-
0.5
-
1
0.5
-
-
1.5
-
0.5
1. Guaranteed by characterization results.
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Symbol
Electrical characteristics
(1)
Table 110. LPSDR SDRAM write timings
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
2Thclk -0.5
2Thclk +0.5
td(SDCLKL _Data
)
-
0
-
2
-
th(SDCLKL _Data)
td(SDCLKL_Add)
1.5
1.5
-
td(SDCLKL-SDNWE)
th(SDCLKL-SDNWE)
td(SDCLKL- SDNE)
th(SDCLKL- SDNE)
td(SDCLKL-SDNRAS)
th(SDCLKL-SDNRAS)
td(SDCLKL-SDNCAS)
td(SDCLKL-SDNCAS)
-
0
-
ns
0.5
-
0.
-
2
0
-
-
2
0
-
1. Guaranteed by characterization results.
6.3.31
Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 111 and Table 112 for Quad-SPI
are derived from tests performed under the ambient temperature, f frequency and V
AHB
DD
supply voltage conditions summarized in Table 16: General operating conditions, with the
following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 20 pF
Measurement points are done at CMOS levels: 0.5 ₓ V
DD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics.
(1)
Table 111. Quad-SPI characteristics in SDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7 V≤ VDD<3.6 V
-
-
108
CL=20 pF
Quad-SPI clock
frequency
Fck1/t(CK)
MHz
1.71 V<VDD<3.6 V
CL=15 pF
-
-
100
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Electrical characteristics
STM32F722xx STM32F723xx
(1)
Table 111. Quad-SPI characteristics (continued)in SDR mode (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tw(CKH)
tw(CKL)
ts(IN)
t(CK)/2 - 0.5
-
t(CK)/2 + 0.5
Quad-SPI clock high
and low time
-
t(CK)/2 - 0.5
-
-
t(CK)/2 + 0.5
Data input setup time
Data input hold time
3
1
-
-
-
th(IN)
-
ns
2.7 V<VDD<3.6 V
-
1.5
1.5
-
3
tv(OUT) Data output valid time
th(OUT) Data output hold time
1.71 V<VDD<3.6 V
-
-
2.5
-
0.5
1. Guaranteed by characterization results.
(1)
Table 112. Quad-SPI characteristics in DDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7 V<VDD<3.6 V
CL=20 pF
-
-
80
1.8 V<VDD<3.6 V
CL=15 pF
Fck1/t(CK) Quad-SPI clock frequency
-
-
-
80
80
MHz
1.71 V<VDD<3.6 V
CL=10 pF
-
-
-
t(CK)/2 -
0.5
t(CK)/2 +
0.5
tw(CKH)
Quad-SPI clock high and
-
low time
tw(CKL)
t(CK)/2 -
0.5
t(CK)/2 +
0.5
2.7 V<VDD<3.6 V
1.71 V<VDD<2 V
2.7 V<VDD<3.6 V
1.71 V<VDD<2 V
2.7 V<VDD<3.6 V
1
0.5
2.25
2.75
-
-
-
ts(IN),
Data input setup time
tsf(IN)
-
-
-
-
-
thr(IN),
Data input hold time
thf(IN)
-
ns
9.5
11.5
1.71 V<VDD<3.6 V
DHHC=0
-
9.5
12.25
tvr(OUT),
Data output valid time
tvf(OUT)
DHHC=1
Thclk/2 Thclk/2
-
+2
+2.5
Pres=1, 2...
DHHC=0
5.5
-
-
thr(OUT),
Data output hold time
thf(OUT)
DHHC=1
Thclk/2
+0.75
-
-
Pres=1, 2...
1. Guaranteed by characterization results.
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Electrical characteristics
Figure 76. Quad-SPI timing diagram - SDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tv(OUT)
th(OUT)
Data output
D0
D1
D2
ts(IN)
th(IN)
Data input
D0
D1
D2
MSv36878V1
Figure 77. Quad-SPI timing diagram - DDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tvf(OUT) thr(OUT)
D0
tvr(OUT)
thf(OUT)
D3
Data output
D1
D2
D4
tsr(IN)thr(IN)
D5
tsf(IN) thf(IN)
Data input
D0
D1
D2
D3
D4
D5
MSv36879V1
6.3.32
SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 113 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, f
frequency and V
PCLK2
DD
supply voltage conditions summarized in Table 16, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output
characteristics.
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Figure 78. SDIO high-speed mode
Figure 79. SD default mode
CK
t
t
OVD
OHD
D, CMD
(output)
ai14888
(1)
Table 113. Dynamic characteristics: SD / MMC characteristics, V =2.7V to 3.6V
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
-
tW(CKL)
tW(CKH)
Clock frequency in data transfer mode
SDMMC_CK/fPCLK2 frequency ratio
Clock low time
-
0
-
-
50
8/3
-
MHz
-
-
-
fpp =50 MHz
fpp =50 MHz
9
9
10
10
ns
ns
ns
Clock high time
-
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU
tIH
Input setup time HS
Input hold time HS
fpp =50 MHz
fpp =50 MHz
1
3
-
-
-
-
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV
tOH
Output valid time HS
Output hold time HS
fpp =50 MHz
fpp =50 MHz
-
11
-
12
-
9
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Electrical characteristics
(1)
Table 113. Dynamic characteristics: SD / MMC characteristics, V =2.7V to 3.6V (continued)
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CMD, D inputs (referenced to CK) in SD default mode
1
3
-
-
-
-
tISUD
tIHD
Input setup time SD
Input hold time SD
fpp =25 MHz
fpp =25 MHz
ns
CMD, D outputs (referenced to CK) in SD default mode
-
2
-
2.5
-
tOVD
tOHD
Output valid default time SD
Output hold default time SD
fpp =25 MHz
fpp =25 MHz
ns
0.5
1. Guaranteed by characterization results,.
(1)(2)
Table 114. Dynamic characteristics: eMMC characteristics, V =1.71V to 1.9V
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
-
tW(CKL)
tW(CKH)
Clock frequency in data transfer mode
SDMMC_CK/fPCLK2 frequency ratio
Clock low time
-
0
-
-
-
50
8/3
-
MHz
-
-
fpp =50 MHz
fpp =50 MHz
9.5
8.5
10.5
9.5
ns
ns
ns
Clock high time
-
CMD, D inputs (referenced to CK) in eMMC mode
tISU
tIH
Input setup time HS
Input hold time HS
fpp =50 MHz
fpp =50 MHz
0
-
-
-
-
4.5
CMD, D outputs (referenced to CK) in eMMC mode
tOV
tOH
Output valid time HS
Output hold time HS
fpp =50 MHz
fpp =50 MHz
-
12
-
14
-
10.5
1. Guaranteed by characterization results.
2. Cload = 20 pF.
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Package information
STM32F722xx STM32F723xx
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
7.1
LQFP64 – 10 x 10 mm, low-profile quad flat package
information
LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package.
Figure 80. LQFP64 outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
D1
D3
L
L1
33
48
32
49
64
b
17
16
1
PIN 1
e
IDENTIFICATION
5W_ME_V3
1. Drawing is not to scale.
Table 115. LQFP64 mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
-
-
-
1.60
0.15
1.45
-
-
0.0630
0.0059
0.0571
A1
A2
0.05
1.350
0.0020
0.0531
-
1.40
0.0551
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Package information
Table 115. LQFP64 mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
b
c
0.17
0.22
-
0.27
0.0067
0.0087
-
0.0106
0.09
0.20
0.0035
0.0079
D
-
12.00
10.00
7.50
12.00
10.00
7.50
0.50
3.5°
0.60
1.00
-
-
-
0.4724
0.3937
0.2953
0.4724
0.3937
0.2953
0.0197
3.5°
-
D1
D3
E
-
-
-
-
-
-
-
-
-
-
-
-
E1
E3
e
-
-
-
-
-
-
-
-
-
-
0°
0.45
-
-
-
7°
K
7°
0°
L
0.75
-
0.0177
0.0236
0.0394
-
0.0295
-
L1
ccc
-
-
-
0.08
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 81. LQFP64 recommended footprint
48
33
0.3
0.5
49
32
12.7
10.3
10.3
7.8
17
64
1.2
16
1
12.7
ai14909c
1. Dimensions are in millimeters.
DS11853 Rev 6
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Package information
STM32F722xx STM32F723xx
LQFP64 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 82. LQFP64 top view example
Product identification(1)
Revision code
R
STM32F722
RET6
Date code
Y WW
Pin 1
indentifier
MSv42090V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
204/229
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STM32F722xx STM32F723xx
Package information
7.2
LQFP100, 14 x 14 mm low-profile quad flat package
information
LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package.
Figure 83. LQFP100 outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
75
C
D
D1
D3
L
L1
51
50
76
100
26
PIN 1
IDENTIFICATION
25
1
e
1L_ME_V5
1. Drawing is not to scale.
Table 116. LQPF100 mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
16.200
14.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
-
0.050
1.350
0.170
0.090
15.800
13.800
-
-
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
16.000
14.000
12.000
16.000
0.6299
0.5512
0.4724
0.6299
D1
D3
E
15.800
16.200
0.6220
0.6378
DS11853 Rev 6
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Package information
Symbol
STM32F722xx STM32F723xx
Table 116. LQPF100 mechanical data (continued)
millimeters
Typ
inches(1)
Min
Max
Min
Typ
Max
E1
E3
e
13.800
14.000
12.000
0.500
0.600
1.000
3.5°
14.200
0.5433
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
0.5591
-
-
-
-
-
-
0.750
-
-
-
0.0295
-
L
0.450
0.0177
L1
k
-
0°
-
-
0°
-
7°
7°
ccc
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 84. LQFP100 recommended footprint
75
51
76
50
0.5
0.3
16.7 14.3
100
26
1.2
1
25
12.3
16.7
ai14906c
1. Dimensions are expressed in millimeters.
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DS11853 Rev 6
STM32F722xx STM32F723xx
Package information
LQFP100 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 85. LQFP100 top view example
(1)
Product identification
STM32F722
Revision code
VET6
R
Date code
Y WW
Pin 1 identifier
MS42091V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS11853 Rev 6
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225
Package information
STM32F722xx STM32F723xx
7.3
LQFP144, 20 x 20 mm low-profile quad flat package
information
LQFP144 is a 144-pin, 20 x 20 mm low-profile quad flat package.
Figure 86. LQFP144 outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
D1
D3
L
L1
108
73
109
72
37
144
1
36
PIN 1
IDENTIFICATION
e
1A_ME_V3
1. Drawing is not to scale.
Table 117. LQFP144 mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
A1
A2
b
-
-
-
1.600
0.150
1.450
0.270
0.200
22.200
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.874
0.050
1.350
0.170
0.090
21.800
0.0020
0.0531
0.0067
0.0035
0.8583
-
1.400
0.220
-
0.0551
0.0087
-
c
D
22.000
0.8661
208/229
DS11853 Rev 6
STM32F722xx STM32F723xx
Package information
Table 117. LQFP144 mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
D1
D3
E
19.800
20.000
17.500
22.000
20.000
17.500
0.500
0.600
1.000
3.5°
20.200
0.7795
0.7874
0.689
0.8661
0.7874
0.6890
0.0197
0.0236
0.0394
3.5°
0.7953
-
-
-
-
21.800
22.200
0.8583
0.8740
E1
E3
e
19.800
20.200
0.7795
0.7953
-
-
-
-
-
-
0.750
-
-
-
0.0295
-
L
0.450
0.0177
L1
k
-
0°
-
-
0°
-
7°
7°
ccc
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 87. LQFP144 recommended footprint
1.35
108
73
109
72
0.35
0.5
19.9
17.85
22.6
144
37
1
36
19.9
22.6
ai14905e
1. Dimensions are expressed in millimeters.
DS11853 Rev 6
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225
Package information
STM32F722xx STM32F723xx
LQP144 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 88. LQFP144 top view example
Revision code
(1)
Product identification
R
STM32F722ZET6
YWW
Date code
Pin 1
identifier
MS42092V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
210/229
DS11853 Rev 6
STM32F722xx STM32F723xx
Package information
7.4
LQFP176 24 x 24 mm low-profile quad flat package
information
LQFP176 is a 176-pin, 24 x 24 mm low-profile quad flat package.
Figure 89. LQFP176 outline
Seating plane
C
0.25 mm
gauge plane
k
A1
L
HD
L1
PIN 1
IDENTIFICATION
D
ZE
E
HE
e
ZD
b
1T_ME_V2
1. Drawing is not to scale.
Table 118. LQFP176 mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
A1
A2
b
-
-
-
-
-
-
-
1.600
0.150
1.450
0.270
0.200
24.100
-
-
-
-
-
-
-
0.0630
0.0059
0.0060
0.0106
0.0079
0.9488
0.050
1.350
0.170
0.090
23.900
0.0020
0.0531
0.0067
0.0035
0.9409
C
D
DS11853 Rev 6
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225
Package information
STM32F722xx STM32F723xx
Table 118. LQFP176 mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
E
e
23.900
-
24.100
0.9409
-
0.9488
-
0.500
-
-
0.0197
-
HD
HE
L
25.900
-
26.100
1.0200
-
1.0276
25.900
-
26.100
1.0200
-
1.0276
0.450
-
0.750
0.0177
-
0.0295
L1
ZD
ZE
ccc
k
-
-
1.000
1.250
1.250
-
-
-
-
0.0394
0.0492
0.0492
-
-
-
-
-
-
-
-
-
0.080
7 °
-
0.0031
7 °
0 °
-
0 °
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
212/229
DS11853 Rev 6
STM32F722xx STM32F723xx
Package information
Figure 90. LQFP176 recommended footprint
1.2
176
133
132
0.5
1
0.3
44
45
89
88
1.2
21.8
26.7
1T_FP_V1
1. Dimensions are expressed in millimeters.
DS11853 Rev 6
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225
Package information
STM32F722xx STM32F723xx
LQFP176 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 91. LQFP176 top view example
(1)
Product identification
STM32F722IET6
Revision code
Date code
Y WW
R
Pin 1
identifier
MS44207V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
214/229
DS11853 Rev 6
STM32F722xx STM32F723xx
Package information
7.5
UFBGA144 package information
UFBGA144 is a 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Figure 92. UFBGA144 outline
Z Seating plane
ddd Z
A4
A2
A
A3
A1
A
E1
X
A1 ball
A1 ball
E
identifier index area
e
F
F
D1
D
e
Y
M
12
1
Øb (144 balls)
Øeee M Z Y X
Øfff M Z
BOTTOM VIEW
TOP VIEW
A0AS_ME_V2
1. Drawing is not to scale.
Table 119. UFBGA144 mechanical data
millimeters
inches(1)
Typ.
Symbol
Min.
Typ.
Max.
Min.
Max.
A
A1
A2
A3
A4
b
0.460
0.050
0.400
-
0.530
0.080
0.450
0.130
0.320
0.280
7.000
5.500
7.000
5.500
0.500
0.750
0.600
0.110
0.500
-
0.0181
0.0020
0.0157
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0110
0.2756
0.2165
0.2756
0.2165
0.0197
0.0295
0.0236
0.0043
0.0197
-
0.270
0.230
6.950
5.450
6.950
5.450
-
0.370
0.320
7.050
5.550
7.050
5.550
-
0.0106
0.0091
0.2736
0.2146
0.2736
0.2146
-
0.0146
0.0126
0.2776
0.2185
0.2776
0.2185
-
D
D1
E
E1
e
F
0.700
0.800
0.0276
0.0315
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225
Package information
STM32F722xx STM32F723xx
Table 119. UFBGA144 mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
ddd
eee
fff
-
-
-
-
-
-
0.100
0.150
0.050
-
-
-
-
-
-
0.0039
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 93. UFBGA144 recommended footprint
Dpad
Dsm
A0AS_FP_V1
Table 120. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.50 mm
0.280 mm
0.370 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
0.280 mm
Between 0.100 mm and 0.125 mm
0.120 mm
216/229
DS11853 Rev 6
STM32F722xx STM32F723xx
Package information
UFBGA144 device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 94. UFBGA144 top view example
Product
STM32F
identification(1)
723ZEI6
Date code
Standard ST logo
Y WW
Revision code
Ball 1 identifier
R
MS44251V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS11853 Rev 6
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225
Package information
STM32F722xx STM32F723xx
7.6
UFBGA176+25, 10 x 10, 0.65 mm ultra thin-pitch ball grid
array package information
UFBGA176+25 is a 176+25-ball, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array
package
Figure 95. UFBGA176 outline
C
Seating plane
A2 A4
ddd
C
A
A1
b
A1 ball
index
area
A
A1 ball
identifier
E
e
F
A
R
F
D
e
B
15
1
Øb (176 + 25 balls)
BOTTOM VIEW
TOP VIEW
Ø eee M
Ø fff
C
C
A B
M
A0E7_ME_V6
1. Drawing is not to scale.
Table 121. UFBGA176+25 mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
0.460
0.050
0.400
0.230
9.950
9.950
-
0.530
0.080
0.450
0.280
10.000
10.000
0.650
0.450
-
0.600
0.110
0.500
0.330
10.050
10.050
-
0.0181
0.002
0.0157
0.0091
0.3917
0.3917
-
0.0209
0.0031
0.0177
0.0110
0.3937
0.3937
0.0256
0.0177
-
0.0236
0.0043
0.0197
0.0130
0.3957
0.3957
-
D
E
e
F
0.400
-
0.500
0.080
0.150
0.080
0.0157
-
0.0197
0.0031
0.0059
0.0031
ddd
eee
fff
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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DS11853 Rev 6
STM32F722xx STM32F723xx
Package information
Figure 96. UFBGA176+25 recommended footprint
Dpad
Dsm
A0E7_FP_V1
Table 122. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.65 mm
0.300 mm
0.400 mm typ. (depends on the soldermask reg-
istration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
0.300 mm
Between 0.100 mm and 0.125 mm
0.100 mm
DS11853 Rev 6
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225
Package information
STM32F722xx STM32F723xx
UFBGA176+25 device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 97. UFBGA176 top view example
Revision code
Product identification(1)
R
STM32F722
IEK6
Date code
Ball A1
indentifier
Y WW
MS44208V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
220/229
DS11853 Rev 6
STM32F722xx STM32F723xx
Package information
7.7
WLCSP100 - 0.4 mm pitch wafer level chip scale package
information
WLCSP100 is a 100-ball, 4.166 x 4.628 mm, 0.4 mm pitch wafer level chip scale package.
Figure 98. WLCSP100 outline
A1 BALL LOCATION
A
DETAIL A
K
BOTTOM VIEW
SIDE VIEW
FRONT VIEW
DETAIL A
ROTATED 90°
A1 ORIENTATION
REFERENCE
aaa
(4X)
TOP VIEW
WAFER BACK SIDE
WLCSP100L_A01Q_ME_V1
1. Drawing is not to scale.
DS11853 Rev 6
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Package information
STM32F722xx STM32F723xx
Table 123. WLCSP100 mechanical data
millimeters
Typ
inches(1)
Min
Symbol
Min
Max
Typ
Max
A
A1
A2
A3(2)
Ø b(3)
D
0.525
0.555
0.17
0.38
0.025
0.25
4.201
4.663
0.4
0.585
0.0207
0.0219
0.0067
0.0150
0.0010
0.0098
0.1654
0.1836
0.0157
0.1417
0.1417
0.0118
0.0209
3.9370
0.0039
0.0039
0.0039
0.0020
0.0020
0.0230
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.22
0.28
0.0110
4.166
4.236
0.1668
E
4.628
4.698
0.1850
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
e1
3.6
e2
3.6
F
0.3005
0.5315
100
G
N
aaa
bbb
ccc
ddd
eee
0.1
0.1
0.1
0.05
0.05
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Figure 99. WLCSP100 recommended footprint
Dpad
Dsm
WLCSP100L_A01Q_FP_V1
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DS11853 Rev 6
STM32F722xx STM32F723xx
Package information
Table 124. WLCSP100 recommended PCB design rules (0.4 mm pitch)
Dimension Recommended values
Pitch
0.4 mm
Dpad
0.225 mm
0.290 mm
0.1 mm
Dsm
Stencil thickness
DS11853 Rev 6
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225
Package information
STM32F722xx STM32F723xx
WLCSP100 device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 100. WLCSP100 top view example
Ball A1 identifier
Product identification(1)
32F723VEY6
Revision code
Y WW
R
MSv44209V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
224/229
DS11853 Rev 6
STM32F722xx STM32F723xx
Package information
7.8
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 125. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
48.5
47.1
35.85
45.6
43.9
42
Thermal resistance junction-ambient
LQFP100 - 14× 14 mm / 0.5 mm pitch
Thermal resistance junction-ambient
WLCSP100 - 0.4 mm pitch
Thermal resistance junction-ambient
LQFP144 - 20 × 20 mm / 0.5 mm pitch
ΘJA
°C/W
Thermal resistance junction-ambient
LQFP176 - 24 × 24 mm / 0.5 mm pitch
Thermal resistance junction-ambient
UFBGA144 - 7 × 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
UFBGA176 - 10× 10 mm / 0.65 mm pitch
41.2
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
DS11853 Rev 6
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Ordering information
STM32F722xx STM32F723xx
8
Ordering information
Table 126. Ordering information scheme
Example:
Device family
STM32
F
722 V C
T
6 xxx
STM32 = Arm-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
722 = STM32F722xx, no OTG PHY HS
723 = STM32F723xx, with OTG PHY HS
Pin count
R = 64 pins
V = 100 pins
Z = 144 pins
I = 176 pins
Flash memory size
C = 256 Kbytes of Flash memory
E = 512 Kbytes of Flash memory
Package
T = LQFP
K = UFBGA (10 x 10 mm)
I = UFBGA (7 x 7 mm)
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options
xxx = programmed parts
TR = tape and reel
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, contact the nearest ST sales office.
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DS11853 Rev 6
STM32F722xx STM32F723xx
Recommendations when using internal reset OFF
Appendix A
Recommendations when using internal reset
OFF
When the internal reset is OFF, the following integrated features are no longer supported:
•
•
•
•
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
The brownout reset (BOR) circuitry must be disabled.
The embedded programmable voltage detector (PVD) is disabled.
V
functionality is no more available and VBAT pin should be connected to V
.
BAT
DD
The over-drive mode is not supported.
A.1
Operating conditions
Table 127. Limitations depending on the operating power supply range
Maximum
Flash
Operating
power
supply
range
memory
access
frequency
Maximum Flash
memory access
frequency with
PossibleFlash
memory
operations
ADC
operation
I/O operation
with no wait wait states (1)(2)
states
(fFlashmax
)
Conversion
time up to
1.2 Msps
180 MHz with 8
wait states and
over-drive OFF
8-bit erase and
program
operations only
VDD =1.7 to
2.1 V(3)
– No I/O
compensation
20 MHz
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no
wait state is required.
2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states
given here does not impact the execution speed from the Flash memory since the ART accelerator or L1-
cache allows to achieve a performance equivalent to 0-wait state program execution.
3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to
Section 3.15.1: Internal reset ON).
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Revision history
STM32F722xx STM32F723xx
Revision history
Table 128. Document revision history
Changes
Date
Revision
03-Feb-2017
1
Initial release.
Updated cover with the maximum SPI speed at 54 Mbit/s.
30-Mar-2017
2
Updated Figure 15: STM32F722xx LQFP64 pinout.
Updated Figure 18: STM32F723xx WLCSP100 ballout (with OTG PHY
HS).
Updated note 1 below all the package device marking figures.
Updated Section 1: Introduction.
Updated Table 60: I/O current injection susceptibility note by ‘injection
is not possible’.
01-Jun-2017
3
Updated Table 67: ADC characteristics RADC min at 1.5 Kohm.
Updated Figure 47: Recommended NRST pin protection note about the
0.1uF capacitor.
Updated Table 78: DAC characteristics RLOAD feature.
Updated Figure 41: ACCHSI versus temperature.
Added Section 1: Introduction.
Removed memory mapping, transferred in the reference manual
(RM0431).
10-Apr-2018
4
Updated Table 10: STM32F722xx and STM32F723xx pin and ball
definition footnote 5 only for PC14, PC15, PH0, PH1.
Updated Table 125: Package thermal characteristics thermal values for
LQFP packages.
Updated Table 1: Device summary adding STM32F723VC.
Added LQFP100 package for STM32F723xx devices:
– Updated Table 2: STM32F722xx and STM32F723xx features and
peripheral counts.
– Updated Section 2.2: STM32F723xx versus STM32F722xx
LQFP100/ LQFP144/ LQFP176 packages.
– Added Figure 3: Compatible board design for LQFP100 package.
– Added Figure 17: STM32F723xx LQFP100 pinout.
23-Mar-2020
5
– Updated Table 10: STM32F722xx and STM32F723xx pin and ball
definition
Added VDDPHYS
– Updated Figure 6: STM32F722xx and STM32F723xx block diagram.
– Updated Figure 29: STM32F723xx power supply scheme.
– Updated Table 13: Voltage characteristics
– Updated Table 16: General operating conditions
Updated Section 7: Package information.
Updated Table 53: Flash memory programming maximum
programming voltage (Vprog) for 32-bit Flash program operation at 3.6V
(instead of 3V).
06-Apr-2020
6
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STM32F722xx STM32F723xx
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