STM32F446ZE [STMICROELECTRONICS]
ARM Cortex-M4 32b MCUFPU, 225DMIPS, up to 512kB Flash/1284KB RAM, USB OTG HS/FS, 17 TIMs, 3 ADCs, 20 comm. interfaces;
| 型号： | STM32F446ZE |
| 厂家： | 
ST |
| 描述： | ARM Cortex-M4 32b MCUFPU, 225DMIPS, up to 512kB Flash/1284KB RAM, USB OTG HS/FS, 17 TIMs, 3 ADCs, 20 comm. interfaces |
| 文件： | 总202页 (文件大小：3058K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32F446xC/E
ARM® Cortex®-M4 32b MCU+FPU, 225DMIPS, up to 512kB Flash/128+4KB RAM,
USB OTG HS/FS, 17 TIMs, 3 ADCs, 20 comm. interfaces
Datasheet - production data
Features
&"'!
®
®
• Core: ARM 32-bit Cortex -M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Fl ash memory, frequency up to 180 MHz,
MPU, 225 DMIPS/1.25 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
• Memories
LQFP64 (10 × 10mm)
LQFP100 (14 × 14mm)
LQFP144 (20 x 20 mm)
UFBGA144 (7 x 7 mm)
UFBGA144 (10 x 10 mm)
WLCSP 81
• Up to 114 I/O ports with interrupt capability
– Up to 111 fast I/Os up to 90 MHz
– Up to 112 5 V-tolerant I/Os
• Up to 20 communication interfaces
– SPDIF-Rx
– 512 kB of Flash memory
– 128 KB of SRAM
– Flexible external memory controller with up
to 16-bit data bus:
2
– Up to 4 × I C interfaces (SMBus/PMBus)
– Up to 4 USARTs/2 UARTs (11.25 Mbit/s,
ISO7816 interface, LIN, IrDA, modem
control)
– Up to 4 SPIs (45 Mbits/s), 3 with muxed I S
for audio class accuracy via internal audio
PLL or external clock
SRAM,PSRAM,SDRAM/LPSDR SDRAM,
Flash NOR/NAND memories
2
– Dual mode Quad SPI interface
• LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 2 x SAI (serial audio interface)
– 2 × CAN (2.0B Active)
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– SDIO interface
– Consumer electronics control (CEC) I/F
• Advanced connectivity
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
• Low power
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
– Dedicated USB power rail enabling on-chip
PHYs operation throughout the entire MCU
power supply range
– Sleep, Stop and Standby modes
– V
supply for RTC, 20×32 bit backup
BAT
registers + optional 4 KB backup SRAM
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels
and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
• Up to 17 timers: 2x watchdog, 1x SysTick timer
and up to twelve 16-bit and two 32-bit timers up
to 180 MHz, each with up to 4 IC/OC/PWM or
pulse counter
• 8- to 14-bit parallel camera interface up to
54 Mbytes/s
• CRC calculation unit
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID
Table 1. Device summary
• Debug mode
Reference
Part number
– SWD & JTAG interfaces
– Cortex -M4 Trace Macrocell™
STM32F446MC, STM32F446ME,
STM32F446RC, STM32F446RE,
STM32F446VC, STM32F446VE,
STM32F446ZC, STM32F446ZE.
®
STM32F446xC/E
September 2016
DocID027107 Rev 6
1/202
This is information on a product in full production.
www.st.com
Contents
STM32F446xC/E
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
Compatibility with STM32F4 family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
ARM® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . 17
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 17
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 18
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 21
3.12 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.13 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.16.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.16.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.17.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 27
3.18 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 28
3.19 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.20
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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3.21.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.21.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.21.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.21.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.21.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.21.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.22 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.23 Universal synchronous/asynchronous receiver transmitters (USART) . . 34
3.24 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.25 HDMI (high-definition multimedia interface) consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.26 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.27 SPDIF-RX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . 35
3.28 Serial Audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.29 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.30 Serial Audio Interface PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.31 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 36
3.32 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.33 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 37
3.34 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 37
3.35 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.36 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.37 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.38 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.39 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.40 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.41 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4
5
6
Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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STM32F446xC/E
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
VCAP_1/VCAP_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Operating conditions at power-up / power-down (regulator ON) . . . . . . 79
Operating conditions at power-up / power-down (regulator OFF) . . . . . 79
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 80
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 101
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 110
6.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 116
6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.19 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.20 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.21 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.3.23
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
BAT
6.3.24 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.25 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.26 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.27 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 172
6.3.28 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 173
6.3.29 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
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7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
7.1
7.2
7.3
7.4
7.5
7.6
7.7
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
LQFP144 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
UFBGA144 7 x 7 mm package information . . . . . . . . . . . . . . . . . . . . . . 186
UFBGA144 10 x 10 mm package information . . . . . . . . . . . . . . . . . . . . 189
WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
A.1
A.2
USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 197
USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 199
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
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List of figures
STM32F446xC/E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Compatible board for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
STM32F446xC/E block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STM32F446xC/E and Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 23
Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 24
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Startup in regulator OFF: slow V slope
DD
power-down reset risen after V
/V
stabilization . . . . . . . . . . . . . . . . . . . . . . . . . 27
CAP_1 CAP_2
Figure 9.
Startup in regulator OFF mode: fast V slope
DD
power-down reset risen before V
/V
stabilization. . . . . . . . . . . . . . . . . . . . . . . . 27
CAP_1 CAP_2
Figure 10. STM32F446xC/xE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 11. STM32F446xC/xE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 12. STM32F446xC LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 13. STM32F446xC/xE WLCSP81 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 14. STM32F446xC/xE UFBGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 15. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 16. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 17. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 18. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 19. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 20. External capacitor C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
EXT
Figure 21. Typical V
current consumption
BAT
(RTC ON/backup RAM OFF and LSE in low power mode) . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 22. Typical V current consumption
BAT
(RTC ON/backup RAM OFF and LSE in high drive mode). . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 23. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 24. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 25. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 26. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 27. LACC
versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
HSI
Figure 28. ACC versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
LSI
Figure 29. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 30. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 31. FT I/O input characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 32. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 33. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
2
Figure 34. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
2
Figure 35. FMPI C timing diagram and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 36. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 37. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 38. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
2
(1)
Figure 39. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
2
(1)
Figure 40. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 41. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 42. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 43. USB OTG full speed timings: definition of data signal rise and fall time. . . . . . . . . . . . . . 138
Figure 44. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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List of figures
Figure 45. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 46. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 47. Power supply and reference decoupling (V
Figure 48. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . 146
). . . . . . . . . . . . . . . . 147
REF+
DDA
connected to V
REF+
DDA
Figure 49. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 50. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 153
Figure 51. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 155
Figure 52. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 53. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 54. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 55. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 56. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 57. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 58. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 59. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 60. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 168
Figure 61. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 168
Figure 62. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 63. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 64. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 65. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 66. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 67. LQFP64-10x10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 176
Figure 68. LQFP64 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 69. LQFP64 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 70. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 179
Figure 71. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 72. LQFP100 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 73. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 182
Figure 74. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 75. LQFP144 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 76. UFBGA144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 77. UFBGA144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 78. UQFP144 7 x 7 mm marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 79. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 80. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 81. UQFP144 10 x 10 mm marking example (package top view). . . . . . . . . . . . . . . . . . . . . . 191
Figure 82. WLCSP81 - 81-pin, 3.693 x 3.815 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 83. WLCSP81- 81-pin, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 84. WLCSP81 10 x 10 mm marking example (package top view) . . . . . . . . . . . . . . . . . . . . . 194
Figure 85. USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . 197
Figure 86. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 197
Figure 87. USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 198
Figure 88. USB controller configured as peripheral, host, or dual-mode
and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
DocID027107 Rev 6
7/202
7
List of tables
STM32F446xC/E
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F446xC/E features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 25
Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 27
Voltage regulator modes in stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
STM32F446xx pin and ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
STM32F446xC/E register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 78
VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Operating conditions at power-up/power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . . 79
Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 79
reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM. . . . . . . 83
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled with prefetch) or RAM . . . . . . . . . 84
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 86
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 89
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 90
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Typical and maximum current consumptions in V
mode. . . . . . . . . . . . . . . . . . . . . . . . 91
BAT
Typical current consumption in Run mode, code with data processing
running from Flash memory or RAM, regulator ON
(ART accelerator enabled except prefetch), VDD=1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Typical current consumption in Run mode, code with data processing running
Table 31.
from Flash memory, regulator OFF (ART accelerator enabled except prefetch). . . . . . . . 94
Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V . . . . . . . . . . . . . . 95
Typical current consumption in Sleep mode, regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . 96
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
LSE
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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List of tables
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Flash memory programming with V
PP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
2
FMPI C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
QSPI dynamic characteristics in SDR Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
QSPI dynamic characteristics in DDR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
2
I S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
ADC static accuracy at f
ADC static accuracy at f
ADC static accuracy at f
= 18 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
= 30 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
= 36 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
ADC
ADC
ADC
ADC dynamic accuracy at f
ADC dynamic accuracy at f
= 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 143
= 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 143
ADC
ADC
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
BAT
internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Asynchronous non-multiplexed SRAM/PSRAM/NOR -
read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Asynchronous non-multiplexed SRAM/PSRAM/NOR read -
Table 87.
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 155
Asynchronous non-multiplexed SRAM/PSRAM/NOR write -
Table 88.
Table 89.
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 157
Table 90.
Table 91.
DocID027107 Rev 6
9/202
10
List of tables
STM32F446xC/E
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 159
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 164
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 100. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 101. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 102. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 103. LPSDR SDRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 104. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 105. Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 106. Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V. . . . . . . . . . . . . . . 175
Table 107. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 108. LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . 176
Table 109. LQPF100, 14 x 14 mm 100-pin low-profile quad flat
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 110. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 183
Table 111. UFBGA144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 112. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) . . . . . . . . . . . . . . . . 187
Table 113. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 114. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 190
Table 115. WLCSP81- 81-pin, 3.693 x 3.815 mm, 0.4 mm pitch wafer level chip scale
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 116. WLCSP81 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 193
Table 117. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 118. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 119. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
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DocID027107 Rev 6
STM32F446xC/E
Introduction
1
Introduction
This document provides the description of the STM32F446xC/E products.
The STM32F446xC/E document should be read in conjunction with the STM32F4xx
reference manual.
®
®
For information on the Cortex -M4 core, please refer to the Cortex -M4 programming
manual (PM0214), available from the www.st.com.
DocID027107 Rev 6
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40
Description
STM32F446xC/E
2
Description
®
®
The STM32F446xC/E devices are based on the high-performance ARM Cortex -M4 32-bit
RISC core operating at a frequency of up to 180 MHz. The Cortex-M4 core features a
®
Floating point unit (FPU) single precision which supports all ARM single-precision data-
processing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
The STM32F446xC/E devices incorporate high-speed embedded memories (Flash memory
up to 512 Kbyte, up to 128 Kbyte of SRAM), up to 4 Kbytes of backup SRAM, and an
extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB
buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers.
They also feature standard and advanced communication interfaces.
2
•
•
Up to four I Cs;
2
2
Four SPIs, three I Ss full simplex. To achieve audio class accuracy, the I S peripherals
can be clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization;
•
•
Four USARTs plus two UARTs;
An USB OTG full-speed and an USB OTG high-speed with full-speed capability (with
the ULPI), both with dedicated power rails allowing to use them throughout the entire
power range;
•
•
Two CANs;
Two SAIs serial audio interfaces. To achieve audio class accuracy, the SAIs can be
clocked via a dedicated internal audio PLL;
•
•
•
•
•
An SDIO/MMC interface;
Camera interface;
HDMI-CEC;
SPDIF Receiver (SPDIFRx);
QuadSPI.
Advanced peripherals include an SDIO, a flexible memory control (FMC) interface, a
camera interface for CMOS sensors. Refer to Table 2: STM32F446xC/E features and
peripheral counts for the list of peripherals available on each part number.
The STM32F446xC/E devices operates in the –40 to +105 °C temperature range from a 1.7
to 3.6 V power supply.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor
(refer to Section 3.16.2: Internal reset OFF). A comprehensive set of power-saving mode
allows the design of low-power applications.
The STM32F446xC/E devices offer devices in 6 packages ranging from 64 pins to 144 pins.
The set of included peripherals changes with the device chosen.
12/202
DocID027107 Rev 6
STM32F446xC/E
Description
These features make the STM32F446xC/E microcontrollers suitable for a wide range of
applications:
•
•
•
•
•
•
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Table 2. STM32F446xC/E features and peripheral counts
STM32F44 STM32F44 STM32F44 STM32F44 STM32F44 STM32F44 STM32F44 STM32F44
Peripherals
6MC
6ME
6RC
6RE
6VC
6VE
6ZC
6ZE
Flash memory in Kbytes
256
512
256
512
256
512
256
512
System
128 (112+16)
SRAM in
Kbytes
Backup
4
(1)
FMC memory controller
No
Yes
General-
purpose
10
2
Timers
Advanced-
control
Basic
2
4/3 (simplex)
4/1 FMP +
4/2
2
(2)
SPI / I S
2
I C
USART/UART
USB OTG FS
USB OTG HS
CAN
Yes (6-Endpoints)
Yes (8-Endpoints)
Communication
interfaces
2
2
SAI
SDIO
Yes
1
SPDIF-Rx
HDMI-CEC
1
(3)
Quad SPI
1
Camera interface
GPIOs
Yes
63
14
50
16
81
16
114
24
3
12-bit ADC
Number of channels
12-bit DAC
Number of channels
Yes
2
Maximum CPU frequency
Operating voltage
180 MHz
(4)
1.8 to 3.6 V
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to + 125 °C
Operating temperatures
Packages
LQFP144
UFBGA144
WLCSP81
LQFP64
LQFP100
DocID027107 Rev 6
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40
Description
STM32F446xC/E
1. For the LQFP100 package, only FMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the
NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used
since Port G is not available in this package.
2. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3. For the LQFP64 package, the Quad SPI is available with limited features.
4.
V
/V
minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external
DD DDA
power supply supervisor (refer to Section 3.16.2: Internal reset OFF).
2.1
Compatibility with STM32F4 family
The STM32F446xC/xV is software and feature compatible with the STM32F4 family.
The STM32F446xC/xV can be used as drop-in replacement of the other STM32F4 products
but some slight changes have to be done on the PCB board.
Figure 1. Compatible board design for LQFP100 package
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14/202
DocID027107 Rev 6
STM32F446xC/E
Description
Figure 2. Compatible board for LQFP64 package
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Figure 3 shows the STM32F446xx block diagram.
DocID027107 Rev 6
15/202
40
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Figure 3. STM32F446xC/E block diagram
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16/202
DocID027107 Rev 6
STM32F446xC/E
Functional overview
3
Functional overview
3.1
ARM® Cortex®-M4 with FPU and embedded Flash and SRAM
®
®
The ARM Cortex -M4 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
®
®
The ARM Cortex -M4 with FPU core is a 32-bit RISC processor that features exceptional
code-efficiency, delivering the high-performance expected from an ARM core in the memory
size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F446xC/E family is compatible with all ARM tools and software.
Figure 3 shows the general block diagram of the STM32F446xC/E family.
Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core.
Note:
3.2
Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
®
®
standard ARM Cortex -M4 with FPU processors. It balances the inherent performance
®
®
advantage of the ARM Cortex -M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 225 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 180 MHz.
3.3
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
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Functional overview
STM32F446xC/E
3.4
3.5
Embedded Flash memory
The devices embed a Flash memory of 512KB available for storing programs and data.
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
3.6
3.7
Embedded SRAM
All devices embed:
•
•
Up to 128Kbytes of system SRAM.
RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.
4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, USB HS) and
the slaves Flash memory, RAM, QuadSPI, FMC, AHB and APB peripherals and ensures a
seamless and efficient operation even when several high-speed peripherals work
simultaneously.
18/202
DocID027107 Rev 6
STM32F446xC/E
Functional overview
Figure 4. STM32F446xC/E and Multi-AHB matrix
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3.8
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
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Functional overview
STM32F446xC/E
The DMA can be used with the main peripherals:
2
•
•
•
•
•
•
•
•
•
•
•
SPI and I S
2
I C
USART
General-purpose, basic and advanced-control timers TIMx
DAC
SDIO
Camera interface (DCMI)
ADC
SAI1/SAI2
SPDIF Receiver (SPDIFRx)
QuadSPI
3.9
Flexible memory controller (FMC)
All devices embed an FMC. It has seven Chip Select outputs supporting the following
modes: SDRAM/LPSDR SDRAM, SRAM, PSRAM, NOR Flash and NAND Flash. With the
possibility to remap FMC bank 1 (NOR/PSRAM 1 and 2) and FMC SDRAM bank 1/2 in the
Cortex-M4 code area.
Functionality overview:
•
•
•
•
8-,16-bit data bus width
Read FIFO for SDRAM controller
Write FIFO
Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is 90 MHz.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.10
Quad SPI memory interface (QUADSPI)
All devices embed a Quad SPI memory interface, which is a specialized communication
interface targeting Single, Dual or Quad SPI flash memories. It can work in direct mode
through registers, external flash status register polling mode and memory mapped mode.
Up to 256 Mbytes external flash are memory mapped, supporting 8, 16 and 32-bit access.
Code execution is supported. The opcode and the frame format are fully programmable.
Communication can be either in Single Data Rate or Dual Data Rate.
20/202
DocID027107 Rev 6
STM32F446xC/E
Functional overview
3.11
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
®
and handle up to 91 maskable interrupt channels plus the 16 interrupt lines of the Cortex -
M4 with FPU core.
•
•
•
•
•
•
•
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.12
3.13
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 114 GPIOs can be connected
to the 16 external interrupt lines.
Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16
MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The application
can then select as system clock either the RC oscillator or an external 4-26 MHz clock
source. This clock can be monitored for failure. If a failure is detected, the system
automatically switches back to the internal RC oscillator and a software interrupt is
generated (if enabled). This clock source is input to a PLL thus allowing to increase the
frequency up to 180 MHz. Similarly, full interrupt management of the PLL clock entry is
available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 180 MHz while the maximum frequency of the high-speed APB domains is
90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.
The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio
2
class performance. In this case, the I S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
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Functional overview
STM32F446xC/E
3.14
Boot modes
At startup, boot pins are used to select one out of three boot options:
•
•
•
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory
2
through a serial (UART, I C, CAN, SPI and USB) communication interface. Refer to
application note AN2606 for details.
3.15
Power supply schemes
•
V
= 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
DD
enabled), provided externally through V pins.
DD
•
V
, V
= 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
DDA
SSA
blocks, RCs and PLL. V
and V
must be connected to V and V , respectively.
DDA
SSA DD SS
Note:
V
/V
minimum value of 1.7 V is obtained with the use of an external power supply
DD DDA
supervisor (refer to Section 3.16.2: Internal reset OFF). Refer to Table 3: Voltage regulator
configuration mode versus device operating mode to identify the packages supporting this
option.
•
V
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
BAT
backup registers (through power switch) when V is not present.
DD
•
V
can be connected either to VDD or an external independent power supply (3.0
DDUSB
to 3.6V) for USB transceivers.
For example, when device is powered at 1.8V, an independent power supply 3.3V can
be connected to V
. When the V
is connected to a separated power supply,
DDUSB
DDUSB
it is independent from V or V
but it must be the last supply to be provided and the
DD
DDA
first to disappear. The following conditions VDDUSB must be respected:
–
–
During power-on phase (V < VDD_MIN), VDDUSB should be always lower than
VDD
DD
During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower
than VDD
–
–
VDDUSB rising and falling time rate specifications must be respected.
In operating mode phase, V
could be lower or higher than VDD:
DDUSB
– If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
are operating between V and V .The V
V
DDUSB
DDUSB_MIN
DDUSB_MAX
DDUSB
supply both USB transceiver (USB OTG_HS and USB OTG_FS).
– If only one USB transceiver is used in the application, the GPIOs associated to
the other USB transceiver are still supplied by V
.
DDUSB
– If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered
by V are operating between V and V
.
DD_MAX
DDUSB
DD_MIN
22/202
DocID027107 Rev 6
STM32F446xC/E
Functional overview
Figure 5. V
connected to an external independent power supply
DDUSB
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3.16
Power supply supervisor
3.16.1
Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other package, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when V is below a specified threshold,
DD
V
or V
, without the need for an external reset circuit.
POR/PDR
BOR
The device also features an embedded programmable voltage detector (PVD) that monitors
the V /V power supply and compares it to the V threshold. An interrupt can be
DD DDA
PVD
generated when V /V
drops below the V
threshold and/or when V /V
is
DD DDA
PVD
DD DDA
higher than the V
threshold. The interrupt service routine can then generate a warning
PVD
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.16.2
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor V and should maintain the device in
DD
reset mode as long as V is below a specified threshold. PDR_ON should be connected to
DD
VSS, to allows device to operate down to 1.7v. Refer to Figure 6: Power supply supervisor
interconnection with internal reset OFF.
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Functional overview
STM32F446xC/E
Figure 6. Power supply supervisor interconnection with internal reset OFF
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The V specified threshold, below which the device must be maintained under reset, is
DD
1.7 V.
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
•
•
•
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
The brownout reset (BOR) circuitry must be disabled
The embedded programmable voltage detector (PVD) is disabled
V
functionality is no more available and V
pin should be connected to V
.
DD
BAT
BAT
All packages, except for the LQFP100/LQFP64, allow to disable the internal reset through
the PDR_ON signal.
3.17
3.17.1
24/202
Voltage regulator
The regulator has four operating modes:
•
Regulator ON
–
–
–
Main regulator mode (MR)
Low power regulator (LPR)
Power-down
•
Regulator OFF
Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
DocID027107 Rev 6
STM32F446xC/E
Functional overview
There are three power modes configured by software when the regulator is ON:
•
MR mode used in Run/sleep modes or in Stop modes
–
In Run/Sleep mode
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). Different voltages scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
The over-drive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
–
In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).
•
•
LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
–
–
LPR operates in normal mode (default mode when LPR is ON)
LPR operates in under-drive mode (reduced leakage mode).
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on V
All packages have the regulator ON feature.
and V
pin.
CAP_1
CAP_2
(1)
Table 3. Voltage regulator configuration mode versus device operating mode
Voltage regulator
Run mode
Sleep mode
Stop mode
Standby mode
configuration
Normal mode
MR
MR
-
MR
MR
-
MR or LPR
-
Over-drive
mode(2)
-
-
-
Under-drive mode
MR or LPR
-
Power-down
mode
-
-
Yes
1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.
3.17.2
Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V voltage source through V
and V
pins.
12
CAP_1
CAP_2
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Functional overview
STM32F446xC/E
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. The two 2.2 µF ceramic capacitors should
be replaced by two 100 nF decoupling capacitors.
When the regulator is OFF, there is no more internal monitoring on V . An external power
12
supply supervisor should be used to monitor the V of the logic power domain. PA0 pin
12
should be used for this purpose, and act as power-on reset on V power domain.
12
In regulator OFF mode, the following features are no more supported:
•
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V logic power
domain which is not reset by the NRST pin.
12
•
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
•
The over-drive and under-drive modes are not available.
Figure 7. Regulator OFF
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The following conditions must be respected:
•
V
should always be higher than V
and V
to avoid current injection
CAP_2
DD
CAP_1
between power domains.
•
If the time for V and V
to reach V minimum value is faster than the time for
CAP_1
CAP_2
12
V
to reach 1.7 V, then PA0 should be kept low to cover both conditions: until V
DD
CAP_1
and V
reach V minimum value and until V reaches 1.7 V (see Figure 8).
12 DD
CAP_2
•
•
Otherwise, if the time for V
and V
to reach V minimum value is slower
CAP_2 12
CAP_1
than the time for V to reach 1.7 V, then PA0 could be asserted low externally (see
DD
Figure 9).
If V
and V
go below V minimum value and V is higher than 1.7 V, then a
CAP_2 12 DD
CAP_1
reset must be asserted on PA0 pin.
Note:
The minimum value of V depends on the maximum frequency targeted in the application.
12
26/202
DocID027107 Rev 6
STM32F446xC/E
Functional overview
Figure 8. Startup in regulator OFF: slow V slope
DD
power-down reset risen after V
/V
stabilization
CAP_1 CAP_2
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1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 9. Startup in regulator OFF mode: fast V slope
DD
power-down reset risen before V
/V
stabilization
CAP_1 CAP_2
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1. This figure is valid whatever the internal reset mode (ON or OFF).
3.17.3
Regulator ON/OFF and internal reset ON/OFF availability
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
Package
LQFP64
LQFP100
Regulator ON
Regulator OFF Internal reset ON Internal reset OFF
Yes
No Yes No
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Functional overview
STM32F446xC/E
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
Package
Regulator ON
Regulator OFF Internal reset ON Internal reset OFF
LQFP144
UFBGA144
WLCSP81
Yes
No
Yes
Yes
PDR_ON
set to VDD
PDR_ON
set to VSS
Yes
Yes
BYPASS_REG
set to Vss
BYPASS_REG
set to VDD
3.18
Real-time clock (RTC), backup SRAM and backup registers
The backup domain includes:
•
•
•
The real-time clock (RTC)
4 Kbytes of backup SRAM
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC provides a programmable alarm and programmable
periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is
also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data
which need to be retained in VBAT and standby mode. This memory area is disabled by
default to minimize power consumption (see Section 3.19: Low-power modes). It can be
enabled by software.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when V power is not present. Backup registers are not reset by a system, a power reset,
DD
or when the device wakes up from the Standby mode (see Section 3.19: Low-power
modes).
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the V supply when present or from the V
pin.
DD
BAT
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3.19
Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
•
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator
modes in stop mode):
–
–
Normal mode (default mode when MR or LPR is enabled)
Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup).
Table 5. Voltage regulator modes in stop mode
Voltage regulator
Main regulator (MR)
Low-power regulator (LPR)
configuration
Normal mode
MR ON
LPR ON
Under-drive mode
MR in under-drive mode
LPR in under-drive mode
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event
occurs.
The standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.
3.20
VBAT operation
The V
pin allows to power the device V
domain from an external battery, an external
BAT
BAT
supercapacitor, or from V when no external battery and an external supercapacitor are
DD
present.
V
operation is activated when V is not present.
DD
BAT
The V
pin supplies the RTC, the backup registers and the backup SRAM.
BAT
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STM32F446xC/E
Note:
When the microcontroller is supplied from V , external interrupts and RTC alarm/events
BAT
do not exit it from V
operation.
BAT
When PDR_ON pin is not connected to V (Internal Reset OFF), the V
functionality is
DD
BAT
no more available and V
pin should be connected to VDD.
BAT
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Functional overview
3.21
Timers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
Table 6. Timer feature comparison
Max
Max
timer
DMA
request
generation channels
Capture/
compare
Timer
type
Counter
resolution
Counter Prescaler
Complementary interface
Timer
type
factor
output
clock
(MHz)
clock
(MHz)(1)
Up,
Down,
Up/down and 65536
Anyinteger
between 1
Advanced- TIM1,
16-bit
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
Yes
Yes
Yes
No
4
4
4
2
1
2
1
0
Yes
No
No
No
No
No
No
No
90
45
45
90
90
45
45
45
180
control
TIM8
Up,
Down,
Up/down and 65536
Anyinteger
between 1
TIM2,
TIM5
90/180
90/180
180
Up,
Down,
Up/down and 65536
Anyinteger
between 1
TIM3,
TIM4
Anyinteger
between 1
and 65536
TIM9
Up
Up
Up
Up
Up
General
purpose
Anyinteger
between 1
and 65536
TIM10,
TIM11
No
180
Anyinteger
between 1
and 65536
TIM12
No
90/180
90/180
90/180
Anyinteger
between 1
and 65536
TIM13,
TIM14
No
Anyinteger
between 1
and 65536
TIM6,
TIM7
Basic
Yes
1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR
register.
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3.21.1
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
•
•
•
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.21.2
General-purpose timers (TIMx)
There are ten synchronized general-purpose timers embedded in the STM32F446xC/E
devices (see Table 6 for differences).
•
TIM2, TIM3, TIM4, TIM5
The STM32F446xC/E include 4 full-featured general-purpose timers: TIM2, TIM5,
TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-
bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives
up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•
TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
3.21.3
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
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3.21.4
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.21.5
3.21.6
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
•
•
•
•
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
3.22
Inter-integrated circuit interface (I2C)
Four I²C bus interfaces can operate in multimaster and slave modes. Three I²C can support
the standard (up to 100 KHz) and fast (up to 400 KHz) modes.
One I²C can support the standard (up to 100 KHz), fast (up to 400 KHz) and fast mode plus
(up to 1MHz) modes.
They (all I²C) support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as
slave).
A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 7).
Table 7. Comparison of I2C analog and digital filters
-
Analog filter
Digital filter
Pulse width of
suppressed spikes
Programmable length from 1 to 15
I2C peripheral clocks
≥ 50 ns
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3.23
Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, and UART5).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate
at up to 5.62 bit/s.
USART1, USART2, USART3 and USART6 also provide hardware management of the CTS
and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.
(1)
Table 8. USART feature comparison
Max. baud
Max. baud
SPI
LIN maste
r
USART Standard
Modem
irD Smartcard rate in Mbit/s rate in Mbit/s
APB
name
features (RTS/CTS)
A
(ISO 7816) (oversamplin (oversamplin mapping
g by 16)
g by 8)
APB2
(max.
90 MHz)
USART1
USART2
USART3
UART4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
X
X
-
5.62
11.25
APB1
(max.
45 MHz)
2.81
2.81
2.81
2.81
5.62
5.62
5.62
5.62
5.62
11.25
APB1
(max.
45 MHz)
APB1
(max.
45 MHz)
APB1
(max.
45 MHz)
UART5
-
-
APB2
(max.
USART6
X
X
90 MHz)
1. X = feature supported.
3.24
Serial peripheral interface (SPI)
The devices feature up to four SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, and SPI4 can communicate at up to 45 Mbits/s, SPI2 and
SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
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The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.
3.25
3.26
HDMI (high-definition multimedia interface) consumer
electronics control (CEC)
The devices embeds a HDMI-CEC controller that provides hardware support of consumer
electronics control (CEC) (Appendix supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead.
Inter-integrated sound (I2S)
2
Three standard I S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in master or slave mode, in simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
2
I S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
3.27
SPDIF-RX Receiver Interface (SPDIFRX)
The SPDIF-RX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main features of the SPDIF-RX are the following:
•
•
•
•
•
•
•
•
•
Up to 4 inputs available
Automatic symbol rate detection
Maximum symbol rate: 12.288 MHz
Stereo stream from 32 to 192 kHz supported
Supports Audio IEC-60958 and IEC-61937, consumer applications
Parity bit management
Communication using DMA for audio samples
Communication using DMA for control and user channel information
Interrupt capabilities
The SPDIF-RX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream.
The user can select the wanted SPDIF input, and when a valid signal will be available, the
SPDIF-RX will re-sample the incoming signal, decode the Manchester stream, recognize
frames, sub-frames and blocks elements. It delivers to the CPU decoded data, and
associated status flags.
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The SPDIF-RX also offers a signal named spdifrx_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
3.28
Serial Audio interface (SAI)
The devices feature two serial audio interfaces (SAI1 and SAI2). Each serial audio
interfaces based on two independent audio sub blocks which can operate as transmitter or
receiver with their FIFO. Many audio protocols are supported by each block: I2S standards,
LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output, supporting audio sampling
frequencies from 8 kHz up to 192 kHz. Both sub blocks can be configured in master or in
slave mode. The SAIs use a PLL to achieve audio class accuracy.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub blocks can be configured in synchronous mode when full-duplex mode is
required.
SAI1 and SA2 can be served by the DMA controller.
3.29
Audio PLL (PLLI2S)
2
The devices feature an additional dedicated PLL for audio I S and SAI applications. It allows
2
to achieve error-free I S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
2
The PLLI2S configuration can be modified to manage an I S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
2
I S/SAI flow with an external PLL (or Codec output).
3.30
3.31
Serial Audio Interface PLL(PLLSAI)
An additional PLL dedicated to audio and USB is used for SAI1 and SAI2 peripheral in case
the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.
The PLLSAI is also used to generate the 48MHz clock for USB FS and SDIO in case the
system PLL is programmed with factors not multiple of 48MHz.
Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
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The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
3.32
3.33
Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.
Universal serial bus on-the-go full-speed (OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The USB has dedicated power
rails allowing its use throughout the entire power range. The major features are:
•
•
•
•
•
•
Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
6 bidirectional endpoints
12 host channels with periodic OUT support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.34
Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.
The USB OTG HS supports both full-speed and high-speed operations. It integrates the
transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI)
for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an
external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The USB has dedicated power
rails allowing its use throughout the entire power range.
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The major features are:
•
•
•
•
•
•
Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
8 bidirectional endpoints
16 host channels with periodic OUT support
Internal FS OTG PHY support
External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
•
•
•
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.35
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can sustain a data transfer rate up to 94.5 Mbyte/s (in 14-bit mode) at 54 MHz.
Its features:
•
•
•
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
•
Supports continuous mode or snapshot (a single frame) mode
Capability to automatically crop the image black & white.
3.36
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 90 MHz.
3.37
Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
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Additional logic functions embedded in the ADC interface allow:
•
•
Simultaneous sample and hold
Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
3.38
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as V , ADC1_IN18, which is used to convert the
BAT
sensor output voltage into a digital value. When the temperature sensor and V
BAT
conversion are enabled at the same time, only V
conversion is performed.
BAT
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
3.39
Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•
•
•
•
•
•
•
•
•
•
two DAC converters: one for each output channel
8-bit or 10-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel
external triggers for conversion
input voltage reference V
REF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
3.40
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
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Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.41
Embedded Trace Macrocell™
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F446xx through a small number of ETM pins to an external hardware trace port
analyser (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
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Pinout and pin description
4
Pinout and pin description
Figure 10. STM32F446xC/xE LQFP64 pinout
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1. The above figure shows the package top view.
DocID027107 Rev 6
41/202
66
Pinout and pin description
STM32F446xC/E
Figure 11. STM32F446xC/xE LQFP100 pinout
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1. The above figure shows the package top view.
42/202
DocID027107 Rev 6
STM32F446xC/E
Pinout and pin description
Figure 12. STM32F446xC LQFP144 pinout
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1. The above figure shows the package top view.
DocID027107 Rev 6
43/202
66
Pinout and pin description
STM32F446xC/E
Figure 13. STM32F446xC/xE WLCSP81 ballout
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1. The above figure shows the package top view.
44/202
DocID027107 Rev 6
STM32F446xC/E
Pinout and pin description
Figure 14. STM32F446xC/xE UFBGA144 ballout
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1. The above picture shows the package top view.
DocID027107 Rev 6
45/202
66
Pinout and pin description
STM32F446xC/E
Table 9. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
FT
FTf
TTa
B
Input / output pin
5 V tolerant I/O
5V tolerant IO, I2C FM+ option
3.3 V tolerant I/O directly connected to ADC
Dedicated BOOT0 pin
I/O structure
Notes
RST
Bidirectional reset pin with weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Functions selected through GPIOx_AFR registers
Alternate
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
Table 10. STM32F446xx pin and ball descriptions
Pin Number
Pin name (function
after reset)
Additional
functions
Alternate functions
TRACECLK, SPI4_SCK,
SAI1_MCLK_A,
QUADSPI_BK1_IO2,
FMC_A23, EVENTOUT
-
1
D7 A3
1
PE2
I/O FT
-
-
TRACED0, SAI1_SD_B,
FMC_A19, EVENTOUT
-
-
2
3
D6 A2
A9 B2
2
3
PE3
PE4
I/O FT
I/O FT
-
-
-
-
TRACED1, SPI4_NSS,
SAI1_FS_A, FMC_A20,
DCMI_D4, EVENTOUT
TRACED2, TIM9_CH1,
SPI4_MISO, SAI1_SCK_A,
FMC_A21, DCMI_D6,
EVENTOUT
-
4
-
B3
4
PE5
I/O FT
-
-
46/202
DocID027107 Rev 6
STM32F446xC/E
Pin Number
Pinout and pin description
Table 10. STM32F446xx pin and ball descriptions (continued)
Pin name (function
after reset)
Additional
functions
Alternate functions
TRACED3, TIM9_CH2,
SPI4_MOSI, SAI1_SD_A,
FMC_A22, DCMI_D7,
EVENTOUT
-
5
-
B4
5
PE6
I/O FT
-
-
1
2
6
7
B9 C2
C8 A1
6
7
VBAT
PC13
S
-
-
-
-
-
I/O FT
I/O FT
EVENTOUT
TAMP_1/WKUP1
PC14-
OSC32_IN(PC14)
3
4
-
8
9
-
C9 B1
D9 C1
8
-
-
-
-
-
EVENTOUT
EVENTOUT
OSC32_IN
PC15-
OSC32_OUT(PC15)
9
I/O FT
I/O FT
I/O FT
I/O FT
OSC32_OUT
I2C2_SDA, FMC_A0,
EVENTOUT
-
-
-
C3
C4
D4
10
11
12
PF0
PF1
PF2
-
-
-
I2C2_SCL, FMC_A1,
EVENTOUT
-
-
I2C2_SMBA, FMC_A2,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E2
E3
E4
D2
D3
13
14
15
16
17
PF3
PF4
PF5
VSS
VDD
I/O FT
I/O FT
I/O FT
-
-
-
-
-
FMC_A3, EVENTOUT
ADC3_IN9
FMC_A4, EVENTOUT
ADC3_IN14
-
FMC_A5, EVENTOUT
ADC3_IN15
10
11
S
S
-
-
-
-
-
-
TIM10_CH1, SAI1_SD_B,
QUADSPI_BK1_IO3,
EVENTOUT
-
-
-
-
-
-
-
-
F3
F2
G3
18
19
PF6
PF7
PF8
I/O FT
I/O FT
I/O FT
-
-
ADC3_IN4
ADC3_IN5
TIM11_CH1,
SAI1_MCLK_B,
QUADSPI_BK1_IO2,
EVENTOUT
SAI1_SCK_B,TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
-
-
20
21
-
-
ADC3_IN6
ADC3_IN7
SAI1_FS_B, TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
-
-
-
-
G2
G1
PF9
I/O FT
I/O FT
-
22
23
PF10
-
-
DCMI_D11, EVENTOUT
EVENTOUT
ADC3_IN8
OSC_IN
5
12 E9 D1
PH0-OSC_IN(PH0) I/O FT
DocID027107 Rev 6
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66
Pinout and pin description
STM32F446xC/E
Table 10. STM32F446xx pin and ball descriptions (continued)
Pin Number
Pin name (function
after reset)
Additional
functions
Alternate functions
PH1-
OSC_OUT(PH1)
6
7
13 F9 E1
14 D8 F1
24
25
I/O FT
-
-
EVENTOUT
-
OSC_OUT
-
RS
NRST
PC0
I/O
T
SAI1_MCLK_B,
OTG_HS_ULPI_STP,
FMC_SDNWE,
8
9
15 G9 H1
26
I/O FT
-
ADC123_IN10
EVENTOUT
SPI3_MOSI/I2S3_SD,
SAI1_SD_A,
SPI2_MOSI/I2S2_SD,
EVENTOUT
16
-
H2
27
28
29
PC1
PC2
PC3
I/O FT
I/O FT
I/O FT
-
-
-
ADC123_IN11
ADC123_IN12
ADC123_IN13
SPI2_MISO,
OTG_HS_ULPI_DIR,
FMC_SDNE0, EVENTOUT
10 17 E8 H3
SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
FMC_SDCKE0,
11 18 F8 H4
EVENTOUT
-
-
19 H9
G8
-
30
-
VDD
VSS
S
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12 20 F7
J1
K1
L1
31
-
VSSA
VREF-
VREF+
VDDA
-
-
-
-
-
21
32
13 22 H8 M1 33
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS,
ADC123_IN0,
WKUP0/TAMP_2
14 23 J9
J2
34
PA0-WKUP(PA0)
I/O FT
-
UART4_TX, EVENTOUT
TIM2_CH2, TIM5_CH2,
USART2_RTS,
UART4_RX,
15 24 G7 K2
35
36
PA1
PA2
I/O FT
I/O FT
-
-
ADC123_IN1
ADC123_IN2
QUADSPI_BK1_IO3,
SAI2_MCLK_B,
EVENTOUT
TIM2_CH3, TIM5_CH3,
TIM9_CH1, USART2_TX,
SAI2_SCK_B, EVENTOUT
16 25 E7
L2
48/202
DocID027107 Rev 6
STM32F446xC/E
Pin Number
Pinout and pin description
Table 10. STM32F446xx pin and ball descriptions (continued)
Pin name (function
after reset)
Additional
functions
Alternate functions
TIM2_CH4, TIM5_CH4,
TIM9_CH2, SAI1_FS_A,
USART2_RX,
17 26 E6 M2 37
PA3
I/O FT
-
ADC123_IN3
OTG_HS_ULPI_D0,
EVENTOUT
18 27
-
J8
-
G4
H5
F4
38
-
VSS
BYPASS_REG
VDD
S
I
-
FT
-
-
-
-
-
-
-
-
-
-
-
-
19 28
39
S
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
ADC12_IN4,
DAC_OUT1
20 29 H7
J3
40
PA4
I/O TC
-
OTG_HS_SOF,
DCMI_HSYNC,
EVENTOUT
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
OTG_HS_ULPI_CK,
EVENTOUT
ADC12_IN5,
DAC_OUT2
21 30 F6 K3
41
42
PA5
PA6
I/O TC
I/O FT
-
-
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
I2S2_MCK, TIM13_CH1,
DCMI_PIXCLK,
22 31 G6 L3
ADC12_IN6
ADC12_IN7
EVENTOUT
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SD,
TIM14_CH1,
23 32 E5 M3 43
PA7
I/O FT
-
FMC_SDNWE,
EVENTOUT
I2S1_MCK, SPDIFRX_IN2,
FMC_SDNE0, EVENTOUT
24 33 J7
J4
44
45
PC4
PC5
I/O FT
I/O FT
-
-
ADC12_IN14
ADC12_IN15
USART3_RX,
SPDIFRX_IN3,
FMC_SDCKE0,
EVENTOUT
25 34
-
K4
DocID027107 Rev 6
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66
Pinout and pin description
STM32F446xC/E
Table 10. STM32F446xx pin and ball descriptions (continued)
Pin Number
Pin name (function
after reset)
Additional
functions
Alternate functions
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
SPI3_MOSI/I2S3_SD,
UART4_CTS,
OTG_HS_ULPI_D1,
SDIO_D1, EVENTOUT
26 35 F5
L4
46
PB0
PB1
I/O FT
-
-
ADC12_IN8
ADC12_IN9
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
OTG_HS_ULPI_D2,
SDIO_D2, EVENTOUT
27 36 H6 M4 47
I/O FT
I/O FT
TIM2_CH4, SAI1_SD_A,
SPI3_MOSI/I2S3_SD,
QUADSPI_CLK,
OTG_HS_ULPI_D4,
SDIO_CK, EVENTOUT
PB2-BOOT1
(PB2)
28 37 J6
J5
48
-
-
-
-
SAI2_SD_B,
FMC_SDNRAS,
DCMI_D12, EVENTOUT
-
-
-
M5 49
PF11
I/O FT
I/O FT
-
-
-
-
-
-
-
-
-
L5
-
50
51
52
PF12
VSS
VDD
-
-
-
FMC_A6, EVENTOUT
-
-
-
S
S
-
-
-
-
G5
FMPI2C1_SMBA,
FMC_A7, EVENTOUT
-
-
-
-
-
-
-
-
-
K5
53
PF13
PF14
PF15
I/O FT
I/O FTf
I/O FTf
-
-
-
-
-
-
FMPI2C1_SCL, FMC_A8,
EVENTOUT
M6 54
FMPI2C1_SDA, FMC_A9,
EVENTOUT
L6
55
-
-
-
-
-
-
K6
J6
56
57
PG0
PG1
I/O FT
I/O FT
-
-
FMC_A10, EVENTOUT
FMC_A11, EVENTOUT
-
-
TIM1_ETR, UART5_RX,
QUADSPI_BK2_IO0,
FMC_D4, EVENTOUT
-
-
-
38 J5 M7 58
PE7
PE8
PE9
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
TIM1_CH1N, UART5_TX,
QUADSPI_BK2_IO1,
FMC_D5, EVENTOUT
39 H5 L7
40 G5 K7
59
60
TIM1_CH1,
QUADSPI_BK2_IO2,
FMC_D6, EVENTOUT
50/202
DocID027107 Rev 6
STM32F446xC/E
Pin Number
Pinout and pin description
Table 10. STM32F446xx pin and ball descriptions (continued)
Pin name (function
after reset)
Additional
functions
Alternate functions
-
-
-
-
-
-
H6
G6
61
62
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM1_CH2N,
-
-
-
-
41 J4
J7
H8
J8
63
64
65
66
67
PE10
PE11
PE12
PE13
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
QUADSPI_BK2_IO3,
FMC_D7, EVENTOUT
-
-
-
-
TIM1_CH2, SPI4_NSS,
SAI2_SD_B, FMC_D8,
EVENTOUT
42
43
44
-
-
-
TIM1_CH3N, SPI4_SCK,
SAI2_SCK_B, FMC_D9,
EVENTOUT
TIM1_CH3, SPI4_MISO,
SAI2_FS_B, FMC_D10,
EVENTOUT
K8
L8
TIM1_CH4, SPI4_MOSI,
SAI2_MCLK_B, FMC_D11,
EVENTOUT
-
-
45
46
-
-
PE14
PE15
I/O FT
I/O FT
-
-
-
-
TIM1_BKIN, FMC_D12,
EVENTOUT
M8 68
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
SAI1_SCK_A,
29 47 H4 M9 69
PB10
I/O FT
-
-
USART3_TX,
OTG_HS_ULPI_D3,
EVENTOUT
TIM2_CH4, I2C2_SDA,
USART3_RX, SAI2_SD_A,
EVENTOUT
-
-
-
M10 70
PB11
I/O FT
-
-
30 48 J3
31 49 H3
H7
-
71
-
VCAP_1
VSS
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
32 50 J2 G7
72
VDD
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
SAI1_SCK_B,
USART3_CK, CAN2_RX,
OTG_HS_ULPI_D5,
33 51 G4 M11 73
PB12
I/O FT
-
-
OTG_HS_ID, EVENTOUT
DocID027107 Rev 6
51/202
66
Pinout and pin description
STM32F446xC/E
Table 10. STM32F446xx pin and ball descriptions (continued)
Pin Number
Pin name (function
after reset)
Additional
functions
Alternate functions
TIM1_CH1N,
SPI2_SCK/I2S2_CK,
34 52 H2 M12 74
35 53 J1 L11 75
36 54 G3 L12 76
PB13
I/O FT
I/O FT
-
-
USART3_CTS, CAN2_TX, OTG_HS_VBUS
OTG_HS_ULPI_D6,
EVENTOUT
TIM1_CH2N, TIM8_CH2N,
SPI2_MISO,
PB14(1)
USART3_RTS,
TIM12_CH1,
-
OTG_HS_DM, EVENTOUT
RTC_REFIN, TIM1_CH3N,
TIM8_CH3N,
PB15(1)
PD8
I/O FT
I/O FT
-
-
SPI2_MOSI/I2S2_SD,
TIM12_CH2, OTG_HS_DP,
EVENTOUT
-
-
USART3_TX,
SPDIFRX_IN1, FMC_D13,
EVENTOUT
-
55
-
L9
77
USART3_RX, FMC_D14,
EVENTOUT
-
-
56
57
-
-
K9
J9
78
79
PD9
I/O FT
I/O FT
-
-
-
-
USART3_CK, FMC_D15,
EVENTOUT
PD10
FMPI2C1_SMBA,
USART3_CTS,
-
-
-
58 H1 H9
80
PD11
PD12
PD13
I/O FT
I/O FTf
I/O FTf
-
-
-
QUADSPI_BK1_IO0,
SAI2_SD_A, FMC_A16,
EVENTOUT
-
-
-
TIM4_CH1,
FMPI2C1_SCL,
USART3_RTS,
59 G2 L10 81
QUADSPI_BK1_IO1,
SAI2_FS_A, FMC_A17,
EVENTOUT
TIM4_CH2,
FMPI2C1_SDA,
QUADSPI_BK1_IO3,
SAI2_SCK_A, FMC_A18,
EVENTOUT
60 G1 K10 82
-
-
-
-
-
-
G8
F8
83
84
VSS
VDD
S
S
-
-
-
-
-
-
-
-
52/202
DocID027107 Rev 6
STM32F446xC/E
Pin Number
Pinout and pin description
Table 10. STM32F446xx pin and ball descriptions (continued)
Pin name (function
after reset)
Additional
functions
Alternate functions
TIM4_CH3,
FMPI2C1_SCL,
SAI2_SCK_A, FMC_D0,
EVENTOUT
-
-
61
62
-
-
K11 85
K12 86
PD14
PD15
I/O FTf
I/O FTf
-
-
-
-
TIM4_CH4,
FMPI2C1_SDA, FMC_D1,
EVENTOUT
-
-
-
-
-
-
J12 87
J11 88
PG2
PG3
I/O FT
I/O FT
-
-
FMC_A12, EVENTOUT
FMC_A13, EVENTOUT
-
-
FMC_A14/FMC_BA0,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
J10 89
H12 90
H11 91
H10 92
PG4
PG5
PG6
PG7
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
-
-
FMC_A15/FMC_BA1,
EVENTOUT
QUADSPI_BK1_NCS,
DCMI_D12, EVENTOUT
USART6_CK, FMC_INT,
DCMI_D13, EVENTOUT
SPDIFRX_IN2,
USART6_RTS,
-
-
-
G11 93
PG8
I/O FT
-
-
FMC_SDCLK, EVENTOUT
-
-
-
-
-
-
-
-
-
94
-
VSS
VDD
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
F10
E1 C11 95
VDDUSB
TIM3_CH1, TIM8_CH1,
FMPI2C1_SCL,
37 63 F1 G12 96
PC6
I/O FTf
-
I2S2_MCK, USART6_TX,
SDIO_D6, DCMI_D0,
EVENTOUT
-
TIM3_CH2, TIM8_CH2,
FMPI2C1_SDA,
SPI2_SCK/I2S2_CK,
I2S3_MCK, SPDIFRX_IN1,
USART6_RX, SDIO_D7,
DCMI_D1, EVENTOUT
38 64 F2 F12 97
PC7
PC8
I/O FTf
I/O FT
-
-
-
-
TRACED0, TIM3_CH3,
TIM8_CH3, UART5_RTS,
USART6_CK, SDIO_D0,
DCMI_D2, EVENTOUT
39 65 F3 F11 98
DocID027107 Rev 6
53/202
66
Pinout and pin description
STM32F446xC/E
Table 10. STM32F446xx pin and ball descriptions (continued)
Pin Number
Pin name (function
after reset)
Additional
functions
Alternate functions
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, UART5_CTS,
QUADSPI_BK1_IO0,
SDIO_D1, DCMI_D3,
EVENTOUT
40 66 D1 E11 99
PC9
I/O FT
-
-
MCO1, TIM1_CH1,
I2C3_SCL, USART1_CK,
OTG_FS_SOF,
41 67 E2 E12 100
PA8
PA9
I/O FT
I/O FT
-
-
-
EVENTOUT
TIM1_CH2, I2C3_SMBA,
SPI2_SCK/I2S2_CK,
SAI1_SD_B, USART1_TX,
DCMI_D0, EVENTOUT
42 68 F4 D12 101
OTG_FS_VBUS
TIM1_CH3, USART1_RX,
OTG_FS_ID, DCMI_D1,
EVENTOUT
43 69 E3 D11 102
44 70 C1 C12 103
45 71 E4 B12 104
PA10
I/O FT
I/O FT
I/O FT
-
-
-
-
TIM1_CH4, USART1_CTS,
CAN1_RX, OTG_FS_DM,
EVENTOUT
PA11(1)
PA12(1)
TIM1_ETR, USART1_RTS,
SAI2_FS_B, CAN1_TX,
OTG_FS_DP, EVENTOUT
-
-
-
-
JTMS-SWDIO,
EVENTOUT
46 72 D2 A12 105 PA13(JTMS-SWDIO) I/O FT
-
73 C2 G9 106
VCAP_2
VSS
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
47 74 B1 G10 107
48 75 A1 F9 108
VDD
JTCK-SWCLK,
EVENTOUT
49 76 C3 A11 109 PA14(JTCK-SWCLK) I/O FT
-
-
JTDI,
TIM2_CH1/TIM2_ETR,
HDMI_CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
UART4_RTS, EVENTOUT
50 77 B2 A10 110
PA15(JTDI)
I/O FT
-
-
54/202
DocID027107 Rev 6
STM32F446xC/E
Pin Number
Pinout and pin description
Table 10. STM32F446xx pin and ball descriptions (continued)
Pin name (function
after reset)
Additional
functions
Alternate functions
SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
QUADSPI_BK1_IO1,
SDIO_D2, DCMI_D8,
EVENTOUT
51 78 D3 B11 111
52 79 D4 B10 112
53 80 A2 C10 113
PC10
PC11
I/O FT
I/O FT
-
-
-
-
SPI3_MISO, USART3_RX,
UART4_RX,
QUADSPI_BK2_NCS,
SDIO_D3, DCMI_D4,
EVENTOUT
I2C2_SDA,
SPI3_MOSI/I2S3_SD,
USART3_CK, UART5_TX,
SDIO_CK, DCMI_D9,
EVENTOUT
PC12
PD0
I/O FT
I/O FT
-
-
-
-
SPI4_MISO,
SPI3_MOSI/I2S3_SD,
CAN1_RX, FMC_D2,
EVENTOUT
-
-
81 B3 E10 114
82 C4 D10 115
SPI2_NSS/I2S2_WS,
CAN1_TX, FMC_D3,
EVENTOUT
PD1
PD2
I/O FT
I/O FT
-
-
-
-
TIM3_ETR, UART5_RX,
SDIO_CMD, DCMI_D11,
EVENTOUT
54 83 D5 E9 116
TRACED1,
SPI2_SCK/I2S2_CK,
USART2_CTS,
QUADSPI_CLK,
FMC_CLK, DCMI_D5,
EVENTOUT
-
84
-
D9 117
PD3
I/O FT
-
-
USART2_RTS, FMC_NOE,
EVENTOUT
-
-
85 A3 C9 118
PD4
PD5
I/O FT
I/O FT
-
-
-
-
USART2_TX, FMC_NWE,
EVENTOUT
86
-
B9 119
-
-
-
-
-
-
E7 120
F7 121
VSS
VDD
S
S
-
-
-
-
-
-
-
-
DocID027107 Rev 6
55/202
66
Pinout and pin description
STM32F446xC/E
Table 10. STM32F446xx pin and ball descriptions (continued)
Pin Number
Pin name (function
after reset)
Additional
functions
Alternate functions
SPI3_MOSI/I2S3_SD,
SAI1_SD_A, USART2_RX,
FMC_NWAIT, DCMI_D10,
EVENTOUT
-
-
87 B4 A8 122
88 A4 A9 123
PD6
PD7
I/O FT
I/O FT
-
-
-
-
USART2_CK,
SPDIFRX_IN0, FMC_NE1,
EVENTOUT
SPDIFRX_IN3,
USART6_RX,
QUADSPI_BK2_IO2,
SAI2_FS_B,
-
-
-
E8 124
PG9
I/O FT
-
-
FMC_NE2/FMC_NCE3,
DCMI_VSYNC,
EVENTOUT
SAI2_SD_B, FMC_NE3,
DCMI_D2, EVENTOUT
-
-
-
-
-
-
D8 125
C8 126
PG10
PG11
I/O FT
I/O FT
-
-
-
-
SPI4_SCK, SPDIFRX_IN0,
DCMI_D3, EVENTOUT
SPI4_MISO,
SPDIFRX_IN1,
USART6_RTS, FMC_NE4,
EVENTOUT
-
-
-
-
-
-
-
-
-
B8 127
D7 128
C7 129
PG12
PG13
PG14
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
TRACED2, SPI4_MOSI,
USART6_CTS, FMC_A24,
EVENTOUT
TRACED3, SPI4_NSS,
USART6_TX,
QUADSPI_BK2_IO3,
FMC_A25, EVENTOUT
-
-
-
-
-
-
-
130
VSS
VDD
S
S
-
-
-
-
-
-
-
-
F6 131
USART6_CTS,
FMC_SDNCAS,
-
-
-
B7 132
PG15
I/O FT
-
-
DCMI_D13, EVENTOUT
JTDO/TRACESWO,
TIM2_CH2, I2C2_SDA,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
EVENTOUT
PB3(JTDO/TRACES
WO)
55 89 A5 A7 133
I/O FT
-
-
56/202
DocID027107 Rev 6
STM32F446xC/E
Pin Number
Pinout and pin description
Table 10. STM32F446xx pin and ball descriptions (continued)
Pin name (function
after reset)
Additional
functions
Alternate functions
NJTRST, TIM3_CH1,
I2C3_SDA, SPI1_MISO,
SPI3_MISO,
SPI2_NSS/I2S2_WS,
EVENTOUT
56 90 B5 A6 134
PB4(NJTRST)
I/O FT
-
-
-
-
TIM3_CH2, I2C1_SMBA,
SPI1_MOSI/I2S1_SD,
SPI3_MOSI/I2S3_SD,
CAN2_RX,
57 91 A6 B6 135
PB5
I/O FT
OTG_HS_ULPI_D7,
FMC_SDCKE1,
DCMI_D10, EVENTOUT
TIM4_CH1, HDMI_CEC,
I2C1_SCL, USART1_TX,
CAN2_TX,
QUADSPI_BK1_NCS,
FMC_SDNE1, DCMI_D5,
EVENTOUT
58 92 C5 C6 136
PB6
I/O FT
-
-
TIM4_CH2, I2C1_SDA,
USART1_RX,
59 93 B6 D6 137
60 94 A7 D5 138
61 95 C6 C5 139
PB7
BOOT0
PB8
I/O FT
-
-
-
SPDIFRX_IN0, FMC_NL,
DCMI_VSYNC,
-
VPP
-
EVENTOUT
I
B
-
TIM2_CH1/TIM2_ETR,
TIM4_CH3, TIM10_CH1,
I2C1_SCL, CAN1_RX,
SDIO_D4, DCMI_D6,
EVENTOUT
I/O FT
TIM2_CH2, TIM4_CH4,
TIM11_CH1, I2C1_SDA,
SPI2_NSS/I2S2_WS,
SAI1_FS_B, CAN1_TX,
SDIO_D5, DCMI_D7,
EVENTOUT
62 96 C7 B5 140
PB9
I/O FT
-
-
TIM4_ETR,
SAI2_MCLK_A,
FMC_NBL0, DCMI_D2,
EVENTOUT
-
-
97
98
-
-
A5 141
A4 142
PE0
PE1
I/O FT
I/O FT
-
-
-
-
FMC_NBL1, DCMI_D3,
EVENTOUT
DocID027107 Rev 6
57/202
66
Pinout and pin description
STM32F446xC/E
Table 10. STM32F446xx pin and ball descriptions (continued)
Pin Number
Pin name (function
after reset)
Additional
functions
Alternate functions
63 99 B7 E6
-
VSS
PDR_ON
VDD
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B8 E5 143
64 100 A8 F5 144
1. PA11, PA12, PB14 and PB15 I/Os are supplied by VDDUSB
58/202
DocID027107 Rev 6
Table 11. Alternate function
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
SAI2/
AF11
AF12
AF13
DCMI
AF14
AF15
SYS
SPI2/3/
USART1/
2/3/UART
5/SPDIFR
X
SAI/
CAN1/2
Port
FMC/
SDIO/
OTG2_FS
TIM8/9/
10/11/
CEC
I2C1/2/3 SPI1/2/3/ SPI2/3/4/
/4/CEC
USART6/ TIM12/13/ QUADSPI/
UART4/5/ 14/ OTG2_HS/
SPDIFRX QUADSPI OTG1_FS
TIM1/2
TIM3/4/5
OTG1_FS
-
4
SAI1
TIM2_CH1/
TIM2_ETR
USART2_
CTS
UART4_
TX
EVENT
OUT
PA0
PA1
-
-
TIM5_CH1
TIM5_CH2
TIM8_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART2_
RTS
UART4_
RX
QUADSPI_
BK1_IO3
SAI2_
MCLK_B
EVENT
OUT
TIM2_CH2
USART2_
TX
SAI2_
SCK_B
EVENT
OUT
PA2
PA3
-
-
TIM2_CH3
TIM2_CH4
TIM5_CH3
TIM5_CH4
TIM9_CH1
TIM9_CH2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI1_
FS_A
USART2_
RX
OTG_HS_
ULPI_D0
EVENT
OUT
-
-
SPI3_NSS
/
I2S3_WS
SPI1_NSS/I
2S1_WS
USART2_
CK
OTG_HS_
SOF
DCMI_
HSYNC
EVENT
OUT
PA4
-
-
-
-
-
-
-
-
-
TIM2_CH1/
TIM2_ETR
TIM8_
CH1N
SPI1_SCK/I
2S1_CK
OTG_HS_
ULPI_CK
EVENT
OUT
PA5
PA6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM1_
BKIN
TIM8_
BKIN
I2S2_
MCK
DCMI_
PIXCLK
EVENT
OUT
TIM3_CH1
SPI1_MISO
TIM13_CH1
-
-
SPI1_MOSI
TIM1_
CH1N
TIM8_
CH1N
FMC_
SDNWE
EVENT
OUT
PA7
-
TIM3_CH2
-
/
-
-
-
-
TIM14_CH1
-
-
-
I2S1_SD
Port A
I2C3_
SCL
USART1_
CK
OTG_FS_
SOF
EVENT
OUT
PA8
PA9
MCO1
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH4
TIM1_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C3_
SMBA
SPI2_SCK
/I2S2_CK
SAI1_
SD_B
USART1_
TX
EVENT
OUT
-
-
-
-
-
-
DCMI_D0
USART1_
RX
OTG_FS_
ID
EVENT
OUT
PA10
PA11
PA12
PA13
PA14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DCMI_D1
USART1_
CTS
OTG_FS_
DM
EVENT
OUT
CAN1_RX
-
-
-
-
USART1_
RTS
SAI2_
FS_B
OTG_FS_
DP
EVENT
OUT
CAN1_TX
JTMS-
SWDIO
EVENT
OUT
-
-
-
-
-
-
-
-
JTCK-
SWCLK
EVENT
OUT
-
SPI3_
NSS/
I2S3_WS
TIM2_CH1/
TIM2_ETR
HDMI_
CEC
SPI1_NSS/
I2S1_WS
UART4_RT
S
EVENT
OUT
PA15
JTDI
-
-
-
-
-
-
-
-
-
Table 11. Alternate function (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
SAI2/
AF11
AF12
AF13
DCMI
AF14
AF15
SYS
SPI2/3/
USART1/
2/3/UART
5/SPDIFR
X
SAI/
CAN1/2
Port
FMC/
SDIO/
OTG2_FS
TIM8/9/
10/11/
CEC
I2C1/2/3 SPI1/2/3/ SPI2/3/4/
/4/CEC
USART6/ TIM12/13/ QUADSPI/
UART4/5/ 14/ OTG2_HS/
SPDIFRX QUADSPI OTG1_FS
TIM1/2
TIM3/4/5
OTG1_FS
-
4
SAI1
SPI3_MOS
I/
I2S3_SD
TIM8_
CH2N
UART4_
CTS
OTG_HS_
ULPI_D1
EVENT
OUT
PB0
PB1
PB2
-
-
TIM1_CH2N TIM3_CH3
TIM1_CH3N TIM3_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
SDIO_D1
SDIO_D2
SDIO_CK
-
-
-
-
-
-
TIM8_
CH3N
OTG_HS_
ULPI_D2
EVENT
OUT
-
-
-
SPI3_MOS
I/
I2S3_SD
SAI1_
SD_A
QUADSPI_
CLK
OTG_HS_
ULPI_D4
EVENT
OUT
-
TIM2_CH4
-
-
JTDO/
SPI3_SCK
I2C2_
SDA
SPI1_SCK
/I2S1_CK
EVENT
OUT
PB3 TRACES TIM2_CH2
WO
-
-
-
-
/
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2S3_CK
I2C3_
SDA
SPI3_
MISO
SPI2_NSS/
I2S2_WS
EVENT
OUT
PB4
PB5
NJTRST
-
-
-
TIM3_CH1
TIM3_CH2
SPI1_MISO
-
SPI3_
MOSI/
I2S3_SD
I2C1_
SMBA
SPI1_MOSI
/I2S1_SD
OTG_HS_
ULPI_D7
FMC_
SDCKE1
DCMI_
D10
EVENT
OUT
-
CAN2_RX
HDMI_
CEC
I2C1_
SCL
USART1_
TX
QUADSPI_
BK1_NCS
FMC_
SDNE1
EVENT
OUT
PB6
PB7
PB8
PB9
-
-
-
-
-
-
-
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
-
-
-
-
-
-
-
CAN2_TX
-
-
-
-
-
DCMI_D5
-
-
-
-
-
I2C1_
SDA
USART1_
RX
SPDIF_
RX0
DCMI_
VSYNC
EVENT
OUT
-
-
-
-
-
FMC_NL
SDIO_D4
SDIO_D5
-
Port B
TIM2_CH1/
TIM2_ETR
TIM10_
CH1
I2C1_
SCL
EVENT
OUT
-
-
-
-
-
CAN1_RX
CAN1_TX
-
DCMI_D6
DCMI_D7
-
TIM2_
CH2
TIM11_
CH1
I2C1_
SDA
SPI2_NSS/
I2S2_WS
SAI1_
FS_B
EVENT
OUT
I2C2_
SCL
SPI2_SCK/
I2S2_CK
SAI1_
SCK_A
USART3_
TX
OTG_HS_
ULPI_D3
EVENT
OUT
PB10
PB11
TIM2_CH3
TIM2_CH4
-
-
I2C2_
SDA
USART3_
RX
SAI2_
SD_A
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C2_
SMBA
SPI2_NSS/
I2S2_WS
SAI1_
SCK_B
USART3_
CK
OTG_HS_
ULPI_D5
OTG_
HS_ID
EVENT
OUT
PB12
TIM1_BKIN
-
-
-
CAN2_RX
SPI2_SCK/
I2S2_CK
USART3_
CTS
OTG_HS_
ULPI_D6
EVENT
OUT
PB13
PB14
PB15
-
-
TIM1_CH1N
TIM1_CH2N
TIM1_CH3N
-
-
-
-
-
-
-
-
-
-
-
-
CAN2_TX
TIM12_CH1
TIM12_CH2
-
-
-
-
-
-
-
-
-
-
TIM8_
CH2N
USART3_
RTS
OTG_
HS_DM
EVENT
OUT
SPI2_MISO
-
-
RTC_
REFIN
TIM8_
CH3N
SPI2_MOSI
/I2S2_SD
OTG_
HS_DP
EVENT
OUT
-
Table 11. Alternate function (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
SAI2/
AF11
AF12
AF13
DCMI
AF14
AF15
SYS
SPI2/3/
USART1/
2/3/UART
5/SPDIFR
X
SAI/
CAN1/2
Port
FMC/
SDIO/
OTG2_FS
TIM8/9/
10/11/
CEC
I2C1/2/3 SPI1/2/3/ SPI2/3/4/
/4/CEC
USART6/ TIM12/13/ QUADSPI/
UART4/5/ 14/ OTG2_HS/
SPDIFRX QUADSPI OTG1_FS
TIM1/2
TIM3/4/5
OTG1_FS
-
4
SAI1
SAI1_
MCLK_B
OTG_HS_
ULPI_STP
FMC_
SDNWE
EVENT
OUT
PC0
PC1
PC2
PC3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI2_MOS
SPI3_MOSI
/I2S3_SD
SAI1_
SD_A
EVENT
OUT
I
-
-
/I2S2_SD
OTG_HS_
ULPI_DIR
FMC_
SDNE0
EVENT
OUT
SPI2_MISO
-
-
-
-
SPI2_MOSI
OTG_HS_
ULPI_NXT
FMC_
SDCKE0
EVENT
OUT
/
I2S2_SD
SPDIF_
RX2
FMC_
SDNE0
EVENT
OUT
PC4
PC5
-
-
-
-
-
-
-
-
-
-
I2S1_MCK
-
-
-
-
-
-
-
-
-
-
-
-
-
USART3_
RX
SPDIF_
RX3
FMC_
SDCKE0
EVENT
OUT
-
FMPI2C1
_SCL
USART6_T
X
EVENT
OUT
-
-
-
-
-
-
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
TIM8_CH1
TIM8_CH2
TIM8_CH3
TIM8_CH4
I2S2_MCK
-
-
-
-
-
-
-
-
-
-
-
-
-
SDIO_D6
SDIO_D7
SDIO_D0
SDIO_D1
DCMI_D0
DCMI_D1
DCMI_D2
DCMI_D3
-
-
-
-
PC6
PC7
PC8
PC9
FMPI2C1 SPI2_SCK/
_SDA
SPDIF_
RX1
USART6_R
X
EVENT
OUT
I2S3_MCK
I2S2_CK
Port C
TRACE
D0
UART5_
RTS
USART6_C
K
EVENT
OUT
-
-
-
-
I2C3_
SDA
UART5_
CTS
QUADSPI_
BK1_IO0
EVENT
OUT
MCO2
I2S_CKIN
-
SPI3_SCK
USART3_
TX
QUADSPI_
BK1_IO1
EVENT
OUT
PC10
PC11
PC12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
/
UART4_TX
UART4_RX
UART5_TX
-
-
-
-
-
-
SDIO_D2
SDIO_D3
SDIO_CK
DCMI_D8
DCMI_D4
DCMI_D9
-
-
-
I2S3_CK
SPI3_
MISO
USART3_
RX
QUADSPI_
BK2_NCS
EVENT
OUT
SPI3_
MOSI/
I2S3_SD
I2C2_
SDA
USART3_
CK
EVENT
OUT
-
EVENT
OUT
PC13
PC14
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
EVENT
OUT
Table 11. Alternate function (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
SAI2/
AF11
AF12
AF13
DCMI
AF14
AF15
SYS
SPI2/3/
USART1/
2/3/UART
5/SPDIFR
X
SAI/
CAN1/2
Port
FMC/
SDIO/
OTG2_FS
TIM8/9/
10/11/
CEC
I2C1/2/3 SPI1/2/3/ SPI2/3/4/
/4/CEC
USART6/ TIM12/13/ QUADSPI/
UART4/5/ 14/ OTG2_HS/
SPDIFRX QUADSPI OTG1_FS
TIM1/2
TIM3/4/5
OTG1_FS
-
4
SAI1
SPI3_
MOSI/
I2S3_SD
EVENT
OUT
PD0
-
-
-
-
-
SPI4_MISO
-
-
CAN1_RX
-
-
FMC_D2
-
-
-
SPI2_NSS/
I2S2_WS
EVENT
OUT
PD1
PD2
PD3
PD4
PD5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CAN1_TX
-
-
-
-
-
-
-
-
-
-
-
FMC_D3
SDIO_CMD
FMC_CLK
FMC_NOE
FMC_NWE
-
-
-
-
-
DCMI_
D11
EVENT
OUT
TIM3_ETR
-
UART5_RX
-
TRACE
D1
SPI2_SCK/
I2S2_CK
USART2_
CTS
QUADSPI_
CLK
DCMI_
D5
EVENT
OUT
-
-
-
-
-
-
USART2_
RTS
EVENT
OUT
-
-
-
-
-
-
-
-
USART2_
TX
EVENT
OUT
SPI3_
MOSI/
I2S3_SD
SAI1_
SD_A
USART2_
RX
FMC_
NWAIT
DCMI_
D10
EVENT
OUT
PD6
-
-
-
-
-
-
-
-
-
-
USART2_
CK
SPDIF_
RX0
EVENT
OUT
PD7
PD8
PD9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_NE1
FMC_D13
FMC_D14
FMC_D15
FMC_A16
FMC_A17
FMC_A18
FMC_D0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port D
USART3_
TX
SPDIF_
RX1
EVENT
OUT
-
-
USART3_
RX
EVENT
OUT
-
-
-
-
-
-
-
USART3_
CK
EVENT
OUT
PD10
PD11
PD12
PD13
PD14
PD15
-
-
FMPI2C1
_SMBA
USART3_
CTS
QUADSPI_
BK1_IO0
EVENT
OUT
-
SAI2_SD_A
FMPI2C1
_SCL
USART3_
RTS
QUADSPI_
BK1_IO1
EVENT
OUT
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
SAI2_FS_A
FMPI2C1
_SDA
QUADSPI_
BK1_IO3
EVENT
OUT
-
-
-
SAI2_SCK_A
FMPI2C1
_SCL
SAI2_
SCK_A
EVENT
OUT
-
-
-
-
FMPI2C1
_SDA
EVENT
OUT
-
FMC_D1
Table 11. Alternate function (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
SAI2/
AF11
AF12
AF13
DCMI
AF14
AF15
SYS
SPI2/3/
USART1/
2/3/UART
5/SPDIFR
X
SAI/
CAN1/2
Port
FMC/
SDIO/
OTG2_FS
TIM8/9/
10/11/
CEC
I2C1/2/3 SPI1/2/3/ SPI2/3/4/
/4/CEC
USART6/ TIM12/13/ QUADSPI/
UART4/5/ 14/ OTG2_HS/
SPDIFRX QUADSPI OTG1_FS
TIM1/2
TIM3/4/5
OTG1_FS
-
4
SAI1
SAI2_
MCLK_A
FMC_
NBL0
EVENT
OUT
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
-
-
-
TIM4_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DCMI_D2
-
-
-
-
-
-
-
-
-
-
-
FMC_
NBL1
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DCMI_D3
TRACE
CLK
SAI1_
MCLK_A
QUADSPI_
BK1_IO2
EVENT
OUT
-
-
SPI4_SCK
-
-
-
-
-
-
FMC_A23
FMC_A19
FMC_A20
FMC_A21
FMC_A22
FMC_D4
FMC_D5
FMC_D6
FMC_D7
-
TRACE
D0
SAI1_
SD_B
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE
D1
SAI1_
FS_A
EVENT
OUT
-
-
SPI4_NSS
-
DCMI_D4
TRACE
D2
SAI1_
SCK_A
EVENT
OUT
-
TIM9_CH1
SPI4_MISO
-
DCMI_D6
TRACE
D3
SAI1_
SD_A
EVENT
OUT
-
TIM9_CH2
SPI4_MOSI
-
DCMI_D7
QUADSPI_
BK2_IO0
EVENT
OUT
-
-
-
-
TIM1_ETR
TIM1_CH1N
TIM1_CH1
TIM1_CH2N
-
-
-
-
-
-
-
-
-
-
-
-
UART5_RX
-
-
-
-
Port E
QUADSPI_
BK2_IO1
EVENT
OUT
UART5_TX
QUADSPI_
BK2_IO2
EVENT
OUT
-
-
QUADSPI_
BK2_IO3
EVENT
OUT
PE10
PE11
SAI2_
SD_B
EVENT
OUT
-
TIM1_CH2
-
-
-
SPI4_NSS
-
-
-
-
-
FMC_D8
-
-
SAI2_
SCK_B
EVENT
OUT
PE12
PE13
PE14
PE15
-
-
-
-
TIM1_CH3N
TIM1_CH3
TIM1_CH4
TIM1_BKIN
-
-
-
-
-
-
-
-
-
-
-
-
SPI4_SCK
SPI4_MISO
SPI4_MOSI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D9
FMC_D10
FMC_D11
FMC_D12
-
-
-
-
-
-
-
-
SAI2_
FS_B
EVENT
OUT
SAI2_
MCLK_B
EVENT
OUT
EVENT
OUT
-
Table 11. Alternate function (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
SAI2/
AF11
AF12
AF13
DCMI
AF14
AF15
SYS
SPI2/3/
USART1/
2/3/UART
5/SPDIFR
X
SAI/
CAN1/2
Port
FMC/
SDIO/
OTG2_FS
TIM8/9/
10/11/
CEC
I2C1/2/3 SPI1/2/3/ SPI2/3/4/
/4/CEC
USART6/ TIM12/13/ QUADSPI/
UART4/5/ 14/ OTG2_HS/
SPDIFRX QUADSPI OTG1_FS
TIM1/2
TIM3/4/5
OTG1_FS
-
4
SAI1
I2C2_
SDA
EVENT
OUT
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C2_
SCL
EVENT
OUT
FMC_A1
I2C2_
SMBA
EVENT
OUT
FMC_A2
EVENT
OUT
-
FMC_A3
-
-
-
-
EVENT
OUT
-
FMC_A4
EVENT
OUT
-
FMC_A5
TIM10_
CH1
SAI1_
SD_B
QUADSPI_
BK1_IO3
EVENT
OUT
-
-
-
-
-
TIM11_
CH1
SAI1_
MCLK_B
QUADSPI_
BK1_IO2
EVENT
OUT
-
Port F
SAI1_
SCK_B
QUADSPI_
BK1_IO0
EVENT
OUT
-
-
-
-
-
-
-
-
-
TIM13_CH1
SAI1_
FS_B
QUADSPI_
BK1_IO1
EVENT
OUT
-
TIM14_CH1
DCMI_
D11
EVENT
OUT
PF10
PF11
PF12
PF13
PF14
PF15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_
SDNRAS
DCMI_
D12
EVENT
OUT
-
SAI2_SD_B
EVENT
OUT
-
-
-
-
-
FMC_A6
FMC_A7
FMC_A8
FMC_A9
-
-
-
-
FMPI2C1
_SMBA
EVENT
OUT
FMPI2C1
_SCL
EVENT
OUT
FMPI2C1
_SDA
EVENT
OUT
Table 11. Alternate function (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
SAI2/
AF11
AF12
AF13
DCMI
AF14
AF15
SYS
SPI2/3/
USART1/
2/3/UART
5/SPDIFR
X
SAI/
CAN1/2
Port
FMC/
SDIO/
OTG2_FS
TIM8/9/
10/11/
CEC
I2C1/2/3 SPI1/2/3/ SPI2/3/4/
/4/CEC
USART6/ TIM12/13/ QUADSPI/
UART4/5/ 14/ OTG2_HS/
SPDIFRX QUADSPI OTG1_FS
TIM1/2
TIM3/4/5
OTG1_FS
-
4
SAI1
EVENT
OUT
PG0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A10
FMC_A11
FMC_A12
FMC_A13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
EVENT
OUT
EVENT
OUT
FMC_A14/
FMC_BA0
EVENT
OUT
FMC_A15/
FMC_BA1
EVENT
OUT
QUADSPI_
BK1_NCS
DCMI_
D12
EVENT
OUT
-
USART6_C
K
DCMI_
D13
EVENT
OUT
-
FMC_INT
Port G
SPDIFRX_ USART6_R
IN2 TS
FMC_
SDCLK
EVENT
OUT
-
-
SPDIFRX_ USART6_R QUADSPI_
IN3
FMC_NE2/
FMC_NCE3 VSYNC
DCMI_
EVENT
OUT
SAI2_FS_B
SAI2_SD_B
(1)
X
BK2_IO2
EVENT
OUT
-
-
-
FMC_NE3
-
DCMI_D2
SPI4_
SCK
SPDIFRX_
IN0
EVENT
OUT
PG11
PG12
PG13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DCMI_D3
-
-
-
SPI4_
MISO
SPDIFRX_ USART6_R
IN1
EVENT
OUT
FMC_NE4
FMC_A24
-
-
TS
TRACE
D2
SPI4_
MOSI
USART6_C
TS
EVENT
OUT
-
TRACE
D3
SPI4_
NSS
USART6_T QUADSPI_
EVENT
OUT
PG14
PG15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A25
-
-
-
X
BK2_IO3
USART6_C
TS
FMC_
SDNCAS
DCMI_
D13
EVENT
OUT
-
-
-
Table 11. Alternate function (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
SAI2/
AF11
AF12
AF13
DCMI
AF14
AF15
SYS
SPI2/3/
USART1/
2/3/UART
5/SPDIFR
X
SAI/
CAN1/2
Port
FMC/
SDIO/
OTG2_FS
TIM8/9/
10/11/
CEC
I2C1/2/3 SPI1/2/3/ SPI2/3/4/
/4/CEC
USART6/ TIM12/13/ QUADSPI/
UART4/5/ 14/ OTG2_HS/
SPDIFRX QUADSPI OTG1_FS
TIM1/2
TIM3/4/5
OTG1_FS
-
4
SAI1
EVENT
OUT
PH0
PH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port H
EVENT
OUT
1.
The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3.
STM32F446xC/E
Memory mapping
5
Memory mapping
The memory map is shown in Figure 15
Figure 15. Memory map
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DocID027107 Rev 6
67/202
71
Memory mapping
STM32F446xC/E
(1)
Table 12. STM32F446xC/E register boundary addresses
Bus
Boundary address
Peripheral
-
0xE00F FFFF - 0xFFFF FFFF
0xE000 0000 - 0xE00F FFFF
0xD000 0000 - 0xDFFF FFFF
0xC000 0000 - 0xCFFF FFFF
0xA000 2000 - 0x0xBFFF FFFF
0xA000 1000 - 0x0xA000 1FFF
0xA000 0000 - 0xA000 0FFF
0x9000 0000 - 0x9FFF FFFF
0x8000 0000 - 0x8FFF FFFF
0x7000 0000 - 0x0x7FFF FFFF
0x6000 0000 - 0x6FFF FFFF
0x5006 0C00- 0x5FFF FFFF
0x5006 0800- 0x500F 07FF
0x5005 0400 - 0x5006 07FF
0x5005 0000 - 0x5005 03FF
0x5004 0000- 0x5004 FFFF
0x5000 0000 - 0X5003 FFFF
Reserved
Cortex-M4
Cortex-M4 internal peripherals
FMC bank 6
FMC bank 5
Reserved
QuadSPI control register
FMC control register
QuadSPI
AHB3
FMC bank 3
Reserved
FMC bank 1
Reserved
-
Reserved
Reserved
AHB2
DCMI
Reserved
USB OTG FS
68/202
DocID027107 Rev 6
STM32F446xC/E
Memory mapping
(1)
Table 12. STM32F446xC/E register boundary addresses (continued)
Bus
Boundary address
Peripheral
-
0x4008 0000- 0x4FFF FFFF
0x4004 0000 - 0x4007 FFFF
0x4002 BC00- 0x4003 FFFF
0x4002 B000 - 0x4002 BBFF
0x4002 9400 - 0x4002 AFFF
0x4002 9000 - 0x4002 93FF
0x4002 8C00 - 0x4002 8FFF
0x4002 8800 - 0x4002 8BFF
0x4002 8400 - 0x4002 87FF
0x4002 8000 - 0x4002 83FF
0x4002 6800 - 0x4002 7FFF
0x4002 6400 - 0x4002 67FF
0x4002 6000 - 0x4002 63FF
0X4002 5000 - 0X4002 5FFF
0x4002 4000 - 0x4002 4FFF
0x4002 3C00 - 0x4002 3FFF
0x4002 3800 - 0x4002 3BFF
0X4002 3400 - 0X4002 37FF
0x4002 3000 - 0x4002 33FF
0x4002 2C00 - 0x4002 2FFF
0x4002 2800 - 0x4002 2BFF
0x4002 2400 - 0x4002 27FF
0x4002 2000 - 0x4002 23FF
0x4002 1C00 - 0x4002 1FFF
0x4002 1800 - 0x4002 1BFF
0x4002 1400 - 0x4002 17FF
0x4002 1000 - 0x4002 13FF
0X4002 0C00 - 0x4002 0FFF
0x4002 0800 - 0x4002 0BFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
Reserved
USB OTG HS
Reserved
DMA2
DMA1
Reserved
BKPSRAM
Flash interface register
AHB1
RCC
Reserved
CRC
Reserved
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
DocID027107 Rev 6
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71
Memory mapping
STM32F446xC/E
(1)
Table 12. STM32F446xC/E register boundary addresses (continued)
Bus
Boundary address
Peripheral
-
0x4001 6C00- 0x4001 FFFF
0x4001 6800 - 0x4001 6BFF
0x4001 5C00 - 0x4001 5FFF
0x4001 6000 - 0x4001 67FF
0x4001 5800 - 0x4001 5BFF
0x4001 5400 - 0x4001 57FF
0x4001 5000 - 0x4001 53FF
0x4001 4C00 - 0x4001 4FFF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2400 - 0x4001 2BFF
0x4001 2000 - 0x4001 23FF
0x4001 1800 - 0x4001 1FFF
0x4001 1400 - 0x4001 17FF
0x4001 1000 - 0x4001 13FF
0x4001 0800 - 0x4001 0FFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
Reserved
SAI2
Reserved
SAI1
Reserved
TIM11
TIM10
TIM9
EXTI
APB2
SYSCFG
SPI4
SPI1
SDIO
Reserved
ADC1 - ADC2 - ADC3
Reserved
USART6
USART1
Reserved
TIM8
TIM1
70/202
DocID027107 Rev 6
STM32F446xC/E
Memory mapping
(1)
Table 12. STM32F446xC/E register boundary addresses (continued)
Bus
Boundary address
Peripheral
-
0x4000 8000- 0x4000 FFFF
0x4000 7C00 - 0x4000 7FFF
0x4000 7800 - 0x4000 7BFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6C00 - 0x4000 6FFF
0x4000 6800 - 0x4000 6BFF
0x4000 6400 - 0x4000 67FF
0x4000 6000 - 0x4000 63FF
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 2400 - 0x4000 27FF
0x4000 2000 - 0x4000 23FF
0x4000 1C00 - 0x4000 1FFF
0x4000 1800 - 0x4000 1BFF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
Reserved
DAC
PWR
HDMI-CEC
CAN2
CAN1
FMPI2C1
I2C3
I2C2
I2C1
UART5
UART4
USART3
USART2
SPDIFRX
SPI3 / I2S3
SPI2 / I2S2
Reserved
IWDG
APB1
WWDG
RTC & BKP Registers
Reserved
TIM14
TIM13
TIM12
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2
1. The grey color is used for reserved boundary addresses.
DocID027107 Rev 6
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71
Electrical characteristics
STM32F446xC/E
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
A
DD
1.7 V ≤ V ≤ 3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 16.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 17.
Figure 16. Pin loading conditions
Figure 17. Pin input voltage
-#5 PIN
-#5 PIN
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72/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
6.1.6
Power supply scheme
Figure 18. Power supply scheme
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1. VDDA and VSSA must be connected to VDDand VSS, respectively.
2. VDDUSB is a dedicated independent USB power supply for the on-chip full-speed OTG PHY module and
associated DP/DM GPIOs. Its value is independent from the VDD and VDDA values, but must be the last
supply to be provided and the first to disappear. If VDD is different from VDDUSB and only one on-chip OTG
PHY is used, the second OTG PHY GPIOs (DP/DM) are still supplied at VDDUSB (3.3V).
3. VDDUSB is available only on WLCSP81, UFBGA144 and LQFP144 packages. For packages where VDDUSB
pin is not available, it is internally connected to VDD
.
4. VCAP_2 pad is not available on LQFP64.
Caution:
Each power supply pair (V /V , V
/V
...) must be decoupled with filtering ceramic
DD SS
DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
DocID027107 Rev 6
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175
Electrical characteristics
STM32F446xC/E
6.1.7
Current consumption measurement
Figure 19. Current consumption measurement scheme
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6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 13: Voltage characteristics,
Table 14: Current characteristics, and Table 15: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 13. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage (including VDDA, VDD,
VDD–VSS
–0.3
4.0
(1)
VDDUSB and VBAT
)
Input voltage on FT & FTf pins(2)
VSS–0.3 VDD+4.0
V
Input voltage on TTa pins
VSS–0.3
4.0
4.0
9.0
50
VIN
Input voltage on any other pin
V
SS–0.3
Input voltage on BOOT0 pin
VSS
|ΔVDDx
|
Variations between different VDD power pins
Variations between all the different ground pins
-
-
mV
-
|VSSX −VSS
|
50
see Section 6.3.15:
Absolute maximum
ratings (electrical
sensitivity)
VESD(HBM)
Electrostatic discharge voltage (human body model)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Table 14 for the values of the maximum allowed
injected current.
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Symbol
Electrical characteristics
Table 14. Current characteristics
Ratings
Max.
Unit
ΣIVDD
Σ IVSS
Σ IVDDUSB
IVDD
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
Total current into VDDUSB power line (source)
240
- 240
25
Maximum current into each VDD power pin (source)(1)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin
Output current sourced by any I/Os and control pin
Total output current sunk by sum of all I/Os and control pins (2)
Total output current sunk by sum of all USB I/Os
Total output current sourced by sum of all I/Os and control pins(2)
Injected current on FT, FTf, RST and B pins
100
IVSS
- 100
25
IIO
- 25
mA
120
ΣIIO
25
-120
–5/+0(3)
±5(4)
±25
IINJ(PIN)
Injected current on TTa pins
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(5)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified
maximum value.
4. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 13 for the maximum allowed input voltage value.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 15. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
125
°C
°C
Maximum junction temperature
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STM32F446xC/E
6.3
Operating conditions
6.3.1
General operating conditions
Table 16. General operating conditions
Symbol
Parameter
Conditions(1)
Min Typ
Max
Unit
Power Scale 3 (VOS[1:0] bits in
PWR_CR register = 0x01),
Regulator ON, over-drive OFF
0
-
-
-
-
-
120
Over-
drive
OFF
144
168
168
180
Power Scale 2 (VOS[1:0] bits
in PWR_CR register = 0x10),
Regulator ON
0
Over-
drive
ON
fHCLK
Internal AHB clock frequency
Over-
drive
OFF
MHz
Power Scale 1 (VOS[1:0] bits
in PWR_CR register= 0x11),
Regulator ON
0
Over-
drive
ON
Over-drive OFF
Over-drive ON
Over-drive OFF
Over-drive ON
0
0
0
0
-
-
-
-
42
45
84
90
fPCLK1 Internal APB1 clock frequency
fPCLK2 Internal APB2 clock frequency
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Symbol
Electrical characteristics
Table 16. General operating conditions (continued)
Parameter Min Typ
Conditions(1)
Max
Unit
VDD
Standard operating voltage
-
1.7(2)
1.7(2)
-
-
3.6
Analog operating voltage
2.4
3.6
(ADC limited to 1.2 M samples)
(3)(4)
(5)
VDDA
Must be the same potential as VDD
Analog operating voltage
2.4
-
(ADC limited to 2.4 M samples)
VBAT
Backup operating voltage
USB supply voltage (supply
-
1.65
1.7
-
-
3.6
3.6
USB not used
VDDUSB voltage for PA11,PA12, PB14
and PB15 pins)
USB used
3
-
3.6
Power Scale 3 ((VOS[1:0] bits in
PWR_CR register = 0x01), 120 MHz 1.08 1.14
HCLK max frequency
1.20
V
Power Scale 2 ((VOS[1:0] bits in
PWR_CR register = 0x10), 144 MHz
HCLK max frequency with over-drive
OFF or 168 MHz with over-drive ON
Regulator ON: 1.2 V internal
voltage on VCAP_1/VCAP_2 pins
1.20 1.26
1.32
1.40
V12
Power Scale 1 ((VOS[1:0] bits in
PWR_CR register = 0x11), 168 MHz
1.26 1.32
HCLK max frequency with over-drive
OFF or 180 MHz with over-drive ON
Max frequency 120 MHz
Max frequency 144 MHz
Max frequency 168 MHz
2 V ≤VDD ≤3.6 V
1.7 V ≤ VDD ≤ 2 V
-
1.10 1.14
1.20 1.26
1.26 1.32
1.20
1.32
1.38
5.5
Regulator OFF: 1.2 V external
voltage must be supplied from
external regulator on
VCAP_1/VCAP_2 pins(6)
–0.3
–0.3
–0.3
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Input voltage on RST, FTf and
FT pins(7)
5.2
VIN
V
Input voltage on TTa pins
V
DDA+0.3
9
Input voltage on BOOT0 pin
-
LQFP64
-
345
417
476
606
392
417
85
WLCSP81
-
Power dissipation at TA = 85 °C
LQFP100
-
PD
for suffix 6 or TA = 105 °C for
mW
suffix 7(8)
LQFP 144
-
UFBGA144 (7x7)
UFBGA144(10x10)
Maximum power dissipation
Low power dissipation(9)
Maximum power dissipation
Low power dissipation(9)
6 suffix version
-
-
–40
–40
–40
–40
–40
–40
Ambient temperature for 6 suffix
version
°C
°C
°C
105
105
125
105
125
TA
TJ
Ambient temperature for 7 suffix
version
Junction temperature range
7 suffix version
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1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.
2. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.16.2:
Internal reset OFF).
3. When the ADC is used, refer to Table 74: ADC characteristics.
4. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
5. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and power-down operation.
6. The over-drive mode is not supported when the internal regulator is OFF.
7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
8. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax
.
9. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax
.
Table 17. Limitations depending on the operating power supply range
Maximum Flash
Maximum HCLK
memory access
frequency vs Flash
Operating
Possible Flash
memory
operations
powersupply ADC operation frequency with
I/O operation
memory wait states
range
no wait states
(fFlashmax
(1)(2)
)
168 MHz with 8 wait
states and over-drive
OFF
8-bit erase and
program
operations only
VDD =1.7 to Conversion time
– No I/O
compensation
20 MHz(4)
22 MHz
24 MHz
30 MHz
2.1 V(3)
up to 1.2 Msps
180 MHz with 8 wait
states and over-drive
ON
16-bit erase and
program
operations
VDD = 2.1 to Conversion time
2.4 V up to 1.2 Msps
– No I/O
compensation
180 MHz with 7 wait – I/O
states and over-drive
ON
16-bit erase and
program
operations
VDD = 2.4 to Conversion time
2.7 V up to 2.4 Msps
compensation
works
180 MHz with 5 wait – I/O
states and over-drive
ON
32-bit erase and
program
operations
VDD = 2.7 to Conversion time
3.6 V(5)
up to 2.4 Msps
compensation
works
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.16.2:
Internal reset OFF).
4. Prefetch is not available.
5. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+
pins will be degraded between 2.7 and 3 V.
6.3.2
VCAP_1/VCAP_2 external capacitor
Stabilization for the main regulator is achieved by connecting external capacitor C
to the
EXT
V
and V
pin. For packages supporting only 1 V
pin, the 2 C
capacitors are
CAP_1
CAP_2
CAP
EXT
replaced by a single capacitor. C
is specified in Table 18.
EXT
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Electrical characteristics
Figure 20. External capacitor C
EXT
&
(65
5ꢈ/HDN
06ꢄꢊꢉꢂꢂ9ꢇ
1. Legend: ESR is the equivalent series resistance.
(1)
Table 18. VCAP_1/VCAP_2 operating conditions
Symbol
Parameter
Conditions
CEXT
ESR
Capacitance of external capacitor
ESR of external capacitor
2.2 µF
< 2 Ω
Capacitance of external capacitor with a
single VCAP pin available
CEXT
ESR
4.7 µF
ESR of external capacitor with a single
VCAP pin available
< 1 Ω
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
6.3.3
Operating conditions at power-up / power-down (regulator ON)
Subject to general operating conditions for T .
A
Table 19. Operating conditions at power-up/power-down (regulator ON)
Symbol
Parameter
Min
Max
VDD rise time rate
20
20
∞
∞
tVDD
VDD fall time rate
6.3.4
Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for T .
A
(1)
Table 20. Operating conditions at power-up / power-down (regulator OFF)
Symbol
Parameter
VDD rise time rate
DD fall time rate
VCAP_1 and VCAP_2 rise time rate Power-up
CAP_1 and VCAP_2 fall time rate Power-down
Conditions
Power-up
Power-down
Min
Max
Unit
20
20
20
20
∞
∞
∞
∞
tVDD
V
µs/V
tVCAP
V
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
1.08 V.
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6.3.5
Reset and power control block characteristics
The parameters given in Table 21 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 16.
DD
Table 21. reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
PLS[2:0]=000 (rising edge)
PLS[2:0]=000 (falling edge)
PLS[2:0]=001 (rising edge)
PLS[2:0]=001 (falling edge)
PLS[2:0]=010 (rising edge)
PLS[2:0]=010 (falling edge)
PLS[2:0]=011 (rising edge)
PLS[2:0]=011 (falling edge)
PLS[2:0]=100 (rising edge)
PLS[2:0]=100 (falling edge)
PLS[2:0]=101 (rising edge)
PLS[2:0]=101 (falling edge)
PLS[2:0]=110 (rising edge)
PLS[2:0]=110 (falling edge)
PLS[2:0]=111 (rising edge)
PLS[2:0]=111 (falling edge)
-
2.09
1.98
2.23
2.13
2.39
2.29
2.54
2.44
2.70
2.59
2.86
2.65
2.96
2.85
3.07
2.95
-
2.14 2.19
2.04 2.08
2.30 2.37
2.19 2.25
2.45 2.51
2.35 2.39
2.60 2.65
2.51 2.56
2.76 2.82
2.66 2.71
2.93 2.99
2.84 3.02
3.03 3.10
2.93 2.99
3.14 3.21
3.03 3.09
V
V
V
V
V
V
V
V
Programmable voltage
detector level selection
VPVD
V
V
V
V
V
V
V
V
(1)
VPVDhyst
PVD hysteresis
100
-
mV
V
Falling edge
1.60
1.64
-
1.68 1.76
1.72 1.80
Power-on/power-down
reset threshold
VPOR/PDR
Rising edge
V
(1)
VPDRhyst
PDR hysteresis
-
40
-
mV
V
Falling edge
2.13
2.23
2.44
2.53
2.75
2.85
-
2.19 2.24
2.29 2.33
2.50 2.56
2.59 2.63
2.83 2.88
2.92 2.97
Brownout level 1
threshold
VBOR1
VBOR2
VBOR3
Rising edge
V
Falling edge
V
Brownout level 2
threshold
Rising edge
V
Falling edge
V
Brownout level 3
threshold
Rising edge
V
(1)
VBORhyst
BOR hysteresis
-
100
1.5
-
mV
TRSTTEMPO
POR reset temporization -
0.5
3.0
ms
(1)(2)
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Electrical characteristics
Table 21. reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ Max Unit
InRush current on
voltage regulator power-
on (POR or wakeup
from Standby)
(1)
IRUSH
-
-
160
-
200
5.4
mA
µC
InRush energy on
voltage regulator power- VDD = 1.7 V, TA = 105 °C,
on (POR or wakeup
from Standby)
(1)
ERUSH
-
IRUSH = 171 mA for 31 µs
1. Guaranteed based on test during characterization.
2. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant
when first instruction is read by the user application code.
6.3.6
Over-drive switching characteristics
When the over-drive mode switches from enabled to disabled or disabled to enabled, the
system clock is stalled during the internal voltage set-up.
The over-drive switching characteristics are given in Table 22. They are sbject to general
operating conditions for T .
A
(1)
Table 22. Over-drive switching characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
HSI
-
45
-
HSE max for 4 MHz
and min for 26 MHz
Over_drive switch
enable time
45
-
100
Tod_swen
External HSE
50 MHz
-
-
40
20
-
-
-
µs
HSI
HSE max for 4 MHz
and min for 26 MHz.
Over_drive switch
disable time
20
80
Tod_swdis
External HSE
50 MHz
-
15
-
1. Guaranteed based on test during characterization.
6.3.7
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 19: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark code.
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Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in input mode with a static value at V or V (no load).
DD SS
All peripherals are disabled except if it is explicitly mentioned.
The Flash memory access time is adjusted both to f frequency and V range
HCLK
DD
(see Table 17: Limitations depending on the operating power supply range).
•
•
Regulator ON
The voltage scaling and over-drive mode are adjusted to f
frequency as follows:
HCLK
–
–
–
Scale 3 for f
≤120 MHz
HCLK
Scale 2 for 120 MHz < f
Scale 1 for 144 MHz < f
≤144 MHz
HCLK
HCLK
PCLK1
≤180 MHz. The over-drive is only ON at 180 MHz.
= f /4, and f = f /2.
•
•
•
•
The system clock is HCLK, f
HCLK
PCLK2
HCLK
External clock frequency is 8 MHz and PLL is ON when f
is higher than 16 MHz.
HCLK
Flash is enabled except if explicitly mentioned as disable.
The maximum values are obtained for V = 3.6 V and a maximum ambient
DD
temperature (T ), and the typical values for T = 25 °C and V = 3.3 V unless
A
A
DD
otherwise specified.
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Table 23. Typical and maximum current consumption in Run mode, code with data processing
(1)
running from Flash memory (ART accelerator enabled except prefetch) or RAM
Max(2)
Symbol
Parameter
Conditions
fHCLK (MHz)
Typ
Unit
TA =
TA =
TA =
25 °C
85 °C
105 °C
180
168
150
144(6)
120
90
72
65
59
54
40
30
21
12
10
6
83.0(5)
71.0
63.6
58.4
44.9
35.3
25.5
16.2
14.41
11.4
9.5
100.0
95.3
85.4
78.8
62.1
50.7
39.2
28.1
26.17
23.1
20.3
18.9
18.1
59.0
51.4
47.8
44.7
36.8
31.8
26.9
22.1
21.24
18.9
17.8
17.23
16.94
110.0(5)
101.0
100.8
91.2
External clock,
PLL ON,
73.2
all peripherals
enabled(3)(4)
60.0
60
46.8
30
36.0
25
32.4
16
25.2
HSI, PLL OFF,
all peripherals
enabled
8
3
22.5
4
2.3
1.8
32
29
26
24
18
14
10
6
8.3
21.1
Supply
2
7.7
20.5
IDD
current in
RUN mode
mA
180
168
150
144(6)
120
90
42.0(5)
35.5
31.5
29.2
23.3
19.0
14.7
10.7
9.96
8.7
75.0(5)
55.7
51.9
External clock,
PLL ON,
48.6
40.4
all Peripherals
disabled(3)
35.1
60
29.9
30
24.9
25
5
24.02
21.9
16
3
HSI, PLL OFF,
all peripherals
disabled(3)
8
2
8.1
20.9
4
1.7
1.4
7.64
7.4
20.32
20.03
2
1. Code and data processing running from SRAM1 using boot pins.
2. Guaranteed based on test during characterization.
3. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.
5. Tested in production.
6. Overdrive OFF
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STM32F446xC/E
Table 24. Typical and maximum current consumption in Run mode, code with data processing
(1)
running from Flash memory (ART accelerator enabled with prefetch) or RAM
Max(2)
Symbol
Parameter
Conditions
fHCLK (MHz)
Typ
Unit
TA =
TA =
TA =
25 °C
85 °C
105 °C
180
168(5)
150
144(5)
120
90
86
79
73
68
54
42
29
16
13
8
93.0
85.1
79.6
73.5
59.3
47.23
33.7
20.8
18.4
13.8
10.8
9.1
115.0
111.2
104.8
97.3
79.7
65.50
49.5
34.0
31.2
25.0
21.1
18.9
17.8
75.0
67.5
65.8
61.9
53.7
46.0
36.4
27.1
25.40
21.8
19.4
18.10
17.39
125.0
117.7
111.2
103.3
84.7
70.10
53.4
37.4
34.5
28.3
24.2
22.0
20.9
86.0
72.6
70.8
66.8
58.0
50.0
40.1
30.2
28.54
25.0
22.5
21.17
20.50
External clock,
PLL ON,
all peripherals
enabled(3)(4)
60
30
25
16
HSI, PLL OFF,
all peripherals
enabled(3)(4)
8
5
4
3.0
2.1
46
43
41
38
32
26
18
10
9
Supply
2
8.1
IDD
current in
RUN mode
mA
180
168
150
144(5)
120
90
55.0
49.6
48.2
43.6
37.3
30.7
22.8
14.9
13.55
11.1
9.5
External clock,
PLL ON,
all Peripherals
disabled(3)
60
30
25
16
5
HSI, PLL OFF,
all peripherals
disabled(3)
8
3
4
2.4
1.8
8.34
7.77
2
1. Code and data processing running from SRAM1 using boot pins.
2. Guaranteed based on test during characterization.
3. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.
5. Overdrive OFF
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Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled)
Max(1)
Symbol
Parameter
Conditions
fHCLK (MHz)
Typ
Unit
TA=
25 °C
TA=85 °C TA=105 °C
180
168(4)
150
144(4)
120
90
81
74
69
63
51
40
28
16
13
8
89.0
80.2
74.9
69.3
56.3
45.32
33.1
20.8
18.4
13.8
10.8
9.1
110.0
105.7
99.5
92.4
76.1
63.19
48.7
34.0
31.2
25.0
21.1
19.0
17.9
69.0
61.9
60.3
56.9
50.2
43.6
35.6
27.0
25.36
21.8
19.4
18.12
17.42
120.0
112.0
105.6
98.1
81.1
67.63
52.6
37.4
34.5
28.2
24.2
22.0
20.9
79.0
67.1
65.4
61.6
54.4
47.5
39.2
30.1
28.47
24.9
22.5
21.17
20.51
External clock,
PLL ON,
all peripherals
enabled(2)(3)
60
30
25
16
8
5
4
3.0
2.1
41
38
37
34
29
24
17
10
8
Supply
External clock,
PLL ON,
2
8.1
IDD
current in
RUN mode
mA
180
168
150
144(4)
120
90
47.0
43.2
41.8
39.3
34.3
28.8
22.0
14.8
13.51
11.1
9.5
all Peripherals
disabled(2)(3)
HSI, PLL OFF,
all peripherals
disabled(3)
60
30
25
16
5
HSI, PLL OFF,
all Peripherals
disabled(3)
8
3
4
2.3
1.8
8.35
7.78
2
1. Guaranteed based on test during characterization unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for
the analog part.
4. Overdrive OFF
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(1)
Table 26. Typical and maximum current consumption in Sleep mode
Max
fHCLK
(MHz)
Symbol Parameter
Conditions
Typ
Unit
TA = 25
°C
TA = 25
°C
TA = 25
°C
180
168(2)
150
144(2)
120
90
51.2
46.8
42.2
38.6
29.3
22.8
16.3
10.1
9.0
59.00
53.94
49.26
45.37
35.70
29.17
22.41
16.03
14.92
13.10
12.31
11.63
11.23
77.25
66.48
60.84
55.47
42.49
34.78
27.12
19.72
18.41
15.1
102.00
79.40
73.41
66.96
51.46
43.12
External
clock,
PLL ON,
Flash on
Supply
current in
Sleep
mode
all
IDD
peripherals
enabled
60
34.83
26.86
25.38
22.3
mA
30
25
16
6.5
HSI, PLL
off, Flash
on
8
5.2
13.5
20.4
4
4.5
12.5
19.3
2
4.1
12.0
18.8
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(1)
Table 26. Typical and maximum current consumption in Sleep mode (continued)
Max
fHCLK
(MHz)
Symbol Parameter
Conditions
Typ
Unit
TA = 25
°C
TA = 25
°C
TA = 25
°C
180
168(2)
150
144(2)
120
90
11.36
10.20
9.53
8.90
7.35
6.39
5.28
4.43
4.23
8.3
17.59
16.19
15.59
14.87
13.24
12.40
11.17
10.31
10.12
13.44
12.25
11.60
11.08
9.64
28.2
22.0
51.6
31.8
21.1
30.9
19.7
28.4
Flash on
16.5
23.3
15.3
21.9
60
14.1
20.7
30
13.1
19.6
25
12.85
30.72
25.16
24.27
23.25
20.95
19.77
18.69
17.66
17.43
30.72
25.16
24.27
23.25
20.95
19.77
18.69
17.66
17.43
19.30
37.20
28.80
27.84
26.28
23.72
22.57
21.32
20.40
20.17
37.20
28.80
27.84
26.28
23.72
22.57
21.32
20.40
20.17
180
168(2)
150
144(2)
120
90
7.3
6.7
External
clock, PLL Deep
on all Power
peripherals Down
Flash in
6.1
Supply
current in
Sleep
IDD
4.7
mA
mode
3.8
8.80
disabled
mode
60
2.8
7.74
30
2.0
6.89
25
1.8
6.70
180
168(2)
150
144(2)
120
90
8.3
13.44
12.25
11.60
11.08
9.64
7.3
6.7
6.1
Flash in
STOP
mode
4.7
3.8
8.80
60
2.8
7.74
30
2.0
6.89
25
1.8
6.70
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(1)
Table 26. Typical and maximum current consumption in Sleep mode (continued)
Max
fHCLK
(MHz)
Symbol Parameter
Conditions
Typ
Unit
TA = 25
°C
TA = 25
°C
TA = 25
°C
16
8
3.89
2.45
1.69
1.28
1.0
4.93
3.29
2.56
2.22
6.65
6.93
6.90
6.88
6.7
11.72
11.66
11.60
11.57
16.54
16.48
16.43
16.41
16.5
18.54
18.46
18.40
18.37
19.50
19.45
19.39
19.37
19.5
Flash on
4
2
16
8
Flash in
Deep
Power
Down
mode
Supply
current in
HSI, PLL
off, all
0.9
IDD
mA
Sleep
mode
peripherals
disabled
4
0.9
2
0.9
16
8
1.0
Flash in
STOP
mode
0.9
6.9
16.5
19.5
4
0.9
6.9
16.4
19.4
2
0.9
6.9
16.4
19.4
1. Guaranteed based on test during characterization unless otherwise specified.
2. Overdrive OFF
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Electrical characteristics
Table 27. Typical and maximum current consumptions in Stop mode
Max
VDD = 3.6 V
TA =
Typ
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA =
25 °C 25 °C(1) 85 °C 105 °C(1)
Flash memory in Stop mode, all
oscillators OFF, no independent 0.234
watchdog
1.2
1
10
9.5
8.5
6
16
15
14
12
Supply current in
Stop mode with
voltage regulator in
main regulator mode
Flash memory in Deep power
down mode, all oscillators OFF, 0.205
no independent watchdog
IDD_STOP_NM
(normal
Flash memory in Stop mode, all
mode)
Supply current in
Stop mode with
voltage regulator in
Low Power regulator
mode
oscillators OFF, no independent
watchdog
0.15
0.95
0.9
Flash memory in Deep power
down mode, all oscillators OFF, 0.121
no independent watchdog
mA
Supply current in
Stop mode with
voltage regulator in
main regulator and
under-drive mode
Flash memory in Deep power
down mode, main regulator in
under-drive mode, all oscillators
OFF, no independent watchdog
0.119
0.4
3
3
5
5
IDD_STOP_UD
M(under-
drive mode)
Supply current in
Stop mode with
voltage regulator in
Low Power regulator
and under-drive
mode
Flash memory in Deep power
down mode, Low Power
regulator in under-drive mode,
all oscillators OFF, no
0.055
0.35
independent watchdog
1. Data based on characterization, tested in production.
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Table 28. Typical and maximum current consumptions in Standby mode
Typ(1)
Max(2)
TA =
TA =
TA =
TA = 25 °C
Symbol
Parameter
Conditions
25 °C 85 °C 105 °C Unit
VDD
1.7 V
=
VDD
2.4 V
=
VDD =
3.3 V
VDD = 3.3 V
Backup SRAM ON, and LSE
oscillator in low power mode
2.43
3.44
4.12
7
6
20
17
36
31
Backup SRAM OFF, RTC ON
and LSE oscillator in low
power mode
1.81
3.32
2.57
2.81
4.33
3.59
3.33
4.95
4.16
Backup SRAM ON, RTC ON
and LSE oscillator in high
drive mode
8
7
21
18
37
32
Supply
IDD_STBY current in
Standby mode
µA
Backup SRAM OFF, RTC ON
and LSE oscillator in high
drive mode
Backup SRAM ON, RTC and
LSE OFF
2.03
1.28
2.73
1.97
3.5
6(3)
5(3)
19
16
35(3)
30(3)
Backup SRAM OFF, RTC
and LSE OFF
2.03
1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.
2. Guaranteed based on test during characterization unless otherwise specified.
3. Tested in production.
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Electrical characteristics
Table 29. Typical and maximum current consumptions in V
mode
Max(2)
BAT
Typ
TA =
85 °C
TA =
105 °C
TA = 25 °C
Symbol Parameter
Conditions(1)
Unit
VBAT
=
1.7 V
VBAT
=
3.3 V
VBAT
2.4 V
=
VBAT = 3.6 V
Backup SRAM ON, RTC ON
and LSE oscillator in low power
mode
1.46
0.72
2.24
1.50
1.62
1.83
1.00
2.64
1.86
6
3
-
11
5
-
Backup SRAM OFF, RTC ON
0.85
2.40
1.64
and LSE oscillator in low power
mode
Backup SRAM ON, RTC ON
Backup
and LSE oscillator in high drive
mode
domain
supply
IDD_VBAT
µA
current
Backup SRAM OFF, RTC ON
-
-
and LSE oscillator in high drive
mode
Backup SRAM ON, RTC and
LSE OFF
0.74
0.05
0.75
0.05
0.78
0.05
5
2
10
4
Backup SRAM OFF, RTC and
LSE OFF
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Guaranteed based on test during characterization.
Figure 21. Typical V
current consumption
BAT
(RTC ON/backup RAM OFF and LSE in low power mode)
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STM32F446xC/E
Figure 22. Typical V
current consumption
BAT
(RTC ON/backup RAM OFF and LSE in high drive mode)
Additional current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are configured in analog mode.
The Flash memory access time is adjusted to fHCLK frequency.
The voltage scaling is adjusted to fHCLK frequency as follows:
–
–
–
Scale 3 for f
≤ 120 MHz,
HCLK
Scale 2 for 120 MHz < f
Scale 1 for 144 MHz < f
≤ 144 MHz
HCLK
HCLK
PCLK1
≤ 180 MHz. The over-drive is only ON at 180 MHz.
•
•
•
•
The system clock is HCLK, f
= f
/4, and f
= f
/2.
HCLK
HCLK
PCLK2
HSE crystal clock frequency is 8 MHz.
Flash is enabled except if explicitly mentioned as disable.
When the regulator is OFF, V12 is provided externally as described in Table 16:
General operating conditions
•
T = 25 °C.
A
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Electrical characteristics
Table 30. Typical current consumption in Run mode, code with data processing
running from Flash memory or RAM, regulator ON
(ART accelerator enabled except prefetch), VDD=1.7 V
(1)
Max
Symbol
Parameter
Conditions
fHCLK (MHz)
Typ
Unit
TA =
TA =
TA =
25 °C
85 °C
105 °C
168
150
144
120
90
65.11
58.31
53.14
39.58
29.99
20.37
11.37
9.65
70.0
62.8
79.7
73.4
69.9
60.7
45.23
35.2
28.4
17.8
42.4
39.4
36.0
32.9
30.0
24.4
15.0
12.57
90.0
79.9
75.3
71.4
49.34
38.2
33.2
24.3
48.5
43.8
41.9
40.8
36.5
30.2
22.0
19.06
57.1
47.2
All Peripherals
enabled
34.70
25.2
60
30
12.9
Supply current in
Run mode from
VDD supply
25
10.9
IDD
mA
168
150
144
120
90
29.74
25.81
24.57
17.69
13.58
9.41
32.43
29.12
26.61
22.09
15.92
11.05
6.64
All Peripherals
disabled
60
30
5.44
25
4.73
5.72
1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC,
or DAC) is not included.
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STM32F446xC/E
Table 31. Typical current consumption in Run mode, code with data processing running
(1)
from Flash memory, regulator OFF (ART accelerator enabled except prefetch)
VDD=3.3 V
VDD=1.7 V
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
IDD12
IDD
IDD12
IDD
168
150
144
120
90
61.72
51.69
51.45
38.94
29.48
19.23
10.41
8.83
1.6
1.5
1.5
1.3
1.1
1.0
0.9
0.8
1.6
1.5
1.5
1.3
1.2
1.0
0.9
0.8
60.15
55.46
50.94
40.66
28.18
20.05
11.26
9.56
1.5
1.4
1.3
1.2
1.0
0.8
0.7
0.6
1.5
1.4
1.3
1.2
1.0
0.8
0.7
0.6
All Peripherals
enabled
60
30
Supply current in
Run mode from
V12 and VDD
supply
25
IDD12 / IDD
mA
168
150
144
120
90
31.44
28.67
25.51
19.06
14.83
10.16
5.41
30.06
27.38
23.37
21.73
14.74
10.30
5.64
All Peripherals
disabled
60
30
25
4.599
4.80
1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC,
or DAC) is not included.
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Electrical characteristics
(1)
Table 32. Typical current consumption in Sleep mode, regulator ON, V =1.7 V
DD
Max
Symbol
Parameter
Conditions
fHCLK (MHz)
Typ
Unit
TA =
TA =
TA =
25 °C
85 °C
105 °C
168
150
144
120
90
43.7
39.2
35.7
26.5
20.0
13.6
7.4
47.5
42.7
38.8
28.6
21.91
15.2
8.5
66.5
60.7
55.3
41.8
33.85
25.8
18.4
16.9
21.2
20.4
18.6
14.9
13.6
12.5
11.3
11.09
79.3
73.3
66.9
51.6
43.20
34.9
27.0
25.5
31.9
31.0
28.5
23.4
22.1
20.8
19.7
19.42
All Peripherals
enabled Flash
on
60
30
Supply current in
Sleep mode from
VDD supply
25
6.3
7.5
IDD
mA
168
150
144
120
90
7.3
8.6
6.6
7.94
7.3
6.0
All Peripherals
disabled, flash
on
4.6
5.5
3.6
4.6
60
2.6
3.4
30
1.8
2.7
25
1.6
2.49
1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC,
or DAC) is not included.
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(1)
Table 33. Typical current consumption in Sleep mode, regulator OFF
VDD=3.3 V
VDD=1.7 V
Unit
-
Symbol
Parameter
Conditions
fHCLK (MHz)
IDD12
IDD
IDD12
IDD
180
168
150
144
120
90
47.605
44.35
40.58
35.68
27.30
20.69
13.88
7.66
1.2
1.0
0.9
0.9
0.9
0.8
0.7
0.7
0.7
1.2
0.9
0.9
0.9
0.9
0.8
0.7
0.7
0.7
NA
41.53
39.96
34.60
29.11
19.78
13.36
7.85
6.66
NA
NA
0.8
0.8
0.7
0.7
0.6
0.6
0.6
0.5
NA
0.8
0.8
0.7
0.7
0.6
0.6
0.6
0.5
All Peripherals
enabled
60
30
Supply current
in Sleep mode
from V12 and
VDD supply
25
6.49
IDD12/IDD
mA
180
168
150
144
120
90
8.71
7.00
8.42
7.61
6.99
5.95
3.96
2.80
1.74
1.52
6.88
6.29
All Peripherals
disabled
4.87
3.78
60
2.66
30
1.65
25
1.45
1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC,
or DAC) is not included.
I/O system current consumption
The current consumption of the I/O system has two components: static and
dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 56: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
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Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 35: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
ISW = VDD × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
is the MCU supply voltage
SW
V
DD
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
INT
EXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
(1)
Table 34. Switching output I/O current consumption
I/O toggling
Symbol
Parameter
Conditions
Typ
Unit
frequency
(fsw)
2 MHz
8 MHz
0.0
0.2
25 MHz
50 MHz
60 MHz
84 MHz
90 MHz
2 MHz
0.6
VDD = 3.3 V
1.1
(2)
C= CINT
1.3
1.8
1.9
I/O switching
Current
IDDIO
mA
0.1
8 MHz
0.4
VDD = 3.3 V
CEXT = 0 pF
25 MHz
50 MHz
60 MHz
84 MHz
90 MHz
1.23
2.43
2.93
3.86
4.07
C = CINT + CEXT
+ CS
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STM32F446xC/E
(1)
Table 34. Switching output I/O current consumption (continued)
I/O toggling
Symbol
Parameter
Conditions
Typ
Unit
frequency
(fsw)
2 MHz
8 MHz
0.18
0.67
2.09
3.6
VDD = 3.3 V
25 MHz
50 MHz
60 MHz
84 MHz
90 MHz
2 MHz
CEXT = 10 pF
C = CINT + CEXT
+ CS
4.5
7.8
9.8
0.26
1.01
3.14
6.39
10.68
0.33
1.29
4.23
11.02
I/O switching
Current
IDDIO
mA
VDD = 3.3 V
8 MHz
CEXT = 22 pF
25 MHz
50 MHz
60 MHz
2 MHz
C = CINT + CEXT
+ CS
VDD = 3.3 V
8 MHz
CEXT = 33 pF
C = CINT + Cext
+ CS
25 MHz
50 MHz
1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value).
2. This test is performed by cutting the LQFP144 package pin (pad removal).
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
•
•
At startup, all I/O pins are in analog input configuration.
All peripherals are disabled unless otherwise mentioned.
HCLK is the system clock. f
= f
/4, and f
= f
/2.
PCLK1
HCLK
PCLK2
HCLK
The given value is calculated by measuring the difference of current consumption
–
–
–
with all peripherals clocked off
with only one peripheral clocked on
f
f
= 180 MHz (Scale1 + over-drive ON), f
= 120 MHz (Scale 3)"
= 144 MHz (Scale 2),
HCLK
HCLK
HCLK
•
Ambient operating temperature is 25 °C and V =3.3 V.
DD
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Electrical characteristics
Table 35. Peripheral current consumption
IDD(Typ Appli)
Peripheral
Unit
Scale 1 +
OverDrive
Scale 2
Scale 3
GPIOA
2.29
2.29
2.14
2.13
1.89
1.89
GPIOB
GPIOC
GPIOD
GPIOE
2.33
2.17
1.93
2.34
2.19
1.94
2.39
2.19
1.93
GPIOF
2.31
2.14
1.91
AHB1
GPIOG
GPIOH
CRC
2.36
2.19
1.94
µA/MHz
2.13
1.98
1.75
0.53
0.51
0.46
BKPSRAM
DMA1(1)
DMA2(1)
OTG_HS+ULPI
DCMI
0.76
0.72
0.65
2.39N + 4.13
2.39N + 4.45
45.45
3.74
2.23N+3.56
2.19N+3.72
42.08
3.42
1.97N+3.51
2.00N+3.66
37.28
3.01
AHB2
AHB3
µA/MHz
µA/MHz
OTGFS
FMC
30.04
16.15
16.78
27.88
15.01
15.60
24.69
13.33
13.84
QSPI
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Table 35. Peripheral current consumption (continued)
IDD(Typ Appli)
Peripheral
Unit
Scale 1 +
OverDrive
Scale 2
Scale 3
TIM2
TIM3
18.18
14.49
15.18
16.91
2.69
2.56
7.07
4.96
5.09
1.07
1.89
1.93
6.91
4.20
4.22
4.13
4.04
3.98
3.91
3.76
5.51
6.58
5.91
0.71
2.96
16.92
13.47
14.11
15.69
2.47
2.44
6.56
4.64
4.72
1.00
1.78
1.81
6.44
3.83
3.94
3.89
3.78
3.69
3.61
3.53
5.19
6.14
5.56
0.69
2.72
15.07
12.00
12.50
14.07
2.20
2.17
5.83
4.07
4.27
0.93
1.57
1.67
5.80
3.40
3.50
3.40
3.33
3.33
3.17
3.13
4.57
5.43
4.90
0.60
2.40
TIM4
TIM5
TIM6
TIM7
TIM12
TIM13
TIM14
WWDG
SPI2(2)
SPI3(2)
SPDIFRX
USART2
USART3
UART4
UART5
I2C1
APB1
µA/MHz
I2C2
I2C3
FMPI2C1
CAN1
CAN2
CEC
DAC
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Electrical characteristics
Table 35. Peripheral current consumption (continued)
IDD(Typ Appli)
Peripheral
Unit
Scale 1 +
OverDrive
Scale 2
Scale 3
TIM1
17.51
18.40
4.53
4.53
4.69
4.70
4.66
9.06
1.97
1.88
1.51
8.17
5.07
5.37
3.89
3.74
8.15
16.28
17.10
4.21
4.21
4.35
4.35
4.31
8.38
1.89
1.75
1.40
7.64
4.75
5.06
3.64
3.49
8.10
14.43
15.22
3.72
3.72
3.85
3.87
3.82
7.47
1.67
1.57
1.23
6.77
4.22
4.50
3.17
3.10
7.13
TIM8
USART1
USART6
ADC1
ADC2
ADC3
SDIO
APB2
SPI1
µA/MHz
SPI4
SYSCFG
TIM9
TIM10
TIM11
SAI1
SAI2
Bus Matrix
1. N = Number of strean enable (1..8)
2. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.
6.3.8
Wakeup time from low-power modes
The wakeup times given in Table 36 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•
•
For Stop or Sleep modes: the wakeup event is WFE.
WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and V =3.3 V.
DD
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Electrical characteristics
STM32F446xC/E
Table 36. Low-power mode wakeup timings
Conditions
Symbol
Parameter
Typ(1)
Max(1)
Unit
CPU
clock
cycle
(2)
tWUSLEEP
Wakeup from Sleep
-
6
6
Wakeup from Sleep
with Flash memory in
Deep power down
mode
(1)
TWUSLEEPFDSM
-
33.5
12.8
50
15
Main regulator is ON
Main regulator is ON and Flash
memory in Deep power down mode
104.9
115
Wakeup from Stop
mode with MR/LP
regulator in normal
mode
(2)
tWUSTOP
Low power regulator is ON
20.6
28
µs
Low power regulator is ON and
Flash memory in Deep power down
mode
112.8
120
Main regulator in under-drive mode
(Flash memory in Deep power-
down mode)
110
140
Wakeup from Stop
mode with MR/LP
regulator in Under-drive
mode
(2)
tWUSTOP
Low power regulator in under-drive
mode
114.4
325
128
400
(Flash memory in Deep power-
down mode)
Wakeup from Standby
mode
(2)(3)
tWUSTDBY
-
1. Guaranteed based on test during characterization.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
instruction.
3. tWUSTDBY maximum value is given at –40 °C.
6.3.9
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 56: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 23.
The characteristics given in Table 37 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 16.
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STM32F446xC/E
Electrical characteristics
Table 37. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
External user clock source
frequency(1)
fHSE_ext
1
-
50
MHz
VHSEH
VHSEL
tw(HSE)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
0.7VDD
VSS
-
-
VDD
V
0.3VDD
-
OSC_IN high or low time(1)
OSC_IN rise or fall time(1)
5
-
-
-
-
tw(HSE)
ns
tr(HSE)
tf(HSE)
10
Cin(HSE) OSC_IN input capacitance(1)
-
-
45
-
5
-
-
pF
%
DuCy(HSE) Duty cycle
-
55
±1
IL
OSC_IN Input leakage current
VSS ≤ VIN ≤ VDD
-
µA
1. Guaranteed by design.
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 56: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 24.
The characteristics given in Table 38 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 16.
Table 38. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User External clock source
frequency(1)
fLSE_ext
-
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
0.7VDD
VSS
-
-
-
VDD
0.3VDD
-
V
VLSEL
tw(LSE)
OSC32_IN input pin low level voltage
OSC32_IN high or low time(1)
-
450
tf(LSE)
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1)
OSC32_IN input capacitance(1)
-
-
200
Cin(LSE)
-
-
30
-
5
-
-
pF
%
DuCy(LSE) Duty cycle
-
70
±1
IL
OSC32_IN Input leakage current
VSS ≤ VIN ≤ VDD
-
µA
1. Guaranteed by design.
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Electrical characteristics
STM32F446xC/E
Figure 23. High-speed external clock source AC timing diagram
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High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 39. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
104/202
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STM32F446xC/E
Electrical characteristics
(1)
Table 39. HSE 4-26 MHz oscillator characteristics
Symbol
fOSC_IN
RF
Parameter
Conditions
Min
Typ
Max Unit
Oscillator frequency
Feedback resistor
-
-
4
-
-
26
-
MHz
200
kΩ
VDD=3.3 V,
ESR= 30 Ω,
CL=5 pF@25 MHz
-
-
450
530
-
-
IDD
HSE current consumption
HSE accuracy
µA
VDD=3.3 V,
ESR= 30 Ω,
CL=10 pF@25 MHz
(2)
ACCHSE
-
-500
-
-
500
ppm
mA/V
ms
Gm_crit_max Maximum critical crystal gm
Startup
-
-
1
-
(3)
tSU(HSE
Startup time
VDD is stabilized
2
1. Guaranteed by design.
2. This parameter depends on the crystal used in the application. The minimum and maximum values must
be respected to comply with USB standard specifications.
3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is Guaranteed based on test during characterization. It is measured for a
standard crystal resonator and it can vary significantly with the crystal manufacturer.
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 25). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 25. Typical application with an 8 MHz crystal
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1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 40. In
the application, the resonator and the load capacitors have to be placed as close as
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Electrical characteristics
STM32F446xC/E
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RF
Feedback resistor
LSE current consumption
LSE accuracy
-
-
18.4
-
1
MΩ
µA
IDD
-
-
-
-
(2)
ACCLSE
-
-500
500
0.56
1.5
-
ppm
Startup low-power mode
Startup high-drive mode
VDD is stabilized
-
-
-
-
Maximum critical crystal
gm
Gm_crit_max
µA/V
s
-
(3)
tSU(LSE)
startup time
2
1. Guaranteed by design.
2. This parameter depends on the crystal used in the application. Refer to application note AN2867.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is guaranteed based on test during characterization. It is
measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 26. Typical application with a 32.768 kHz crystal
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106/202
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STM32F446xC/E
Electrical characteristics
6.3.10
Internal clock source characteristics
The parameters given in Table 41 and Table 42 are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 16.
DD
High-speed internal (HSI) RC oscillator
(1)
Table 41. HSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ
Max Unit
fHSI
-
-
16
-
MHz
%
User-trimmed with the RCC_CR
register(2)
-
-
1
TA = - 40 to 105 °C(3)
TA = - 10 to 85 °C(3)
TA = 25 °C(4)
- 8
- 4
- 1
-
-
-
4.5
4
%
%
%
Accuracy of the HSI
oscillator
ACCHSI
1
HSI oscillator
startup time
(2)
tsu(HSI)
-
-
-
-
2.2
60
4
µs
HSI oscillator
power consumption
(2)
IDD(HSI)
80
µA
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed based on test during characterization.
4. Factory calibrated, parts not soldered.
Figure 27. LACC
versus temperature
HSI
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4YPICAL
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1. Guaranteed based on test during characterization.
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STM32F446xC/E
Low-speed internal (LSI) RC oscillator
(1)
Table 42. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(2)
fLSI
Frequency
17
-
32
15
47
40
kHz
µs
(3)
tsu(LSI)
LSI oscillator startup time
LSI oscillator power consumption
(3)
IDD(LSI)
-
0.4
0.6
µA
1.
VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed based on test during characterization..
3. Guaranteed by design.
Figure 28. ACC versus temperature
LSI
-3ꢄꢆꢅꢄꢀ6ꢄ
6.3.11
PLL characteristics
The parameters given in Table 43 and Table 44 are derived from tests performed under
temperature and V supply voltage conditions summarized in Table 16.
DD
Table 43. Main PLL characteristics
Symbol
Parameter
PLL input clock(1)
Conditions
Min
Typ
Max
Unit
fPLL_IN
-
-
0.95(2)
12.5
1
-
2.10
180
MHz
MHz
fPLL_OUT
PLL multiplier output clock
48 MHz PLL multiplier output
clock
fPLL48_OUT
fVCO_OUT
-
-
-
48
-
75
MHz
MHz
PLL VCO output
100
432
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Symbol
Electrical characteristics
Table 43. Main PLL characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
VCO freq = 100 MHz
VCO freq = 432 MHz
75
100
-
-
-
200
300
-
tLOCK
PLL lock time
µs
RMS
25
peak
to
peak
Cycle-to-cycle jitter
-
-
-
150
15
-
-
-
System clock
120 MHz
RMS
Jitter(3)
ps
peak
to
Period Jitter
200
peak
Cycle to cycle at 1 MHz
on 1000 samples
Bit Time CAN jitter
-
330
-
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
0.40
0.75
(4)
IDD(PLL)
PLL power consumption on VDD
-
-
mA
mA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
0.40
0.85
PLL power consumption on
VDDA
(4)
IDDA(PLL)
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Guaranteed based on test during characterization.
Table 44. PLLI2S (audio PLL) characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLI2S_IN
fPLLI2S_OUT
fVCO_OUT
PLLI2S input clock(1)
-
0.95(2)
1
-
2.10
216
432
200
300
-
MHz
MHz
MHz
PLLI2S multiplier output clock
PLLI2S VCO output
-
-
-
100
75
100
-
-
VCO freq = 100 MHz
VCO freq = 432 MHz
-
tLOCK
PLLI2S lock time
µs
-
-
RMS
90
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
peak
to
peak
-
280
-
ps
Master I2S clock jitter
WS I2S clock jitter
Average frequency of
12.288 MHz
Jitter(3)
-
-
90
-
-
ps
ps
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 KHz
on 1000 samples
400
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Table 44. PLLI2S (audio PLL) characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
0.40
0.75
PLLI2S power consumption on
VDD
(4)
IDD(PLLI2S)
-
mA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
0.40
0.85
PLLI2S power consumption on
VDDA
(4)
IDDA(PLLI2S)
-
mA
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed based on test during characterization.
Table 45. PLLISAI characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLSAI_IN
fPLLSAI_OUT
fVCO_OUT
PLLSAI input clock(1)
-
0.95(2)
1
-
2.10
216
432
200
300
-
MHz
MHz
MHz
PLLSAI multiplier output clock
PLLSAI VCO output
-
-
-
100
75
100
-
-
VCO freq = 100 MHz
VCO freq = 432 MHz
-
tLOCK
PLLSAI lock time
µs
-
-
RMS
90
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
peak
to
peak
-
280
90
-
ps
Main SAI clock jitter
Average frequency of
12.288 MHz
Jitter(3)
-
-
-
-
ps
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 KHz
on 1000 samples
FS clock jitter
400
ps
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
0.40
0.75
PLLSAI power consumption on
VDD
(4)
IDD(PLLSAI)
-
-
mA
mA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
0.40
0.85
PLLSAI power consumption on
VDDA
(4)
IDDA(PLLSAI)
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed based on test during characterization.
6.3.12
PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 52: EMI characteristics). It is available only on the main PLL.
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Symbol
Electrical characteristics
Table 46. SSCG parameters constraint
Parameter
Min
Typ
Max(1)
Unit
fMod
md
Modulation frequency
-
0.25
-
-
-
-
10
2
KHz
%
Peak modulation depth
-
MODEPER * INCSTEP
1. Guaranteed by design.
2
15−1
-
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round[fPLL_IN ⁄ (4 × fMod)]
f
and f
must be expressed in Hz.
PLL_IN
Mod
As an example:
If f = 1 MHz, and f
= 1 kHz, the modulation depth (MODEPER) is given by
PLL_IN
MOD
equation 1:
MODEPER = round[106 ⁄ (4 × 103)] = 250
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
INCSTEP = round[((215 – 1) × md × PLLN) ⁄ (100 × 5 × MODEPER)]
f
must be expressed in MHz.
VCO_OUT
With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
INCSTEP = round[((215 – 1) × 2 × 240) ⁄ (100 × 5 × 250)] = 126md(quantitazed)%
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
mdquantized% = (MODEPER × INCSTEP × 100 × 5) ⁄ ((215 – 1) × PLLN)
As a result:
mdquantized% = (250 × 126 × 100 × 5) ⁄ ((215 – 1) × 240) = 2.002%(peak)
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STM32F446xC/E
Figure 29 and Figure 30 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is f
nominal.
PLL_OUT
T
is the modulation period.
mode
md is the modulation depth.
Figure 29. PLL output clock waveforms in center spread mode
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6.3.13
Memory characteristics
Flash memory
The characteristics are given at TA = - 40 to 105 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Table 47. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Write / Erase 8-bit mode, VDD = 1.7 V
-
-
-
5
8
-
IDD
Supply current Write / Erase 16-bit mode, VDD = 2.1 V
Write / Erase 32-bit mode, VDD = 3.3 V
-
-
mA
12
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Min(1) Typ Max(1) Unit
Table 48. Flash memory programming
Symbol
tprog
Parameter
Conditions
Program/eraseparallelism
(PSIZE) = x 8/16/32
Word programming time
-
-
-
-
-
-
-
-
-
-
-
-
-
16
100(2) µs
800
Program/eraseparallelism
(PSIZE) = x 8
400
300
250
Program/eraseparallelism
(PSIZE) = x 16
tERASE16KB Sector (16 KB) erase time
tERASE64KB Sector (64 KB) erase time
tERASE128KB Sector (128 KB) erase time
600
500
ms
ms
s
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
1200 2400
Program/eraseparallelism
(PSIZE) = x 16
700
550
2
1400
1100
4
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
Program/eraseparallelism
(PSIZE) = x 16
1.3
1
2.6
2
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
8
16
Program/eraseparallelism
(PSIZE) = x 16
tME
Mass erase time
5.5
8
11
s
Program/eraseparallelism
(PSIZE) = x 32
16
32-bit program operation
16-bit program operation
8-bit program operation
2.7
2.1
1.7
-
-
-
3.6
3.6
3.6
V
V
V
Vprog
Programming voltage
1. Guaranteed based on test during characterization.
2. The maximum programming time is measured after 100K erase operations.
Table 49. Flash memory programming with V
PP
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
tprog
Double word programming
-
16
230
490
875
3.5
-
100(2)
µs
tERASE16KB Sector (16 KB) erase time
tERASE64KB Sector (64 KB) erase time
tERASE128KB Sector (128 KB) erase time
-
-
-
TA = 0 to +40 °C
VDD = 3.3 V
-
-
ms
VPP = 8.5 V
-
tME
Mass erase time
-
-
s
Vprog
Programming voltage
-
2.7
3.6
V
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Table 49. Flash memory programming with V (continued)
PP
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
VPP
VPP voltage range
-
7
-
9
-
V
Minimum current sunk on
the VPP pin
IPP
-
-
10
-
-
mA
Cumulative time during
which VPP is applied
(3)
tVPP
-
1
hour
1. Guaranteed by design.
2. The maximum programming time is measured after 100K erase operations.
3. VPP should only be connected during programming/erasing.
Table 50. Flash memory endurance and data retention
Symbol
Parameter
Conditions
Value
Unit
-
-
Min(1)
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
NEND
Endurance
10
Kcycles
Years
1 kcycle(2) at TA = 85 °C
1 kcycle(2) at TA = 105 °C
10 kcycles(2) at TA = 55 °C
30
10
20
tRET
Data retention
1. Guaranteed based on test during characterization.
2. Cycling performed over the whole temperature range.
6.3.14
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
DD
SS
A device reset allows normal operations to be resumed.
The test results are given in Table 51. They are based on the EMS levels and classes
defined in application note AN1709.
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Level/
Table 51. EMS characteristics
Parameter
Symbol
Conditions
Class
VDD = 3.3 V, LQFP144, TA =
+25 °C, fHCLK = 168 MHz, conforms
to IEC 61000-4-2
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP144,
TA = +25 °C, fHCLK = 168 MHz,
conforms to IEC 61000-4-2
VEFTB
4B
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
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Max vs.
Table 52. EMI characteristics
Conditions
Monitored
frequency band
[fHSE/fCPU
]
Symbol
Parameter
Unit
8/180 MHz
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1GHz
SAE EMI Level
0.1 to 30 MHz
11
10
11
3
VDD = 3.3 V, TA = 25 °C, LQFP144
package, conforming to SAE J1752/3
EEMBC, ART ON, all peripheral clocks
enabled, clock dithering disabled.
dBµV
-
dBµV
-
SEMI
Peak level
24
25
20
4
VDD = 3.3 V, TA = 25 °C, LQFP144
package, conforming to SAE J1752/3
EEMBC, ART ON, all peripheral clocks
enabled, clock dithering enabled
30 to 130 MHz
130 MHz to 1GHz
SAE EMI level
6.3.15
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 53. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Electrostatic
Conditions
Class
Unit
value(1)
VESD(HBM) discharge voltage
(human body model)
TA = + 25 °C conforming to ANSI/JEDEC JS-001
2
2000
TA = + 25 °C conforming to ANSI/ESD STM5.3.1,
LQFP64, LQFP100, WLCSP81 packages
C4
500
250
V
Electrostatic
VESD(CDM) discharge voltage
(charge device model)
TA = + 25 °C conforming to ANSI/ESD STM5.3.1,
LQFP144, UFBGA144 (7 x 7), UFBGA144 (10 x 10)
packages
C3
1. Guaranteed based on test during characterization.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
•
•
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
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These tests are compliant with EIA/JESD 78A IC latchup standard.
Table 54. Electrical sensitivities
Conditions
Symbol
Parameter
Class
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
II level A
6.3.16
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3 V-capable I/O pins) should be avoided during normal product
DD
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –
5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 55.
(1)
Table 55. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on BOOT0 pin
–0
–0
NA
NA
Injected current on NRST pin
Injected current on PE2, PE3,PE4, PE5, PE6, PC13, PC14,
PF10, PH0, PH1, NRST, PC0, PC1, PC2, PC3, PG15, PB3,
PB4, PB5, PB6, PB7, PB8, PB9, PE0, PE1
IINJ
–0
NA
mA
Injected current on any other FT and FTf pins
Injected current on any other pins
-5
NA
+5
–5
1. NA = not applicable.
Note:
It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
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6.3.17
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 56: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 16. All I/Os are
CMOS and TTL compliant.
Table 56. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.35VDD–0.04(1)
FT, FTf, TTa and NRST I/O
input low level voltage
1.7 V≤VDD≤3.6 V
-
-
(2)
0.3VDD
1.75 V ≤ VDD
3.6 V,
– 40 °C≤ TA ≤
105 °C
≤
VIL
V
-
-
BOOT0 I/O input low level
voltage
0.1VDD+0.1(1)
1.7 V ≤ VDD ≤ 3.6 V,
0 °C ≤ TA ≤105 °C
-
-
-
0.45VDD+0.3(1)
FT, FTf, TTa and NRST I/O
input high level voltage(4)
1.7 V≤VDD≤3.6 V
-
-
(2)
0.7VDD
1.75 V≤VDD ≤3.6 V,
– 40 °C≤TA ≤105 °C
VIH
V
BOOT0 I/O input high level
voltage
0.17VDD+0.7(1)
-
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
FT, FTf, TTa and NRST I/O
input hysteresis
1.7 V≤VDD≤3.6 V
-
-
10%VDD
100m
-
-
1.75 V≤VDD ≤3.6 V,
–40 °C≤TA ≤105 °C
VHYS
V
BOOT0 I/O input hysteresis
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
-
-
-
-
I/O input leakage current (3) VSS ≤VIN ≤VDD
-
-
1
3
Ilkg
µA
I/O FT input leakage current
VIN = 5 V
(4)
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Symbol
Electrical characteristics
Table 56. I/O static characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
All pins
except for
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
30
40
50
Weakpull-up
RPU
equivalent
VIN = VSS
resistor(5)
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
7
10
40
14
50
kΩ
All pins
except for
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
30
Weak pull-
down
RPD
VIN = VDD
equivalent
resistor(6)
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
7
-
10
5
14
-
(7)
CIO
I/O pin capacitance
-
pF
1. Guaranteed by design.
2. Tested in production.
3. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 55: I/O
current injection susceptibility
4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 55: I/O current injection
susceptibility
5. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the
series resistance is minimum (~10% order).
6. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
7. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed based on test during characterization.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 31.
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Figure 31. FT I/O input characteristics
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or
source up to 20 mA (with a relaxed V /V ) except PC13, PC14 and PC15 which can
OL OH
sink or source up to 3mA. When using the PC13 to PC15 GPIOs in output mode, the speed
should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 14).
VDD
•
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
ΣI
(see Table 14).
VSS
Output voltage levels
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 16. All I/Os are CMOS and TTL compliant.
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Table 57. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max Unit
(1)
VOL
Output low level voltage for an I/O pin
CMOS port(2)
IIO = +8 mA
-
0.4
V
(3)
VOH
VOL
VOH
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
VDD–0.4
-
2.7 V ≤VDD ≤3.6 V
(1)
(3)
TTL port(2)
IIO =+ 8mA
-
0.4
V
2.4
-
2.7 V ≤VDD ≤3.6 V
(1)
VOL
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
-
1.3(4)
IIO = +20 mA
V
(3)
VDD–1.3(4)
-
2.7 V ≤VDD ≤3.6 V
VOH
VOL
VOH
-
0.4(4)
(1)
IIO = +6 mA
V
(3)
VDD–0.4(4)
-
1.8 V ≤VDD ≤3.6 V
(1)
VOL
-
0.4(5)
IIO = +4 mA
V
VOH
VDD–0.4(5)
-
(3)
1.7 V ≤VDD ≤3.6V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 14.
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 14 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
4. Based on characterization data.
5. Guaranteed by design.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 32 and
Table 58, respectively.
Unless otherwise specified, the parameters given in Table 58 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 16.
(1)(2)
Table 58. I/O AC characteristics
OSPEEDR
y[1:0] bit
value(1)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
CL = 50 pF, VDD ≥ 2.7 V
CL = 50 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 10 pF, VDD ≥ 1.8 V
CL = 10 pF, VDD ≥ 1.7 V
-
-
-
-
-
-
-
-
-
-
4
2
fmax(IO)out Maximum frequency(3)
8
4
3
MHz
ns
00
Output high to low level fall
time and output low to high
level rise time
tf(IO)out
/
CL = 50 pF, VDD = 1.7 V
to 3.6 V
-
-
100
tr(IO)out
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OSPEEDR
STM32F446xC/E
(1)(2)
Table 58. I/O AC characteristics
(continued)
y[1:0] bit
Symbol
Parameter
Conditions
Min
Typ
Max Unit
value(1)
CL = 50 pF, VDD≥ 2.7 V
CL = 50 pF, VDD≥ 1.8 V
CL = 50 pF, VDD≥ 1.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 10 pF, VDD≥ 1.8 V
CL = 10 pF, VDD≥ 1.7 V
CL = 50 pF, VDD ≥ 2.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 50 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 40 pF, VDD ≥ 2.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 40 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 1.8 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 40 pF, VDD ≥2.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 40 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 30 pF, VDD ≥ 2.7 V
CL = 30 pF, VDD ≥ 1.8 V
CL = 30 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD≥ 2.7 V
CL = 10 pF, VDD ≥ 1.8 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 30 pF, VDD ≥ 2.7 V
CL = 30 pF, VDD ≥1.8 V
CL = 30 pF, VDD ≥1.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 10 pF, VDD ≥1.8 V
CL = 10 pF, VDD ≥1.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
25
12.5
10
fmax(IO)out Maximum frequency(3)
MHz
50
20
12.5
10
01
Output high to low level fall
time and output low to high
level rise time
6
tf(IO)out
tr(IO)out
/
ns
20
10
50(4)
100(4)
fmax(IO)out Maximum frequency(3)
25
50
MHz
10
42.5
6
Output high to low level fall
time and output low to high
level rise time
4
tf(IO)out
tr(IO)out
/
ns
10
6
100(4)
50
42.5
180(4)
100
72.5
4
fmax(IO)out Maximum frequency(3)
MHz
11
6
Output high to low level fall
time and output low to high
level rise time
7
tf(IO)out
tr(IO)out
/
ns
ns
2.5
3.5
4
Pulse width of external
signals detected by the EXTI
controller
-
tEXTIpw
-
10
-
-
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1. Guaranteed by design.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of
the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 32.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.
Figure 32. I/O AC characteristics definition
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6.3.18
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 56: I/O static characteristics).
PU
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 16.
Table 59. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RPU
Weak pull-up equivalent resistor(1)
NRST Input filtered pulse
VIN = VSS
-
30
-
40
-
50
kΩ
ns
ns
µs
(2)
VF(NRST)
100
(2)
VNF(NRST)
NRST Input not filtered pulse
VDD > 2.7 V
Internal Reset source
300
20
-
-
-
TNRST_OUT Generated reset pulse duration
-
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
2. Guaranteed by design.
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Electrical characteristics
STM32F446xC/E
Figure 33. Recommended NRST pin protection
9
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1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 59. Otherwise the reset is not taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
6.3.19
TIM timer characteristics
The parameters given in Table 60 are guaranteed by design.
Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)(2)
Table 60. TIMx characteristics
Symbol
Parameter
Conditions(3)
Min
Max
Unit
AHB/APBx prescaler=1 or
2 or 4, fTIMxCLK = 180 MHz
1
-
tTIMxCLK
tres(TIM)
Timer resolution time
AHB/APBx prescaler>4,
1
-
tTIMxCLK
fTIMxCLK = 90 MHz
Timer external clock
frequency on CH1 to CH4
fEXT
0
-
f
TIMxCLK/2
16/32
MHz
bit
fTIMxCLK = 180 MHz
ResTIM
Timer resolution
Maximum possible count with
32-bit counter
tMAX_COUNT
-
-
65536 × 65536
tTIMxCLK
1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR
register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK = 4x PCLKx.
6.3.20
Communications interfaces
I2C interface characteristics
2
2
The I C interface meets the requirements of the standard I C communication protocol with
the following restrictions: the I/O pins SDA and SCL too are mapped as not “true”
open-drain. When configured as open-drain, the PMOS connected between the I/O pin and
V
is disabled, but is still present.
DD
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Electrical characteristics
2
The I C characteristics are described in Table 61. Refer also to Section 6.3.17: I/O port
for more details on the input/output alternate function characteristics (SDA
characteristics
and SCL)
.
2
Table 61. I C characteristics
Standard mode
Fast mode I2C(1)(2)
I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
250
-
-
1.3
0.6
100
-
-
µs
-
-
-
-
SDA data hold time
3450(3)
3.45
900(4)
0.9
tv(SDA, ACK) Data, ACK valid time
-
-
ns
tr(SDA)
SDA and SCL rise time
tr(SCL)
-
1000
-
300
tf(SDA)
SDA and SCL fall time
tf(SCL)
-
300
-
300
th(STA)
tsu(STA)
Start condition hold time
4.0
4.7
4.0
4.7
-
-
-
-
0.6
0.6
0.6
1.3
-
-
-
-
µs
Repeated Start condition
setup time
tsu(STO)
Stop condition setup time
µs
µs
Stop to Start condition time
(bus free)
tw(STO:STA)
Pulse width of the spikes
that are suppressed by the
analog filter for standard and
fast mode
tSP
-
-
-
0.05
-
0.09(5)
400
µs
pF
Capacitive load for each bus
line
Cb
400
Guaranteed based on test during characterization.
1.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode
clock.
3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
5. The minimum width of the spikes filtered by the analog filter is above tSP(max).
DocID027107 Rev 6
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Electrical characteristics
STM32F446xC/E
2
Figure 34. I C bus AC waveforms and measurement circuit
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1. RS = series protection resistor.
2. RP = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.
126/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
FMPI2C characteristics
The FMPI2C characteristics are described in Table 62.
Refer also to Section 6.3.17: I/O port characteristics for more details on the input/output
alternate function characteristics (SDA and SCL).
2
(1)
Table 62. FMPI C characteristics
Standard mode Fast mode
Fast+ mode
Min Max
-
Parameter
Unit
Min
Max
Min
Max
17
fFMPI2CC
FMPI2CCLK frequency
2
-
8
-
-
16(2)
tw(SCLL) SCL clock low time
tw(SCLH) SCL clock high time
4.7
4.0
0.25
0
-
1.3
0.6
0.10
0
-
-
0.5
0.26
0.05
0
-
-
-
tsu(SDA)
tH(SDA)
SDA setup time
-
-
-
-
-
SDA data hold time
-
tv(SDA,ACK) Data, ACK valid time
-
3.45
-
0.9
-
0.45
tr(SDA)
SDA and SCL rise time
tr(SCL)
-
0.100
-
0.30
-
0.12
tf(SDA)
us
SDA and SCL fall time
tf(SCL)
-
0.30
-
0.30
-
0.12
th(STA)
Start condition hold time
4
-
-
-
-
0.6
0.6
0.6
1.3
-
-
-
-
0.26
0.26
0.26
0.5
-
-
-
-
Repeated Start condition
setup time
tsu(STA)
4.7
4
tsu(STO)
Stop condition setup time
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
Pulse width of the spikes that
are suppressed by the
analog filter for standard and
fast mode
tSP
-
-
-
0.05
-
0.09
400
0.05
-
0.09
Capacitive load for each bus
Line
Cb
400
550(3)
pF
1. Guaranteed based on test during characterization.
2. When tr(SDA,SCL)<=110ns.
3. Can be limited. Maximum supported value can be retrieved by referring to the following formulas:
tr(SDA/SCL) = 0.8473 x Rp x Cload
Rp(min) = (VDD -VOL(max)) / IOL(max)
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Electrical characteristics
STM32F446xC/E
2
Figure 35. FMPI C timing diagram and measurement circuit
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s
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128/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 63 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 16, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C=30pF
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)
Table 63. SPI dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master full duplex/receiver mode,
2.7 V≤VDD≤3.6 V
45
SPI1/4
Master transmitter
1.71V <VDD< 3.6V
SPI1/4
45
Master
1.71V <VDD< 3.6V
SPI1/2/3/4
22.5
fSCK
SPI clock frequency
-
-
MHz
Slave transmitter/
full duplex mode
SPI1/4
1/tc(SCK)
45
45
2.7V <VDD< 3.6V
Slave receiver mode
SPI1/4
1.71V <VDD< 3.6V
Slave mode
SPI1/2/3/4
1.71V <VDD< 3.6V
22.5(2)
70
Duty cycle of SPI clock
frequency
Duty(SCK)
Slave mode
30
50
%
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Electrical characteristics
STM32F446xC/E
(1)
Table 63. SPI dynamic characteristics (continued)
Parameter Conditions Min
Symbol
Typ
Max
Unit
tw(SCKH)
tw(SCKL)
tsu(NSS) NSS setup time
SCK high and low time Master mode, SPI presc = 2
TPCLK - 1.5 TPCLK TPCLK + 1.5
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
Master mode
4TPCLK
-
-
th(NSS)
tsu(MI)
tsu(SI)
th(MI)
NSS hold time
2TPCLK
4
3
4
2
7
5
-
-
-
-
-
-
-
-
Data input setup time
Slave mode
Master mode
-
Data input hold time
th(SI)
Slave mode
-
ns
ta(SO
)
Data output access time Slave mode
Data output disable time Slave mode
21
12
tdis(SO)
Slave mode (after enable edge),
2.7V ≤ VDD ≤ 3.6V
-
-
7.5
7.5
-
22
10.5
-
Data output valid/hold
time
tv(SO)
Slave mode (after enable edge),
1.7 V ≤ VDD ≤ 3.6 V
Data output valid/hold
time
th(SO)
Slave mode (after enable edge)
5
tv(MO)
th(MO)
Data output valid time
Data output hold time
Master mode (after enable edge)
Master mode (after enable edge)
-
1.5
-
5
-
0
1. Guaranteed based on test during characterization.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%.
Figure 36. SPI timing diagram - slave mode and CPHA = 0
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130/202
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Electrical characteristics
Figure 37. SPI timing diagram - slave mode and CPHA = 1
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Figure 38. SPI timing diagram - master mode
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DLꢄꢂꢄꢀꢃF
DocID027107 Rev 6
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175
Electrical characteristics
STM32F446xC/E
QSPI interface characteristics
Unless otherwise specified, the parameters given in Table 64 for QSPI are derived from
tests performed under the ambient temperature, f frequency and V supply voltage
AHB
DD
conditions summarized in Table 16, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C=20pF
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics.
(1)
Table 64. QSPI dynamic characteristics in SDR Mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Write mode
1.71 V≤VDD≤3.6 V
-
-
90
Cload = 15 pF
fSCK
QSPI clock frequency
Read mode
2.7V <VDD< 3.6V
Cload = 15 pF
MHz
1/tc(SCK)
-
-
90
1.71 V≤VDD≤3.6 V
-
-
48
tw(CKH)
tw(CKL)
ts(IN)
(T(CK) / 2) - 2
-
T(CK) / 2
QSPI clock high and low
-
T(CK) / 2
-
-
(T(CK) / 2) +2
Data input setup time
Data input hold time
-
-
-
-
2
4.5
-
-
-
ns
th(IN)
-
tv(OUT) Data output valid time
th(OUT) Data output hold time
1.5
-
3
-
0
1. Guaranteed based on test during characterization.
(1)
Table 65. QSPI dynamic characteristics in DDR Mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Write mode
1.71 V≤VDD≤3.6 V
-
-
60
Cload = 15 pF
fSCK
Read mode
2.7V <VDD< 3.6V
Cload = 15 pF
QSPI clock frequency
MHz
1/tc(SCK)
60
48
-
-
-
-
1.71 V≤VDD≤3.6 V
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Electrical characteristics
(1)
Table 65. QSPI dynamic characteristics in DDR Mode (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tw(CKH)
tw(CKL)
ts(IN)
(T(CK) / 2) - 2
-
-
T(CK) / 2
QSPI clock high and low
-
T(CK) / 2
(T(CK) / 2) +2
Data input setup time
Data input hold time
-
-
0
5.5
-
-
-
-
th(IN)
-
ns
2.7V <VDD< 3.6V
5.5
8
-
6.5
9.5
-
tv(OUT) Data output valid time
1.71V <VDD< 3.6V
-
-
th(OUT) Data output hold time
3.5
1. Guaranteed based on test during characterization.
I2S interface characteristics
2
Unless otherwise specified, the parameters given in Table 66 for the I S interface are
derived from tests performed under the ambient temperature, f frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 16, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
2
(1)
Table 66. I S dynamic characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S Main clock output
-
256 x 8K 256 x Fs(2) MHz
Master data
Slave data
-
-
64 x Fs
64 x Fs
70
fCK
I2S clock frequency
MHz
%
DCK
I2S clock frequency duty cycle Slave receiver
30
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Electrical characteristics
STM32F446xC/E
2
(1)
Table 66. I S dynamic characteristics (continued)
Parameter Conditions Min
Symbol
Max
Unit
tv(WS)
th(WS)
tsu(WS)
-
WS valid time
WS hold time
Master mode
Master mode
Slave mode
-
1
5.5
-
1
-
WS setup time
PCM short pulse Slave mode(3)
2
-
th(WS)
Slave mode
3
-
WS hold time
-
PCM short pulse Slave mode(3)
Master receiver
1.5
3
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
-
-
Data input setup time
Data input hold time
Data output valid time
Data output hold time
ns
Slave receiver
2.5
4
Master receiver
-
Slave receiver
1
-
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
-
16
4.5
-
-
5
1
-
1. Guaranteed based on test during characterization.
2. The maximum value of 256xFs is 45 MHz (APB1 maximum frequency).
3. Measurement done with respect to I2S_CK rising edge.
Note:
Refer to the I2S section of RM0390 reference manual for more details on the sampling
frequency (F ).
S
f
, f , and D values reflect only the digital peripheral behavior. The values of these
CK
MCK CK
parameters might be slightly impacted by the source clock precision. D depends mainly
CK
on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). F
maximum value is supported for each mode/condition.
S
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Electrical characteristics
2
(1)
Figure 39. I S slave timing diagram (Philips protocol)
t
c(CK)
CPOL = 0
CPOL = 1
WS input
t
t
t
t
w(CKL)
h(WS)
w(CKH)
t
t
t
v(SD_ST)
h(SD_ST)
su(WS)
SD
transmit
receive
(2)
LSB transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
su(SD_SR)
h(SD_SR)
(2)
LSB receive
Bitn receive
LSB receive
SD
ai14881b
1. .LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
(1)
Figure 40. I S master timing diagram (Philips protocol)
t
t
r(CK)
f(CK)
t
c(CK)
CPOL = 0
CPOL = 1
WS output
t
w(CKH)
t
t
t
v(WS)
h(WS)
w(CKL)
t
t
h(SD_MT)
v(SD_MT)
SD
transmit
receive
LSB transmit(2)
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
t
h(SD_MR)
su(SD_MR)
LSB receive(2)
Bitn receive
LSB receive
ai14884b
SD
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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175
Electrical characteristics
STM32F446xC/E
SAI characteristics
Unless otherwise specified, the parameters given in Table 67 for SAI are derived from tests
performed under the ambient temperature, f frequency and VDD supply voltage
PCLKx
conditions summarized in Table 16, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C=30 pF
Measurement points are performed at CMOS levels: 0.5V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
(3)
(1)
Table 67. SAI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
SAI Main clock output
-
256 x 8K
256 x Fs
128 x Fs(3)
128 x Fs(3)
MHz
Master data: 32 bits
-
-
fCK
SAI clock frequency(2)
FS valid time
MHz
%
Slave data: 32 bits
Master mode
-
-
14
2.7 V ≤ VDD ≤3.6 V
tv(FS)
Master mode
17.5
1.71 V ≤ VDD ≤3.6 V
th(FS)
tsu(FS)
FS hold time
FS setup time
FS hold time
Master mode
Slave mode
7
1
1
1
1
5
1
-
-
-
-
-
-
-
th(FS)
Slave mode
tsu(SD_A_MR)
tsu(SD_B_SR)
th(SD_A_MR)
th(SD_B_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
Data input setup time
Data input hold time
ns
Slave trasmitter (after enable edge
2.7 V ≤ VDD ≤3.6 V
-
9.5
tv(SD_B_ST) Data output valid time
th(SD_B_ST) Data output hold time
tv(SD_B_ST) Data output valid time
th(SD_B_ST) Data output hold time
Slave transmitter (after enable edge
1.71 V ≤ VDD ≤3.6 V
-
6
-
16
-
Slave transmitter (after enable edge
Master transmitter (after enable edge
2.7 V ≤ VDD ≤3.6 V
15
Master transmitter (after enable edge
1.71 V ≤ VDD ≤3.6 V
-
18
-
Master transmitter (after enable edge
7
1. Guaranteed based on test during characterization.
2. 256xFs maximum corresponds to 45 MHz (APB2 xaximum frequency)
3. With Fs = 192 KHz
136/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
Figure 41. SAI master timing waveforms
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USB OTG full speed (FS) characteristics
This interface is present in both the USB OTG HS and USB OTG FS controllers.
Table 68. USB OTG full speed startup time
Symbol
Parameter
Max
Unit
(1)
tSTARTUP
USB OTG full speed transceiver startup time
1
µs
1. Guaranteed by design.
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175
Electrical characteristics
Symbol
STM32F446xC/E
Table 69. USB OTG full speed DC electrical characteristics
Parameter
Conditions
Min.(1) Typ. Max.(1) Unit
USB OTG full speed
VDDUSB transceiver operating
voltage
-
3.0(2)
-
3.6
V
Differential input
sensitivity
I(USB_FS_DP/DM,
USB_HS_DP/DM)
(3)
VDI
0.2
0.8
1.3
-
-
-
-
Input
levels
Differential common mode
range
(3)
VCM
Includes VDI range
2.5
2.0
V
V
Single ended receiver
threshold
(3)
VSE
-
VOL
VOH
Static output level low
Static output level high
RL of 1.5 kΩto 3.6 V(4)
-
-
-
0.3
3.6
Output
levels
(4)
RL of 15 kΩto VSS
2.8
PA11, PA12, PB14, PB15
(USB_FS_DP/DM,
USB_HS_DP/DM)
17
0.65
1.5
21
1.1
1.8
24
2.0
2.1
RPD
VIN = VDDUSB
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
kΩ
PA12, PB15
(USB_FS_DP,
USB_HS_DP)
VIN = VSS
RPU
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
VIN = VSS
0.25 0.37 0.55
1. All the voltages are measured from the local ground potential.
2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed
electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
3. Guaranteed by design.
RL is the load connected on the USB OTG full speed drivers.
4.
When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state
(floating input), not as alternate function. A typical 200 µA current consumption of the
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 and PB13 when the feature is enabled.
Note:
Figure 43. USB OTG full speed timings: definition of data signal rise and fall time
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138/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
(1)
Table 70. USB OTG full speed electrical characteristics
Driver characteristics
Conditions
Symbol
Parameter
Min
Max
Unit
tr
tf
Rise time(2)
Fall time(2)
CL = 50 pF
CL = 50 pF
tr/tf
4
4
20
20
ns
ns
%
V
trfm
VCRS
Rise/ fall time matching
90
1.3
110
2.0
Output signal crossover voltage
Output driver impedance(3)
-
Driving high or
low
ZDRV
28
44
Ω
1. Guaranteed by design.
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
2.
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.
USB high speed (HS) characteristics
Unless otherwise specified, the parameters given in Table 73 for ULPI are derived from
tests performed under the ambient temperature, fHCLK frequency summarized in Table 72
and V supply voltage conditions summarized in Table 71, with the following configuration:
DD
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10, unless otherwise specified
Capacitive load C = 30 pF, unless otherwise specified
Measurement points are done at CMOS levels: 0.5V
.
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Table 71. USB HS DC electrical characteristics
Symbol
Input level
Parameter
Min.(1)
Max.(1)
Unit
VDD
USB OTG HS operating voltage
1.7
3.6
V
1. All the voltages are measured from the local ground potential.
(1)
Table 72. USB HS clock timing parameters
Symbol
Parameter
Min
Typ
Max
Unit
fHCLK value to guarantee proper operation of
USB HS interface
-
30
-
-
MHz
FSTART_8BIT
FSTEADY
DSTART_8BIT
DSTEADY
Frequency (first transition)
8-bit ±10%
54
59.97
40
60
60
50
50
66
60.03
60
MHz
MHz
%
Frequency (steady state) ±500 ppm
Duty cycle (first transition)
8-bit ±10%
Duty cycle (steady state) ±500 ppm
49.975
50.025
%
Time to reach the steady state frequency and
duty cycle after the first transition
tSTEADY
-
-
1.4
ms
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175
Electrical characteristics
Symbol
STM32F446xC/E
(1)
Table 72. USB HS clock timing parameters (continued)
Parameter
Min
Typ
Max
Unit
tSTART_DEV
Peripheral
Host
-
-
-
-
5.6
-
Clock startup time after the
de-assertion of SuspendM
ms
tSTART_HOST
PHY preparation time after the first transition
of the input clock
tPREP
-
-
-
µs
1. Guaranteed by design.
Figure 44. ULPI timing diagram
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Table 73. Dynamic characteristics: USB ULPI
Symbol
Parameter
Conditions
Min.
Typ.
Max. Unit
tSC
tHC
tSD
tHD
Control in (ULPI_DIR, ULPI_NXT) setup time
Control in (ULPI_DIR, ULPI_NXT) hold time
Data in setup time
-
-
-
-
1
-
-
-
-
-
-
-
1.5
1.5
1.5
Data in hold time
-
ns
2.7 V < VDD < 3.6 V,
CL = 20 pF
-
-
6
6
8.5
tDC/tDD Data/control output delay
1.71 V < VDD < 3.6 V,
CL = 15 pF
11.5
1. Guaranteed based on test during characterization.
CAN (controller area network) interface
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (CANx_TX and CANx_RX).
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Electrical characteristics
6.3.21
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 74 are derived from tests
performed under the ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 16.
Table 74. ADC characteristics
Conditions
Symbol
Parameter
Power supply
Min
Typ
Max
Unit
VDDA
1.7(1)
1.7(1)
-
-
-
3.6
VDDA
-
VDDA −VREF+ < 1.2 V
VREF+ Positive reference voltage
V
VREF-
Negative reference voltage
-
0
V
V
DDA = 1.7(1) to 2.4 V
DDA = 2.4 to 3.6 V
0.6
15
30
18
MHz
MHz
fADC
ADC clock frequency
0.6
36
fADC = 30 MHz,
12-bit resolution
-
-
-
-
-
1764
17
kHz
1/fADC
V
(2)
fTRIG
External trigger frequency
Conversion voltage range(3)
-
-
0 (VSSA or VREF-
tied to ground)
VAIN
VREF+
See Equation 1 for
details
(2)
RAIN
External input impedance
Sampling switch resistance
-
-
-
-
-
50
6
κΩ
κΩ
pF
(2)(4)
RADC
-
-
Internal sample and hold
capacitor
(2)
CADC
4
7
fADC = 30 MHz
-
-
-
0.100
3(5)
0.067
2(5)
16
µs
1/fADC
µs
Injection trigger conversion
latency
(2)
tlat
-
-
fADC = 30 MHz
-
-
-
Regular trigger conversion
latency
(2)
tlatr
-
-
1/fADC
µs
fADC = 30 MHz
0.100
-
(2)
tS
Sampling time
Power-up time
-
3
-
-
480
3
1/fADC
µs
(2)
tSTAB
-
2
f
ADC = 30 MHz
0.50
0.43
0.37
0.30
-
-
-
-
16.40
16.34
16.27
16.20
µs
µs
12-bit resolution
ADC = 30 MHz
10-bit resolution
Total conversion time (including fADC = 30 MHz
f
(2)
tCONV
µs
sampling time)
8-bit resolution
ADC = 30 MHz
6-bit resolution
f
µs
9 to 492 (tS for sampling +n-bit resolution for successive
approximation)
1/fADC
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Electrical characteristics
STM32F446xC/E
Table 74. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
12-bit resolution
Single ADC
-
-
2
Msps
12-bit resolution
Sampling rate
-
-
3.75
Msps
Interleave Dual ADC
mode
(2)
fS
(fADC = 30 MHz, and
tS = 3 ADC cycles)
12-bit resolution
-
-
-
-
6
Msps
µA
Interleave Triple ADC
mode
ADC VREF DC current
consumption in conversion
mode
(2)
IVREF+
-
-
300
1.6
500
1.8
ADC VDDA DC current
consumption in conversion
mode
(2)
IVDDA
mA
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.16.2:
Internal reset OFF).
2. Guaranteed based on test during characterization.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA
.
4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 74.
Equation 1: R
max formula
AIN
(k – 0.5)
RAIN = ---------------------------------------------------------------- – RADC
fADC × CADC × ln(2N + 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
(1)
Table 75. ADC static accuracy at f
= 18 MHz
Typ
ADC
Symbol
Parameter
Test conditions
Max(2)
Unit
ET
Total unadjusted error
±3
±4
f
ADC =18 MHz
EO
EG
ED
EL
Offset error
±2
±1
±1
±2
±3
±3
±2
±3
VDDA = 1.7 to 3.6 V
VREF = 1.7 to 3.6 V
LSB
Gain error
VDDA −VREF < 1.2 V
Differential linearity error
Integral linearity error
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Guaranteed based on test during characterization.
142/202
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STM32F446xC/E
Electrical characteristics
a
(1)
Table 76. ADC static accuracy at f
= 30 MHz
ADC
Symbol
Parameter
Test conditions
Typ
Max(2)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
±2
±5
±2.5
±3
f
ADC = 30 MHz,
±1.5
±1.5
±1
RAIN < 10 kΩ,
Gain error
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V,
VDDA −VREF < 1.2 V
LSB
Differential linearity error
Integral linearity error
±2
±1.5
±3
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Guaranteed based on test during characterization.
(1)
Table 77. ADC static accuracy at f
= 36 MHz
ADC
Symbol
Parameter
Test conditions
Typ
Max(2)
Unit
ET
Total unadjusted error
±4
±7
f
ADC =36 MHz,
EO
EG
ED
EL
Offset error
±2
±3
±2
±3
±3
±6
±3
±6
V
DDA = 2.4 to 3.6 V,
LSB
Gain error
VREF = 1.7 to 3.6 V
Differential linearity error
Integral linearity error
VDDA −VREF < 1.2 V
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Guaranteed based on test during characterization.
(1)
Table 78. ADC dynamic accuracy at f
Parameter
= 18 MHz - limited test conditions
ADC
Symbol
Test conditions
Min
Typ
Max Unit
ENOB
SINAD
SNR
Effective number of bits
10.3
64
10.4
64.2
65
-
-
-
-
bits
fADC =18 MHz
Signal-to-noise and distortion ratio
Signal-to-noise ratio
VDDA = VREF+= 1.7 V
Input Frequency = 20 KHz
Temperature = 25 °C
64
dB
THD
Total harmonic distortion
-67
-72
1. Guaranteed based on test during characterization.
(1)
Table 79. ADC dynamic accuracy at f
= 36 MHz - limited test conditions
ADC
Symbol
Parameter
Test conditions
Min
Typ
Max Unit
ENOB
SINAD
SNR
Effective number of bits
Signal-to noise and distortion ratio
Signal-to noise ratio
10.6
66
10.8
67
-
-
-
-
bits
fADC =36 MHz
VDDA = VREF+ = 3.3 V
Input Frequency = 20 KHz
Temperature = 25 °C
64
68
dB
THD
Total harmonic distortion
- 70
- 72
1. Guaranteed based on test during characterization.
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
DocID027107 Rev 6
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175
Electrical characteristics
STM32F446xC/E
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for I
Section 6.3.17 does not affect the ADC accuracy.
and ΣI
in
INJ(PIN)
INJ(PIN)
Figure 45. ADC accuracy characteristics
6
6
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1. See also Table 76.
2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
144/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
Figure 46. Typical connection diagram using the ADC
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1. Refer to Table 74 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
f
ADC should be reduced.
DocID027107 Rev 6
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175
Electrical characteristics
STM32F446xC/E
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 47 or Figure 48,
depending on whether V is connected to V or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 47. Power supply and reference decoupling (V not connected to V
)
DDA
REF+
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1. VREF+ and VREF– inputs are both available on UFBGA144. VREF+ is also available on LQFP100, LQFP144,
and WLCSP81. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA
.
146/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
Figure 48. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
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1. VREF+ and VREF– inputs are both available on UFBGA144. VREF+ is also available on LQFP100, LQFP144,
and WLCSP81. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA
.
6.3.22
Temperature sensor characteristics
Table 80. Temperature sensor characteristics
Symbol
Parameter
Min
Typ Max
Unit
(1)
TL
VSENSE linearity with temperature
-
-
1
2.5
0.76
6
2
°C
mV/°C
V
Avg_Slope(1) Average slope
-
(1)
V25
Voltage at 25 °C
Startup time
-
-
10
-
(2)
tSTART
-
µs
(2)
TS_temp
ADC sampling time when reading the temperature (1 °C accuracy)
10
-
µs
1. Guaranteed based on test during characterization.
2. Guaranteed by design.
Table 81. Temperature sensor calibration values
Symbol
Parameter
Memory address
0x1FFF 7A2C - 0x1FFF 7A2D
TS_CAL1
TS_CAL2
TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V
TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F
DocID027107 Rev 6
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175
Electrical characteristics
STM32F446xC/E
6.3.23
V
monitoring characteristics
BAT
Table 82. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
50
4
-
-
KΩ
-
Ratio on VBAT measurement
Error on Q
Er(1)
- 1
-
+ 1
%
ADC sampling time when reading the VBAT
1 mV accuracy
(2)(2)
TS_vbat
5
-
-
µs
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.24
Reference voltage
The parameters given in Table 83 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 16.
DD
Table 83. internal reference voltage
Symbol
VREFINT
Parameter
Conditions
Min
Typ
Max
Unit
Internal reference voltage
–40 °C < TA < +105 °C 1.18 1.21
1.24
V
ADC sampling time when reading the
internal reference voltage
(1)
TS_vrefint
-
10
-
-
-
µs
Internal reference voltage spread over the
temperature range
(2)
VRERINT_s
VDD = 3V 10mV
3
5
mV
(2)
TCoeff
Temperature coefficient
Startup time
-
-
-
-
30
6
50
10
ppm/°C
µs
(2)
tSTART
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
Table 84. Internal reference voltage calibration values
Parameter Memory address
VREFIN_CAL Raw data acquired at temperature of 30 °C VDDA = 3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B
Symbol
6.3.25
DAC electrical characteristics
Table 85. DAC characteristics
Conditions Min Typ Max Unit
Symbol
Parameter
Comments
Analog supply
voltage
VDDA
-
1.7(1)
1.7(1)
-
-
3.6
3.6
V
V
-
Reference supply
voltage
VREF+
-
VREF+ ≤VDDA
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Electrical characteristics
Table 85. DAC characteristics (continued)
Symbol
Parameter
Conditions
Min Typ Max Unit
Comments
VSSA
Ground
-
0
5
-
-
0
-
V
-
Connected
to VSSA
-
-
DAC
output
buffer ON
(2)
RLOAD
Resistive load
kΩ
Connected
to VDDA
25
-
-
-
-
When the buffer is OFF, the
Minimum resistive load
Impedance output
with buffer OFF
(2)
RO
-
15
kΩ between DAC_OUT and VSS
to have a 1% accuracy is
1.5 MΩ
Maximum capacitive load at
pF DAC_OUT pin (when the
buffer is ON).
(2)
CLOAD
Capacitive load
-
-
-
-
-
50
-
Lower DAC_OUT
voltage with buffer
ON
It gives the maximum output
excursion of the DAC.
DAC_OUT
min(2)
0.2
V
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
VREF+ = 3.6 V and (0x1C7) to
(0xE38) at VREF+ = 1.7 V
Higher DAC_OUT
voltage with buffer
ON
DAC_OUT
max(2)
VDDA
– 0.2
-
-
-
-
-
-
-
0.5
-
V
mV
V
Lower DAC_OUT
voltage with buffer
OFF
DAC_OUT
min(2)
-
It gives the maximum output
excursion of the DAC.
Higher DAC_OUT
voltage with buffer
OFF
VREF
DAC_OUT
max(2)
–
+
1LSB
With no load, worst code
(0x800) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs
-
-
170 240
DAC DC VREF
current
consumption in
quiescent mode
(Standby mode)
(4)
IVREF+
µA
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs
-
-
-
-
-
-
50
75
With no load, middle code
(0x800) on the inputs
280 380
475 625
µA
µA
DAC DC VDDA
current
(4)
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs
IDDA
consumption in
quiescent mode(3)
Differential non
linearity Difference
between two
consecutive code-
1LSB)
Given for the DAC in 10-bit
configuration.
-
-
-
-
-
-
±0.5 LSB
DNL(4)
Given for the DAC in 12-bit
configuration.
±2
LSB
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Electrical characteristics
STM32F446xC/E
Comments
Table 85. DAC characteristics (continued)
Symbol
Parameter
Integral non
Conditions
Min Typ Max Unit
Given for the DAC in 10-bit
configuration.
-
-
-
±1
LSB
linearity(difference
between
measured value at
Code i and the
value at Code i on
a line drawn
between Code 0
and last Code
1023)
INL(4)
Given for the DAC in 12-bit
configuration.
-
-
-
±4
LSB
Offset error
Given for the DAC in 12-bit
configuration
-
-
-
-
-
-
-
-
-
-
-
-
±10 mV
(difference
between
measured value at
Code (0x800) and
the ideal value =
VREF+/2)
Given for the DAC in 10-bit at
Offset(4)
±3
LSB
VREF+ = 3.6 V
Given for the DAC in 12-bit at
VREF+ = 3.6 V
±12 LSB
Gain
Given for the DAC in 12-bit
configuration
Gain error
±0.5
%
µs
dB
error(4)
Total Harmonic
Distortion
(4
tSETTLING
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
-
-
-
-
3
-
6
-
)
Buffer ON
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
THD(4)
-
Max frequency for
a correct
DAC_OUT change
when small
variation in the
input code (from
code i to i+1LSB)
Update
rate(2)
MS/ CLOAD ≤ 50 pF,
-
-
-
1
s
RLOAD ≥ 5 kΩ
Wakeup time from
off state (Setting
the ENx bit in the
DAC Control
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
input code between lowest
and highest possible ones.
(4)
tWAKEUP
-
-
-
-
6.5
10
µs
register)
Power supply
rejection ratio (to
VDDA) (static DC
measurement)
PSRR+ (2)
- 67 - 40
dB No RLOAD, CLOAD = 50 pF
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.16.2:
Internal reset OFF).
2. Guaranteed by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed based on test during characterization.
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Electrical characteristics
Figure 49. 12-bit buffered/non-buffered DAC
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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
DocID027107 Rev 6
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175
Electrical characteristics
STM32F446xC/E
6.3.26
FMC characteristics
Unless otherwise specified, the parameters given in Table 86 to Table 93 for the FMC
interface are derived from tests performed under the ambient temperature, f frequency
HCLK
and V supply voltage conditions summarized in Table 15, with the following configuration:
DD
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitance load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 50 through Figure 53 represent asynchronous waveforms and Table 86 through
Table 93 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
•
•
•
AddressSetupTime = 0x1
AddressHoldTime = 0x1
DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
BusTurnAroundDuration = 0x0
In all timing tables, the T
is the HCLK clock period.
HCLK
152/202
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STM32F446xC/E
Electrical characteristics
Figure 50. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
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175
Electrical characteristics
STM32F446xC/E
Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR -
(1)(2)
read timings
Parameter
FMC_NE low time
Symbol
Min
Max
Unit
tw(NE)
tv(NOE_NE)
tw(NOE)
2THCLK – 2 2 THCLK + 0.5
FMC_NEx low to FMC_NOE low
FMC_NOE low time
0
1
2THCLK - 1
2THCLK + 0.5
th(NE_NOE)
tv(A_NE)
FMC_NOE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
0
-
-
0.5
th(A_NOE)
Address hold time after FMC_NOE high
FMC_NEx low to FMC_BL valid
FMC_BL hold time after FMC_NOE high
Data to FMC_NEx high setup time
Data to FMC_NOEx high setup time
Data hold time after FMC_NOE high
Data hold time after FMC_NEx high
FMC_NEx low to FMC_NADV low
FMC_NADV low time
0
-
tv(BL_NE)
-
2
ns
th(BL_NOE)
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NOE)
th(Data_NE)
tv(NADV_NE)
tw(NADV)
0
-
THCLK - 2
-
THCLK - 2
-
0
0
-
-
-
0
-
THCLK +1
1. CL = 30 pF.
2. Guaranteed based on test during characterization.
Table 87. Asynchronous non-multiplexed SRAM/PSRAM/NOR read -
(1)(2)
NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
7THCLK + 1
7THCLK
tw(NOE)
tw(NWAIT)
FMC_NWE low time
FMC_NWAIT low time
5THCLK – 1
THCLK – 0.5
5THCLK + 1
ns
-
-
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high 5THCLK+ 1.5
FMC_NEx hold time after FMC_NWAIT
invalid
th(NE_NWAIT)
4THCLK + 1
-
1. CL = 30 pF.
2. Guaranteed based on test during characterization.
154/202
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STM32F446xC/E
Electrical characteristics
Figure 51. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
T
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1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
(1)(2)
Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
tw(NE)
Parameter
Min
Max
Unit
FMC_NE low time
3 THCLK - 2 3 THCLK +0.5
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
FMC_NEx low to FMC_NWE low
FMC_NWE low time
THCLK – 0.5 THCLK + 0.5
THCLK
THCLK+ 0.5
FMC_NWE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
THCLK + 0.5
-
-
0
th(A_NWE)
tv(BL_NE)
th(BL_NWE)
tv(Data_NE)
Address hold time after FMC_NWE high
FMC_NEx low to FMC_BL valid
FMC_BL hold time after FMC_NWE high
Data to FMC_NEx low to Data valid
THCLK - 0.5
-
ns
-
1
THCLK + 0.5
-
-
THCLK + 2
th(Data_NWE) Data hold time after FMC_NWE high
tv(NADV_NE) FMC_NEx low to FMC_NADV low
THCLK + 0.5
-
-
-
0
tw(NADV)
FMC_NADV low time
THCLK+ 0.5
1. CL = 30 pF.
2. Guaranteed based on test during characterization.
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Electrical characteristics
STM32F446xC/E
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR write -
(1)(2)
NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
FMC_NWE low time
8THCLK - 0.5
8THCLK + 1
tw(NWE)
6THCLK - 0.5 6THCLK + 1
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
6THCLK - 0.5
4THCLK + 2
-
-
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT)
invalid
1. CL = 30 pF.
2. Guaranteed based on test during characterization.
Figure 52. Asynchronous multiplexed PSRAM/NOR read waveforms
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156/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
(1)(2)
Table 90. Asynchronous multiplexed PSRAM/NOR read timings
Symbol Parameter Min
FMC_NE low time 3THCLK – 2 3THCLK+0.5
Max
Unit
tw(NE)
tv(NOE_NE)
ttw(NOE)
FMC_NEx low to FMC_NOE low
FMC_NOE low time
2THCLK – 0.5
2THCLK
THCLK – 1
THCLK + 0.5
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FMC_NOE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
0
-
-
2
2
0
THCLK – 0.5 THCLK + 0.5
FMC_AD(address) valid hold time after
FMC_NADV high)
th(AD_NADV)
0
-
ns
th(A_NOE)
th(BL_NOE)
tv(BL_NE)
Address hold time after FMC_NOE high
FMC_BL time after FMC_NOE high
FMC_NEx low to FMC_BL valid
THCLK – 0.5
-
-
0
-
2
-
tsu(Data_NE)
Data to FMC_NEx high setup time
THCLK + 1.5
tsu(Data_NOE) Data to FMC_NOE high setup time
THCLK + 1
-
th(Data_NE)
th(Data_NOE)
Data hold time after FMC_NEx high
Data hold time after FMC_NOE high
0
0
-
-
1. CL = 30 pF.
2. Guaranteed based on test during characterization.
(1)(2)
Table 91. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
FMC_NWE low time
8THCLK - 1
5THCLK – 1
8THCLK + 2
tw(NOE)
5THCLK + 1
-
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK + 1.5
FMC_NEx hold time after FMC_NWAIT
invalid
th(NE_NWAIT)
4THCLK + 1
-
1. CL = 30 pF.
2. Guaranteed based on test during characterization.
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Electrical characteristics
STM32F446xC/E
Figure 53. Asynchronous multiplexed PSRAM/NOR write waveforms
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DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
(1)(2)
Table 92. Asynchronous multiplexed PSRAM/NOR write timings
Symbol
Parameter
FMC_NE low time
Min
Max
Unit
tw(NE)
4THCLK - 2 4THCLK+0.5
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FMC_NEx low to FMC_NWE low
FMC_NWE low time
THCLK
2THCLK
THCLK
-
THCLK + 0.5
2THCLK + 0.5
FMC_NWE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
0
1
0.5
THCLK – 0.5 THCLK+ 0.5
ns
FMC_AD(adress) valid hold time after
FMC_NADV high)
th(AD_NADV)
THCLK – 2
-
th(A_NWE)
th(BL_NWE)
Address hold time after FMC_NWE high
FMC_BL hold time after FMC_NWE high
FMC_NEx low to FMC_BL valid
THCLK
-
THCLK–2
-
tv(BL_NE)
-
2
tv(Data_NADV)
th(Data_NWE)
1. CL = 30 pF.
FMC_NADV high to Data valid
-
THCLK + 1.5
-
Data hold time after FMC_NWE high
THCLK + 0.5
2. Guaranteed based on test during characterization.
(1)(2)
Table 93. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
FMC_NWE low time
9THCLK
9THCLK + 0.5
tw(NWE)
7THCLK
7THCLK + 2
-
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
6THCLK + 1.5
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT)
invalid
4THCLK – 1
-
1. CL = 30 pF.
2. Guaranteed based on test during characterization.
Synchronous waveforms and timings
Figure 54 through Figure 57 represent synchronous waveforms and Table 94 through
Table 97 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
•
•
•
•
BurstAccessMode = FMC_BurstAccessMode_Enable;
MemoryType = FMC_MemoryType_CRAM;
WriteBurst = FMC_WriteBurst_Enable;
CLKDivision = 1; (0 is not supported, see the STM32F446 reference manual: RM0390)
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
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STM32F446xC/E
In all timing tables, the T
is the HCLK clock period (with maximum
HCLK
FMC_CLK = 90 MHz).
Figure 54. Synchronous multiplexed NOR/PSRAM read timings
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STM32F446xC/E
Electrical characteristics
(1)(2)
Table 94. Synchronous multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
2THCLK
-
2.5
-
td(CLKL-NExL)
td(CLKH_NExH)
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
-
THCLK - 0.5
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
0
0
-
td(CLKL-AV)
td(CLKH-AIV)
td(CLKL-NOEL)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK low to FMC_NOE low
-
2.5
-
THCLK
-
2
ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high
THCLK – 0.5
-
td(CLKL-ADV)
td(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
-
0.5
-
0
FMC_A/D[15:0] valid data before FMC_CLK
high
tsu(ADV-CLKH)
th(CLKH-ADV)
1
-
FMC_A/D[15:0] valid data after FMC_CLK high
3.5
1
-
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
3.5
-
1. CL = 30 pF.
2. Guaranteed based on test during characterization.
DocID027107 Rev 6
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175
Electrical characteristics
STM32F446xC/E
Figure 55. Synchronous multiplexed PSRAM write timings
"53452. ꢍ ꢅ
T
T
Wꢎ#,+ꢏ
Wꢎ#,+ꢏ
&-#?#,+
$ATA LATENCY ꢍ ꢅ
Dꢎ#,+,ꢊ.%X,ꢏ
T
T
Dꢎ#,+(ꢊ.%X(ꢏ
&-#?.%X
T
T
Dꢎ#,+,ꢊ.!$6,ꢏ
Dꢎ#,+,ꢊ.!$6(ꢏ
&-#?.!$6
T
Dꢎ#,+(ꢊ!)6ꢏ
T
T
Dꢎ#,+,ꢊ!6ꢏ
&-#?!;ꢃꢉꢓꢄꢈ=
T
Dꢎ#,+(ꢊ.7%(ꢏ
Dꢎ#,+,ꢊ.7%,ꢏ
&-#?.7%
T
T
T
Dꢎ#,+,ꢊ!$)6ꢏ
T
Dꢎ#,+,ꢊ$ATAꢏ
Dꢎ#,+,ꢊ$ATAꢏ
Dꢎ#,+,ꢊ!$6ꢏ
&-#?!$;ꢄꢉꢓꢅ=
!$;ꢄꢉꢓꢅ=
$ꢄ
$ꢃ
&-#?.7!)4
ꢎ7!)4#&' ꢍ ꢅBꢒ
7!)40/, ꢌ ꢅBꢏ
T
T
Hꢎ#,+(ꢊ.7!)46ꢏ
SUꢎ.7!)46ꢊ#,+(ꢏ
T
Dꢎ#,+(ꢊ.",(ꢏ
&-#?.",
-3ꢀꢃꢇꢉꢁ6ꢄ
162/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
(1)(2)
Table 95. Synchronous multiplexed PSRAM write timings
Symbol
tw(CLK)
Parameter
Min
Max
Unit
FMC_CLK period, VDD range= 2.7 to 3.6 V
2THCLK - 1
-
2.5
-
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
THCLK + 0.5
-
2
-
0
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
2
-
THCLK
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low
-
0
-
ns
THCLK - 0.5
-
3
-
0
-
3
-
0
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
THCLK - 0.5
-
4
0
-
-
1. CL = 30 pF.
2. Guaranteed based on test during characterization.
DocID027107 Rev 6
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175
Electrical characteristics
STM32F446xC/E
Figure 56. Synchronous non-multiplexed NOR/PSRAM read timings
T
T
Wꢎ#,+ꢏ
Wꢎ#,+ꢏ
&-#?#,+
T
T
Dꢎ#,+(ꢊ.%X(ꢏ
Dꢎ#,+,ꢊ.%X,ꢏ
$ATA LATENCY ꢍ ꢅ
Dꢎ#,+,ꢊ.!$6(ꢏ
&-#?.%X
T
T
Dꢎ#,+,ꢊ.!$6,ꢏ
&-#?.!$6
&-#?!;ꢃꢉꢓꢅ=
T
T
Dꢎ#,+(ꢊ!)6ꢏ
Dꢎ#,+,ꢊ!6ꢏ
T
T
Dꢎ#,+(ꢊ./%(ꢏ
Dꢎ#,+,ꢊ./%,ꢏ
&-#?./%
T
T
SUꢎ$6ꢊ#,+(ꢏ
Hꢎ#,+(ꢊ$6ꢏ
T
T
Hꢎ#,+(ꢊ$6ꢏ
SUꢎ$6ꢊ#,+(ꢏ
&-#?$;ꢄꢉꢓꢅ=
&-#?.7!)4
$ꢄ
$ꢃ
T
T
T
SUꢎ.7!)46ꢊ#,+(ꢏ
Hꢎ#,+(ꢊ.7!)46ꢏ
ꢎ7!)4#&' ꢍ ꢄBꢒ
7!)40/, ꢌ ꢅBꢏ
T
T
Hꢎ#,+(ꢊ.7!)46ꢏ
SUꢎ.7!)46ꢊ#,+(ꢏ
&-#?.7!)4
ꢎ7!)4#&' ꢍ ꢅBꢒ
7!)40/, ꢌ ꢅBꢏ
T
SUꢎ.7!)46ꢊ#,+(ꢏ
Hꢎ#,+(ꢊ.7!)46ꢏ
-3ꢀꢃꢇꢉꢆ6ꢄ
(1)(2)
Table 96. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
FMC_CLK low to FMC_NEx low (x=0..2)
2THCLK
-
t(CLKL-NExL)
-
2.5
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
THCLK – 0.5
-
0
-
-
0
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
2.5
-
THCLK
ns
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high
-
2
-
THCLK – 0.5
tsu(DV-CLKH)
th(CLKH-DV)
FMC_D[15:0] valid data before FMC_CLK high
FMC_D[15:0] valid data after FMC_CLK high
1
-
3.5
1
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
-
3.5
-
164/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
1. CL = 30 pF.
2. Guaranteed based on test during characterization.
Figure 57. Synchronous non-multiplexed PSRAM write timings
T
T
Wꢎ#,+ꢏ
Wꢎ#,+ꢏ
&-#?#,+
T
T
Dꢎ#,+,ꢊ.%X,ꢏ
&-#?.%X
Dꢎ#,+(ꢊ.%X(ꢏ
$ATA LATENCY ꢍ ꢅ
Dꢎ#,+,ꢊ.!$6(ꢏ
T
T
Dꢎ#,+,ꢊ.!$6,ꢏ
&-#?.!$6
&-#?!;ꢃꢉꢓꢅ=
&-#?.7%
T
Dꢎ#,+(ꢊ!)6ꢏ
T
T
Dꢎ#,+,ꢊ!6ꢏ
TDꢎ#,+(ꢊ.7%(ꢏ
Dꢎ#,+,ꢊ.7%,ꢏ
T
T
Dꢎ#,+,ꢊ$ATAꢏ
Dꢎ#,+,ꢊ$ATAꢏ
&-#?$;ꢄꢉꢓꢅ=
$ꢄ
$ꢃ
&-#?.7!)4
ꢎ7!)4#&' ꢍ ꢅBꢒ 7!)40/, ꢌ ꢅBꢏ
&-#?.",
T
T
Dꢎ#,+(ꢊ.",(ꢏ
SUꢎ.7!)46ꢊ#,+(ꢏ
T
Hꢎ#,+(ꢊ.7!)46ꢏ
-3ꢀꢃꢇꢈꢅ6ꢄ
DocID027107 Rev 6
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175
Electrical characteristics
STM32F446xC/E
(1)(2)
Table 97. Synchronous non-multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
2THCLK – 1
-
2.5
-
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
THCLK – 0.5
-
2
-
0
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
2
-
0
ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low
-
3
-
THCLK + 1
-
2.5
-
3
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
THCLK + 1.5
-
1.5
0
-
-
1. CL = 30 pF.
2. Guaranteed based on test during characterization.
NAND controller waveforms and timings
Figure 58 through Figure 61 represent synchronous waveforms, and Table 98 and Table 99
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
COM.FSMC_SetupTime = 0x01;
COM.FMC_WaitSetupTime = 0x03;
COM.FMC_HoldSetupTime = 0x02;
COM.FMC_HiZSetupTime = 0x01;
ATT.FMC_SetupTime = 0x01;
ATT.FMC_WaitSetupTime = 0x03;
ATT.FMC_HoldSetupTime = 0x02;
ATT.FMC_HiZSetupTime = 0x01;
Bank = FMC_Bank_NAND;
MemoryDataWidth = FMC_MemoryDataWidth_16b;
ECC = FMC_ECC_Enable;
ECCPageSize = FMC_ECCPageSize_512Bytes;
TCLRSetupTime = 0;
TARSetupTime = 0.
In all timing tables, the T
is the HCLK clock period.
DocID027107 Rev 6
HCLK
166/202
STM32F446xC/E
Electrical characteristics
Figure 58. NAND controller waveforms for read access
&-#?.#%X
!,% ꢎ&-#?!ꢄꢇꢏ
#,% ꢎ&-#?!ꢄꢈꢏ
&-#?.7%
T
THꢎ./%ꢊ!,%ꢏ
Dꢎ!,%ꢊ./%ꢏ
&-#?./% ꢎ.2%ꢏ
&-#?$;ꢄꢉꢓꢅ=
T
T
Hꢎ./%ꢊ$ꢏ
SUꢎ$ꢊ./%ꢏ
-3ꢀꢃꢇꢈꢇ6ꢄ
Figure 59. NAND controller waveforms for write access
&-#?.#%X
!,% ꢎ&-#?!ꢄꢇꢏ
#,% ꢎ&-#?!ꢄꢈꢏ
T
T
Hꢎ.7%ꢊ!,%ꢏ
Dꢎ!,%ꢊ.7%ꢏ
&-#?.7%
&-#?./% ꢎ.2%ꢏ
&-#?$;ꢄꢉꢓꢅ=
T
T
Hꢎ.7%ꢊ$ꢏ
Vꢎ.7%ꢊ$ꢏ
-3ꢀꢃꢇꢈꢁ6ꢄ
DocID027107 Rev 6
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175
Electrical characteristics
STM32F446xC/E
Figure 60. NAND controller waveforms for common memory read access
&-#?.#%X
!,% ꢎ&-#?!ꢄꢇꢏ
#,% ꢎ&-#?!ꢄꢈꢏ
T
T
Hꢎ./%ꢊ!,%ꢏ
Dꢎ!,%ꢊ./%ꢏ
&-#?.7%
&-#?./%
T
Wꢎ./%ꢏ
T
T
Hꢎ./%ꢊ$ꢏ
SUꢎ$ꢊ./%ꢏ
&-#?$;ꢄꢉꢓꢅ=
-3ꢀꢃꢇꢈꢆ6ꢄ
Figure 61. NAND controller waveforms for common memory write access
&-#?.#%X
!,% ꢎ&-#?!ꢄꢇꢏ
#,% ꢎ&-#?!ꢄꢈꢏ
T
T
T
Hꢎ./%ꢊ!,%ꢏ
Dꢎ!,%ꢊ./%ꢏ
Wꢎ.7%ꢏ
&-#?.7%
&-#?. /%
T
Dꢎ$ꢊ.7%ꢏ
T
T
Vꢎ.7%ꢊ$ꢏ
Hꢎ.7%ꢊ$ꢏ
&-#?$;ꢄꢉꢓꢅ=
-3ꢀꢃꢇꢇꢅ6ꢄ
(1)
Table 98. Switching characteristics for NAND Flash read cycles
Parameter Min Max
FMC_NOE low width 4THCLK – 0.5 4THCLK + 0.5
Symbol
Unit
tw(N0E)
tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high
th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high
td(ALE-NOE) FMC_ALE valid before FMC_NOE low
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid
1. CL = 30 pF.
9
-
2.5
-
ns
-
3THCLK - 0.5
3THCLK – 2
-
168/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
(1)
Table 99. Switching characteristics for NAND Flash write cycles
Symbol
tw(NWE)
tv(NWE-D)
Parameter
FMC_NWE low width
Min
Max
Unit
4THCLK - 2
0
4THCLK
ns
ns
ns
ns
FMC_NWE low to FMC_D[15-0] valid
FMC_NWE high to FMC_D[15-0] invalid
FMC_D[15-0] valid before FMC_NWE high
FMC_ALE valid before FMC_NWE low
FMC_NWE high to FMC_ALE invalid
-
-
-
th(NWE-D)
3THCLK – 1
5THCLK – 3
-
td(D-NWE)
td(ALE-NWE)
th(NWE-ALE)
1. CL = 30 pF.
3THCLK - 0.5 ns
ns
3THCLK – 2
-
SDRAM waveforms and timings
Figure 62. SDRAM read access waveforms (CL = 1)
&-#?3$#,+
TDꢎ3$#,+,?!DD#ꢏ
THꢎ3$#,+,?!DD2ꢏ
TDꢎ3$#,+,?!DD2ꢏ
2OW N
#OLꢄ
#OLꢃ
#OLI
#OLN
&-#?!>ꢄꢇꢎꢉ@
THꢎ3$#,+,?!DD#ꢏ
THꢎ3$#,+,?3.$%ꢏ
THꢎ3$#,+,?.#!3ꢏ
TDꢎ3$#,+,?3.$%ꢏ
&-#?3$.%;ꢄꢓꢅ=
TDꢎ3$#,+,?.2!3ꢏ
THꢎ3$#,+,?.2!3ꢏ
&-#?3$.2!3
&-#?3$.#!3
TDꢎ3$#,+,?.#!3ꢏ
&-#?3$.7%
&-#?$;ꢀꢄꢓꢅ=
TSUꢎ3$#,+(?$ATAꢏ
THꢎ3$#,+(?$ATAꢏ
$ATAꢄ $ATAꢃ $ATAI
$ATAN
-3ꢀꢃꢇꢉꢄ6ꢃ
DocID027107 Rev 6
169/202
175
Electrical characteristics
Symbol
STM32F446xC/E
(1)(2)
Table 100. SDRAM read timings
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data input setup time
Data input hold time
Address valid time
2THCLK-0.5
2THCLK+0.5
tsu(SDCLKH _Data)
th(SDCLKH_Data)
td(SDCLKL_Add)
td(SDCLKL_ SDNE)
th(SDCLKL_SDNE)
1
4
-
-
-
3
Chip select valid time
Chip select hold time
-
1.5
-
ns
0
-
td(SDCLKL_SDNRAS) SDNRAS valid time
th(SDCLKL_SDNRAS) SDNRAS hold time
td(SDCLKL_SDNCAS) SDNCAS valid time
th(SDCLKL_SDNCAS) SDNCAS hold time
1.5
-
0
-
0.5
-
0
1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK.
2. Guaranteed based on test during characterization.
(1)(2)
Max
Table 101. LPSDR SDRAM read timings
Symbol
tw(SDCLK)
Parameter
Min
Unit
FMC_SDCLK period
Data input setup time
Data input hold time
Address valid time
2THCLK - 0.5
2THCLK + 0.5
tsu(SDCLKH _Data)
th(SDCLKH_Data)
td(SDCLKL_Add)
1
5
-
-
-
3
3
-
td(SDCLKL_ SDNE)
th(SDCLKL_SDNE)
Chip select valid time
Chip select hold time
-
ns
0
-
td(SDCLKL_SDNRAS) SDNRAS valid time
th(SDCLKL_SDNRAS) SDNRAS hold time
td(SDCLKL_SDNCAS) SDNCAS valid time
th(SDCLKL_SDNCAS) SDNCAS hold time
2
-
0
-
2
-
0
1. CL = 10 pF.
2. Guaranteed based on test during characterization.
170/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
Figure 63. SDRAM write access waveforms
&-#?3$#,+
TDꢎ3$#,+,?!DD#ꢏ
THꢎ3$#,+,?!DD2ꢏ
TDꢎ3$#,+,?!DD2ꢏ
2OW N
#OLꢄ
#OLꢃ
#OLI
#OLN
&-#?!>ꢄꢇꢎꢉ@
THꢎ3$#,+,?!DD#ꢏ
THꢎ3$#,+,?3.$%ꢏ
TDꢎ3$#,+,?3.$%ꢏ
&-#?3$.%;ꢄꢓꢅ=
TDꢎ3$#,+,?.2!3ꢏ
THꢎ3$#,+,?.2!3ꢏ
&-#?3$.2!3
&-#?3$.#!3
&-#?3$.7%
THꢎ3$#,+,?.#!3ꢏ
THꢎ3$#,+,?.7%ꢏ
TDꢎ3$#,+,?.#!3ꢏ
TDꢎ3$#,+,?.7%ꢏ
TDꢎ3$#,+,?$ATAꢏ
$ATAꢄ
$ATAꢃ
$ATAI
$ATAN
&-#?$;ꢀꢄꢓꢅ=
TDꢎ3$#,+,?.",ꢏ
&-#?.",;ꢀꢓꢅ=
THꢎ3$#,+,?$ATAꢏ
-3ꢀꢃꢇꢉꢃ6ꢃ
(1)(2)
Table 102. SDRAM write timings
Symbol
Parameter
Min
Max
Unit
F(SDCLK)
Frequency of operation
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
-
90
MHz
tw(SDCLK)
2THCLK - 0.5
2THCLK + 0.5
td(SDCLKL _Data)
th(SDCLKL _Data)
td(SDCLK _Add)
-
0.5
-
2
-
3
td(SDCLKL _SDNWE)) SDNWE valid time
th(SDCLKL_SDNWE)) SDNWE hold time
-
1.5
-
0
-
ns
td(SDCLKL_SDNE))
th(SDCLKL_SDNE)
Chip select valid time
Chip select hold time
1.5
-
0
-
td(SDCLKL_SDNRAS) SDNRAS valie time
th(SDCLKL_SDNRAS) SDNRAS hold time
td(SDCLKL_SDNCAS) SDNCAS valid time
th(SDCLKL_SDNCAS) SDNCAS hold time
1
0
-
-
1
0
-
1. CL = 10 pF on data and address line. CL=15 pF on FMC_SDCLK.
2. Guaranteed based on test during characterization.
DocID027107 Rev 6
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175
Electrical characteristics
Symbol
STM32F446xC/E
(1)(2)
Max
Table 103. LPSDR SDRAM write timings
Parameter
Min
Unit
F(SDCLK)
Frequency of operation
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
-
84
MHz
tw(SDCLK)
2THCLK - 0.5
2THCLK + 0.5
td(SDCLKL _Data)
th(SDCLKL _Data)
td(SDCLK _Add)
-
0.5
-
5
-
3
3
-
td(SDCLKL _SDNWE)) SDNWE valid time
th(SDCLKL_SDNWE)) SDNWE hold time
-
0
-
ns
td(SDCLKL_SDNE))
th(SDCLKL_ SDNE)
Chip select valid time
Chip select hold time
2.5
-
0
-
td(SDCLKL_SDNRAS) SDNRAS valid time
th(SDCLKL_SDNRAS) SDNRAS hold time
td(SDCLKL_SDNCAS) SDNCAS valid time
td(SDCLKL_SDNCAS) SDNCAS hold time
2
-
0
-
2
-
0
1. CL = 10 pF.
2. Guaranteed based on test during characterization.
6.3.27
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 104 for DCMI are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 16, with the following configuration:
•
•
•
DCMI_PIXCLK polarity: falling
DCMI_VSYNC and DCMI_HSYNC polarity: high
Data formats: 14 bits
Table 104. DCMI characteristics
Parameter
Frequency ratio DCMI_PIXCLK/f
Symbol
Min
Max
Unit
-
-
-
0.4
54
70
-
-
HCLK
DCMI_PIXCLK Pixel clock input
MHz
%
DPixel
tsu(DATA)
th(DATA)
Pixel clock input duty cycle
30
1
Data input setup time
Data input hold time
3.5
-
tsu(HSYNC)
tsu(VSYNC)
th(HSYNC)
th(VSYNC)
ns
DCMI_HSYNC/DCMI_VSYNC input setup time
DCMI_HSYNC/DCMI_VSYNC input hold time
2
0
-
-
172/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
Figure 64. DCMI timing diagram
ꢄꢋ'&0,B3,;&/.
'&0,B3,;&/.
'&0,B+6<1&
'&0,B96<1&
'$7$>ꢉꢎꢄꢀ@
WKꢍ+6<1&ꢏ
WVXꢍ+6<1&ꢏ
WKꢍ+6<1&ꢏ
WVXꢍ96<1&ꢏ
WVXꢍ'$7$ꢏ WKꢍ'$7$ꢏ
06ꢀꢇꢂꢄꢂ9ꢇ
6.3.28
SD/SDIO MMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Table 105 for the SDIO are derived
from tests performed under the ambient temperature, f frequency and V supply
PCLK2
DD
voltage conditions summarized in Table 16, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Figure 65. SDIO high-speed mode
T
T
R
F
T
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T
T
7ꢎ#+(ꢏ
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T
T
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T
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$ꢒ #-$
ꢎINPUTꢏ
AIꢄꢂꢁꢁꢇ
DocID027107 Rev 6
173/202
175
Electrical characteristics
STM32F446xC/E
Figure 66. SD default mode
#+
T
T
/6$
/($
$ꢒ #-$
ꢎOUTPUTꢏ
AIꢄꢂꢁꢁꢁ
(1)(2)
Table 105. Dynamic characteristics: SD / MMC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
-
tW(CKL)
tW(CKH)
Clock frequency in data transfer mode
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
0
-
-
-
50
8/3
-
MHz
-
-
fpp =50MHz
fpp =50MHz
9.5
8.5
10.5
9.5
ns
ns
ns
Clock high time
-
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU
tIH
Input setup time HS
Input hold time HS
fpp =50MHz
fpp =50MHz
1
-
-
-
-
4.5
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV
tOH
Output valid time HS
Output hold time HS
fpp =50MHz
fpp =50MHz
-
12.5
-
13
-
11
CMD, D inputs (referenced to CK) in SD default mode
2.5
5.5
-
-
-
-
tISUD
tIHD
Input setup time SD
Input hold time SD
fpp =25MHz
fpp =25MHz
ns
ns
CMD, D outputs (referenced to CK) in SD default mode
-
3.5
-
4
-
tOVD
tOHD
Output valid default time SD
Output hold default time SD
fpp =24MHz
fpp =24MHz
2
1. Guaranteed based on test during characterization.
2. VDD = 2.7 to 3.6 V.
174/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
(1)(2)
Table 106. Dynamic characteristics: eMMC characteristics V = 1.7 V to 1.9 V
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
-
tW(CKL)
tW(CKH)
Clock frequency in data transfer mode
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
-
0
-
-
-
50
8/3
-
MHz
-
fpp =50MHz
fpp =50MHz
9.5
8.5
10.5
9.5
ns
ns
ns
Clock high time
-
CMD, D inputs (referenced to CK) in eMMC mode
tISU
tIH
Input setup time HS
Input hold time HS
fpp =50MHz
fpp =50MHz
0.5
7.5
-
-
-
-
CMD, D outputs (referenced to CK) in eMMC mode
tOV
tOH
Output valid time HS
Output hold time HS
fpp =50MHz
fpp =50MHz
-
13.5
-
14.5
-
12
1. Guaranteed based on test during characterization.
2. VDD = 2.7 to 3.6 V.
6.3.29
RTC characteristics
Table 107. RTC characteristics
Conditions
Symbol
Parameter
Min
Max
Any read/write operation
from/to an RTC register
-
fPCLK1/RTCCLK frequency ratio
4
-
DocID027107 Rev 6
175/202
175
Package information
STM32F446xC/E
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
7.1
LQFP64 package information
Figure 67. LQFP64-10x10 mm 64 pin low-profile quad flat package outline
6($7,1*ꢈ3/$1(
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H
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1. Drawing is not to scale
Table 108. LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.050
1.350
0.170
0.090
-
0.0020
0.0531
0.0067
0.0035
-
1.400
0.220
-
0.0551
0.0087
-
c
176/202
DocID027107 Rev 6
STM32F446xC/E
Package information
Table 108. LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
D
D1
D3
E
11.800
12.000
10.000
7.500
12.000
10.000
7.500
0.500
0.600
1.000
3.5°
12.200
0.4646
0.4724
0.3937
0.2953
0.4724
0.3937
0.2953
0.0197
0.0236
0.0394
3.5°
0.4803
9.800
10.200
0.3858
0.4016
-
-
-
-
11.800
12.200
0.4646
0.4803
E1
E3
e
9.800
10.200
0.3858
0.4016
-
-
-
-
-
-
0.750
-
-
-
0.0295
-
L
0.450
0.0177
L1
K
-
0°
-
-
0°
-
7°
7°
ccc
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 68. LQFP64 Recommended footprint
ꢂꢁ
ꢀꢀ
ꢅꢑꢀ
ꢅꢑꢉ
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ꢄꢃꢑꢇ
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ꢄꢅꢑꢀ
ꢇꢑꢁ
ꢄꢇ
ꢈꢂ
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ꢄ
ꢄꢃꢑꢇ
AIꢄꢂꢆꢅꢆC
1. Drawing is not to scale.
2. Dimensions are in millimeters.
DocID027107 Rev 6
177/202
199
Package information
STM32F446xC/E
Device marking for LQFP64
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 69. LQFP64 marking example (package top view)
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1. Parts marked as “ES”, "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
178/202
DocID027107 Rev 6
STM32F446xC/E
Package information
7.2
LQFP100 package information
Figure 70. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline
3%!4).' 0,!.%
#
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1. Drawing is not to scale.
Table 109. LQPF100, 14 x 14 mm 100-pin low-profile quad flat
package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
16.200
14.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
-
0.050
1.350
0.170
0.090
15.800
13.800
-
-
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
16.000
14.000
12.000
16.000
0.6299
0.5512
0.4724
0.6299
D1
D3
E
15.800
16.200
0.6220
0.6378
DocID027107 Rev 6
179/202
199
Package information
STM32F446xC/E
Table 109. LQPF100, 14 x 14 mm 100-pin low-profile quad flat
package mechanical data (continued)
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
E1
E3
e
13.800
14.000
12.000
0.500
0.600
1.000
3.5°
14.200
0.5433
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
0.5591
-
-
-
-
-
-
0.750
-
-
-
0.0295
-
L
0.450
0.0177
L1
k
-
0°
-
-
0°
-
7°
7°
ccc
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 71. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint
ꢇꢉ
ꢉꢄ
ꢇꢈ
ꢉꢅ
ꢅꢑꢉ
ꢅꢑꢀ
ꢄꢈꢑꢇ ꢄꢂꢑꢀ
ꢄꢅꢅ
ꢃꢈ
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ꢄ
ꢃꢉ
ꢄꢃꢑꢀ
ꢄꢈꢑꢇ
AIꢄꢂꢆꢅꢈC
1. Dimensions are expressed in millimeters.
180/202
DocID027107 Rev 6
STM32F446xC/E
Package information
Device marking for LQFP100 package
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 72. LQFP100 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID027107 Rev 6
181/202
199
Package information
STM32F446xC/E
7.3
LQFP144 package information.
Figure 73. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline
ꢉꢌꢇꢅꢈPP
*$8*(ꢈ3/$1(
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H
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1. Drawing is not to scale.
182/202
DocID027107 Rev 6
STM32F446xC/E
Symbol
Package information
Table 110. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
21.800
19.800
-
-
1.600
0.150
1.450
0.270
0.200
22.200
20.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.874
0.7953
-
-
0.0020
0.0531
0.0067
0.0035
0.8583
0.7795
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
22.000
20.000
17.500
22.000
20.000
17.500
0.500
0.600
1.000
3.5°
0.8661
0.7874
0.689
0.8661
0.7874
0.6890
0.0197
0.0236
0.0394
3.5°
D1
D3
E
21.800
19.800
-
22.200
20.200
-
0.8583
0.7795
-
0.8740
0.7953
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID027107 Rev 6
183/202
199
Package information
STM32F446xC/E
Figure 74. LQFP144 recommended footprint
ꢄꢌꢀꢅ
ꢄꢉꢁ
ꢆꢀ
ꢄꢉꢊ
ꢆꢇ
ꢉꢌꢀꢅ
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ꢇꢇꢌꢃ
DLꢄꢂꢊꢉꢅH
1. Dimensions are expressed in millimeters.
184/202
DocID027107 Rev 6
STM32F446xC/E
Package information
Device marking for LQFP144 package
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 75. LQFP144 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID027107 Rev 6
185/202
199
Package information
STM32F446xC/E
7.4
UFBGA144 7 x 7 mm package information
Figure 76. UFBGA144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline
= 6HDWLQJꢈSODQH
GGG =
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= < ;
=
III
$ꢉ$6B0(B9ꢇ
1. Drawing is not in scale.
Table 111. UFBGA144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
A3
A4
b
0.460
0.050
0.400
-
0.530
0.080
0.450
0.130
0.320
0.280
7.000
5.500
7.000
5.500
0.500
0.750
0.600
0.110
0.500
-
0.0181
0.0020
0.0157
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0110
0.2756
0.2165
0.2756
0.2165
0.0197
0.0295
0.0236
0.0043
0.0197
-
0.270
0.230
6.950
5.450
6.950
5.450
-
0.370
0.320
7.050
5.550
7.050
5.550
-
0.0106
0.0091
0.2736
0.2146
0.2736
0.2146
-
0.0146
0.0126
0.2776
0.2185
0.2776
0.2185
-
D
D1
E
E1
e
F
0.700
0.800
0.0276
0.0315
186/202
DocID027107 Rev 6
STM32F446xC/E
Package information
Table 111. UFBGA144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
ddd
eee
fff
-
-
-
-
-
-
0.100
0.150
0.050
-
-
-
-
-
-
0.0039
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 77. UFBGA144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package recommended footprint
'SDG
'VP
ꢃϬꢃ^ͺ&Wͺsϭ
Table 112. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.50 mm
0.280 mm
0.370 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
0.280 mm
Between 0.100 mm and 0.125 mm
0.120 mm
DocID027107 Rev 6
187/202
199
Package information
STM32F446xC/E
Device marking for UFBGA144 7 x 7 mm package
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 78. UQFP144 7 x 7 mm marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
188/202
DocID027107 Rev 6
STM32F446xC/E
Package information
7.5
UFBGA144 10 x 10 mm package information
Figure 79. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package outline
& 6HDWLQJꢈSODQH
GGG =
$ꢂ
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$
$ꢀ
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III 0 &
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1. Drawing is not to scale.
Table 113. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
A3
A4
b
0.460
0.050
0.400
0.050
0.270
0.360
9.950
8.750
9.950
8.750
0.750
0.530
0.080
0.450
0.080
0.320
0.400
10.000
8.800
10.000
8.800
0.800
0.600
0.110
0.500
0.110
0.370
0.440
10.050
8.850
10.050
8.850
0.850
0.0181
0.0020
0.0157
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0110
0.2756
0.2362
0.2756
0.2362
0.0197
0.0236
0.0043
0.0197
-
0.0106
0.0091
0.2736
0.2343
0.2736
0.2343
-
0.0146
0.0130
0.2776
0.2382
0.2776
0.2382
-
D
D1
E
E1
e
DocID027107 Rev 6
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199
Package information
STM32F446xC/E
Table 113. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
F
0.550
0.600
0.650
0.080
0.150
0.080
0.0177
0.0197
0.0217
0.0039
0.0059
0.0020
ddd
eee
fff
-
-
-
-
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 80. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package recommended footprint
'SDG
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ꢃϬϮzͺ&Wͺsϭ
Table 114. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.80 mm
0.400 mm
0.550 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
0.400 mm
Between 0.100 mm and 0.125 mm
0.120 mm
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Package information
Device marking for UFBGA144 10 x 10 mm package
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 81. UQFP144 10 x 10 mm marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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Package information
STM32F446xC/E
7.6
WLCSP81 package information
Figure 82. WLCSP81 - 81-pin, 3.693 x 3.815 mm, 0.4 mm pitch wafer level chip scale
package outline
EEE =
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1. Drawing is not to scale.
Table 115. WLCSP81- 81-pin, 3.693 x 3.815 mm, 0.4 mm pitch wafer level chip scale
package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
-
Max
Min
Typ
Max
A
A1
A2
A3(2)
b(3)
D
-
0.600
-
-
0.0236
-
0.170
0.380
0.025
0.250
3.693
3.815
0.400
3.200
3.200
-
-
0.0067
0.0150
0.0010
0.0098
0.1454
0.1502
0.0157
0.1260
0.1260
-
-
-
-
-
-
-
-
-
0.220
0.280
0.0087
0.0110
3.658
3.728
0.1440
0.1468
E
3.780
3.850
0.1488
0.1516
e
-
-
-
-
-
-
-
-
-
-
-
-
e1
e2
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STM32F446xC/E
Package information
Table 115. WLCSP81- 81-pin, 3.693 x 3.815 mm, 0.4 mm pitch wafer level chip scale
package mechanical data (continued)
millimeters
inches(1)
Symbol
Min
Typ
Max
-
Min
Typ
Max
-
F
-
-
-
-
-
-
-
0.2465
-
-
-
-
-
-
-
0.0097
G
0.3075
-
0.0121
-
aaa
bbb
ccc
ddd
eee
-
-
-
-
-
0.100
0.100
0.100
0.050
0.050
-
-
-
-
-
0.0039
0.0039
0.0039
0.0020
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Figure 83. WLCSP81- 81-pin, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint
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Table 116. WLCSP81 recommended PCB design rules (0.4 mm pitch)
Dimension
Recommended values
Pitch
Dpad
0.4 mm
0.225 mm
0.290 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
0.250 mm
0.100 mm
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199
Package information
STM32F446xC/E
Device marking for WLCSP81 package
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 84. WLCSP81 10 x 10 mm marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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DocID027107 Rev 6
STM32F446xC/E
Package information
7.7
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in ° C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 117. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm
46
42
33
51
48
48
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP144 - 20 × 20 mm / 0.5 mm pitch
Θ
°C/W
JA
Thermal resistance junction-ambient
UFBGA144 - 7 × 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
UFBGA144 - 10 × 10 mm / 0.8 mm pitch
Thermal resistance junction-ambient
WLCSP81
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
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Part numbering
STM32F446xC/E
8
Part numbering
Table 118. Ordering information scheme
STM32
Example:
F
446 V
C
T
6
xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
446= STM32F446xC/E,
Pin count
M = 81 pins
R = 64 pins
V = 100 pins
Z = 144 pins
Flash memory size
C=256 Kbytes of Flash memory
E=512 Kbytes of Flash memory
Package
H = UFBGA (7 x 7 mm)
J = UFBGA (10 x 10 mm)
T = LQFP
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options
xxx = programmed parts
TR = tape and reel
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
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Application block diagrams
Appendix A
Application block diagrams
A.1
USB OTG full speed (FS) interface solutions
Figure 85. USB controller configured as peripheral-only and used in Full speed mode
9''
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1. External voltage regulator only needed when building a VBUS powered device.
2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance
thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
Figure 86. USB controller configured as host-only and used in full speed mode
6$$
%.
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#URRENT LIMITER
ꢉ 6 0WR
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/VERCURRENT
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1. The current limiter is required only if the application has to support a VBUS powered device. A basic power
switch can be used if 5 V are available on the application board.
2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance
thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
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Application block diagrams
STM32F446xC/E
Figure 87. USB controller configured in dual mode and used in full speed mode
6$$
ꢉ 6 TO 6$$
VOLTAGE REGULATOR
ꢎꢄꢏ
6$$
%.
'0)/
ꢉ 6 0WR
#URRENT LIMITER
POWER SWITCH
ꢎꢃꢏ
/VERCURRENT
'0)/ꢌ)21
34-ꢂꢅ&ꢁXX
6"53
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6
33
-3ꢄꢆꢅꢅꢃ6ꢀ
1. External voltage regulator only needed when building a VBUS powered device.
2. The current limiter is required only if the application has to support a VBUS powered device. A basic power
switch can be used if 5 V are available on the application board.
3. The ID pin is required in dual role only.
4. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance
thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
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Application block diagrams
A.2
USB OTG high speed (HS) interface solutions
Figure 88. USB controller configured as peripheral, host, or dual-mode
and used in high speed mode
34-ꢂꢅ&ꢁXX
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53" (3
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5,0)?340
CONNECTOR
6"53
633
5,0)
5,0)?.84
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/4' 0(9
84ꢄ
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ꢃꢂ OR ꢃꢈ -(Z 84ꢎꢄꢏ
-#/ꢄ OR -#/ꢃ
8)
-3ꢄꢆꢅꢅꢉ6ꢃ
1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the
STM32F446xx with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example
of a possible connection.
2. The ID pin is required in dual role only.
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199
Revision history
STM32F446xC/E
Revision history
Table 119. Document revision history
Changes
Date
Revision
17-Feb-2015
1
Initial release.
Added note 2 inside Table 2
Updated Table 11, Table 23, Table 24, Table 25, Table 26, Table 30,
Table 51, Table 52, Table 53, and Table 61
16-Mar-2015
2
Added condition inside Typical and maximum current consumption and
Additional current consumption
Added FMPI2C characteristics
Added Table 62 and Figure 35
Updated:
– Section 6.3.15: Absolute maximum ratings (electrical sensitivity)
– Section 7: Package information
– Table 2: STM32F446xC/E features and peripheral counts
– Table 13: STM32F446xC/xE WLCSP81 ballout
– Figure 53: ESD absolute maximum ratings
– Figure 54: Synchronous multiplexed NOR/PSRAM read timings
Added:
29-May-2015
3
– Figure 78: UQFP144 7 x 7 mm marking example (package top view),
– Figure 81: UQFP144 10 x 10 mm marking example (package top
view),
– Figure 84: WLCSP81 10 x 10 mm marking example (package top
view)
Updated:
– Figure 14: STM32F446xC/xE UFBGA144 ballout
– Table 10: STM32F446xx pin and ball descriptions
– Table 18: VCAP_1/VCAP_2 operating conditions
– Section 3.15: Power supply schemes
– Section 6.3.2: VCAP_1/VCAP_2 external capacitor
Added:
10-Aug-2015
4
– Figure 5: VDDUSB connected to an external independent power
supply
– Notes 3 and 4 below Figure 18: Power supply scheme
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STM32F446xC/E
Revision history
Table 119. Document revision history (continued)
Revision Changes
Date
Updated:
– Introduction;
– Table 2: STM32F446xC/E features and peripheral counts
– Table 43: Main PLL characteristics
– Title of Table 45: PLLISAI characteristics
– Table 109: LQPF100, 14 x 14 mm 100-pin low-profile quad flat
package mechanical data
03-Nov-2015
5
– Table 118: Ordering information scheme
– Figure 10: STM32F446xC/xE LQFP64 pinout
– Figure 11: STM32F446xC/xE LQFP100 pinout
Added:
– Figure 77: UFBGA144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine
pitch ball grid array package recommended footprint
– Figure 111: UFBGA144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine
pitch ball grid array package mechanical data
Updated:
– Section 7: Package information;
– Table 30: Typical current consumption in Run mode, code with data
processing running from Flash memory or RAM, regulator ON (ART
accelerator enabled except prefetch), VDD=1.7 V
02-Sep-2016
6
– Table 74: ADC characteristics
– Table 85: DAC characteristics
Added:
– Note 3 in Figure 33: Recommended NRST pin protection
– Note 4 in Table 41: HSI oscillator characteristics
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STM32F446xC/E
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
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