STM32F401CDU6 [STMICROELECTRONICS]
Clock, reset and supply management;
| 型号： | STM32F401CDU6 |
| 厂家： | 
ST |
| 描述： | Clock, reset and supply management 时钟 CD 外围集成电路 |
| 文件： | 总135页 (文件大小：2072K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32F401xD STM32F401xE
ARM® Cortex®-M4 32b MCU+FPU, 105 DMIPS,
512KB Flash/96KB RAM, 11 TIMs, 1 ADC, 11 comm. interfaces
Datasheet - production data
Features
)%*$
®
®
• Core: ARM 32-bit Cortex -M4 CPU with
FPU, Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 84 MHz,
memory protection unit,
UFBGA100
(7 × 7 mm)
UFQFPN48
(7 × 7 mm)
LQFP100 (14 × 14 mm
(3.06 x 3.06 mm) LQFP64 (10 × 10 mm)
WLCSP49
105 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1),
and DSP instructions
• Debug mode
– Serial wire debug (SWD) & JTAG
• Memories
interfaces
– up to 512 Kbytes of Flash memory
– up to 96 Kbytes of SRAM
®
– Cortex -M4 Embedded Trace Macrocell™
• Up to 81 I/O ports with interrupt capability
• Clock, reset and supply management
– Up to 78 fast I/Os up to 42 MHz
– All I/O ports are 5 V-tolerant
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
• Up to 12 communication interfaces
2
– Up to 3 x I C interfaces (SMBus/PMBus)
– Up to 3 USARTs (2 x 10.5 Mbit/s,
1 x 5.25 Mbit/s), ISO 7816 interface, LIN,
IrDA, modem control)
• Power consumption
– Up to 4 SPIs (up to 42Mbit/s at
– Run: 146 µA/MHz (peripheral off)
f
= 84 MHz), SPI2 and SPI3 with muxed
CPU
2
full-duplex I S to achieve audio class
accuracy via internal audio PLL or external
clock
– Stop (Flash in Stop mode, fast wakeup
time): 42 µA Typ @ 25C; 65 µA max
@25 °C
– SDIO interface
– Stop (Flash in Deep power down mode,
fast wakeup time): down to 10 µA @ 25 °C;
30 µA max @25 °C
– Advanced connectivity: USB 2.0 full-speed
device/host/OTG controller with on-chip
PHY
• CRC calculation unit
– Standby: 2.4 µA @25 °C / 1.7 V without
RTC; 12 µA @85 °C @1.7 V
• 96-bit unique ID
– V
supply for RTC: 1 µA @25 °C
BAT
• RTC: subsecond accuracy, hardware calendar
• All packages (WLCSP49, LQFP64/100,
• 1×12-bit, 2.4 MSPS A/D converter: up to 16
®
channels
UFQFPN48, UFBGA100) are ECOPACK 2
• General-purpose DMA: 16-stream DMA
controllers with FIFOs and burst support
Table 1. Device summary
• Up to 11 timers: up to six 16-bit, two 32-bit
timers up to 84 MHz, each with up to four
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input, two watchdog
timers (independent and window) and a
SysTick timer
Reference
Part number
STM32F401CD,
STM32F401RD, STM32F401VD
STM32F401xD
STM32F401CE,
STM32F401RE, STM32F401VE
STM32F401xE
January 2015
DocID025644 Rev 3
1/135
This is information on a product in full production.
www.st.com
Contents
STM32F401xD STM32F401xE
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
Compatibility with STM32F4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
ARM® Cortex®-M4 with FPU core with embedded Flash and SRAM . . . 15
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 15
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 16
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 18
3.10 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.12 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.14 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.15 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15.3 Regulator ON/OFF and internal power supply supervisor availability . . 25
3.16 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 25
3.17 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.19 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.19.1 Advanced-control timers (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.19.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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3.19.3 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.19.4 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.19.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.20 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.21 Universal synchronous/asynchronous receiver transmitters (USART) . . 29
3.22 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.23 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.24 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.25 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 31
3.26 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 31
3.27 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.28 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.29 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.30 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.31 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4
5
6
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
VCAP1/VCAP2 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Operating conditions at power-up/power-down (regulator ON) . . . . . . . 63
Operating conditions at power-up / power-down (regulator OFF) . . . . . 63
Embedded reset and power control block characteristics . . . . . . . . . . . 64
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Contents
STM32F401xD STM32F401xE
6.3.6
6.3.7
6.3.8
6.3.9
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . . 84
6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 89
6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.22
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
BAT
6.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.24 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 113
6.3.25 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
7.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
7.1.1
WLCSP49, 3.06 x 3.06 mm, 0.4 mm pitch wafer level chip
size package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.1.2
7.1.3
7.1.4
7.1.5
UFQFPN48, 7 x 7 mm, 0.5 mm pitch package . . . . . . . . . . . . . . . . . . 119
LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package . . . . . . . . 122
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package . . . . . . 125
UFBGA100, 7 x 7 mm, 0.5 mm pitch package . . . . . . . . . . . . . . . . . . 128
7.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.2.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
8
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F401xD/xE features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Regulator ON/OFF and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 25
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
STM32F401xD/xE pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
STM32F401xD register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Features depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . . 61
VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 63
Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 63
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 64
Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - V = 1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . 66
DD
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory- V = 1.7 V. . . 67
DD
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory - V = 3.3 V . . 67
DD
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory . . . . . . . . . . . . . . . . 68
Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Typical and maximum current consumptions in Stop mode - V =1.8 V. . . . . . . . . . . . . . 69
DD
Typical and maximum current consumption in Stop mode - V =3.3 V. . . . . . . . . . . . . . . 70
DD
Typical and maximum current consumption in Standby mode - V =1.8 V. . . . . . . . . . . . 70
DD
Typical and maximum current consumption in Standby mode - V =3.3 V. . . . . . . . . . . . 70
DD
Typical and maximum current consumptions in V
mode. . . . . . . . . . . . . . . . . . . . . . . . 71
BAT
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
(1)
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
LSE
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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List of tables
STM32F401xD STM32F401xE
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Flash memory programming with V voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PP
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
EMS characteristics for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
EMI characteristics for WLCSP49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
EMI characteristics for LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SCL frequency (f
= 42 MHz, V = V
= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . 99
PCLK1
DD
DD_I2C
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2
I S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
USB OTG FS electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
ADC accuracy at f
ADC accuracy at f
ADC accuracy at f
= 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
= 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
= 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ADC
ADC
ADC
ADC dynamic accuracy at f
ADC dynamic accuracy at f
= 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 109
= 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 109
ADC
ADC
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
BAT
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
STM32F401xCE WLCSP49 wafer level chip size package mechanical data. . . . . . . . . . 116
WLCSP49 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 118
UFQFPN48, 7 x 7 mm, 0.5 mm pitch, package mechanical data. . . . . . . . . . . . . . . . . . . 119
LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 123
LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 126
UFBGA100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Device order codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 85.
Table 86.
Table 87.
Table 88.
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STM32F401xD/xE block diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 20
PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Startup in regulator OFF: slow V slope -
DD
power-down reset risen after V
/V
stabilization. . . . . . . . . . . . . . . . . . . . . . . . . 24
CAP_1 CAP_2
Figure 9.
Startup in regulator OFF mode: fast V slope -
DD
power-down reset risen before V
/V
stabilization . . . . . . . . . . . . . . . . . . . . . . . 24
CAP_1 CAP_2
Figure 10. STM32F401xD/xE WLCSP49 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. STM32F401xD/xE UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 12. STM32F401xD/xE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13. STM32F401xD/xE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 14. STM32F401xD/xE UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 15. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 16. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 17. Input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 18. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 19. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 20. External capacitor C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
EXT
Figure 21. Typical V
current consumption (LSE and RTC ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
BAT
Figure 22. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 23. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 24. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 25. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 26. ACC
versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
HSI
Figure 27. ACC versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
LSI
Figure 28. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 29. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 30. FT I/O input characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 31. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 32. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2
Figure 33. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 34. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
(1)
Figure 35. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
(1)
Figure 36. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
2
(1)
Figure 37. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
2
(1)
Figure 38. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 39. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 106
Figure 40. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 41. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 42. Power supply and reference decoupling (V
Figure 43. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . 111
). . . . . . . . . . . . . . . . 111
REF+
DDA
connected to V
REF+
DDA
Figure 44. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 45. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 46. WLCSP49 wafer level chip size package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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8
List of figures
STM32F401xD STM32F401xE
Figure 47. WLCSP49 0.4 mm pitch wafer level chip size recommended footprint . . . . . . . . . . . . . . 117
Figure 48. Example of WLCSP49 marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 49. UFQFPN48, 7 x 7 mm, 0.5 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 50. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 51. Example of UFQFPN48 marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 52. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 122
Figure 53. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 54. Example of LQFP64 marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 55. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 125
Figure 56. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 57. Example of LQPF100 marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 58. UFBGA100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 59. Recommended PCB design rules for pads (0.5 mm-pitch BGA) . . . . . . . . . . . . . . . . . . . 129
Figure 60. Example of UFBGA100 marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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STM32F401xD STM32F401xE
Introduction
1
Introduction
This datasheet provides the description of the STM32F401xD/xE line of microcontrollers.
The STM32F401xD/xE datasheet should be read in conjunction with RM0368 reference
manual which is available from the STMicroelectronics website www.st.com. It includes all
information concerning Flash memory programming.
For information on the Cortex -M4 core, please refer to the Cortex -M4 programming
manual (PM0214) available from www.st.com.
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54
Description
STM32F401xD STM32F401xE
2
Description
®
®
The STM32F401XD/XE devices are based on the high-performance ARM Cortex -M4 32-
®
bit RISC core operating at a frequency of up to 84 MHz. Its Cortex -M4 core features a
Floating point unit (FPU) single precision which supports all ARM single-precision data-
processing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
The STM32F401xD/xE incorporate high-speed embedded memories (512 Kbytes of Flash
memory, 96 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals
connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
All devices offer one 12-bit ADC, a low-power RTC, six general-purpose 16-bit timers
including one PWM timer for motor control, two general-purpose 32-bit timers. They also
feature standard and advanced communication interfaces.
2
•
•
•
Up to three I Cs
Up to four SPIs
2
2
Two full duplex I Ss. To achieve audio class accuracy, the I S peripherals can be
clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization.
•
•
•
Three USARTs
SDIO interface
USB 2.0 OTG full speed interface
Refer to for the peripherals available for each part number.
The STM32F401xD/xE operate in the –40 to +105 °C temperature range from a 1.7 (PDR
OFF) to 3.6 V power supply. A comprehensive set of power-saving mode allows the design
of low-power applications.
These features make the STM32F401xD/xE microcontrollers suitable for a wide range of
applications:
•
•
•
•
•
•
•
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Mobile phone sensor hub
Figure 3 shows the general block diagram of the devices.
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STM32F401xD STM32F401xE
Description
Table 2. STM32F401xD/xE features and peripheral counts
Peripherals
STM32F401xD
STM32F401xE
Flash memory in Kbytes
384
512
SRAM in Kbytes
Timers
System
96
7
General-
purpose
Advanced-
control
1
4/2 (full
duplex)
4/2 (full
duplex)
SPI/ I2S
3/2 (full duplex)
3/2 (full duplex)
I2C
3
3
Communication
interfaces
USART
SDIO
-
1
-
1
USB OTG FS
GPIOs
1
1
36
10
50
81
36
10
50
81
12-bit ADC
Number of channels
16
16
Maximum CPU frequency
Operating voltage
84 MHz
1.7 to 3.6 V
Ambient temperatures: –40 to +85 °C/–40 to +105 °C
Junction temperature: –40 to + 125 °C
UFBGA100 WLCSP49
Operating temperatures
Package
WLCSP49
UFBGA100
LQFP100
LQFP64
LQFP64
UFQFPN48
LQFP100 UFQFPN48
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54
Description
STM32F401xD STM32F401xE
2.1
Compatibility with STM32F4 series
The STM32F401xD/xE are fully software and feature compatible with the STM32F4 series
(STM32F42x, STM32F43x, STM32F41x, STM32F405 and STM32F407)
The STM32F401xD/xE can be used as drop-in replacement of the other STM32F4 products
but some slight changes have to be done on the PCB board.
Figure 1. Compatible board design for LQFP100 package
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ꢆꢇ
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5HSODFHGꢈE\ꢈ9&$3ꢁ
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966 9''
966 9''
06ꢀꢁꢂꢃꢄ9ꢅ
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STM32F401xD STM32F401xE
Description
Figure 2. Compatible board design for LQFP64 package
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9''
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9''
9''
966
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9''
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ꢈꢂꢀ 3$ꢁꢉ
ꢂꢅ 3$ꢊ
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ꢂꢉ 3&ꢊ
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ꢀꢄ 3&ꢃ
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DocID025644 Rev 3
13/135
54
7HPSHUDWXUHꢈVHQVRU
Description
STM32F401xD STM32F401xE
Figure 3. STM32F401xD/xE block diagram
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1. The timers connected to APB2 are clocked from TIMxCLK up to 84 MHz, while the timers connected to APB1 are clocked
from TIMxCLK up to 42 MHz.
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DocID025644 Rev 3
STM32F401xD STM32F401xE
Functional overview
3
Functional overview
3.1
ARM® Cortex®-M4 with FPU core with embedded Flash and
SRAM
®
®
The ARM Cortex -M4 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
®
®
The ARM Cortex -M4 with FPU 32-bit RISC processor features exceptional code-
efficiency, delivering the high-performance expected from an ARM core in the memory size
usually associated with 8- and 16-bit devices. The processor supports a set of DSP
instructions which allow efficient signal processing and complex algorithm execution. Its
single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F401xD/xE devices are compatible with all ARM tools and software.
Figure 3 shows the general block diagram of the STM32F401xD/xE.
®
®
Note:
Cortex -M4 with FPU is binary compatible with Cortex -M3.
3.2
Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
®
®
®
standard ARM Cortex -M4 with FPU processors. It balances the inherent performance
®
advantage of the ARM Cortex -M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 105 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 84 MHz.
3.3
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
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54
Functional overview
STM32F401xD STM32F401xE
3.4
3.5
Embedded Flash memory
The devices embed 512 Kbytes of Flash memory available for storing programs and data.
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
3.6
3.7
Embedded SRAM
All devices embed:
•
96 Kbytes of system SRAM which can be accessed (read/write) at CPU clock speed
with 0 wait states
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.
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DocID025644 Rev 3
STM32F401xD STM32F401xE
Functional overview
Figure 4. Multi-AHB matrix
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3.8
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
2
•
•
•
•
•
•
SPI and I S
2
I C
USART
General-purpose, basic and advanced-control timers TIMx
SD/SDIO/MMC host interface
ADC
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Functional overview
STM32F401xD STM32F401xE
3.9
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the
®
Cortex -M4 with FPU.
•
•
•
•
•
•
•
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.10
3.11
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 21 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 81 GPIOs can be connected
to the 16 external interrupt lines.
Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The
application can then select as system clock either the RC oscillator or an external 4-26 MHz
clock source. This clock can be monitored for failure. If a failure is detected, the system
automatically switches back to the internal RC oscillator and a software interrupt is
generated (if enabled). This clock source is input to a PLL thus allowing to increase the
frequency up to 84 MHz. Similarly, full interrupt management of the PLL clock entry is
available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 84 MHz while the maximum frequency of the high-speed APB domains is 84 MHz.
The maximum allowed frequency of the low-speed APB domain is 42 MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
2
performance. In this case, the I S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
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STM32F401xD STM32F401xE
Functional overview
3.12
Boot modes
At startup, boot pins are used to select one out of three boot options:
•
•
•
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using either USART1(PA9/10), USART2(PD5/6), USB OTG FS in device mode (PA11/12)
through DFU (device firmware upgrade), I2C1(PB6/7), I2C2(PB10/3), I2C3(PA8/PB4),
SPI1(PA4/5/6/7), SPI2(PB12/13/14/15) or SPI3(PA15, PC10/11/12).
For more detailed information on the bootloader, refer to Application Note: AN2606,
STM32™ microcontroller system memory boot mode.
3.13
Power supply schemes
•
V
= 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor
DD
(POR/PDR) disabled, provided externally through V pins. Requires the use of an
DD
external power supply supervisor connected to the VDD and PDR_ON pins.
•
•
V
= 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when
DD
enabled), provided externally through V pins.
DD
V
, V
= 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
SSA DDA
and PLL. V
and V
must be connected to V and V , respectively, with
SSA DD SS
DDA
decoupling technique.
V = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
BAT
•
backup registers (through power switch) when V is not present.
DD
Refer to Figure 18: Power supply scheme for more details.
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54
Functional overview
STM32F401xD STM32F401xE
3.14
Power supply supervisor
3.14.1
Internal reset ON
This feature is available for V operating voltage range 1.8 V to 3.6 V.
DD
The internal power supply supervisor is enabled by holding PDR_ON high.
The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes.
The device remains in reset mode when V is below a specified threshold, V
or
POR/PDR
DD
V
, without the need for an external reset circuit.
BOR
The device also features an embedded programmable voltage detector (PVD) that monitors
the V /V power supply and compares it to the V threshold. An interrupt can be
DD DDA
PVD
generated when V /V
drops below the V
threshold and/or when V /V
is
DD DDA
PVD
DD DDA
higher than the V
threshold. The interrupt service routine can then generate a warning
PVD
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.14.2
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to
low.
An external power supply supervisor should monitor V and should maintain the device in
DD
reset mode as long as V is below a specified threshold. PDR_ON should be connected to
DD
this external power supply supervisor. Refer to Figure 5: Power supply supervisor
interconnection with internal reset OFF.
(1)
Figure 5. Power supply supervisor interconnection with internal reset OFF
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1. The PRD_ON pin is only available in the WLCSP49 and UFBGA100 packages.
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STM32F401xD STM32F401xE
Functional overview
The V specified threshold, below which the device must be maintained under reset, is
DD
1.7 V (see Figure 6).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no longer supported:
•
•
•
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
The brownout reset (BOR) circuitry must be disabled.
The embedded programmable voltage detector (PVD) is disabled.
V
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.
BAT
DD
Figure 6. PDR_ON control with internal reset OFF
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3.15
Voltage regulator
The regulator has four operating modes:
•
Regulator ON
–
–
–
Main regulator mode (MR)
Low power regulator (LPR)
Power-down
•
Regulator OFF
3.15.1
Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
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54
Functional overview
STM32F401xD STM32F401xE
There are three power modes configured by software when the regulator is ON:
•
MR is used in the nominal regulation mode (With different voltage scaling in Run)
In Main regulator mode (MR mode), different voltage scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
•
•
LPR is used in the Stop modes
The LP regulator mode is configured by software when entering Stop mode.
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Depending on the package, one or two external ceramic capacitors should be connected on
the V and V pins. The V pin is only available for the LQFP100 and
CAP_1
CAP_2
CAP_2
UFBGA100 packages.
All packages have the regulator ON feature.
3.15.2
Regulator OFF
The Regulator OFF is available only on the UFBGA100, which features the BYPASS_REG
pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode
allows to supply externally a V12 voltage source through V
and V
pins.
CAP_1
CAP_2
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. Refer to Table 14: General operating
conditions.
The two 2.2 µF V
ceramic capacitors should be replaced by two 100 nF decoupling
CAP
capacitors. Refer to Figure 18: Power supply scheme.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
•
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
•
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
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DocID025644 Rev 3
STM32F401xD STM32F401xE
Functional overview
Figure 7. Regulator OFF
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The following conditions must be respected:
•
V
should always be higher than V
and V
to avoid current injection
CAP_2
DD
CAP_1
between power domains.
•
If the time for V and V
to reach V minimum value is faster than the time for
CAP_1
CAP_2
12
V
to reach 1.7 V, then PA0 should be kept low to cover both conditions: until V
DD
CAP_1
and V
reach V minimum value and until V reaches 1.7 V (see Figure 8).
12 DD
CAP_2
•
•
Otherwise, if the time for V
and V
to reach V minimum value is slower
CAP_2 12
CAP_1
than the time for V to reach 1.7 V, then PA0 could be asserted low externally (see
DD
Figure 9).
If V
and V
go below V minimum value and V is higher than 1.7 V, then a
CAP_2 12 DD
CAP_1
reset must be asserted on PA0 pin.
Note:
The minimum value of V depends on the maximum frequency targeted in the application
12
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54
Functional overview
STM32F401xD STM32F401xE
Figure 8. Startup in regulator OFF: slow V slope -
DD
power-down reset risen after V
/V
stabilization
CAP_1 CAP_2
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0LQꢈ9ꢁꢅ
WLPH
1567
WLPH
06Yꢀꢁꢁꢄꢊ9ꢁ
1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 9. Startup in regulator OFF mode: fast V slope -
DD
power-down reset risen before V
/V
stabilization
CAP_1 CAP_2
9''
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9ꢁꢅ
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06Yꢀꢁꢁꢇꢉ9ꢁ
1. This figure is valid whatever the internal reset mode (ON or OFF).
24/135
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STM32F401xD STM32F401xE
Functional overview
3.15.3
Regulator ON/OFF and internal power supply supervisor availability
Table 3. Regulator ON/OFF and internal power supply supervisor availability
Power supply
supervisor ON
Power supply
supervisor OFF
Package
Regulator ON
Regulator OFF
UFQFPN48
WLCSP49
Yes
No
Yes
No
Yes
Yes
Yes
No
PDR_ON external
PDR_ON set to VDD
control(1)
LQFP64
Yes
Yes
Yes
No
No
Yes
Yes
No
No
LQFP100
Yes
Yes
Yes
UFBGA100
BYPASS_REG set to BYPASS_REG set to
VSS VDD
PDR_ON external
PDR_ON set to VDD
control (1)
1. Refer to Section 3.14: Power supply supervisor
3.16
Real-time clock (RTC) and backup registers
The backup domain includes:
•
•
The real-time clock (RTC)
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC features a reference clock detection, a more precise
second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC
provides a programmable alarm and programmable periodic interrupts with wakeup from
Stop and Standby modes. The sub-seconds value is also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when V power is not present. Backup registers are not reset by a system, a power reset,
DD
or when the device wakes up from the Standby mode (see Section 3.17: Low-power
modes).
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
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Functional overview
STM32F401xD STM32F401xE
The RTC and backup registers are supplied through a switch that is powered either from the
supply when present or from the V pin.
V
DD
BAT
3.17
Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
•
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm/ wakeup/
tamper/ time stamp events).
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm/ wakeup/ tamper/time stamp event
occurs.
Standby mode is not supported when the embedded voltage regulator is bypassed and
the 1.2 V domain is controlled by an external power.
3.18
VBAT operation
The VBAT pin allows to power the device V
domain from an external battery, an external
BAT
super-capacitor, or from V when no external battery and an external super-capacitor are
DD
present.
V
operation is activated when V is not present.
DD
BAT
The VBAT pin supplies the RTC and the backup registers.
Note:
When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from V
operation. When PDR_ON pin is not connected to V (internal
BAT
DD
Reset OFF), the V
functionality is no more available and VBAT pin should be connected
BAT
to V
.
DD
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Functional overview
3.19
Timers and watchdogs
The devices embed one advanced-control timer, seven general-purpose timers and two
watchdog timers.
All timer counters can be frozen in debug mode.
Table 4 compares the features of the advanced-control and general-purpose timers.
Table 4. Timer feature comparison
Max.
Max.
DMA
request
generation channels
Capture/
compare
Timer
type
Counter Counter Prescaler
Complementary interface timer
Timer
resolution
type
factor
output
clock
(MHz) (MHz)
clock
Any
Up,
integer
Advanced-
control
TIM1
16-bit
Down, between1
Up/down
Yes
Yes
Yes
No
4
4
4
2
1
Yes
84
42
42
84
84
84
84
84
84
84
and
65536
Any
integer
Down, between1
Up,
TIM2,
TIM5
32-bit
16-bit
16-bit
16-bit
No
No
No
No
Up/down
and
65536
Any
integer
Down, between1
Up,
TIM3,
TIM4
Up/down
and
65536
General
purpose
Any
integer
between1
and
TIM9
Up
65536
Any
integer
between1
and
TIM1
0,
TIM11
Up
No
65536
3.19.1
Advanced-control timers (TIM1)
The advanced-control timer (TIM1) can be seen as three-phase PWM generators
multiplexed on 4 independent channels. It has complementary PWM outputs with
programmable inserted dead times. It can also be considered as a complete general-
purpose timer. Its 4 independent channels can be used for:
•
•
•
•
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
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STM32F401xD STM32F401xE
If configured as standard 16-bit timers, it has the same features as the general-purpose
TIMx timers. If configured as a 16-bit PWM generator, it has full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 supports independent DMA request generation.
3.19.2
General-purpose timers (TIMx)
There are seven synchronizable general-purpose timers embedded in the
STM32F401xD/xE (see Table 4 for differences).
•
TIM2, TIM3, TIM4, TIM5
The STM32F401xD/xE devices are 4 full-featured general-purpose timers: TIM2, TIM5,
TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-
bit auto-reload up/downcounter and a 16-bit prescaler. They all feature four
independent channels for input capture/output compare, PWM or one-pulse mode
output. This gives up to 15 input capture/output compare/PWMs.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•
TIM9, TIM10 and TIM11
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10 and TIM11 feature one independent channel, whereas TIM9 has two
independent channels for input capture/output compare, PWM or one-pulse mode
output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured
general-purpose timers. They can also be used as simple time bases.
3.19.3
3.19.4
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
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Functional overview
3.19.5
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
•
•
•
•
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
3.20
Inter-integrated circuit interface (I2C)
2
Up to three I C bus interfaces can operate in multimaster and slave modes. They can
support the standard (up to 100 kHz) and fast (up to 400 kHz) modes. The I2C bus
frequency can be increased up to 1 MHz. For more details about the complete solution,
please contact your local ST sales representative.They also support the 7/10-bit addressing
mode and the 7-bit dual addressing mode (as slave). A hardware CRC
generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 5).
Table 5. Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
≥ 50 ns
Programmable length from 1 to 15 I2C peripheral clocks
3.21
Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed three universal synchronous/asynchronous receiver transmitters
(USART1, USART2 and USART6).
These three interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
communicate at speeds of up to 10.5 Mbit/s. The USART2 interface communicates at up to
5.25 bit/s.
USART1 and USART2 also provide hardware management of the CTS and RTS signals,
Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All
interfaces can be served by the DMA controller.
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STM32F401xD STM32F401xE
Table 6. USART feature comparison
Max. baud
Max. baud
Smartcard rate in Mbit/s rate in Mbit/s
USART Standard Modem
SPI
master
APB
(ISO 7816) (oversampling (oversampling mapping
LIN
irDA
name
features (RTS/CTS)
by 16)
by 8)
APB2
(max.
84 MHz)
USART1
USART2
USART6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
5.25
10.5
APB1
(max.
42 MHz)
2.62
5.25
5.25
10.5
APB2
(max.
N.A
84 MHz)
3.22
3.23
3.24
Serial peripheral interface (SPI)
The devices feature up to four SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1 and SPI4 can communicate at up to 42 Mbit/s, SPI2 and SPI3
can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies
and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification
supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.
Inter-integrated sound (I2S)
2
Two standard I S interfaces (multiplexed with SPI2 and SPI3) are available. They can be
operated in master or slave mode, in full duplex and simplex communication modes and
can be configured to operate with a 16-/32-bit resolution as an input or output channel.
Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of
2
the I S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
2
All I Sx can be served by the DMA controller.
Audio PLL (PLLI2S)
2
The devices feature an additional dedicated PLL for audio I S application. It allows to
2
achieve error-free I S sampling clock accuracy without compromising on the CPU
performance.
2
The PLLI2S configuration can be modified to manage an I S sample rate change without
disabling the main PLL (PLL) used for the CPU.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 kHz to 192 kHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S
flow with an external PLL (or Codec output).
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Functional overview
3.25
Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
3.26
Universal serial bus on-the-go full-speed (OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The major features are:
•
•
•
•
•
•
Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
4 bidirectional endpoints
8 host channels with periodic OUT support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.27
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 84 MHz.
3.28
Analog-to-digital converter (ADC)
One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels,
performing conversions in the single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
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Functional overview
STM32F401xD STM32F401xE
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4 or TIM5 timer.
3.29
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value. Refer to the reference manual for additional information.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
3.30
3.31
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
Embedded Trace Macrocell™
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F401xD/xE through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using any high-speed
channel available. Real-time instruction and data flow activity can be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
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Pinouts and pin description
4
Pinouts and pin description
Figure 10. STM32F401xD/xE WLCSP49 pinout
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1. The above figure shows the package bump side.
DocID025644 Rev 3
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54
Pinouts and pin description
STM32F401xD STM32F401xE
Figure 11. STM32F401xD/xE UFQFPN48 pinout
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1. The above figure shows the package top view.
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STM32F401xD STM32F401xE
Pinouts and pin description
Figure 12. STM32F401xD/xE LQFP64 pinout
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DocID025644 Rev 3
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54
Pinouts and pin description
STM32F401xD STM32F401xE
Figure 13. STM32F401xD/xE LQFP100 pinout
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1. The above figure shows the package top view.
36/135
DocID025644 Rev 3
STM32F401xD STM32F401xE
Pinouts and pin description
Figure 14. STM32F401xD/xE UFBGA100 pinout
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1. This figure shows the package top view
DocID025644 Rev 3
37/135
54
Pinouts and pin description
STM32F401xD STM32F401xE
Table 7. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
FT
B
Input/ output pin
5 V tolerant I/O
Dedicated BOOT0 pin
I/O structure
Notes
NRST
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Functions selected through GPIOx_AFR registers
Alternate
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
Table 8. STM32F401xD/xE pin definitions
Pin Number
Pin name
Additional
functions
(function
Alternate functions
after reset)(1)
SPI4_SCK, TRACECLK,
EVENTOUT
-
-
-
-
-
-
-
-
-
1
2
3
B2
A1
B1
PE2
PE3
PE4
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
TRACED0, EVENTOUT
SPI4_NSS, TRACED1,
EVENTOUT
SPI4_MISO, TIM9_CH1,
TRACED2, EVENTOUT
-
-
-
-
-
-
4
5
C2
D2
PE5
PE6
I/O FT
I/O FT
-
-
-
-
SPI4_MOSI, TIM9_CH2,
TRACED3, EVENTOUT
-
-
-
-
-
-
-
-
D3
C4
E2
VSS
VDD
VBAT
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
1
B7
1
6
RTC_TAMP1,
RTC_OUT, RTC_TS
(2) (3)
2
D5
2
7
C1
PC13
I/O FT
EVENTOUT,
38/135
DocID025644 Rev 3
STM32F401xD STM32F401xE
Pinouts and pin description
Table 8. STM32F401xD/xE pin definitions (continued)
Pin Number
Pin name
(function
Additional
functions
Alternate functions
after reset)(1)
PC14-
OSC32_IN
(PC14)
(2) (3)
(4)
3
4
C7
C6
3
4
8
9
D1
I/O FT
EVENTOUT
EVENTOUT
OSC32_IN
PC15-
(2) (3)
(4)
E1 OSC32_OUT I/O FT
(PC15)
OSC32_OUT
-
-
-
-
-
-
10 F2
11 G2
VSS
VDD
S
S
-
-
-
-
-
-
-
-
PH0-OSC_IN
(PH0)
(4)
5
6
D7
D6
5
6
12 F1
13 G1
I/O FT
I/O FT
EVENTOUT
EVENTOUT
OSC_IN
PH1-
OSC_OUT
(PH1)
(4)
OSC_OUT
7
-
E7
7
8
9
14 H2
15 H1
16 J2
NRST
PC0
I/O FT
I/O FT
I/O FT
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
-
ADC1_IN10
ADC1_IN11
-
-
-
PC1
SPI2_MISO, I2S2ext_SD,
EVENTOUT
-
-
-
10 17 J3
11 18 K2
PC2
PC3
I/O FT
I/O FT
-
-
ADC1_IN12
ADC1_IN13
SPI2_MOSI/I2S2_SD,
EVENTOUT
-
-
-
8
-
-
19
-
-
VDD
VSSA/VREF-
VSSA
S
S
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E6 12 20
-
-
-
-
-
-
-
J1
K1
-
-
VREF-
9
-
-
13
-
VDDA/VREF+
VREF+
-
21 L1
22 M1
-
F7
-
VDDA
USART2_CTS,
TIM2_CH1/TIM2_ETR,
TIM5_CH1, EVENTOUT
(5)
10 F6 14 23 L2
11 G7 15 24 M2
12 E5 16 25 K3
PA0
PA1
PA2
I/O FT
I/O FT
I/O FT
ADC1_IN0, WKUP
ADC1_IN1
USART2_RTS, TIM2_CH2,
TIM5_CH2, EVENTOUT
-
-
USART2_TX, TIM2_CH3,
TIM5_CH3, TIM9_CH1,
EVENTOUT
ADC1_IN2
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54
Pinouts and pin description
STM32F401xD STM32F401xE
Table 8. STM32F401xD/xE pin definitions (continued)
Pin Number
Pin name
(function
Additional
functions
Alternate functions
after reset)(1)
USART2_RX, TIM2_CH4,
TIM5_CH4, TIM9_CH2,
EVENTOUT
13 E4 17 26 L3
PA3
I/O FT
-
ADC1_IN3
-
-
-
-
18 27
19 28
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
BYPASS_
REG
-
-
-
-
E3
I
FT
-
-
-
-
SPI1_NSS,
14 G6 20 29 M3
15 F5 21 30 K4
PA4
PA5
I/O FT
I/O FT
SPI3_NSS/I2S3_WS,
USART2_CK, EVENTOUT
ADC1_IN4
SPI1_SCK,
-
TIM2_CH1/TIM2_ETR,
EVENTOUT
ADC1_IN5
SPI1_MISO, TIM1_BKIN,
TIM3_CH1, EVENTOUT
16 F4 22 31 L4
17 F3 23 32 M4
PA6
PA7
I/O FT
I/O FT
-
-
ADC1_IN6
ADC1_IN7
SPI1_MOSI, TIM1_CH1N,
TIM3_CH2, EVENTOUT
-
-
-
-
24 33 K5
25 34 L5
PC4
PC5
I/O FT
I/O FT
-
-
EVENTOUT
EVENTOUT
ADC1_IN14
ADC1_IN15
TIM1_CH2N, TIM3_CH3,
EVENTOUT
18 G5 26 35 M5
PB0
PB1
I/O FT
I/O FT
-
-
ADC1_IN8
ADC1_IN9
TIM1_CH3N, TIM3_CH4,
EVENTOUT
19 G4 27 36 M6
20 G3 28 37 L6
PB2
PE7
PE8
PE9
PE10
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
-
EVENTOUT
BOOT1
-
-
-
-
-
-
-
-
-
-
-
-
38 M7
39 L7
40 M8
41 L8
TIM1_ETR, EVENTOUT
TIM1_CH1N, EVENTOUT
TIM1_CH1, EVENTOUT
TIM1_CH2N, EVENTOUT
-
-
-
-
SPI4_NSS, TIM1_CH2,
EVENTOUT
-
-
-
-
-
-
-
-
-
42 M9
43 L9
44 M10
PE11
PE12
PE13
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
SPI4_SCK, TIM1_CH3N,
EVENTOUT
SPI4_MISO, TIM1_CH3,
EVENTOUT
40/135
DocID025644 Rev 3
STM32F401xD STM32F401xE
Pinouts and pin description
Table 8. STM32F401xD/xE pin definitions (continued)
Pin Number
Pin name
(function
Additional
functions
Alternate functions
after reset)(1)
SPI4_MOSI, TIM1_CH4,
EVENTOUT
-
-
-
-
-
-
45 M11
46 M12
PE14
PE15
I/O FT
I/O FT
-
-
-
-
TIM1_BKIN, EVENTOUT
SPI2_SCK/I2S2_CK,
I2C2_SCL, TIM2_CH3,
EVENTOUT
21 E3 29 47 L10
PB10
I/O FT
I/O FT
-
-
-
-
-
-
K9
PB11
VCAP1
VSS
-
-
-
-
EVENTOUT
-
-
-
-
22 G2 30 48 L11
23 D3 31 49 F12
24 F2 32 50 G12
S
S
S
-
-
-
-
-
-
VDD
SPI2_NSS/I2S2_WS,
I2C2_SMBA, TIM1_BKIN,
EVENTOUT
25 E2 33 51 L12
PB12
I/O FT
-
-
SPI2_SCK/I2S2_CK,
TIM1_CH1N, EVENTOUT
26 G1 34 52 K12
27 F1 35 53 K11
28 E1 36 54 K10
PB13
PB14
PB15
I/O FT
I/O FT
I/O FT
-
-
-
-
SPI2_MISO, I2S2ext_SD,
TIM1_CH2N, EVENTOUT
-
SPI2_MOSI/I2S2_SD,
TIM1_CH3N, EVENTOUT
RTC_REFIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
55
-
PD8
PD9
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
-
-
EVENTOUT
-
-
-
-
-
-
-
-
56 K8
57 J12
58 J11
59 J10
60 H12
61 H11
62 H10
EVENTOUT
PD10
PD11
PD12
PD13
PD14
PD15
EVENTOUT
EVENTOUT
TIM4_CH1, EVENTOUT
TIM4_CH2, EVENTOUT
TIM4_CH3, EVENTOUT
TIM4_CH4, EVENTOUT
I2S2_MCK, USART6_TX,
TIM3_CH1, SDIO_D6,
EVENTOUT
-
-
-
-
37 63 E12
38 64 E11
PC6
PC7
I/O FT
I/O FT
-
-
-
-
I2S3_MCK, USART6_RX,
TIM3_CH2, SDIO_D7,
EVENTOUT
DocID025644 Rev 3
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54
Pinouts and pin description
STM32F401xD STM32F401xE
Table 8. STM32F401xD/xE pin definitions (continued)
Pin Number
Pin name
(function
Additional
functions
Alternate functions
after reset)(1)
USART6_CK, TIM3_CH3,
SDIO_D0, EVENTOUT
-
-
-
-
39 65 E10
PC8
PC9
I/O FT
I/O FT
-
-
-
-
I2S_CKIN, I2C3_SDA,
TIM3_CH4, SDIO_D1,
MCO_2, EVENTOUT
40 66 D12
I2C3_SCL, USART1_CK,
TIM1_CH1, OTG_FS_SOF,
MCO_1, EVENTOUT
29 D1 41 67 D11
PA8
I/O FT
-
-
I2C3_SMBA, USART1_TX,
TIM1_CH2, EVENTOUT
30 D2 42 68 D10
31 C2 43 69 C12
PA9
I/O FT
I/O FT
-
-
OTG_FS_VBUS
-
USART1_RX, TIM1_CH3,
OTG_FS_ID, EVENTOUT
PA10
USART1_CTS, USART6_TX,
TIM1_CH4, OTG_FS_DM,
EVENTOUT
32 C1 44 70 B12
PA11
PA12
I/O FT
-
-
USART1_RTS, USART6_RX,
TIM1_ETR, OTG_FS_DP,
EVENTOUT
33 C3 45 71 A12
34 B3 46 72 A11
I/O FT
I/O FT
-
-
-
-
PA13 (JTMS-
SWDIO)
JTMS-SWDIO, EVENTOUT
-
-
-
73 C11
VCAP2
VSS
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
35 B1 47 74 F11
36
-
-
48 75 G11
VDD
B2
-
-
-
VDD
PA14 (JTCK-
SWCLK)
37 A1 49 76 A10
I/O FT
-
JTCK-SWCLK, EVENTOUT
-
JTDI, SPI1_NSS,
SPI3_NSS/I2S3_WS,
TIM2_CH1/TIM2_ETR, JTDI,
EVENTOUT
38 A2 50 77 A9
PA15 (JTDI) I/O FT
-
-
SPI3_SCK/I2S3_CK,
SDIO_D2, EVENTOUT
-
-
-
-
51 78 B11
52 79 C10
53 80 B10
PC10
PC11
I/O FT
I/O FT
-
-
-
-
I2S3ext_SD, SPI3_MISO,
SDIO_D3, EVENTOUT
SPI3_MOSI/I2S3_SD,
SDIO_CK, EVENTOUT
-
-
-
-
PC12
PD0
I/O FT
I/O FT
-
-
-
-
-
81 C9
EVENTOUT
42/135
DocID025644 Rev 3
STM32F401xD STM32F401xE
Pinouts and pin description
Table 8. STM32F401xD/xE pin definitions (continued)
Pin Number
Pin name
(function
Additional
functions
Alternate functions
after reset)(1)
-
-
-
-
-
82 B9
PD1
PD2
I/O FT
I/O FT
-
-
EVENTOUT
-
-
TIM3_ETR, SDIO_CMD,
EVENTOUT
54 83 C8
SPI2_SCK/I2S2_CK,
USART2_CTS, EVENTOUT
-
-
-
84 B8
PD3
I/O FT
-
-
-
-
-
-
-
-
85 B7
86 A6
PD4
PD5
I/O FT
I/O FT
-
-
USART2_RTS, EVENTOUT
USART2_TX, EVENTOUT
-
-
SPI3_MOSI/I2S3_SD,
USART2_RX, EVENTOUT
-
-
-
-
-
-
87 B6
88 A5
PD6
PD7
I/O FT
I/O FT
-
-
-
-
USART2_CK, EVENTOUT
JTDO-SWO, SPI1_SCK,
SPI3_SCK/I2S3_CK,
I2C2_SDA, TIM2_CH2,
EVENTOUT
PB3
39 A3 55 89 A8
I/O FT
I/O FT
I/O FT
-
-
-
-
(JTDO-SWO)
NJTRST, SPI1_MISO,
SPI3_MISO, I2S3ext_SD,
I2C3_SDA, TIM3_CH1,
EVENTOUT
PB4
(NJTRST)
40 A4 56 90 A7
SPI1_MOSI,
SPI3_MOSI/I2S3_SD,
I2C1_SMBA, TIM3_CH2,
EVENTOUT
41 B4 57 91 C5
42 C4 58 92 B5
PB5
PB6
-
-
-
-
I2C1_SCL, USART1_TX,
TIM4_CH1, EVENTOUT
I/O FT
I/O FT
I2C1_SDA, USART1_RX,
TIM4_CH2, EVENTOUT
43 D4 59 93 B4
44 A5 60 94 A4
PB7
-
-
-
BOOT0
I
B
-
VPP
I2C1_SCL, TIM4_CH3,
TIM10_CH1, SDIO_D4,
EVENTOUT
45 B5 61 95 A3
46 C5 62 96 B3
PB8
PB9
I/O FT
I/O FT
-
-
-
-
SPI2_NSS/I2S2_WS,
I2C1_SDA, TIM4_CH4,
TIM11_CH1, SDIO_D5,
EVENTOUT
-
-
-
-
-
-
97 C3
98 A2
PE0
PE1
I/O FT
I/O FT
-
-
TIM4_ETR, EVENTOUT
EVENTOUT
-
-
DocID025644 Rev 3
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54
Pinouts and pin description
STM32F401xD STM32F401xE
Table 8. STM32F401xD/xE pin definitions (continued)
Pin Number
Pin name
(function
Additional
functions
Alternate functions
after reset)(1)
47 A6 63 99
-
H3
-
VSS
PDR_ON
VDD
S
I
-
FT
-
-
-
-
-
-
-
-
-
-
-
B6
-
-
48 A7 64 100
S
1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F401xx reference manual.
4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
5. If the device is delivered in an UFBGA100 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode),
then PA0 is used as an internal Reset (active low)
44/135
DocID025644 Rev 3
Table 9. Alternate function mapping
AF00
AF01
AF02
AF03
AF04
AF05
AF06
AF07
AF08
AF09
AF10
AF11
AF12 AF13 AF14 AF15
Port
TIM9/
TIM10/
TIM11
SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4
SPI3/I2S3/
USART1/ USART6
USART2
TIM3/
TIM4/ TIM5
I2C1/I2C2/
I2C3
SPI2/I2S2/
SPI3/ I2S3
I2C2/
I2C3
SYS_AF
TIM1/TIM2
OTG1_FS
SDIO
TIM2_CH1/
TIM2_ETR
USART2_
CTS
EVENT
OUT
PA0
-
TIM5_CH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART2_
RTS
EVENT
OUT
PA1
PA2
-
TIM2_CH2 TIM5_CH2
-
-
USART2_
EVENT
OUT
-
TIM2_CH3 TIM5_CH3 TIM9_CH1
TIM2_CH4 TIM5_CH4 TIM9_CH2
-
-
TX
USART2_
EVENT
OUT
PA3
-
-
-
RX
SPI3_NSS/
I2S3_WS
USART2_
EVENT
OUT
PA4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI1_NSS
SPI1_SCK
-
CK
TIM2_CH1/
TIM2_ETR
EVENT
OUT
PA5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI1_
MISO
EVENT
OUT
PA6
-
TIM1_BKIN TIM3_CH1
TIM1_CH1N TIM3_CH2
-
SPI1_
MOSI
-
-
-
-
-
-
EVENT
OUT
PA7
-
-
USART1_
CK
OTG_FS_
SOF
EVENT
OUT
PA8
MCO_1
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH4
TIM1_ETR
-
-
-
-
-
-
-
-
-
I2C3_SCL
-
I2C3_
SMBA
USART1_
TX
OTG_FS_
VBUS
EVENT
OUT
PA9
-
-
-
-
-
-
-
-
-
-
-
-
--
-
-
-
-
-
-
-
-
USART1_
RX
OTG_FS_I
D
EVENT
OUT
PA10
PA11
PA12
PA13
PA14
PA15
-
-
-
-
-
-
-
USART1_ USART6_
CTS TX
OTG_FS_
DM
EVENT
OUT
-
-
USART1_ USART6_
RTS
OTG_FS_
DP
EVENT
OUT
-
-
RX
JTMS_
SWDIO
EVENT
OUT
-
-
-
-
-
-
-
JTCK_
SWCLK
EVENT
OUT
-
-
-
-
-
-
-
TIM2_CH1/
TIM2_ETR
SPI3_NSS/
I2S3_WS
EVENT
OUT
JTDI
SPI1_NSS
-
Table 9. Alternate function mapping (continued)
AF00
AF01
AF02
AF03
AF04
AF05
AF06
AF07
AF08
AF09
AF10
AF11
AF12 AF13 AF14 AF15
Port
TIM9/
TIM10/
TIM11
SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4
SPI3/I2S3/
USART1/ USART6
USART2
TIM3/
TIM4/ TIM5
I2C1/I2C2/
I2C3
SPI2/I2S2/
SPI3/ I2S3
I2C2/
I2C3
SYS_AF
TIM1/TIM2
OTG1_FS
SDIO
EVENT
OUT
PB0
-
-
-
TIM1_CH2N TIM3_CH3
TIM1_CH3N TIM3_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PB1
PB2
-
-
EVENT
OUT
-
-
-
-
JTDO-
SWO
SPI3_SCK/
I2S3_CK
EVENT
OUT
PB3
TIM2_CH2
-
SPI1_SCK
I2C2_SDA
SPI1_
MISO
I2S3ext_S
D
EVENT
OUT
PB4
JTRST
-
TIM3_CH1
TIM3_CH2
TIM4_CH1
TIM4_CH2
SPI3_MISO
I2C3_SDA
I2C1_
SMBA
SPI1
_MOSI
SPI3_MOSI/
I2S3_SD
EVENT
OUT
PB5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART1_
TX
EVENT
OUT
PB6
-
I2C1_SCL
I2C1_SDA
-
-
-
-
-
-
-
-
-
-
USART1_
RX
EVENT
OUT
PB7
-
SDIO_
D4
EVENT
OUT
PB8
-
TIM4_CH3 TIM10_CH1 I2C1_SCL
TIM4_CH4 TIM11_CH1 I2C1_SDA
-
-
-
-
-
-
-
SPI2_NSS/I
2S2_WS
SDIO_
D5
EVENT
OUT
PB9
-
SPI2_SCK/I
2S2_CK
EVENT
OUT
PB10
PB12
PB13
PB14
PB15
TIM2_CH3
TIM1_BKIN
TIM1_CH1N
TIM1_CH2N
TIM1_CH3N
-
-
-
-
-
-
-
-
-
-
I2C2_SCL
-
-
-
-
-
I2C2_
SMBA
SPI2_NSS/I
2S2_WS
EVENT
OUT
SPI2_SCK/I
2S2_CK
EVENT
OUT
-
-
-
EVENT
OUT
SPI2_MISO I2S2ext_SD
RTC_
REFN
SPI2_MOSI
-
EVENT
OUT
/I2S2_SD
Table 9. Alternate function mapping (continued)
AF00
AF01
AF02
AF03
AF04
AF05
AF06
AF07
AF08
AF09
AF10
AF11
AF12 AF13 AF14 AF15
Port
TIM9/
TIM10/
TIM11
SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4
SPI3/I2S3/
USART1/ USART6
USART2
TIM3/
TIM4/ TIM5
I2C1/I2C2/
I2C3
SPI2/I2S2/
SPI3/ I2S3
I2C2/
I2C3
SYS_AF
TIM1/TIM2
OTG1_FS
SDIO
EVENT
OUT
PC0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PC1
PC2
-
-
-
-
SPI2_
MISO
EVENT
OUT
-
-
-
-
I2S2ext_SD
SPI2_MOSI
/I2S2_SD
EVENT
OUT
PC3
-
-
-
-
-
EVENT
OUT
PC4
-
-
-
-
-
-
EVENT
OUT
PC5
-
-
-
-
-
-
USART6_
TX
SDIO_
D6
EVENT
OUT
PC6
-
--
TIM3_CH1
-
I2S2_MCK
-
USART6_
RX
SDIO_
D7
EVENT
OUT
PC7
-
TIM3_CH2
-
-
I2S3_MCK
USART6_
CK
SDIO_
D0
EVENT
OUT
PC8
-
-
-
-
-
-
-
-
-
TIM3_CH3
-
-
-
-
SDIO_
D1
EVENT
OUT
PC9
MCO_2
TIM3_CH4
I2C3_SDA
I2S_CKIN
-
-
-
-
-
-
-
-
SPI3_SCK/
I2S3_CK
SDIO_
D2
EVENT
OUT
PC10
PC11
PC12
PC13
PC14
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2S3ext_
SD
SDIO_
D3
EVENT
OUT
SPI3_MISO
SPI3_MOSI/
I2S3_SD
SDIO_
CK
EVENT
OUT
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
EVENT
OUT
EVENT
OUT
Table 9. Alternate function mapping (continued)
AF00
AF01
AF02
AF03
AF04
AF05
AF06
AF07
AF08
AF09
AF10
AF11
AF12 AF13 AF14 AF15
Port
TIM9/
TIM10/
TIM11
SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4
SPI3/I2S3/
USART1/ USART6
USART2
TIM3/
TIM4/ TIM5
I2C1/I2C2/
I2C3
SPI2/I2S2/
SPI3/ I2S3
I2C2/
I2C3
SYS_AF
TIM1/TIM2
OTG1_FS
SDIO
EVENT
OUT
PD0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PD1
PD2
-
SDIO_
CMD
EVENT
OUT
TIM3_ETR
-
SPI2_SCK/
I2S2_CK
USART2_
CTS
EVENT
OUT
PD3
-
--
-
-
-
-
-
-
-
-
-
-
-
-
-
USART2_
RTS
EVENT
OUT
PD4
-
-
-
USART2_
TX
EVENT
OUT
PD5
-
-
-
-
-
-
-
-
-
-
-
-
SPI3_MOSI
/I2S3_SD
USART2_
RX
EVENT
OUT
PD6
-
USART2_
CK
EVENT
OUT
PD7
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PD8
-
-
-
-
-
-
-
-
-
EVENT
OUT
PD9
-
EVENT
OUT
PD10
PD11
PD12
PD13
PD14
PD15
-
EVENT
OUT
-
EVENT
OUT
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
EVENT
OUT
EVENT
OUT
EVENT
OUT
Table 9. Alternate function mapping (continued)
AF00
AF01
AF02
AF03
AF04
AF05
AF06
AF07
AF08
AF09
AF10
AF11
AF12 AF13 AF14 AF15
Port
TIM9/
TIM10/
TIM11
SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4
SPI3/I2S3/
USART1/ USART6
USART2
TIM3/
TIM4/ TIM5
I2C1/I2C2/
I2C3
SPI2/I2S2/
SPI3/ I2S3
I2C2/
I2C3
SYS_AF
TIM1/TIM2
OTG1_FS
SDIO
EVENT
OUT
PE0
-
-
-
TIM4_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PE1
PE2
TIM1_CH2N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACECL
K
EVENT
OUT
-
SPI4_SCK
EVENT
OUT
PE3 TRACED0
PE4 TRACED1
PE5 TRACED2
PE6 TRACED3
-
-
-
EVENT
OUT
-
-
SPI4_NSS
EVENT
OUT
-
TIM9_CH1
SPI4_MISO
EVENT
OUT
-
TIM9_CH2
SPI4_MOSI
EVENT
OUT
PE7
PE8
-
-
-
-
-
-
-
-
-
TIM1_ETR
TIM1_CH1N
TIM1_CH1
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
TIM1_CH4
TIM1_BKIN
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
EVENT
OUT
PE9
-
EVENT
OUT
PE10
PE11
PE12
PE13
PE14
PE15
-
EVENT
OUT
SPI4_NSS
SPI4_SCK
SPI4_MISO
SPI4_MOSI
-
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
Table 9. Alternate function mapping (continued)
AF00
AF01
AF02
AF03
AF04
AF05
AF06
AF07
AF08
AF09
AF10
AF11
AF12 AF13 AF14 AF15
Port
TIM9/
TIM10/
TIM11
SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4
SPI3/I2S3/
USART1/ USART6
USART2
TIM3/
TIM4/ TIM5
I2C1/I2C2/
I2C3
SPI2/I2S2/
SPI3/ I2S3
I2C2/
I2C3
SYS_AF
TIM1/TIM2
OTG1_FS
SDIO
EVENT
OUT
PH0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PH1
STM32F401xD STM32F401xE
Memory mapping
5
Memory mapping
The memory map is shown in Figure 15.
Figure 15. Memory map
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DocID025644 Rev 3
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54
Memory mapping
STM32F401xD STM32F401xE
Table 10. STM32F401xD register boundary addresses
Bus
Boundary address
Peripheral
0xE010 0000 - 0xFFFF FFFF
0xE000 0000 - 0xE00F FFFF
0x5004 0000 - 0xDFFF FFFF
0x5000 0000 - 0x5003 FFFF
0x4002 6800 - 0x4FFF FFFF
0x4002 6400 - 0x4002 67FF
0x4002 6000 - 0x4002 63FF
0x4002 5000 - 0x4002 4FFF
0x4002 3C00 - 0x4002 3FFF
0x4002 3800 - 0x4002 3BFF
0x4002 3400 - 0x4002 37FF
0x4002 3000 - 0x4002 33FF
0x4002 2000 - 0x4002 2FFF
0x4002 1C00 - 0x4002 1FFF
0x4002 1400 - 0x4002 1BFF
0x4002 1000 - 0x4002 13FF
0x4002 0C00 - 0x4002 0FFF
0x4002 0800 - 0x4002 0BFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
Reserved
®
Cortex -M4
Cortex-M4 internal peripherals
Reserved
USB OTG FS
Reserved
DMA2
AHB2
DMA1
Reserved
Flash interface register
RCC
Reserved
CRC
AHB1
Reserved
GPIOH
Reserved
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
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Memory mapping
Table 10. STM32F401xD register boundary addresses (continued)
Bus
Boundary address
Peripheral
0x4001 4C00- 0x4001 FFFF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2400 - 0x4001 2BFF
0x4001 2000 - 0x4001 23FF
0x4001 1800 - 0x4001 1FFF
0x4001 1400 - 0x4001 17FF
0x4001 1000 - 0x4001 13FF
0x4001 0800 - 0x4001 0FFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
0x4000 7400 - 0x4000 FFFF
Reserved
TIM11
TIM10
TIM9
EXTI
SYSCFG
SPI4/I2S4
SPI1
SDIO
APB2
Reserved
ADC1
Reserved
USART6
USART1
Reserved
TIM8
TIM1
Reserved
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Memory mapping
STM32F401xD STM32F401xE
Table 10. STM32F401xD register boundary addresses (continued)
Bus
Boundary address
Peripheral
0x4000 7000 - 0x4000 73FF
0x4000 6000 - 0x4000 6FFF
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 4800 - 0x4000 53FF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 1000 - 0x4000 27FF
0x4000 0C00 - 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
PWR
Reserved
I2C3
I2C2
I2C1
Reserved
USART2
I2S3ext
SPI3 / I2S3
SPI2 / I2S2
I2S2ext
IWDG
APB1
WWDG
RTC & BKP Registers
Reserved
TIM5
TIM4
TIM3
TIM2
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Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3 σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
A
DD
1.7 V ≤ V ≤ 3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2 σ).
6.1.3
6.1.4
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 16.
Figure 16. Pin loading conditions
-#5 PIN
# ꢒ ꢌꢊ P&
-3ꢂꢑꢊꢂꢂ6ꢎ
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Electrical characteristics
STM32F401xD STM32F401xE
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 17.
Figure 17. Input voltage measurement
-#5 PIN
6
).
-3ꢂꢑꢊꢂꢊ6ꢎ
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STM32F401xD STM32F401xE
Electrical characteristics
6.1.6
Power supply scheme
Figure 18. Power supply scheme
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1. To connect PDR_ON pin, refer to Section 3.14: Power supply supervisor.
2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
3. VCAP_2 pad is only available on LQFP100 and UFBGA100 packages.
4. VDDA=VDD and VSSA=VSS
.
Caution:
Each power supply pair (V /V , V
/V
...) must be decoupled with filtering ceramic
DD SS
DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
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Electrical characteristics
STM32F401xD STM32F401xE
6.1.7
Current consumption measurement
Figure 19. Current consumption measurement scheme
)
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6
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AIꢂꢍꢂꢎꢆ
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics,
Table 12: Current characteristics, and Table 13: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 11. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage (including VDDA, VDD and
VDD–VSS
–0.3
4.0
(1)
VBAT
)
Input voltage on FT pins(2)
VSS–0.3 VDD+4.0
V
VIN
Input voltage on any other pin
V
SS–0.3
4.0
9.0
50
Input voltage for BOOT0
VSS
|ΔVDDx
|
Variations between different VDD power pins
Variations between all the different ground pins
-
-
mV
|VSSX −VSS
|
50
see Section 6.3.14:
Absolute maximum
ratings (electrical
sensitivity)
VESD(HBM)
Electrostatic discharge voltage (human body model)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed
injected current.
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STM32F401xD STM32F401xE
Symbol
Electrical characteristics
Table 12. Current characteristics
Ratings
Max.
Unit
ΣIVDD
Σ IVSS
IVDD
Total current into sum of all VDD_x power lines (source)(1)
Total current out of sum of all VSS_x ground lines (sink)(1)
Maximum current into each VDD_x power line (source)(1)
Maximum current out of each VSS_x ground line (sink)(1)
Output current sunk by any I/O and control pin
160
-160
100
-100
25
IVSS
IIO
Output current sourced by any I/O and control pin
Total output current sunk by sum of all I/O and control pins (2)
Total output current sourced by sum of all I/Os and control pins(2)
Injected current on FT pins (4)
-25
mA
120
-120
ΣIIO
(3)
–5/+0
IINJ(PIN)
Injected current on NRST and B pins (4)
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(5)
±25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 13. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
125
Maximum junction temperature
°C
Maximum lead temperature during soldering
(WLCSP49, LQFP64/100, UFQFPN48,
UFBGA100)
TLEAD
see note (1)
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (ROHS
directive 2011/65/EU, July 2011).
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STM32F401xD STM32F401xE
6.3
Operating conditions
6.3.1
General operating conditions
Table 14. General operating conditions
Symbol
Parameter
Conditions
Min Typ
Max Unit
Power Scale3: Regulator ON,
0
0
-
-
60
VOS[1:0] bits in PWR_CR register = 0x01
fHCLK Internal AHB clock frequency
Power Scale2: Regulator ON,
84
MHz
VOS[1:0] bits in PWR_CR register = 0x10
fPCLK1 Internal APB1 clock frequency
fPCLK2 Internal APB2 clock frequency
0
0
-
-
-
42
84
VDD
Standard operating voltage
1.7(1)
3.6
Analog operating voltage
1.7(1)
-
2.4
(ADC limited to 1.2 M samples)
VDDA
(4)
Must be the same potential as VDD
(2)(3)
Analog operating voltage
2.4
-
-
3.6
3.6
(ADC limited to 2.4 M samples)
VBAT
Backup operating voltage
1.65
VOS[1:0] bits in PWR_CR register = 0x01
Max frequency 60 MHz
1.08(5) 1.14 1.20(5)
1.20(5) 1.26 1.32(5)
Regulator ON: 1.2 V internal
voltage on VCAP_1/VCAP_2 pins
V
V12
VOS[1:0] bits in PWR_CR register = 0x10
Max frequency 84 MHz
Regulator OFF: 1.2 V external Max. frequency 60 MHz.
voltage must be supplied on
Max. frequency 84 MHz.
VCAP_1/VCAP_2 pins
1.1
1.2
1.14
1.2
V12
1.26 1.32
2 V ≤ VDD ≤ 3.6 V
–0.3
-
-
-
-
-
-
-
-
5.5
5.2
9
Input voltage on RST and FT
pins(6)
VIN
VDD ≤ 2 V
–0.3
Input voltage on BOOT0 pin
UFQFPN48
0
-
625
392
313
465
323
WLCSP49
-
Maximum allowed package
PD
LQFP64
-
mW
power dissipation for suffix 7(7)
LQFP100
-
UFBGA100
-
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Electrical characteristics
Table 14. General operating conditions (continued)
Symbol
Parameter
Conditions
Min Typ
Max Unit
Maximum power dissipation
Low power dissipation(8)
Maximum power dissipation
Low power dissipation(8)
6 suffix version
–40
–40
–40
–40
–40
–40
-
-
-
-
-
-
85
Ambient temperature for 6
suffix version
105
TA
105
°C
125
Ambient temperature for 7
suffix version
105
125
TJ
Junction temperature range
7 suffix version
1. VDD/VDDA minimum value of 1.7 V with the use of an external power supply supervisor (refer to Section 3.14.2: Internal
reset OFF).
2. When the ADC is used, refer to Table 66: ADC characteristics.
3. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
4. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA
can be tolerated during power-up and power-down operation.
5. Guaranteed by test in production
6. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
7. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax
.
8. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax
.
Table 15. Features depending on the operating power supply range
Maximum
Flash
Operating
power
supply
range
memory
access
frequency
Maximum Flash
memory access
frequency with
Possible
Flash
memory
operations
Clock output
frequency on
I/O pins(3)
ADC
operation
I/O operation
with no wait wait states (1)(2)
states
(fFlashmax
)
8-bit erase
and program
operations
only
Conversion
time up to
1.2 Msps
VDD =1.7 to
2.1 V(4)
84 MHz with 4 – No I/O
wait states compensation
20 MHz(5)
up to 30 MHz
up to 30 MHz
Conversion
time up to
1.2 Msps
16-bit erase
and program
operations
VDD = 2.1 to
2.4 V
84 MHz with 3 – No I/O
22 MHz
24 MHz
wait states
compensation
Conversion
time up to
2.4 Msps
– I/O
16-bit erase
and program
operations
VDD = 2.4 to
2.7 V
84 MHz with 3
wait states
compensation up to 48 MHz
works
– up to
84 MHz
when VDD
3.0 to 3.6 V
=
Conversion
time up to
2.4 Msps
– I/O
compensation
works
32-bit erase
and program
operations
VDD = 2.7 to
3.6 V(6)
84 MHz with 2
wait states
30 MHz
– up to
48 MHz
when VDD
=
2.7 to 3.0 V
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1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
3. Refer to for frequencies vs. external load.
4. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 3.14.2: Internal
reset OFF).
5. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.
6. The voltage range for the USB full speed embedded PHY can drop down to 2.7 V. However the electrical characteristics of
D- and D+ pins will be degraded between 2.7 and 3 V.
6.3.2
VCAP1/VCAP2 external capacitors
Stabilization for the main regulator is achieved by connecting external capacitor C
to the
EXT
VCAP1 and VCAP2 pin. For packages supporting only 1 VCAP pin, the 2 CEXT capacitors
are replaced by a single capacitor.
C
is specified in Table 16.
EXT
Figure 20. External capacitor C
EXT
&
(65
5ꢈ/HDN
06ꢁꢊꢉꢂꢂ9ꢅ
1. Legend: ESR is the equivalent series resistance.
(1)
Table 16. VCAP1/VCAP2 operating conditions
Parameter
Symbol
Conditions
Capacitance of external capacitor with available
VCAP1 and VCAP2 pins
CEXT
2.2 µF
< 2 Ω
4.7 µF
< 1 Ω
ESR of external capacitor with available VCAP1 and
VCAP2 pins
ESR
CEXT
ESR
Capacitance of external capacitor with a single VCAP
pin available
ESR of external capacitor with a single VCAP pin
available
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
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Electrical characteristics
6.3.3
Operating conditions at power-up/power-down (regulator ON)
Subject to general operating conditions for T .
A
Table 17. Operating conditions at power-up / power-down (regulator ON)
Symbol
Parameter
VDD rise time rate
VDD fall time rate
Min
Max
Unit
20
20
∞
∞
tVDD
µs/V
6.3.4
Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for T .
A
(1)
Table 18. Operating conditions at power-up / power-down (regulator OFF)
Symbol
Parameter
VDD rise time rate
DD fall time rate
Conditions
Power-up
Power-down
Min
Max
Unit
20
20
20
20
∞
∞
∞
∞
tVDD
V
µs/V
VCAP_1 and VCAP_2 rise time rate Power-up
VCAP_1 and VCAP_2 fall time rate Power-down
tVCAP
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
1.08 V.
Note:
This feature is only available for UFBGA100 package.
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6.3.5
Embedded reset and power control block characteristics
The parameters given in Table 19 are derived from tests performed under ambient
temperature and V supply voltage @ 3.3V.
DD
Table 19. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
PLS[2:0]=000 (rising edge)
PLS[2:0]=000 (falling edge)
PLS[2:0]=001 (rising edge)
PLS[2:0]=001 (falling edge)
PLS[2:0]=010 (rising edge)
PLS[2:0]=010 (falling edge)
PLS[2:0]=011 (rising edge)
PLS[2:0]=011 (falling edge)
PLS[2:0]=100 (rising edge)
PLS[2:0]=100 (falling edge)
PLS[2:0]=101 (rising edge)
PLS[2:0]=101 (falling edge)
PLS[2:0]=110 (rising edge)
PLS[2:0]=110 (falling edge)
PLS[2:0]=111 (rising edge)
PLS[2:0]=111 (falling edge)
2.09
1.98
2.23
2.13
2.39
2.29
2.54
2.44
2.70
2.59
2.86
2.65
2.96
2.85
3.07
2.95
-
2.14 2.19
2.04 2.08
2.30 2.37
2.19 2.25
2.45 2.51
2.35 2.39
2.60 2.65
2.51 2.56
V
2.76 2.82
Programmable voltage
detector level selection
VPVD
2.66 2.71
2.93 2.99
2.84 3.02
3.03 3.10
2.93 2.99
3.14 3.21
3.03 3.09
(2)
VPVDhyst
PVD hysteresis
100
-
mV
V
1.60(1)
1.64
-
Falling edge
Rising edge
1.68 1.76
1.72 1.80
Power-on/power-down
reset threshold
VPOR/PDR
(2)
VPDRhyst
PDR hysteresis
40
-
mV
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
2.13
2.23
2.44
2.53
2.75
2.85
-
2.19 2.24
2.29 2.33
2.50 2.56
2.59 2.63
2.83 2.88
2.92 2.97
Brownout level 1
threshold
VBOR1
VBOR2
VBOR3
Brownout level 2
threshold
V
Brownout level 3
threshold
(2)
VBORhyst
BOR hysteresis
POR reset timing
100
1.5
-
mV
ms
TRSTTEMPO
0.5
3.0
(2)(3)
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Electrical characteristics
Table 19. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ Max Unit
InRush current on
voltage regulator power-
on (POR or wakeup from
Standby)
(2)
IRUSH
-
160
-
200
5.4
mA
µC
InRush energy on
voltage regulator power-
on (POR or wakeup from IRUSH = 171 mA for 31 µs
Standby)
V
DD = 1.7 V, TA = 105 °C,
(2)
ERUSH
-
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
3. The reset timing is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first
instruction is fetched by the user application code.
6.3.6
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 19: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in input mode with a static value at VDD or VSS (no load).
All peripherals are disabled except if it is explicitly mentioned.
The Flash memory access time is adjusted to both f
frequency and VDD ranges
HCLK
(refer to Table 15: Features depending on the operating power supply range).
•
The voltage scaling is adjusted to f frequency as follows:
HCLK
–
–
Scale 3 for f
≤ 60 MHz
HCLK
Scale 2 for 60 MHz < f
≤ 84 MHz
HCLK
•
•
•
The system clock is HCLK, f
= f
/2, and f
= f
.
PCLK1
HCLK
PCLK2
HCLK
External clock is 4 MHz and PLL is on
The maximum values are obtained for V = 3.6 V and a maximum ambient
DD
temperature (T ), and the typical values for T = 25 °C and V = 3.3 V unless
A
A
DD
otherwise specified.
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Electrical characteristics
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Table 20. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - V = 1.7 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA=
25 °C
TA= 25 °C TA=85 °C TA=105 °C
84
60
40
20
84
60
40
20
21.8
15.8
11.4
6.0
23.1
16.5
11.9
6.3
24.1
17.5
12.9
7.3
25.3(4)
18.7
13.9
8.3
External clock,
all peripherals
enabled(2)(3)
Supply current
in Run mode
IDD
mA
12.7
9.2
13.5
10.5
7.1
14.5
11.5
8.1
16.3(4)
12.8
9.1
External clock,
all peripherals
disabled(3)
6.7
3.6
3.8
4.8
5.8
1. Guaranteed by characterization, not tested in production unless otherwise specified
2. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be
considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the
analog part.
4. Tested in production.
Table 21. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Typ
Unit
TA= 25 °C TA=85 °C TA=105 °C
84
60
40
20
84
60
40
20
22.0
16.0
11.6
6.2
23.1
16.9
12.1
6.5
24.1
17.9
13.1
7.5
25.3
19.8
14.1
8.5
External clock,
all peripherals
enabled(2)(3)
Supply current
in Run mode
IDD
mA
12.9
9.5
14.0
10.5
7.3
15.0
11.5
8.3
16.3
12.8
9.3
External clock,
all peripherals
disabled(3)
6.9
3.8
4.0
5.0
6.0
1. Guaranteed by characterization, not tested in production unless otherwise specified
2. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be
considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the
analog part.
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Electrical characteristics
Table 22. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory- V = 1.7 V
DD
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Typ
Unit
TA =
TA =
TA =
25 °C
85 °C 105 °C
84
60
40
30
20
84
60
40
30
20
23.2
15.1
10.8
8.8
24.5
16.3
12.1
10.0
8.0
25.6
17.4
13.2
11.1
9.0
26.6
18.4
14.2
12.2
10.1
15.7
11.5
9.4
External clock,
all peripherals enabled(2)(3)
6.9
Supply current
in Run mode
IDD
mA
12.3
8.2
13.6
9.4
14.7
10.5
8.3
External clock,
6.0
7.3
all peripherals disabled(3)
4.9
6.2
7.2
8.3
4.0
5.1
6.1
7.2
1. Guaranteed by characterization, not tested in production unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.
Table 23. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory - V = 3.3 V
DD
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Typ
Unit
TA =
TA =
TA =
25 °C
85 °C 105 °C
84
60
40
30
20
84
60
40
30
20
23.4
15.3
11.0
9.0
24.7
16.5
12.3
10.2
8.2
25.8
17.6
13.4
11.3
9.2
26.8
18.6
14.4
12.4
10.3
15.9
11.7
9.6
External clock,
all peripherals enabled(2)(3)
7.1
Supply current
in Run mode
IDD
mA
12.5
8.4
13.8
9.6
14.9
10.7
8.5
External clock,
6.2
7.5
all peripherals disabled(3)
5.1
6.4
7.4
8.5
4.2
5.3
6.3
7.4
1. Guaranteed by characterization, not tested in production unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.
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.
Table 24. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Typ
Unit
TA =
TA =
TA =
25 °C
85 °C 105 °C
84
60
40
30
20
84
60
40
30
20
31.1
21.7
15.5
12.6
9.8
32.2
22.1
16.1
13.1
10.1
21.3
15.3
11.2
9.2
34.3
23.2
17.1
14.1
11.1
23.4
16.3
12.2
10.2
8.2
36.3
24.2
18.1
15.1
12.1
25.4
17.3
13.3
11.2
9.2
External clock,
all peripherals enabled(2)(3)
Supply current
in Run mode
IDD
mA
20.2
14.9
10.6
8.8
External clock,
all peripherals disabled(3)
6.9
7.2
1. Guaranteed by characterization, not tested in production unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.
Table 25. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Typ
Unit
TA =
TA =
TA =
25 °C
85 °C 105 °C
84
60
40
30
20
84
60
40
30
20
32.5
22.2
16.0
12.9
10.2
21.6
15.3
11.2
9.0
33.3
23.3
17.1
14.1
11.1
22.4
16.4
12.3
10.2
8.2
34.3
24.3
18.1
15.1
12.1
23.5
17.4
13.3
11.2
9.2
35.4
25.3
19.2
16.1
13.1
24.5
18.4
14.3
12.3
10.2
External clock,
all peripherals enabled(2)(3)
Supply current
in Run mode
IDD
mA
External clock,
all peripherals disabled(3)
7.3
1. Guaranteed by characterization, not tested in production unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.
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Table 26. Typical and maximum current consumption in Sleep mode
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Typ
Unit
TA =
TA =
TA =
25 °C
85 °C 105 °C
84
60
40
30
20
84
60
40
30
20
16.6
10.8
8.3
6.8
5.9
5.3
3.7
2.9
2.7
2.7
17.4
11.2
9.0
7.1
6.1
6.1
4.1
3.1
3.1
3.1
18.4
12.3
10.0
8.1
19.5
13.3
11.0
9.1
External clock,
all peripherals enabled(2)(3)
7.1
8.1
Supply current
in Sleep mode
IDD
mA
7.1
8.2
5.1
6.1
External clock,
4.1
5.1
all peripherals disabled(3)(4)
4.1
5.1
4.1
5.1
1. Guaranteed by characterization, not tested in production unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the
analog part.
4. Same current consumption for fHCLK at 30 MHz and 20 MHz due to VCO running slower at 30 MHz.
Table 27. Typical and maximum current consumptions in Stop mode - V =1.8 V
DD
Max(1)
Typ
Symbol
Parameter
Conditions
Unit
TA =
TA = TA = TA =
25 °C 25 °C 85 °C 105 °C
Main regulator usage
Flash in Stop mode, all
oscillators OFF, no
independent watchdog
109
41
135
65
440
310 530(2)
345 530
260 510(2)
230 460
650
Low power regulator usage
IDD_STOP
µA
Main regulator usage
Flash in Deep power
down mode, all oscillators
OFF, no independent
watchdog
72
12
10
95
36
27
Low power regulator usage
Low power low voltage regulator usage
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by test in production.
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Table 28. Typical and maximum current consumption in Stop mode - V =3.3 V
DD
Max(1)
Typ
Symbol
Parameter
Conditions
Unit
TA =
TA = TA = TA =
25 °C 25 °C 85 °C 105 °C
Main regulator usage
Flash in Stop mode, all
oscillators OFF, no
independent watchdog
111
42
140
65
450
330
670
560
Low power regulator usage
IDD_STOP
µA
Main regulator usage
Flash in Deep power
down mode, all oscillators
OFF, no independent
watchdog
73
12
10
100
36
360
270
230
560
520
470
Low power regulator usage
Low power low voltage regulator usage
28
1. Guaranteed by characterization, not tested in production.
Table 29. Typical and maximum current consumption in Standby mode - V =1.8 V
DD
Typ(1)
Max(2)
Symbol
Parameter
Conditions
Unit
TA =
TA = TA =
TA =
25 °C 25 °C 85 °C 105 °C
Low-speed oscillator (LSE) and RTC ON
RTC and LSE OFF
2.4
1.8
4.0
12.0
24.0
Supply current in
Standby mode
IDD_STBY
µA
3.0(3) 11.0
23.0(3)
1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.
2. Guaranteed by characterization, not tested in production unless otherwise specified.
3. Guaranteed by test in production.
Table 30. Typical and maximum current consumption in Standby mode - V =3.3 V
DD
Typ(1)
Max(2)
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA =
TA =
25 °C 25 °C 85 °C 105 °C
Low-speed oscillator (LSE) and RTC ON
RTC and LSE OFF
2.8
2.1
5.0
14.0
28.0
Supply current in
Standby mode
IDD_STBY
µA
4.0(3) 13.0
27.0(3)
1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.
2. Guaranteed by characterization, not tested in production unless otherwise specified.
3. Guaranteed by test in production.
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Table 31. Typical and maximum current consumptions in V
mode
BAT
Typ
Max(2)
TA = TA =
TA = 25 °C
Symbol Parameter
Conditions(1)
85 °C 105 °C Unit
VBAT = 3.6 V
VBAT = VBAT= VBAT
1.7 V 2.4 V 3.3 V
=
Backup
DD_VBAT domainsupply
current
Low-speed oscillator (LSE) and RTC ON 0.66
0.76
0.1
0.97
0.1
3.0
2.0
5.0
4.0
I
µA
RTC and LSE OFF
0.1
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Guaranteed by characterization, not tested in production.
Figure 21. Typical V
current consumption (LSE and RTC ON)
BAT
ꢅ
ꢎꢃꢌ
ꢎ
ꢂꢃꢆꢌ6
ꢂꢃꢈ6
ꢂꢃꢄ6
ꢎ6
ꢎꢃꢍ6
ꢎꢃꢈ6
ꢅ6
ꢂꢃꢌ
ꢂ
ꢊꢃꢌ
ꢊ
ꢅꢃꢅ6
ꢅꢃꢆ6
ꢊ #
ꢎꢌ #
ꢌꢌ #
ꢄꢌ #
ꢂꢊꢌ #
4EMPERATURE
-3ꢅꢊꢍꢑꢊ6ꢂ
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 54: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
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required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 33: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
ISW = VDD × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
is the MCU supply voltage
SW
V
DD
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
INT
EXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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Table 32. Switching output I/O current consumption
I/O toggling
Symbol
Parameter
Conditions(1)
Typ
Unit
frequency (fSW
)
2 MHz
8 MHz
0.05
0.15
0.45
0.85
1.00
1.40
0.10
0.35
1.05
2.20
2.40
3.55
0.20
0.65
1.85
2.45
4.70
8.80
0.25
1.00
3.45
7.15
11.55
0.32
1.27
3.88
12.34
25 MHz
50 MHz
60 MHz
84 MHz
2 MHz
VDD = 3.3 V
C = CINT
8 MHz
VDD = 3.3 V
CEXT = 0 pF
25 MHz
50 MHz
60 MHz
84 MHz
2 MHz
C = CINT + CEXT + CS
I/O switching
current
IDDIO
8 MHz
mA
VDD = 3.3 V
CEXT =10 pF
25 MHz
50 MHz
60 MHz
84 MHz
2 MHz
C = CINT + CEXT + CS
8 MHz
VDD = 3.3 V
CEXT = 22 pF
25 MHz
50 MHz
60 MHz
2 MHz
C = CINT + CEXT + CS
VDD = 3.3 V
CEXT = 33 pF
8 MHz
25 MHz
50 MHz
C = CINT + CEXT + CS
1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value).
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On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
•
•
•
•
At startup, all I/O pins are in analog input configuration.
All peripherals are disabled unless otherwise mentioned.
The ART accelerator is ON.
Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V.
HCLK is the system clock at 84 MHz. f = f /2, and f = f .
HCLK
PCLK1
HCLK
PCLK2
The given value is calculated by measuring the difference of current consumption
–
–
with all peripherals clocked off
with only one peripheral clocked on
•
Ambient operating temperature is 25 °C and V =3.3 V.
DD
Table 33. Peripheral current consumption
Peripheral
IDD (typ)
Unit
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOH
CRC
1.55
1.55
1.55
1.55
1.55
1.55
0.36
20.24
21.07
11.19
8.57
8.33
11.19
0.71
3.33
3.10
2.62
2.86
1.90
1.67
0.71
AHB1
µA/MHz
(up to 84MHz)
DMA1
DMA2
TIM2
TIM3
TIM4
TIM5
PWR
USART2
I2C1/2/3
SPI2(1)
SPI3(1)
I2S2
APB1
µA/MHz
(up to 42MHz)
I2S3
WWDG
AHB2
OTG_FS
23.93
µA/MHz
(up to 84MHz)
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Table 33. Peripheral current consumption (continued)
Peripheral
IDD (typ)
Unit
TIM1
TIM9
5.71
2.86
1.79
2.02
2.98
1.19
3.10
2.86
5.95
1.31
0.71
TIM10
TIM11
ADC1(2)
SPI1
APB2
µA/MHz
(up to 84MHz)
USART1
USART6
SDIO
SPI4
SYSCFG
1. I2SMOD bit set in SPI_I2SCFGR register, and then the I2SE bit set to enable I2S peripheral.
2. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6
mA for the analog part.
6.3.7
Wakeup time from low-power modes
The wakeup times given in Table 34 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•
•
For Stop or Sleep modes: the wakeup event is WFE.
WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and V =3.3 V.
DD
Table 34. Low-power mode wakeup timings(1)
Min(1) Typ(1) Max(1)
Symbol
Parameter
Unit
CPU
clock
cycle
(2)
Wakeup from Sleep mode
-
4
6
tWUSLEEP
Wakeup from Stop mode, usage of main regulator
-
-
-
-
13.5
105
21
14.5
111
33
Wakeup from Stop mode, usage of main regulator, Flash
memory in Deep power down mode
(2)
µs
tWUSTOP
Wakeup from Stop mode, regulator in low power mode
Wakeup from Stop mode, regulator in low power mode,
Flash memory in Deep power down mode
113
130
(2)(3)
Wakeup from Standby mode
-
314
407
µs
tWUSTDBY
1. Guaranteed by characterization, not tested in production.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
3. WUSTDBY maximum value is given at –40 °C.
t
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6.3.8
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 54. However, the recommended clock input
waveform is shown in Figure 22.
The characteristics given in Table 35 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 14.
Table 35. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
External user clock source
frequency(1)
fHSE_ext
1
-
50
MHz
VHSEH
VHSEL
tw(HSE)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
0.7VDD
VSS
-
-
VDD
V
0.3VDD
OSC_IN high or low time(1)
OSC_IN rise or fall time(1)
5
-
-
-
-
tw(HSE)
ns
tr(HSE)
tf(HSE)
10
Cin(HSE) OSC_IN input capacitance(1)
-
45
-
5
-
-
pF
%
DuCy(HSE) Duty cycle
55
±1
IL
OSC_IN Input leakage current
VSS ≤ VIN ≤ VDD
-
µA
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 54. However, the recommended clock input
waveform is shown in Figure 23.
The characteristics given in Table 36 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 14.
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Table 36. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User External clock source
frequency(1)
fLSE_ext
-
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
tw(LSE)
0.7VDD
VSS
-
-
-
VDD
0.3VDD
-
V
OSC32_IN input pin low level voltage
OSC32_IN high or low time(1)
450
tf(LSE)
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1)
-
-
50
Cin(LSE)
OSC32_IN input capacitance(1)
-
30
-
5
-
-
pF
%
DuCy(LSE) Duty cycle
70
±1
IL
OSC32_IN Input leakage current
VSS ≤ VIN ≤ VDD
-
µA
1. Guaranteed by design, not tested in production.
Figure 22. High-speed external clock source AC timing diagram
6
(3%(
ꢑꢊꢓ
ꢂꢊ ꢓ
(3%,
6
T
T
T
7ꢀ(3%ꢁ
T
T
7ꢀ(3%ꢁ
Rꢀ(3%ꢁ
Fꢀ(3%ꢁ
4
(3%
F
(3%?EXT
%XTERNAL
CLOCK SOURCE
)
,
/3# ?) .
34-ꢅꢎ&
AIꢂꢈꢌꢎꢄ
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Figure 23. Low-speed external clock source AC timing diagram
6
,3%(
ꢑꢊꢓ
ꢂꢊꢓ
6
,3%,
T
T
T
7ꢀ,3%ꢁ
T
T
7ꢀ,3%ꢁ
Rꢀ,3%ꢁ
Fꢀ,3%ꢁ
4
,3%
F
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High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 37. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 37. HSE 4-26 MHz oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
fOSC_IN
RF
Oscillator frequency
Feedback resistor
4
-
-
26
-
MHz
200
kΩ
VDD=3.3 V,
ESR= 30 Ω,
-
-
450
530
-
-
CL=5 pF @25 MHz
IDD
HSE current consumption
µA
VDD=3.3 V,
ESR= 30 Ω,
CL=10 pF @25 MHz
Gm_crit_max Maximum critical crystal gm
Startup
-
-
-
1
-
mA/V
ms
(2)
tSU(HSE)
Startup time
VDD is stabilized
2
1. Guaranteed by design, not tested in production.
2. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 24). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
78/135
STM32F401xD STM32F401xE
Electrical characteristics
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 24. Typical application with an 8 MHz crystal
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1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 38. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RF
Feedback resistor
-
-
-
-
18.4
-
MΩ
IDD
LSE current consumption
-
-
1
µA
Gm_crit_max Maximum critical crystal gm
Startup
0.56 µA/V
(2)
tSU(LSE)
startup time
VDD is stabilized
2
-
s
1. Guaranteed by design, not tested in production.
2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is guaranteed by characterization and not tested in
production. It is measured for a standard crystal resonator and it can vary significantly with the crystal
manufacturer.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
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114
Electrical characteristics
STM32F401xD STM32F401xE
Figure 25. Typical application with a 32.768 kHz crystal
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6.3.9
Internal clock source characteristics
The parameters given in Table 39 and Table 40 are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 14.
DD
High-speed internal (HSI) RC oscillator
L
(1)
Table 39. HSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ
Max Unit
fHSI
-
16
-
MHz
%
User-trimmed with the RCC_CR
register(2)
-
-
1
TA = –40 to 105 °C(3) –8
-
-
-
4.5
4
%
%
%
Accuracy of the HSI
oscillator
ACCHSI
Factory-
calibrated
TA = –10 to 85 °C(3)
–4
–1
TA = 25 °C
1
HSI oscillator
startup time
(2)
tsu(HSI)
-
-
2.2
60
4
µs
HSI oscillator
power consumption
(2)
IDD(HSI)
80
µA
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production
3. Guaranteed by characterization, not tested in production
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STM32F401xD STM32F401xE
Electrical characteristics
Figure 26. ACC versus temperature
HSI
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Low-speed internal (LSI) RC oscillator
(1)
Table 40. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(2)
fLSI
Frequency
17
-
32
15
47
40
kHz
µs
(3)
tsu(LSI)
LSI oscillator startup time
(3)
IDD(LSI)
LSI oscillator power consumption
-
0.4
0.6
µA
1.
VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by characterization, not tested in production.
3. Guaranteed by design, not tested in production.
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114
Electrical characteristics
STM32F401xD STM32F401xE
Figure 27. ACC
versus temperature
LSI
-3ꢂꢑꢊꢂꢅ6ꢂ
6.3.10
PLL characteristics
The parameters given in Table 41 and Table 42 are derived from tests performed under
temperature and V supply voltage conditions summarized in Table 14.
DD
Table 41. Main PLL characteristics
Symbol
Parameter
PLL input clock(1)
Conditions
Min
Typ
Max
Unit
fPLL_IN
0.95(2)
24
1
-
2.10
84
MHz
MHz
fPLL_OUT
PLL multiplier output clock
48 MHz PLL multiplier output
clock
fPLL48_OUT
fVCO_OUT
-
48
75
MHz
MHz
PLL VCO output
192
75
100
-
-
-
432
200
300
-
VCO freq = 192 MHz
VCO freq = 432 MHz
tLOCK
PLL lock time
µs
ps
-
RMS
25
peak
to
Cycle-to-cycle jitter
Period Jitter
-
-
-
150
15
-
-
-
peak
System clock
84 MHz
Jitter(3)
RMS
peak
to
200
peak
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STM32F401xD STM32F401xE
Electrical characteristics
Table 41. Main PLL characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45
0.40
0.75
(4)
IDD(PLL)
PLL power consumption on VDD
-
mA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55
0.40
0.85
PLL power consumption on
VDDA
(4)
IDDA(PLL)
-
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design, not tested in production.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Guaranteed by characterization, not tested in production.
Table 42. PLLI2S (audio PLL) characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLI2S_IN
fPLLI2S_OUT
fVCO_OUT
PLLI2S input clock(1)
0.95(2)
1
-
2.10
216
432
200
300
-
PLLI2S multiplier output clock
PLLI2S VCO output
-
MHz
192
75
100
-
-
VCO freq = 192 MHz
VCO freq = 432 MHz
-
tLOCK
PLLI2S lock time
µs
-
RMS
90
Cycle to cycle at
12.288 MHz on
48 KHz period,
N=432, R=5
peak
to
peak
-
280
90
-
Master I2S clock jitter
WS I2S clock jitter
Average frequency of
12.288 MHz
Jitter(3)
ps
-
-
-
-
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 KHz
on 1000 samples
400
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45
0.40
0.75
PLLI2S power consumption on
VDD
(4)
IDD(PLLI2S)
-
-
mA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55
0.40
0.85
PLLI2S power consumption on
VDDA
(4)
IDDA(PLLI2S)
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design, not tested in production.
3. Value given with main PLL running.
4. Guaranteed by characterization, not tested in production.
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114
Electrical characteristics
STM32F401xD STM32F401xE
6.3.11
PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences(see Table 49: EMI characteristics for WLCSP49). It is available only on the
main PLL.
Table 43. SSCG parameters constraint
Symbol
Parameter
Min
Typ
Max(1)
Unit
fMod
md
Modulation frequency
Peak modulation depth
-
0.25
-
-
-
-
10
2
KHz
%
MODEPER * INCSTEP
215-1
-
1. Guaranteed by design, not tested in production.
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round[fPLL_IN ⁄ (4 × fMod)]
f
and f
must be expressed in Hz.
PLL_IN
Mod
As an example:
If f = 1 MHz, and f
= 1 kHz, the modulation depth (MODEPER) is given by
MOD
PLL_IN
equation 1:
MODEPER = round[106 ⁄ (4 × 103)] = 250
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
INCSTEP = round[((215 – 1) × md × PLLN) ⁄ (100 × 5 × MODEPER)]
f
must be expressed in MHz.
VCO_OUT
With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
INCSTEP = round[((215 – 1) × 2 × 240) ⁄ (100 × 5 × 250)] = 126md(quantitazed)%
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
mdquantized% = (MODEPER × INCSTEP × 100 × 5) ⁄ ((215 – 1) × PLLN)
As a result:
mdquantized% = (250 × 126 × 100 × 5) ⁄ ((215 – 1) × 240) = 2,002%(peak)
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STM32F401xD STM32F401xE
Electrical characteristics
Figure 28 and Figure 29 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is f
nominal.
PLL_OUT
T
is the modulation period.
mode
md is the modulation depth.
Figure 28. PLL output clock waveforms in center spread mode
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6.3.12
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 105 °C unless otherwise specified.
A
The devices are shipped to customers with the Flash memory erased.
Table 44. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Write / Erase 8-bit mode, VDD = 1.7 V
Write / Erase 16-bit mode, VDD = 2.1 V
Write / Erase 32-bit mode, VDD = 3.3 V
-
-
-
5
8
-
-
-
IDD
Supply current
mA
12
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114
Electrical characteristics
STM32F401xD STM32F401xE
Table 45. Flash memory programming
Symbol
Parameter
Conditions
Min(1) Typ Max(1) Unit
Program/eraseparallelism
(PSIZE) = x 8/16/32
tprog
Word programming time
-
-
-
-
-
-
-
-
-
-
-
-
-
16
100(2) µs
800
Program/eraseparallelism
(PSIZE) = x 8
400
300
250
Program/eraseparallelism
(PSIZE) = x 16
tERASE16KB Sector (16 KB) erase time
tERASE64KB Sector (64 KB) erase time
tERASE128KB Sector (128 KB) erase time
600
500
ms
ms
s
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
1200 2400
Program/eraseparallelism
(PSIZE) = x 16
700
550
2
1400
1100
4
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
Program/eraseparallelism
(PSIZE) = x 16
1.3
1
2.6
2
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
8
16
11
Program/eraseparallelism
(PSIZE) = x 16
tME
Mass erase time
5.5
4
s
Program/eraseparallelism
(PSIZE) = x 32
8
32-bit program operation
16-bit program operation
8-bit program operation
2.7
2.1
1.7
-
-
-
3.6
3.6
3.6
V
V
V
Vprog
Programming voltage
1. Guaranteed by characterization, not tested in production.
2. The maximum programming time is measured after 100K erase operations.
Table 46. Flash memory programming with V voltage
PP
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
tprog
Double word programming
-
-
-
-
-
16
230
100(2)
µs
ms
s
tERASE16KB Sector (16 KB) erase time
tERASE64KB Sector (64 KB) erase time
tERASE128KB Sector (128 KB) erase time
-
-
-
-
TA = 0 to +40 °C
VDD = 3.3 V
490
VPP = 8.5 V
875
tME
Mass erase time
1.750
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STM32F401xD STM32F401xE
Electrical characteristics
Table 46. Flash memory programming with V voltage (continued)
PP
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
Vprog
VPP
Programming voltage
VPP voltage range
2.7
7
-
-
3.6
9
V
V
Minimum current sunk on
the VPP pin
IPP
10
-
-
-
-
mA
Cumulative time during
which VPP is applied
(3)
tVPP
1
hour
1. Guaranteed by design, not tested in production.
2. The maximum programming time is measured after 100K erase operations.
3. VPP should only be connected during programming/erasing.
Table 47. Flash memory endurance and data retention
Value
Symbol
Parameter
Conditions
Unit
Min(1)
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
NEND Endurance
kcycles
Years
10
1 kcycle(2) at TA = 85 °C
30
10
20
tRET
Data retention 1 kcycle(2) at TA = 105 °C
10 kcycles(2) at TA = 55 °C
1. Guaranteed by characterization, not tested in production.
2. Cycling performed over the whole temperature range.
6.3.13
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
DD
SS
A device reset allows normal operations to be resumed.
The test results are given in Table 48. They are based on the EMS levels and classes
defined in application note AN1709.
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114
Electrical characteristics
Symbol
STM32F401xD STM32F401xE
Table 48. EMS characteristics for LQFP100 package
Level/
Class
Parameter
Conditions
VDD = 3.3 V, LQFP100, WLCSP49,
TA = +25 °C, fHCLK = 84 MHz,
conforms to IEC 61000-4-2
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VFESD
2B
4A
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP100, WLCSP49,
TA = +25 °C, fHCLK = 84 MHz,
conforms to IEC 61000-4-4
VEFTB
When the application is exposed to a noisy environment, it is recommended to avoid pin
exposition to disturbances. The pins showing a middle range robustness are: PA0, PA1,
PA2, on LQFP100 packages and PDR_ON on WLCSP49.
As a consequence, it is recommended to add a serial resistor (1 kΩ maximum) located as
close as possible to the MCU to the pins exposed to noise (connected to tracks longer than
50 mm on PCB).
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
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STM32F401xD STM32F401xE
Electrical characteristics
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 49. EMI characteristics for WLCSP49
Max vs.
[fHSE/fCPU
]
Monitored
frequency band
Symbol
Parameter
Conditions
Unit
8/84 MHz
0.1 to 30 MHz
30 to 130 MHz
-4
-4
dBµV
-
VDD = 3.6 V, TA = 25 °C, conforming to
IEC61967-2
SEMI
Peak level
130 MHz to 1 GHz
SAE EMI Level
-2
1.5
Table 50. EMI characteristics for LQFP100
Max vs.
[fHSE/fCPU
]
Monitored
Conditions
Symbol
Parameter
Unit
frequency band
8/84 MHz
0.1 to 30 MHz
19
19
11
30 to 130 MHz
dBµV
-
VDD = 3.6 V, TA = 25 °C, conforming to
IEC61967-2
SEMI
Peak level
130 MHz to 1 GHz
SAE EMI Level
3.5
6.3.14
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
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114
Electrical characteristics
STM32F401xD STM32F401xE
Maximum
Table 51. ESD absolute maximum ratings
Conditions
Symbol
Ratings
Class
Unit
value(1)
Electrostatic discharge
voltage (human body model) A114
TA = +25 °C conforming to JESD22-
VESD(HBM)
2
2000
V
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C conforming to
ANSI/ESD STM5.3.1
II
400
1. Guaranteed by characterization, not tested in production.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
•
•
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.
Table 52. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
II level A
6.3.15
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3 V-capable I/O pins) should be avoided during normal product
DD
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins
(out of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator
frequency deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 53.
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Electrical characteristics
Table 53. I/O current injection susceptibility(1)
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on BOOT0 pin
Injected current on NRST pin
–0
–0
NA
NA
Injected current on PB3, PB4, PB5, PB6,
PB7, PB8, PB9, PC13, PC14, PC15, PH1,
PDR_ON, PC0, PC1,PC2, PC3, PD1,
PD5, PD6, PD7, PE0, PE2, PE3, PE4,
PE5, PE6
IINJ
–0
NA
mA
Injected current on any other FT pin
Injected current on any other pins
–5
–5
NA
+5
1. NA = not applicable.
Note:
It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
6.3.16
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 54 are derived from tests
performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL
compliant.
Table 54. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.35VDD–0.04(1)
FT, and NRST I/O input low
level voltage
1.7 V≤ VDD≤ 3.6 V
-
-
(2)
0.3VDD
1.75 V≤ VDD ≤ 3.6 V,
-40 °C≤ TA ≤ 105 °C
VIL
V
-
-
BOOT0 I/O input low level
voltage
0.1VDD+0.1
1.7 V≤ VDD ≤ 3.6 V,
0 °C≤ TA ≤ 105 °C
-
-
-
0.45VDD+0.3(1)
-
FT and NRST I/O input high
level voltage(5)
1.7 V≤ VDD≤ 3.6 V
(2)
0.4VDD
1.75 V≤ VDD ≤ 3.6 V,
-40 °C≤ TA ≤ 105 °C
VIH
V
BOOT0 I/O input high level
voltage
0.17VDD+0.7(1)
-
-
1.7 V≤ VDD ≤ 3.6 V,
0 °C≤ TA ≤ 105 °C
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Electrical characteristics
STM32F401xD STM32F401xE
Table 54. I/O static characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
FT and NRST I/O input
hysteresis
10%
VDD
1.7 V≤ VDD≤ 3.6 V
-
-
V
(3)
1.75 V≤ VDD ≤ 3.6 V,
-40 °C≤ TA ≤ 105 °C
VHYS
BOOT0 I/O input hysteresis
-
100
-
mV
µA
1.7 V≤ VDD ≤ 3.6 V,
0 °C≤ TA ≤ 105 °C
I/O input leakage current (4)
VSS ≤ VIN ≤ VDD
VIN = 5 V
-
-
-
-
1
3
Ilkg
I/O FT input leakage current (5)
All pins
except for
PA10
(OTG_FS_ID
)
30
7
40
10
40
50
14
50
Weak pull-up
equivalent
resistor(6)
RPU
VIN = VSS
PA10
(OTG_FS_ID
)
kΩ
All pins
except for
PA10
(OTG_FS_ID
)
30
Weak pull-down
equivalent
RPD
VIN = VDD
resistor(7)
PA10
(OTG_FS_ID
)
7
-
10
5
14
-
(8)
CIO
I/O pin capacitance
-
pF
1. Guaranteed by design, not tested in production.
2. Guaranteed by test in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 53: I/O
current injection susceptibility
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 53: I/O current injection
susceptibility
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the
series resistance is minimum (~10% order).
7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization, not tested in production.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 30.
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STM32F401xD STM32F401xE
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Figure 30. FT I/O input characteristics
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or
source up to 20 mA (with a relaxed V /V ) except PC13, PC14 and PC15 which can
OL OH
sink or source up to 3mA. When using the PC13 to PC15 GPIOs in output mode, the
speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 12).
VDD
•
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
ΣI
(see Table 12).
VSS
Output voltage levels
Unless otherwise specified, the parameters given in Table 55 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 14. All I/Os are CMOS and TTL compliant.
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Electrical characteristics
STM32F401xD STM32F401xE
Table 55. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max Unit
(1)
VOL
VOH
VOL
VOH
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
CMOS port(2)
IIO = +8 mA
-
0.4
V
(3)
(1)
(3)
VDD–0.4
-
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2)
IIO =+8 mA
-
0.4
V
2.4
-
2.7 V ≤ VDD ≤ 3.6 V
(1)
VOL
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
-
1.3(4)
IIO = +20 mA
V
(3)
VDD–1.3(4)
-
2.7 V ≤ VDD ≤ 3.6 V
VOH
VOL
VOH
-
0.4(4)
(1)
IIO = +6 mA
V
(3)
VDD–0.4(4)
-
1.8 V ≤ VDD ≤ 3.6 V
(1)
VOL
-
0.4(5)
IIO = +4 mA
V
VOH
VDD–0.4(5)
-
(3)
1.7 V ≤ VDD ≤ 3.6 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12.
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
4. Guaranteed by characterization results, not tested in production.
5. Guaranteed by design, not tested in production..
.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 31 and ,
respectively.
Unless otherwise specified, the parameters given in Table 56 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 14.
(1)(2)
Table 56. I/O AC characteristics
OSPEEDRy
[1:0] bit
Symbol
Parameter
Conditions
Min
Typ
Max Unit
value(1)
CL = 50 pF, VDD ≥ 2.70 V
CL = 50 pF, VDD≥ 1.7 V
CL = 10 pF, VDD ≥ 2.70 V
CL = 10 pF, VDD ≥ 1.7 V
-
-
-
-
-
-
-
-
4
2
fmax(IO)out Maximum frequency(3)
Output high to low level fall
MHz
8
00
4
tf(IO)out
/
CL = 50 pF, VDD = 1.7 V to
3.6 V
time and output low to high
level rise time
-
-
100
ns
tr(IO)out
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STM32F401xD STM32F401xE
Electrical characteristics
(1)(2)
Table 56. I/O AC characteristics
(continued)
OSPEEDRy
[1:0] bit
Symbol
Parameter
Conditions
Min
Typ
Max Unit
value(1)
CL = 50 pF, VDD ≥ 2.70 V
CL = 50 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 2.70 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 50 pF, VDD ≥2.7 V
CL = 50 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 2.70 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 40 pF, VDD ≥ 2.70 V
CL = 40 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 2.70 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 40 pF, VDD≥ 2.70 V
CL = 40 pF, VDD≥ 1.7 V
CL = 10 pF, VDD≥ 2.70 V
CL = 10 pF, VDD≥ 1.7 V
CL = 30 pF, VDD ≥ 2.70 V
CL = 30 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 2.70 V
CL = 10 pF, VDD≥ 1.7 V
CL = 30 pF, VDD ≥ 2.70 V
CL = 30 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD≥ 2.70 V
CL = 10 pF, VDD≥ 1.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
25
12.5
MHz
50
fmax(IO)out Maximum frequency(3)
20
10
01
Output high to low level fall
time and output low to high
level rise time
20
ns
6
tf(IO)out
tr(IO)out
/
10
50(4)
25
fmax(IO)out Maximum frequency(3)
MHz
100(4)
50(4)
6
10
Output high to low level fall
time and output low to high
level rise time
10
ns
4
tf(IO)out
tr(IO)out
/
6
100(4)
50(4)
MHz
Fmax(IO)out Maximum frequency(3)
180(4)
100(4)
11
4
Output high to low level fall
time and output low to high
level rise time
6
tf(IO)out
tr(IO)out
/
ns
2.5
4
Pulse width of external signals
-
tEXTIpw detected by the EXTI
controller
10
-
-
ns
1. Guaranteed by characterization, not tested in production.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of
the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 31.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.
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Electrical characteristics
STM32F401xD STM32F401xE
Figure 31. I/O AC characteristics definition
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6.3.17
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 54).
PU
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 14. Refer to Table 54: I/O static characteristics for the values of VIH and VIL for
NRST pin.
Table 57. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Weak pull-up equivalent
resistor(1)
RPU
VIN = VSS
30
40
50
kΩ
(2)
VF(NRST)
NRST Input filtered pulse
-
-
-
100
-
ns
ns
(2)
VNF(NRST)
NRST Input not filtered pulse
VDD > 2.7 V
300
Internal Reset
source
TNRST_OUT Generated reset pulse duration
20
-
-
µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
2. Guaranteed by design, not tested in production.
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STM32F401xD STM32F401xE
Electrical characteristics
Figure 32. Recommended NRST pin protection
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1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 57. Otherwise the reset is not taken into account by the device.
6.3.18
TIM timer characteristics
The parameters given in Table 58 are guaranteed by design.
Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)(2)
Table 58. TIMx characteristics
Conditions(3)
Symbol
Parameter
Min
Max
Unit
AHB/APBx prescaler=1
tTIMxCLK
1
-
-
or 2 or 4, fTIMxCLK
84 MHz
=
11.9
ns
tTIMxCLK
ns
tres(TIM)
Timer resolution time
1
11.9
0
-
AHB/APBx prescaler>4,
fTIMxCLK = 84 MHz
-
fTIMxCLK/2
MHz
MHz
bit
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK = 84 MHz
0
42
ResTIM
Timer resolution
-
16/32
16-bit counter clock
period when internal clock
is selected
tCOUNTER
fTIMxCLK = 84 MHz
0.0119
780
µs
65536 ×
65536
tTIMxCLK
S
-
-
Maximum possible count
with 32-bit counter
tMAX_COUNT
fTIMxCLK = 84 MHz
51.1
1. TIMx is used as a general term to refer to the TIM1 to TIM11 timers.
2. Guaranteed by design, not tested in production.
3. The maximum timer frequency on APB1 is 42 MHz and on APB2 is up to 84 MHz, by setting the TIMPRE
bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise
TIMxCLK >= 4x PCLKx.
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Electrical characteristics
STM32F401xD STM32F401xE
6.3.19
Communications interfaces
I2C interface characteristics
2
The I2C interface meets the requirements of the standard I C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is
disabled, but is still present.
2
The I C characteristics are described in Table59. Refer also to Section 6.3.16: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
2
The I C bus interface supports standard mode (up to 100 kHz) and fast mode (up to 400
kHz). The I2C bus frequency can be increased up to 1 MHz. For more details about the
complete solution, please contact your local ST sales representative.
2
Table 59. I C characteristics
Standard mode I2C(1)
Fast mode I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
250
0
-
-
-
-
1.3
0.6
100
0
-
µs
-
-
SDA data hold time
900(3)
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
-
1000
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
Start condition hold time
-
300
-
300
th(STA)
tsu(STA)
4.0
4.7
4.0
4.7
-
-
-
-
0.6
0.6
0.6
1.3
-
-
-
-
µs
Repeated Start condition
setup time
tsu(STO)
Stop condition setup time
µs
µs
Stop to Start condition time
(bus free)
tw(STO:STA)
Capacitive load for each bus
line
Cb
-
400
-
400
pF
Guaranteed by design, not tested in production.
1.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode
clock.
3. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
98/135
STM32F401xD STM32F401xE
Electrical characteristics
2
Figure 33. I C bus AC waveforms and measurement circuit
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1. RS = series protection resistor.
2. RP = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.
(1)(2)
Table 60. SCL frequency (f
= 42 MHz, VDD = VDD_I2C = 3.3 V)
I2C_CCR value
PCLK1
fSCL (kHz)
RP = 4.7 kΩ
400
300
200
100
50
0x8019
0x8021
0x8032
0x0096
0x012C
0x02EE
20
1. RP = External pull-up resistance, fSCL = I2C speed
2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the
tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external
components used to design the application.
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SPI interface characteristics
Unless otherwise specified, the parameters given in Table 61 for the SPI interface are
derived from tests performed under the ambient temperature, f frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 14, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)
Table 61. SPI dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode, SPI1/4,
2.7 V < VDD < 3.6 V
42
Slave mode, SPI1/4,
2.7 V < VDD < 3.6 V
42
38(2)
21
fSCK
Slave transmitter/full-duplex mode,
SPI1/4, 2.7 V < VDD < 3.6 V
SPI clock frequency
-
-
MHz
1/tc(SCK)
Master mode, SPI1/2/3/4,
1.7 V < VDD < 3.6 V
Slave mode, SPI1/2/3/4,
1.7 V < VDD < 3.6 V
21
Duty cycle of SPI clock
frequency
Duty(SCK)
Slave mode
30
50
70
%
tw(SCKH)
tw(SCKL)
TPCLK
SCK high and low time Master mode, SPI presc = 2
TPCLK−1.5
TPCLK+1.5 ns
tsu(NSS)
th(NSS)
tsu(MI)
tsu(SI)
th(MI)
NSS setup time
NSS hold time
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
Master mode
4TPCLK
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
2TPCLK
0
2.5
6
-
Data input setup time
Data input hold time
Slave mode
-
Master mode
-
th(SI)
Slave mode
2.5
9
-
ta(SO
)
Data output access time Slave mode
Data output disable time Slave mode
20
13
tdis(SO)
8
Slave mode (after enable edge),
2.7 V < VDD < 3.6 V
-
9.5
9.5
-
13
17
-
ns
ns
ns
ns
tv(SO)
Data output valid time
Data output hold time
Slave mode (after enable edge),
1.7 V < VDD < 3.6 V
-
Slave mode (after enable edge),
2.7 V < VDD < 3.6 V
5.5
3.5
th(SO)
Slave mode (after enable edge),
1.7 V < VDD < 3.6 V
-
-
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STM32F401xD STM32F401xE
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(1)
Table 61. SPI dynamic characteristics (continued)
Symbol
Parameter
Data output valid time Master mode (after enable edge)
Master mode (after enable edge)
Conditions
Min
Typ
Max
Unit
tv(MO)
th(MO)
-
3
-
5
-
ns
ns
2
Data output hold time
1. Guaranteed by characterization, not tested in production.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%
Figure 34. SPI timing diagram - slave mode and CPHA = 0
NSS input
t
c(SCK)
t
t
h(NSS)
SU(NSS)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
t
dis(SO)
r(SCK)
f(SCK)
v(SO)
a(SO)
h(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134c
(1)
Figure 35. SPI timing diagram - slave mode and CPHA = 1
NSS input
t
t
t
h(NSS)
SU(NSS)
t
c(SCK)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
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Electrical characteristics
STM32F401xD STM32F401xE
(1)
Figure 36. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
MSBIN
t
BIT6 IN
LSB IN
h(MI)
MOSI
M SB OUT
BIT1 OUT
LSB OUT
OUTPUT
t
t
v(MO)
h(MO)
ai14136
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Electrical characteristics
I2S interface characteristics
2
Unless otherwise specified, the parameters given in Table 62 for the I S interface are
derived from tests performed under the ambient temperature, f
frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 14, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
2
(1)
Table 62. I S dynamic characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S Main clock output
I2S clock frequency
-
256x8K 256xFs(2)
MHz
Master data: 32 bits
Slave data: 32 bits
-
-
64xFs
fCK
MHz
%
64xFs
DCK
tv(WS)
I2S clock frequency duty cycle Slave receiver
30
0
70
6
-
WS valid time
WS hold time
WS setup time
WS hold time
Master mode
Master mode
Slave mode
th(WS)
0
tsu(WS)
1
-
th(WS)
Slave mode
0
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
7.5
2
-
Data input setup time
Data input hold time
-
ns
0
-
0
-
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
Slave transmitter (after enable edge)
-
27
Data output valid time
Data output hold time
Master transmitter (after enable edge)
Master transmitter (after enable edge)
-
20
-
2.5
1. Guaranteed by characterization, not tested in production.
2. The maximum value of 256xFs is 42 MHz (APB1 maximum frequency).
Note:
Refer to the I2S section of the reference manual for more details on the sampling frequency
(F ).
S
f
, f , and D values reflect only the digital peripheral behavior. The values of these
CK
MCK CK
parameters might be slightly impacted by the source clock precision. D depends mainly
CK
on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). F
maximum value is supported for each mode/condition.
S
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STM32F401xD STM32F401xE
2
(1)
Figure 37. I S slave timing diagram (Philips protocol)
t
c(CK)
CPOL = 0
CPOL = 1
WS input
t
t
t
t
w(CKL)
h(WS)
w(CKH)
t
t
t
v(SD_ST)
h(SD_ST)
su(WS)
SD
transmit
(2)
LSB transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
su(SD_SR)
h(SD_SR)
(2)
LSB receive
Bitn receive
LSB receive
SD
receive
ai14881b
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
(1)
Figure 38. I S master timing diagram (Philips protocol)
t
t
r(CK)
f(CK)
t
c(CK)
CPOL = 0
CPOL = 1
WS output
t
w(CKH)
t
t
h(WS)
t
v(WS)
w(CKL)
t
t
v(SD_MT)
h(SD_MT)
(2)
SD
transmit
LSB transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
t
h(SD_MR)
su(SD_MR)
(2)
SD
LSB receive
Bitn receive
LSB receive
receive
ai14884b
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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Electrical characteristics
USB OTG full speed (FS) characteristics
This interface is present in USB OTG FS controller.
Table 63. USB OTG FS startup time
Parameter
USB OTG FS transceiver startup time
Symbol
Max
Unit
(1)
tSTARTUP
1
µs
1. Guaranteed by design, not tested in production.
Table 64. USB OTG FS DC electrical characteristics
Symbol
VDD
Parameter
Conditions
Min.(1) Typ. Max.(1) Unit
USB OTG FS operating
voltage
3.0(2)
0.2
-
-
-
3.6
-
V
(3)
VDI
Differential input sensitivity
I(USB_FS_DP/DM)
Includes VDI range
Input
Differential common mode
range
(3)
levels
VCM
0.8
2.5
V
Single ended receiver
threshold
(3)
VSE
1.3
-
2.0
VOL Static output level low
VOH Static output level high
RL of 1.5 kΩ to 3.6 V(4)
-
-
-
0.3
3.6
Output
levels
V
(4)
RL of 15 kΩ to VSS
2.8
PA11, PA12
(USB_FS_DM/DP)
17
0.65
1.5
21
1.1
1.8
24
2.0
2.1
RPD
VIN = VDD
PA9 (OTG_FS_VBUS)
kΩ
PA11, PA12
(USB_FS_DM/DP)
VIN = VSS
VIN = VSS
RPU
PA9 (OTG_FS_VBUS)
0.25 0.37 0.55
1. All the voltages are measured from the local ground potential.
2. The USB OTG FS functionality is ensured down to 2.7 V but not the full USB full speed electrical
characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
3. Guaranteed by design, not tested in production.
RL is the load connected on the USB OTG FS drivers.
4.
When VBUS sensing feature is enabled, PA9 should be left at their default state (floating
input), not as alternate function. A typical 200 µA current consumption of the embedded
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 when the feature is enabled.
Note:
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Electrical characteristics
STM32F401xD STM32F401xE
Figure 39. USB OTG FS timings: definition of data signal rise and fall time
Crossover
points
Differential
Data Lines
V
CR S
V
SS
t
t
r
f
ai14137
Table 65. USB OTG FS electrical characteristics(1)
Driver characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tr
tf
Rise time(2)
Fall time(2)
CL = 50 pF
CL = 50 pF
tr/tf
4
4
20
20
ns
ns
%
V
trfm
VCRS
Rise/ fall time matching
90
1.3
110
2.0
Output signal crossover voltage
1. Guaranteed by design, not tested in production.
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
2.
6.3.20
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 66 are derived from tests
performed under the ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 14.
Table 66. ADC characteristics
Conditions
Symbol
Parameter
Power supply
Min
Typ
Max
Unit
VDDA
1.7(1)
1.7(1)
0.6
-
3.6
VDDA
18
V
VDDA − VREF+ < 1.2 V
VREF+ Positive reference voltage
-
V
V
DDA = 1.7(1) to 2.4 V
DDA = 2.4 to 3.6 V
ADC = 30 MHz,
15
30
MHz
MHz
fADC
ADC clock frequency
V
0.6
36
f
-
-
-
-
-
1764
17
kHz
1/fADC
V
(2)
12-bit resolution
fTRIG
External trigger frequency
Conversion voltage range(3)
0 (VSSA or VREF-
tied to ground)
VAIN
VREF+
See Equation 1 for
(2)
RAIN
External input impedance
Sampling switch resistance
-
-
-
-
-
50
6
kΩ
kΩ
pF
details
(2)(4)
RADC
Internal sample and hold
capacitor
(2)
CADC
4
7
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Electrical characteristics
Table 66. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
f
f
ADC = 30 MHz
-
-
-
0.100
3(5)
0.067
2(5)
16
µs
1/fADC
µs
Injection trigger conversion
latency
(2)
tlat
-
ADC = 30 MHz
-
-
Regular trigger conversion
latency
(2)
tlatr
-
-
1/fADC
µs
fADC = 30 MHz
0.100
-
(2)
tS
Sampling time
Power-up time
3
-
-
480
3
1/fADC
µs
(2)
tSTAB
2
fADC = 30 MHz
12-bit resolution
0.50
0.43
0.37
0.30
-
-
-
-
16.40
16.34
16.27
16.20
µs
µs
f
ADC = 30 MHz
10-bit resolution
Total conversion time (including
sampling time)
fADC = 30 MHz
8-bit resolution
(2)
tCONV
µs
fADC = 30 MHz
6-bit resolution
µs
9 to 492 (tS for sampling +n-bit resolution for successive
approximation)
1/fADC
Msps
12-bit resolution
-
-
-
-
2
Single ADC
12-bit resolution
Sampling rate
3.75
Msps
Interleave Dual ADC
mode
(2)
fS
(fADC = 30 MHz, and
tS = 3 ADC cycles)
12-bit resolution
-
-
-
-
6
Msps
µA
Interleave Triple ADC
mode
ADC VREF DC current
consumption in conversion
mode
(2)
IVREF+
300
1.6
500
1.8
ADC VDDA DC current
consumption in conversion
mode
(2)
IVDDA
mA
1. VDDA minimum value of 1.7 V is possible with the use of an external power supply supervisor (refer to Section 3.14.2:
Internal reset OFF).
2. Guaranteed by characterization, not tested in production.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA
.
4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 66.
Equation 1: R
max formula
AIN
(k – 0,5)
RAIN = -------------------------------------------------------------- – RADC
fADC × CADC × ln(2N + 2
)
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Electrical characteristics
STM32F401xD STM32F401xE
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
(1)
Table 67. ADC accuracy at f
= 18 MHz
Typ
ADC
Symbol
Parameter
Test conditions
Max(2)
Unit
ET
Total unadjusted error
±3
±4
f
ADC =18 MHz
EO
EG
ED
EL
Offset error
±2
±1
±1
±2
±3
±3
±2
±3
VDDA = 1.7 to 3.6 V
VREF = 1.7 to 3.6 V
VDDA − VREF < 1.2 V
LSB
Gain error
Differential linearity error
Integral linearity error
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Guaranteed by characterization, not tested in production.
(1)
Table 68. ADC accuracy at f
= 30 MHz
Typ
ADC
Symbol
Parameter
Test conditions
Max(2)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
±2
±5
±2.5
±4
fADC = 30 MHz,
RAIN < 10 kΩ,
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V,
VDDA − VREF < 1.2 V
±1.5
±1.5
±1
Gain error
LSB
Differential linearity error
Integral linearity error
±2
±1.5
±3
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Guaranteed by characterization, not tested in production.
(1)
Table 69. ADC accuracy at f
= 36 MHz
ADC
Symbol
Parameter
Test conditions
Typ
Max(2)
Unit
ET
Total unadjusted error
±4
±7
f
ADC =36 MHz,
EO
EG
ED
EL
Offset error
±2
±3
±2
±3
±3
±6
±3
±6
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V
VDDA − VREF < 1.2 V
LSB
Gain error
Differential linearity error
Integral linearity error
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Guaranteed by characterization, not tested in production.
108/135
STM32F401xD STM32F401xE
Electrical characteristics
(1)
Table 70. ADC dynamic accuracy at f
= 18 MHz - limited test conditions
ADC
Symbol
Parameter
Test conditions
Min
Typ
Max Unit
ENOB
SINAD
SNR
Effective number of bits
Signal-to-noise and distortion ratio
Signal-to-noise ratio
10.3
64
10.4
64.2
65
-
-
-
-
bits
fADC =18 MHz
VDDA = VREF+= 1.7 V
Input Frequency = 20 KHz
Temperature = 25 °C
64
dB
THD
Total harmonic distortion
-67
-72
1. Guaranteed by characterization, not tested in production.
(1)
Table 71. ADC dynamic accuracy at f
= 36 MHz - limited test conditions
ADC
Symbol
Parameter
Test conditions
Min
Typ
Max Unit
ENOB
SINAD
SNR
Effective number of bits
Signal-to noise and distortion ratio
Signal-to noise ratio
10.6
66
10.8
67
-
-
-
-
bits
fADC = 36 MHz
VDDA = VREF+ = 3.3 V
Input Frequency = 20 KHz
Temperature = 25 °C
64
68
dB
THD
Total harmonic distortion
-70
-72
1. Guaranteed by characterization, not tested in production.
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for I
Section 6.3.16 does not affect the ADC accuracy.
and ΣI
in
INJ(PIN)
INJ(PIN)
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Electrical characteristics
STM32F401xD STM32F401xE
Figure 40. ADC accuracy characteristics
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1. See also Table 68.
2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 41. Typical connection diagram using the ADC
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1. Refer to Table 66 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
f
ADC should be reduced.
110/135
STM32F401xD STM32F401xE
Electrical characteristics
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 42 or Figure 43,
depending on whether V is connected to V or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 42. Power supply and reference decoupling (V
not connected to V
)
DDA
REF+
STM32F
V
REF+
(See note 1)
1 µF // 10 nF
V
V
DDA
1 µF // 10 nF
/V
SSA REF-
(See note 1)
ai17535
1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When
REF+ and VREF- are not available, they are internally connected to VDDA and VSSA
V
.
Figure 43. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
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1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When
VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA
.
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114
Electrical characteristics
STM32F401xD STM32F401xE
6.3.21
Temperature sensor characteristics
Table 72. Temperature sensor characteristics
Parameter
VSENSE linearity with temperature
Symbol
Min
Typ Max
Unit
(1)
TL
-
-
1
2.5
0.76
6
2
°C
mV/°C
V
Avg_Slope(1) Average slope
-
(1)
V25
Voltage at 25 °C
Startup time
-
-
10
-
(2)
tSTART
-
µs
(2)
TS_temp
ADC sampling time when reading the temperature (1 °C accuracy)
10
-
µs
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by design, not tested in production.
Table 73. Temperature sensor calibration values
Parameter
TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V
TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F
Symbol
Memory address
0x1FFF 7A2C - 0x1FFF 7A2D
TS_CAL1
TS_CAL2
6.3.22
V
monitoring characteristics
BAT
Table 74. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
50
4
-
-
KΩ
Ratio on VBAT measurement
Error on Q
Er(1)
–1
-
+1
%
ADC sampling time when reading the VBAT
1 mV accuracy
(2)(2)
TS_vbat
5
-
-
µs
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.23
Embedded reference voltage
The parameters given in Table 75 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 14.
DD
Table 75. Embedded internal reference voltage
Symbol
VREFINT
Parameter
Conditions
Min
Max
Unit
Typ
Internal reference voltage
–40 °C < TA < +105 °C 1.18 1.21
1.24
V
ADC sampling time when reading the
internal reference voltage
(1)
TS_vrefint
-
10
-
-
-
µs
Internal reference voltage spread over the
temperature range
(2)
VRERINT_s
VDD = 3V 10mV
3
5
mV
112/135
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Electrical characteristics
Table 75. Embedded internal reference voltage (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Typ
(2)
TCoeff
Temperature coefficient
Startup time
-
-
-
-
30
6
50
10
ppm/°C
µs
(2)
tSTART
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production
Table 76. Internal reference voltage calibration values
Symbol
Parameter
Memory address
Raw data acquired at temperature of
30 °C VDDA = 3.3 V
VREFIN_CAL
0x1FFF 7A2A - 0x1FFF 7A2B
6.3.24
SD/SDIO MMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Table 77 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, f
frequency and V
PCLK2
DD
supply voltage conditions summarized in Table 14, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
Figure 44. SDIO high-speed mode
t
t
r
f
t
C
t
t
W(CKH)
W(CKL)
CK
t
t
OV
OH
D, CMD
(output)
t
t
ISU
IH
D, CMD
(input)
ai14887
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Electrical characteristics
STM32F401xD STM32F401xE
Figure 45. SD default mode
CK
t
t
OVD
OHD
D, CMD
(output)
ai14888
(1)(2)
Table 77. Dynamic characteristics: SD / MMC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
-
tW(CKL)
tW(CKH)
Clock frequency in data transfer mode
SDIO_CK/fPCLK2 frequency ratio
Clock low time
0
-
-
-
48
8/3
-
MHz
-
fpp = 48MHz
fpp = 48MHz
8.5
8.3
9
ns
ns
ns
ns
ns
Clock high time
10
-
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU
tIH
Input setup time HS
Input hold time HS
fpp = 48MHz
fpp = 48MHz
3.5
0
-
-
-
-
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV
tOH
Output valid time HS
Output hold time HS
fpp = 48MHz
fpp = 48MHz
-
4.5
-
7
-
3
CMD, D inputs (referenced to CK) in SD default mode
tISUD
tIHD
Input setup time SD
Input hold time SD
fpp = 24MHz
fpp = 24MHz
1.5
0.5
-
-
-
-
CMD, D outputs (referenced to CK) in SD default mode
tOVD
tOHD
Output valid default time SD
Output hold default time SD
fpp =24MHz
fpp =24MHz
-
4.5
-
6.5
-
3.5
1. Data based on characterization results, not tested in production.
2. VDD = 2.7 to 3.6 V.
6.3.25
RTC characteristics
Table 78. RTC characteristics
Symbol
Parameter
Conditions
Min
Max
Any read/write operation
from/to an RTC register
-
fPCLK1/RTCCLK frequency ratio
4
-
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STM32F401xD STM32F401xE
Package characteristics
7
Package characteristics
7.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
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Package characteristics
STM32F401xD STM32F401xE
7.1.1
WLCSP49, 3.06 x 3.06 mm, 0.4 mm pitch wafer level chip
size package
Figure 46. WLCSP49 wafer level chip size package outline
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1. Drawing is not to scale.
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Table 79. STM32F401xCE WLCSP49 wafer level chip size package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
0.525
-
0.555
0.175
0.585
-
0.0207
-
0.0219
0.0069
0.0230
-
A1
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Package characteristics
Table 79. STM32F401xCE WLCSP49 wafer level chip size package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A2
A3(2)
b(3)
D
-
0.380
0.025
0.250
3.029
3.029
0.400
2.400
2.400
0.3145
0.3145
0.100
0.100
0.100
0.050
0.050
-
-
0.0150
0.0010
0.0098
0.1193
0.1193
0.0157
0.0945
0.0945
0.0124
0.0124
0.0039
0.0039
0.0039
0.0020
0.0020
-
-
-
-
-
0.220
0.280
0.0087
0.0110
2.994
3.064
0.1179
0.1206
E
2.994
3.064
0.1179
0.1206
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
e1
e2
F
G
aaa
bbb
ccc
ddd
eee
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Figure 47. WLCSP49 0.4 mm pitch wafer level chip size recommended footprint
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133
Package characteristics
STM32F401xD STM32F401xE
Table 80. WLCSP49 recommended PCB design rules (0.4 mm pitch)
Dimension
Recommended values
Pitch
0.4 mm
260 µm max. (circular)
220 µm recommended
Dpad
Dsm
300 µm min. (for 260 µm diameter pad)
PCB pad design
Non-solder mask defined via underbump allowed
Device marking
Figure 48. Example of WLCSP49 marking (top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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STM32F401xD STM32F401xE
Package characteristics
7.1.2
UFQFPN48, 7 x 7 mm, 0.5 mm pitch package
Figure 49. UFQFPN48, 7 x 7 mm, 0.5 mm pitch, package outline
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1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
Table 81. UFQFPN48, 7 x 7 mm, 0.5 mm pitch, package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
D
0.500
0.000
6.900
6.900
5.500
5.500
0.300
0.550
0.020
7.000
7.000
5.600
5.600
0.400
0.600
0.050
7.100
7.100
5.700
5.700
0.500
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0118
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0157
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
0.0197
E
D2
E2
L
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Package characteristics
STM32F401xD STM32F401xE
Table 81. UFQFPN48, 7 x 7 mm, 0.5 mm pitch, package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
T
b
e
-
0.200
-
0.152
0.250
0.500
-
0.300
-
-
0.0079
-
0.0060
0.0098
0.0197
-
0.0118
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 50. UFQFPN48 recommended footprint
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1. Dimensions are in millimeters.
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Device marking
Package characteristics
Figure 51. Example of UFQFPN48 marking (top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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Package characteristics
STM32F401xD STM32F401xE
7.1.3
LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package
Figure 52. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline
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1. Drawing is not to scale.
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Package characteristics
Table 82. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
b
-
-
1.60
-
-
0.0630
0.05
-
0.15
0.0020
-
0.0059
1.35
1.40
0.22
-
1.45
0.0531
0.0551
0.0087
-
0.0571
0.17
0.27
0.0067
0.0106
c
0.09
0.20
0.0035
0.0079
D
-
12.00
10.00
12.00
10.00
0.50
3.5°
0.60
1.00
-
-
0.4724
0.3937
0.4724
0.3937
0.0197
3.5°
-
D1
E
-
-
-
-
-
-
-
-
E1
e
-
-
-
-
-
-
-
-
K
0°
0.45
-
7°
0.75
-
0°
0.0177
-
7°
0.0295
-
L
0.0236
0.0394
L1
Number of pins
64
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 53. LQFP64 recommended footprint
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AIꢂꢍꢑꢊꢑC
1. Dimensions are in millimeters.
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Package characteristics
STM32F401xD STM32F401xE
Device marking
Figure 54. Example of LQFP64 marking (top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
124/135
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STM32F401xD STM32F401xE
Package characteristics
7.1.4
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
Figure 55. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline
3%!4).' 0,!.%
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1. Drawing is not to scale.
DocID025644 Rev 3
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Package characteristics
STM32F401xD STM32F401xE
Table 83. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
b
-
-
-
1.6
0.15
1.45
0.27
0.2
16.2
14.2
-
-
-
0.063
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
-
0.05
1.35
0.17
0.09
15.8
13.8
-
0.002
0.0531
0.0067
0.0035
0.622
0.5433
-
-
1.4
0.22
-
0.0551
0.0087
-
c
D
16
14
12
16
14
12
0.5
0.6
1
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
D1
D3
E
15.8
13.8
-
16.2
14.2
-
0.622
0.5433
-
0.6378
0.5591
-
E1
E3
e
-
-
-
-
L
0.45
-
0.75
-
0.0177
-
0.0295
-
L1
K
0.0°
3.5°
0.08
7.0°
0.0°
7.0°
ccc
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
Figure 56. LQFP100 recommended footprint
ꢈꢌ
ꢌꢂ
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1. Dimensions are in millimeters.
Device marking
Figure 57. Example of LQPF100 marking (top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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133
Package characteristics
STM32F401xD STM32F401xE
7.1.5
UFBGA100, 7 x 7 mm, 0.5 mm pitch package
Figure 58. UFBGA100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package outline
= 6HDWLQJꢈSODQH
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HHH 0 = < ;
III 0 =
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723ꢈ9,(:
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1. Drawing is not to scale.
Table 84. UFBGA100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package
mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
A3
A4
b
0.460
0.050
0.400
-
0.530
0.080
0.450
0.130
0.320
0.250
7.000
5.500
7.000
5.500
0.500
0.750
0.600
0.110
0.500
-
0.0181
0.0020
0.0157
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0098
0.2756
0.2165
0.2756
0.2165
0.0197
0.0295
0.0236
0.0043
0.0197
-
0.270
0.200
6.950
5.450
6.950
5.450
-
0.370
0.300
7.050
5.550
7.050
5.550
-
0.0106
0.0079
0.2736
0.2146
0.2736
0.2146
-
0.0146
0.0118
0.2776
0.2185
0.2776
0.2185
-
D
D1
E
E1
e
F
0.700
0.800
0.0276
0.0315
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Package characteristics
Table 84. UFBGA100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package
mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
ddd
eee
fff
-
-
-
-
-
-
0.100
0.150
0.050
-
-
-
-
-
-
0.0039
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 59. Recommended PCB design rules for pads (0.5 mm-pitch BGA)
0.5 mm
Pitch
D pad
0.27 mm
0.35 mm typ (depends on
the soldermask registration
tolerance)
Dsm
Solder paste
0.27 mm aperture diameter
Dpad
Dsm
ai15495
1. Non solder mask defined (NSMD) pads are recommended.
2. 4 to 6 mils solder paste screen printing process.
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Package characteristics
STM32F401xD STM32F401xE
Device marking
Figure 60. Example of UFBGA100 marking (top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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Package characteristics
7.2
Thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
Table 14: General operating conditions on page 60.
The maximum chip-junction temperature, T max., in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (PD max x Θ )
J
A
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
PD max is the sum of P
max and P max (PD max = P
max + P max),
INT I/O
INT
I/O
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 85. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
UFQFPN48
32
51
50
42
56
Thermal resistance junction-ambient
WLCSP49
Thermal resistance junction-ambient
LQFP64
ΘJA
°C/W
Thermal resistance junction-ambient
LQFP100
Thermal resistance junction-ambient
UFBGA100
7.2.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
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Part numbering
STM32F401xD STM32F401xE
8
Part numbering
Table 86. Ordering information scheme
STM32 401 C E Y 6 TR
Example:
F
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Device subfamily
401 = 401 family
Pin count
C = 48/49 pins
R = 64 pins
V = 100 pins
Flash memory size
D = 384 Kbytes of Flash memory
E = 512 Kbytes of Flash memory
Package
H = UFBGA
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C
Packing
TR = tape and reel
No character = tray or tube
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Part numbering
Table 87. Device order codes
Order codes
Reference
STM32F401CDY6, STM32F401RDT6, STM32F401VDT6, STM32F401CDU6,
STM32F401VDH6
STM32F401xD
STM32F401CEY6, STM32F401RET6, STM32F401VET6, STM32F401CEU6,
STM32F401VEH6
STM32F401xE
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Revision history
STM32F401xD STM32F401xE
9
Revision history
Table 88. Document revision history
Date
Revision
Changes
16-Jan-2014
1
Initial release.
Updated Flash memory size in Table 2:
STM32F401xD/xE features and peripheral counts.
24-Feb-2014
2
Added alternate functions mapped on PCx, PDx and
PEx GPIOS in Table 9: Alternate function mapping
Updated UFQFPN48 in Table 3: Regulator ON/OFF and
internal power supply supervisor availability.
Updated number of EXTI lines in Section 3.10: External
interrupt/event controller (EXTI).
Updated Table 54: I/O static characteristics
Added WLCSP49 Figure 47: WLCSP49 0.4 mm pitch
wafer level chip size recommended footprint and
Table 80: WLCSP49 recommended PCB design rules
(0.4 mm pitch). Updated Figure 48: Example of
WLCSP49 marking (top view).
22-Jan-2015
3
Updated Figure 51: Example of UFQFPN48 marking
(top view).
Updated Figure 54: Example of LQFP64 marking (top
view).
Updated Figure 57: Example of LQPF100 marking (top
view).
Updated Figure 60: Example of UFBGA100 marking
(top view).
Added notes below all engineering sample marking
schematics.
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