STCOM05 [STMICROELECTRONICS]
Powerline communication and application system-on-chip;
| 型号： | STCOM05 |
| 厂家： | 
ST |
| 描述： | Powerline communication and application system-on-chip |
| 文件： | 总58页 (文件大小：707K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STCOM
Powerline communication and application system-on-chip
Datasheet - production data
– 5 USARTs (ISO 7816 compliant), 5 SPI,
2
3 I C
– 12-bit general purpose ADC with
6 channels
Cryptographic engine
– AES 128/192/256 engine
TQFP176 (20 x 20 x 1 mm)
– True random number generator
Memories
Features
– 640 kB or 1 MB of embedded Flash
– 128 kB of embedded SRAM
Integrated differential PLC analog front-end
– PGA with automatic gain control and ADC
– Current DAC with transmission predriver
– Digital transmission level control
– 8 kB of embedded shared RAM
– Flexible static memory controller
Clock management
– 24 MHz external crystal for system clock
with internal QFS synthesizer
– Zero crossing comparator
– Up to 500 kHz PLC signal bandwidth
– 32.768 kHz external crystal for RTC
Integrated dual line driver
Power management
– 14 V p-p single ended, 28 V p-p differential
output range
– 3.3 V and 8 - 18 V external supply voltages
– 1.2 V and 5 V integrated linear regulators
– Normal and low power modes
– Very high linearity for EMC compliance
– Externally configurable amplifier topology
– 1 A rms max. current
Real-time clock (RTC)
– Embedded overtemperature protection
– Suitable for all PLC signals up to 500 kHz
– VBAT supply with battery health monitoring
for RTC and backup registers
-40 °C to +85 °C operating temperature range
Fully reprogrammable real-time engine (RTE)
modem for PLC standards up to 500 kHz
®
Applications
Integrated application core: ARM 32-bit
Cortex™-M4F CPU
Smart metering, smart grid and “Internet of
– 96 MHz maximum frequency
– 8-channel direct memory access controller
– 8-region memory protection unit
– Serial wire and JTAG interfaces
– Cortex-M4 Embedded Trace Macrocell™
– Up to 86 multiplexed GPIOs
– 11 timers
Things” applications
Compliant with CENELEC, FCC, ARIB
regulations
– 1 flexible CRC calculation unit
October 2015
DocID028515 Rev 1
1/58
This is information on a product in full production.
www.st.com
Contents
STCOM
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
1.2
Device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power line communication (PLC) sub-system . . . . . . . . . . . . . . . . . . . . . . 9
1.2.1
1.2.2
1.2.3
1.2.4
Real-time engine (RTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Digital front-end (DFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Analog front-end (AFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Line driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3
Application core sub-system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
®
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.3.9
ARM Cortex™-M4F core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Floating point unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 11
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Debug and trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
General purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 16
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timers and watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3.10 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 18
1.3.11 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4
Cryptographic engine (CRYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4.1
1.4.2
True random number generator (TRNG) . . . . . . . . . . . . . . . . . . . . . . . . 19
Pseudo random number generator (PRNG) . . . . . . . . . . . . . . . . . . . . . 19
1.5
1.6
Interprocessor communication (IPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.6.1
1.6.2
1.6.3
1.6.4
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
One-time programmable (OTP) section . . . . . . . . . . . . . . . . . . . . . . . . . 20
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 21
1.7
1.8
Reset, control, clock generation (RCC) and system controller
(SYS_CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Contents
1.9
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.10 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 27
1.11 Temperature sensors and overtemperature protection . . . . . . . . . . . . . . 28
1.12 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.13 System reprogrammability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.13.1 In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.13.2 In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2
Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.1
2.2
Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
GPIOs multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3
4
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1
4.2
4.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PLC analog front-end (AFE) and line driver characteristics . . . . . . . . . . . 50
4.4
4.4.1
4.4.2
4.4.3
Line driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Line driver test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
AFE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.5
Embedded Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.1
5.2
TQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6
7
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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58
List of tables
STCOM
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Cortex™-M4F core configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Interrupt definition and position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DMA channels muxing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Embedded Flash sectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Boot mode and security level relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Boot modes and BOOT0/1 pin values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
GPIOs multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Absolute maximum ratings - voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Absolute maximum ratings - current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Analog supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Digital supply characteristics - RTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Digital supply characteristics - Cortex™-M4 fetching from RAM . . . . . . . . . . . . . . . . . . . . 47
Digital supply characteristics - Cortex™-M4 fetching data from eFlash . . . . . . . . . . . . . . . 47
Digital supply characteristics - DOZE (sleep)/deepsleep mode . . . . . . . . . . . . . . . . . . . . . 47
Supply characteristics - QFS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
24 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
32 kHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Digital supply characteristics - I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Digital supply characteristics - power consumption under battery . . . . . . . . . . . . . . . . . . . 49
Line driver characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Predriver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Receiver input referred noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
PLC PGA characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Zero crossing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Flash memory current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
TQFP176 (20 x 20 x 1 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
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STCOM
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STCOM basic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STCOM detailed architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset, clock and system controller interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STCOM clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power supply scheme - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power supply scheme - PLC AFE and line driver section. . . . . . . . . . . . . . . . . . . . . . . . . . 26
TQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Line driver test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 10. TQFP176 (20 x 20 x 1 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DocID028515 Rev 1
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58
Description
STCOM
1
Description
The STCOM is a device that integrates a power line communication (PLC) modem
and a high-performance application core.
The PLC modem architecture has been designed to target EN50065, FCC, ARIB compliant
PLC applications. Together with the application core, it enables the STCOM to support the
®
PRIME, G1, G3, IEEE 1901.2, METERS AND MORE and other narrow band PLC protocol
specifications.
The STCOM basic block diagram is shown in Figure 1.
Figure 1. STCOM basic block diagram
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6/58
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STCOM
Description
1.1
Device architecture
The architecture is composed of the following parts:
1. PLC front-end including digital front-end and analog front-end
2. PLC line driver
3. Real-time engine: the digital core running the lower layers of the PLC protocol stack
and implementing modulation and demodulation
4. Protocol engine: the main digital core for running the upper layers of the PLC protocol
stack
5. Wide range of peripherals logically divided into 4 blocks:
–
–
–
–
Basic peripherals
Com1 peripherals
Com2 peripherals
Crypto peripherals.
The STCOM detailed architecture is shown in Figure 2.
DocID028515 Rev 1
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58
Description
STCOM
Figure 2. STCOM detailed architecture
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8/58
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STCOM
Description
1.2
Power line communication (PLC) sub-system
The STCOM device embeds a full narrow band power line communication (NB-PLC) sub-
system, comprising the RTE, DFE, AFE and line driver.
The AFE and line driver have been designed for a differential power line interface; however,
single-ended operation is possible for simpler hardware application development.
The DC to 500 kHz signal bandwidth is supported, targeting a number of possible NB-PLC
solutions.
1.2.1
1.2.2
Real-time engine (RTE)
To match a performance required by emerging NB-PLC standards, the STCOM embeds
a proprietary dedicated reprogrammable machine, the real-time engine. It is able to address
specific functionalities exploited by OFDM and the ones adopted in the current and future
NB- PLC standards in an efficient way.
Digital front-end (DFE)
Transmission and reception filter chains
The DFE includes programmable transmission/reception digital filter chains to fit the signal
bandwidth in different PLC modulation cases. The ADC and DAC clock frequencies are
controlled by the DFE to get the right sample rate fitting the filter chain configuration.
Automatic gain control (AGC)
The DFE implements the automatic gain control (AGC) block for the PGA, whose purpose is
to adapt the signal to the ADC dynamic.
Current control (CC)
The DFE includes also the current control (CC) block for the line driver to limit the maximum
output current.
1.2.3
Analog front-end (AFE)
Receiving chain
The STCOM AFE features a programmable gain amplifier (PGA) and a dedicated analog-to-
digital converter (ADC) to achieve high RX sensitivity and a wide input range.
Transmission chain
The transmitted signal, generated in the digital domain, is fed into a dedicated digital-to-
analog converter (DAC).
The DAC output is then fed into a predriver for buffering and applying an additional gain
before the line driver.
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Zero crossing comparator
The mains line zero crossing can be detected by providing a mains synchronous bipolar
(AC) signal at the input of this comparator.
The zero crossing comparator provides positive and negative event information
(rising/falling edge or high/low level).
1.2.4
Line driver
The STCOM is equipped with an integrated high-performance dual power line driver. It has
very low distortion, allowing the device to comply with EMC requirements.
When supplied at maximum voltage, the line driver is capable to provide 28 V p-p in
differential configuration or 14 V p-p in single-ended configuration.
The output current can reach 1 A rms in both differential and single-ended configurations, in
order to drive very low power line impedance.
Any overtemperature event will force the line driver to shut down, thus preventing the
STCOM to get damaged.
1.3
Application core sub-system
®
1.3.1
ARM Cortex™-M4F core
The Cortex™-M4 processor is built on a high-performance processor core, with a 3-stage
pipeline Harvard architecture, making it ideal for demanding embedded applications. The
processor delivers exceptional power efficiency through an efficient instruction set and
extensively optimized design, providing high end processing hardware including IEEE754-
compliant single precision (32-bit) floating point computation, a range of a single cycle and
SIMD multiplication and multiply with accumulate capabilities, saturating arithmetic and
dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex™-M4 processor implements
tightly coupled system components that reduce processor area while significantly improving
interrupt handling and system debug capabilities. The Cortex™-M4 processor implements
®
®
a version of the Thumb instruction set based on Thumb-2 technology, ensuring high code
density and reduced program memory requirements. The Cortex™-M4 instruction set
provides the exceptional performance expected of a modern 32-bit architecture, with the
high code density of 8-bit and 16-bit microcontrollers.
The Cortex™-M4 processor provides multiple interfaces using AMBA™ technology to
provide high-speed, low latency memory accesses. It supports unaligned data accesses
and implements atomic bit manipulation that enables faster peripheral controls, system
spinlocks and thread-safe Boolean data handling.
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Description
Table 1. Cortex™-M4F core configuration
Comment
Component
Presence
JTAG
ETM
Yes
Yes
Yes
Yes
Yes
Yes
N/A
N/A
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Full-featured debug access port (DAP), SWJ-DP and AHB access port
Embedded Trace Macrocell present
ITM
Instrumentation Trace Macrocell
TPIU
Trace port unit interface present
FPB
Flash patch breakpoint
DWT
Data watchpoint and trace
DEBUG level
IRQ
Full debug with data matching for watchpoint generation
80 IRQ source
Priority level
MPU
Set to 5:32 levels
Memory protection unit present. 8 regions implemented
Floating point unit present (single precision)
Bit banding region present
FPU
BB
RESET_ALL_REGS
CLKGATE
WIC
Reset all synchronous state
Possibility to minimize dynamic power dissipation by clock gating
10 lines: NMI, WWDG, RTC, GPIOs, IPC, DMA, GPT0, SPI0 and USART0
1.3.2
Floating point unit (FPU)
The FPU fully supports single precision add, subtract, multiply, divide, multiply and
accumulate, and square root operations. It also provides conversions between the fixed
point and floating point data formats, and floating point constant instructions.
The FPU provides floating point operations that are compliant with the NSI/IEEE Std 754-
©
2008 A, IEEE Standard for Binary Floating-point Arithmetic , referred to as the IEEE 754
Standard.
The FPU contains 32 single precision extension registers, which can also be accessible as
16 double word registers for load, store, and move operations.
1.3.3
Nested vectored interrupt controller (NVIC)
The STCOM embeds a NVIC able to handle 80 maskable interrupts. The software priority
level is configurable in the range of 0 - 31 for each interrupt. A higher level corresponds to
a lower priority, so the level 0 is the highest interrupt priority. In case two or more interrupt
lines share the same software priority level, the hardware priority level, which is described in
Table 2, is used.
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Table 2. Interrupt definition and position
Position Priority
Acronym
Description
Reset
-
-
-3
-2
-1
0
Reset
NMI
Wake-up interrupt - non maskable interrupt - system error
All class of fault
-
HardFault
-
MemManage
BusFault
MPU mismatch
-
1
Prefetch fault, memory access fault
Undefined instruction or illegal state
System service call via SWI instruction
Debug monitor
-
2
UsageFault
SVCall
-
3
-
4
DebugMonitor
PendSV
-
5
Pendable request for system service
System tick timer
-
6
SysTick
0
7
WDG_WIC
RTC_WIC
Wake-up interrupt - window watchdog
Wake-up interrupt - RTC interrupts
Reserved
1
8
2
9
-
3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
GPIO_WIC
IPC_WIC
Wake-up interrupt - GPIO interrupts
Wake-up interrupt - IPC interrupts
Wake-up interrupt - DMAC interrupts
Wake-up interrupt - GPT0 global interrupt
Wake-up interrupt - SPI0 global interrupt
Wake-up interrupt - USART0 global interrupt
Reserved
4
5
DMAC_WIC
GPT0_WIC
SPI0_WIC
6
7
8
USART0_WIC
-
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TAMPER
Tamper pin interrupt
RTC
Real-time clock
FLASH_FATAL_ERROR
FLASH_ECC_RWW_ERROR
FLASH_ARY_DONE
IPC_MBOX
IPC_QUEUES
IPC_SHAREDRAM
DMA_Ch(1)
DMA_Ch(2)
DMA_Ch(3)
DMA_Ch(4)
DMA_Ch(5)
DMA_Ch(6)
DMA_Ch(7)
Flash interface
Flash interface
Flash interface
IPC mailbox
IPC queues
IPC shared memory
DMA global interrupt channel 1
DMA global interrupt channel 2
DMA global interrupt channel 3
DMA global interrupt channel 4
DMA global interrupt channel 5
DMA global interrupt channel 6
DMA global interrupt channel 7
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Description
Table 2. Interrupt definition and position (continued)
Position Priority
Acronym
Description
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
DMA_Ch(8)
ADC
DMA global interrupt channel 8
ADC global interrupt
Reserved
-
-
Reserved
FSMC_FILL_FIFO
SPI1
FSMC interface
SPI1 global interrupt
SPI2 global interrupt
SPI3 global interrupt
SPI4 global interrupt
I2C0 global event interrupt
I2C0 global error interrupt
I2C1 global event interrupt
I2C1 global error interrupt
I2C2 global event interrupt
I2C2 global error interrupt
Advanced timer 0 - BRK
Advanced timer 0 - update
SPI2
SPI3
SPI4
I2C0_EVENT
I2C0_ERROR
I2C1_EVENT
I2C1_ERROR
I2C2_EVENT
I2C2_ERROR
AT0_BRK
AT0_UP
AT0_TRG_COM
AT0_CC
AT1_BRK
AT1_UP
AT1_TRG_COM
AT1_CC
GPT1
Advanced timer 0 - trigger and commutation (COM)
Advanced timer 0 - 4 CAPCOM
Advanced timer 1 - BRK
Advanced timer 1 - update
Advanced timer 1 - trigger and commutation (COM)
Advanced timer 1 - 4 CAPCOM
GPT1 - global interrupt
GPT2
GPT2 - global interrupt
GPT3
GPT3 - global interrupt
USART1
USART2
USART3
USART4
CAN0
USART1 global interrupt
USART2 global interrupt
USART3 global interrupt
USART4global interrupt
CAN0 global interrupt
CAN1
CAN1 global interrupt
AES
AES global interrupt
GPIO00
GPIO00 global interrupt
GPIO01
GPIO01 global interrupt
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Table 2. Interrupt definition and position (continued)
Position Priority
Acronym
Description
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
GPIO02
GPIO03
GPIO04
GPIO05
GPIO06
GPIO07
GPIO08
GPIO09
GPIO10
GPT4
GPT5
GPT6
GPT7
-
GPIO02 global interrupt
GPIO03 global interrupt
GPIO04 global interrupt
GPIO05 global interrupt
GPIO06 global interrupt
GPIO07 global interrupt
GPIO08 global interrupt
GPIO09 global interrupt
GPIO10 global interrupt
GPT4 - global interrupt
GPT5 - global interrupt
GPT6 - global interrupt
GPT7 - global interrupt
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
1.3.4
DMA controller (DMA)
The STCOM embeds 1 general purpose dual port DMA controller with 8 channels. It is able
to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers.
It features dedicated FIFOs for APB/AHB peripherals, a supports burst transfer and is
designed to provide the maximum peripheral bandwidth (AHB/APB).
The DMA controller supports circular buffer management, so that no specific code is needed
when the controller reaches the end of the buffer. It also has a double buffering feature,
which automates the use and switching of two memory buffers without requiring any special
code.
Each channel is connected to dedicated hardware DMA requests, with support for
a software trigger on each stream. Configuration is made by software and transfer sizes
between source and destination are independent.
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Table 3. DMA channels muxing scheme
Peripheral
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8(1)
ADC
SPI0
ADC
SPI0_TX
SPI2_TX
SPI0_RX
SPI2_RX
SPI1
SPI1_TX
SPI3_TX
SPI1_RX
SPI3_RX
SPI2
SPI3
SPI4
SPI4_TX
SPI4_RX
USART0
USART1
USART2
USART3
USART4
I2C0
USART0_TX USART0_RX
USART3_TX USART3_RX
USART1_TX USART1_RX
USART2_TX USART2_RX
USART4_TX USART4_RX
I2C0_TX
AT0_CH4
I2C0_RX
I2C1
I2C1_TX
AT0_CH1
AT0_CH3
I2C1_RX
AT0_CH2
I2C2
I2C2_TX
I2C2_RX
AT0
AT0_TRIG
AT0_COM
AT1
AT0_UP
AT1_CH3
AT1_TRIG
AT1_COM
AT1_CH4
GPT0
AT1_UP
AT1_CH1
GPT1_UP
AT1_CH2
GPT2_UP
GPT0_UP
GPT1
GPT2
GPT3
GPT3_UP
GPT4
GPT4_UP
GPT5
GPT5_UP
GPT6
GPT6_UP
GPT7
GPT7_UP
1. Channel 8 is reserved.
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1.3.5
Memory protection unit (MPU)
The MPU divides the memory map into up to 8 regions, and defines the location, size,
access permissions, and memory attributes of each region. It supports:
Independent attribute settings for each region
Overlapping regions
Export of memory attributes to the system.
Background region
When memory regions overlap, memory access is affected by the attributes of the region
with the highest number.
The background region has the same memory access attributes as the default memory
map, but is accessible from privileged software only.
The MPU is useful to isolate and protect different parts of the firmware by giving different
levels of access privileges. If a part of the firmware tries to access a memory location that is
prohibited by the MPU, the processor generates a fault. This causes a fault exception that
could be detected by the privileged firmware, which can take the appropriate action.
The MPU is optional and can be bypassed for applications that do not need it.
1.3.6
Debug and trace
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Embedded Trace Macrocell™ (ETM)
The ARM Embedded Trace Macrocell provides greater visibility of the instruction and data
flow inside the Cortex™-M4 core by streaming compressed data at a very high rate from the
STCOM device through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is then connected to a host in order to record and then
format the information for displaying and analysis.
1.3.7
General purpose input/outputs (GPIOs)
The STCOM device has 11 GPIOs ports named from GPIO00 to GPIO10. Each port is able
to manage 8 pins, except the GPIO08 port that manages 6 pins. Each GPIO pin can be
individually configured by software as output (push-pull or open drain, with or without pull-up
or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral
alternate functions (with or without pull-up or pull-down). Each GPIO pin can also generate
interrupt depending on a level (low and high), or a transactional value of the pin (rising or
falling edge).
External interrupt
Each GPIOs port can generate interrupts. For each port one interrupt line is dedicated. The
pins of one port share the same interrupt line.
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1.3.8
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (Cortex™-M4, DMA, and real-
time engine) and the slaves (Flash memory, RAM, AHB and APB peripherals, and real-time
engine) and ensures a seamless and efficient operation even when several high-speed
peripherals work simultaneously.
1.3.9
Timers and watchdog
The STCOM embeds 8 general purpose timers, two advanced timers and one window
watchdog. The Cortex™-M4 is also equipped with a SysTick timer.
General purpose timer (GPT)
The STCOM device includes 8 full-featured general purpose timers based on a 16-bit
autoreload up/down counter and a 16-bit programmable prescaler.
Advanced timers (AT)
The STCOM includes 2 advanced-control timers based on a 16-bit autoreload up/down
counter driven by a 16-bit programmable prescaler. They all feature 4 independent channels
for input capture, output compare, PWM generation or one pulse mode output.
It may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM,
complementary PWM with deadtime insertion).
Window watchdog (WWDG)
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interference or by unforeseen logical conditions, which causes the
application program to abandon its normal sequence. The watchdog circuit generates
a device reset on expiry of a programmed time period, unless the program refreshes the
contents of the down counter register. A device reset is also generated if the down counter
value is refreshed before the down counter has reached the proper window register value.
This implies that the counter must be refreshed in a limited window.
The window watchdog is based on a 7-bit free-running down counter with two conditional
resets: the down counter is reloaded outside the window or the down counter value
becomes less than 0x40.
The window watchdog supports early wake-up interrupt trigged when the down counter is
equal to 0x40.
SysTick timer
The Cortex™-M4 has a 24-bit system timer, SysTick, which counts down from the
programmable reload value to zero. It supports the autoreload and can generate
a maskable system interrupt when the counter reaches zero.
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1.3.10
CRC (cyclic redundancy check) calculation unit
The cyclic redundancy check (CRC) is a widely used method for detecting errors. The CRC
calculation unit is used to get a CRC code in a flexible way using a configurable polynomial.
Output data size can be selected between 8, 16, 24 or 32 bits.
Input data size can be configured between 1, 8, 16, 24 or 32 bits with selectable bit and byte
endianness.
The CRC unit allows the specification of the initial value (all zero, all one, or a generic value)
and the possibility to select an automatic XOR with all one when reading the data output.
1.3.11
Communication interfaces
Inter-integrated circuit interface (I2C)
2
The STCOM embeds 3 I C bus interfaces that can operate in multimaster and slave modes.
They can support the Standard and Fast modes. They support the 7/10-bit addressing mode
and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is
embedded.
2
The I C peripherals can be served by DMA and support SMBus 2.0/PMBus™ operations.
Universal synchronous/asynchronous receiver transmitters (USART)
The STCOM embeds 5 universal synchronous/asynchronous receiver transmitters.
®
These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,
a multiprocessor communication mode, single-wire half-duplex communication mode and
have an LIN Master/Slave capability.
The peripherals also provide hardware management of the CTS and RTS signals,
a Smartcard mode (ISO 7816 compliant) and a SPI-like communication capability. All
interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)
The STCOM embeds 5 SPIs in slave and master modes in full-duplex and simplex
communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame
is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic
SD Card™/MMC™ modes. All SPIs can be served by the DMA controller.
The SPI interface can be configured to operate in a TI™ mode for communications in
master mode and slave mode.
Controller area network (CAN)
The STCOM embeds 2 CAN modules able to perform communication according to the CAN
protocol version 2.0 part A and B. The bitrate can be programmed to values up to
1 MBit/s. For communication on a CAN network, individual message objects are configured.
Each message object has its own identifier mask. The message objects and identifier masks
are stored in the 256 byte size message RAM with a programmable FIFO mode. All
functions concerning the handling of messages are implemented in the message handler.
Those functions are the acceptance filtering, the transfer of messages between the CAN
core and the message RAM, and the handling of transmission requests as well as the
generation of the module interrupt.
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General purpose analog-to-digital converter (ADC)
One 12-bit SAR ADC working at a maximum conversion rate of 2 Msps is embedded in the
STCOM. The ADC has 6 external available input channels performing conversion in
a single, continuous or scan mode. The core accesses to the peripheral through a 4x12-bit
FIFO interface.
The ADC can be served by the DMA controller. Additional 2 channels are internally used to
monitor the VBAT and the low power temperature sensor.
1.4
Cryptographic engine (CRYP)
The STCOM embeds an advanced hardware AES peripheral which implements an
advanced standard cryptographic algorithm according to the NIST FIPS 197. The block
processes 128-bit data blocks using a key with the following possible sizes: 128, 192, 256
bits. The peripheral also supports the following modes: “Electronic Code Book” (ECB),
“Cipher Block Chaining” (CBC), “Counter “mode (CTR), “Galois/Counter Mode” (GCM),
GMAC and CCM modes.
The peripheral is able to encrypt and decrypt data. Interrupt can be generated when one
operation is finished.
1.4.1
1.4.2
1.5
True random number generator (TRNG)
The STCOM embeds a TRNG processor based on a continuous analog noise that provides
a random 16-bit value. To avoid pseudo random sequences, two consecutive accesses
have to be performed when the ready bit in the status register is set to 1.
Pseudo random number generator (PRNG)
The STCOM embeds a PRNG processor that provides a pseudo random 32-bit value. Initial
seed can be configured by software.
Interprocessor communication (IPC)
The Cortex™-M4 core and the real-time engine communicate by means of an additional
8 kByte shared static RAM. This memory can be accessed by the two cores through an
interprocessor communication block that guarantees coherent and consistent read and
modify operations, to provide several functionalities to the system, among the others:
Configuration of real-time engine modes and functionalities during the normal working
operations
Data and information exchange between the Cortex™-M4 and real-time engine in both
directions.
The Cortex™-M4 wake up from a low power mode triggered by the real-time engine.
The real-time engine wakes up from a low power mode triggered by the Cortex™-M4.
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1.6
Memories
1.6.1
Embedded Flash memory
The embedded Flash has the following features:
640 kB or 1 MB of size
128-bit wide data read
64-bit data write through a double 32-bit bus write
Sector erase with possibility to suspend erase procedure in case of read access to
other flash sectors
Multiple sector erase.
Table 4. Embedded Flash sectors
Block
Name
Number
Base address
Size
Note
Main memory
B0F0
B0F1
B0F2
B0F3
B0F4
B0F5
B0F6
B0F7
B0F8
B0F9
B0FA
B0FB
B0FC
B0FD
0
1
0x00000000
0x00004000
0x00008000
0x00010000
0x00018000
0x0001C000
0x00020000
0x00030000
0x00040000
0x00060000
0x00080000
0x000A0000
0x000C0000
0x000E0000
0x00100000
16 kB
16 kB
32 kB
32 kB
16 kB
16 kB
64 kB
64 kB
128 kB
128 kB
128 kB
128 kB
128 kB
128 kB
16 kB
2
3
4
5
6
7
8
9
10
11
12
13
14
Not available in STCOM05
Not available in STCOM05
Not available in STCOM05
Shadow sector B0SH
Shadow sector is accessible only in some security levels (see Section 1.12: Boot modes on
page 28).
1.6.2
One-time programmable (OTP) section
The STCOM embeds a one-time programmable (OTP) section in the shadow sector of the
embedded Flash memory. During the manufacturing process, the EUI48 is stored in this
section. The user can also write its private key used during the boot process to verify and
authenticate the firmware image. This OTP section can be configured to avoid reads by
firmware in order to protect user confidential information (see Section 1.12).
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1.6.3
Embedded SRAM
The STCOM device has 128 kB of a static RAM. The Cortex™-M4 can perform byte, half
word (16 bits) or full word (32 bits) access to the SRAM at maximum speed, with zero wait
states for both read and write operations. The SRAM start address is 0x20000000, the end
address is 0x20001FFFF.
The SRAM is split into two blocks of 64 kB with a capability for concurrent access by AHB
master sub-systems.
The Cortex™-M4 can also execute a code from the RAM at a zero wait state.
1.6.4
Flexible static memory controller (FSMC)
The STCOM embeds a FSMC peripheral able to interface external memory devices. The
types of memory supported are:
Asynchronous parallel NOR Flash with up to 21-bit address bus (no synchronous
parallel NOR supported)
Asynchronous SRAM memories
The data bus can be selected between 16 bits or 8 bits (reducing the total amount of
accessible memory), for little or big endian operation.
The FSMC peripheral can connect up to 2 memories with 2 independent chip select lines
(Ebar). The maximum size of each memory is 4 MB. Having 2 chip select lines, the
maximum external memory size is 8 MB.
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1.7
Reset, control, clock generation (RCC) and system controller
(SYS_CTRL)
All the clock and reset configuration registers are located in the MISC and SYSCTRL
blocks. Figure 3 shows the interaction between these blocks.
Figure 3. Reset, clock and system controller interaction
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The system reset is generated by the RESETn pin (active low). Through the system
controller is also possible to assert a system software reset. The software reset to single
peripherals can be forced through MISC registers.
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Description
Clock management
Two external clock sources are required for the STCOM:
1. 24 MHz frequency
2. 32.768 kHz frequency
Internal clocks are generated by a quadruple frequency synthesizer (QFS) that is fed by the
24 MHz source. Digital blocks can also use the external sources as clock reference.
The clock strategy is depicted in Figure 4.
Figure 4. STCOM clock tree
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DocID028515 Rev 1
23/58
58
Description
STCOM
At a startup the 24 MHz oscillator clock is selected. This source must be always present to
allow the STCOM starting correctly. 24 MHz can be provided by a quartz crystal or by any
other source. In this latter case, the clock must be provided through the MCLK_IN pin while
the MCLK_OUT pin must be tied to DGND. 32.768 KHz must be provided by a quartz
crystal.
APB peripherals can work up to 48 MHz. Each PCLK prescaler to the sub-systems should
be configured to respect this maximum frequency.
The general purpose ADC clock can run up to 33 MHz. The RTC core uses only the 32 KHz
external oscillator. The TRNG can work with the external 32 kHz or with the internal
cpu_hclk. If the internal clock is selected, the divisor should be configured to provide an
accurate 32 kHz clock in order to respect the requirements for a true random generation.
One master clock output line can be enabled. The MCO1 is multiplexed with one general
purpose I/O and can take one of the QFS outputs with a configurable prescaler.
1.8
Power management
The STCOM should be powered with, at least, two external supply voltages:
3.3 V for I/Os, embedded Flash, QFS, DAC, OSC, ADC general purpose, 1.2 V
regulator
8 - 18 V for line driver
The device needs also two more supply voltages that can be generated internally:
1.2 V for digital cores and logic, embedded Flash, QFS and oscillator
5 V for the PLC AFE
1.2 V and 5 V can be provided by two internal linear regulators connected respectively to
DVDD_1V2 and AVDD_5V pins and supplied respectively by DVDD_3V3_REG and PVCC
pins. A bypass mode is available for the 1.2 V regulator in case an external source is used.
The power-on reset (POR) is conditioned by the level of DVDD_3 V3_IO and DVDD_1V2: at
power on, the whole STCOM device is kept under reset until the two supply voltages are
above the respective turn-on thresholds named V(DVDD_3 V3_IO)_TH and
V(DVDD_1V2)_TH, while the device is turned off as soon as one of the voltages goes below
its turn-off thresholds, namely V(DVDD_3 V3_IO)_TL and V(DVDD_1V2)_TL.
An internal comparator checks the supply voltage on AVDD_5V_AFE as well, enabling the
use of the PLC AFE when the voltage is above V(AVDD_5V_AFE)_TH and disabling it when
the voltage goes below V(AVDD_5V_AFE)_TL.
Refer to Figure 5 and Figure 6 for the detailed power supply scheme.
24/58
DocID028515 Rev 1
STCOM
Description
Figure 5. Power supply scheme - digital section
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DocID028515 Rev 1
25/58
58
Description
STCOM
Figure 6. Power supply scheme - PLC AFE and line driver section
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26/58
DocID028515 Rev 1
STCOM
Description
VBAT operation
In case the RTC peripheral is used, the VBAT pin shall be supplied (2.0 V to 3.6 V) for the
RTC core operation and persistence of backup registers. An external battery or a similar
power source can be used.
The VBAT operation is activated, through an on-chip power switch, when the
DVDD_3V3_IO is not present. In this case the main core of the RTC and the backup
registers are under the VBAT domain.
The application can constantly monitor the health of the battery by reading the voltage level
present at the VBAT pin through the channel 7 of the general purpose 12-bit ADC.
A dedicated cutoff switch has been included to avoid continuous leakage from the battery
when the ADC is not sampling the line.
1.9
Low power modes
A clock gating is available for any peripheral in order to save all the dynamic power
contributes related the resources not used by the application.
The CPU is able to run at maximum frequency but, in case lower speed is sufficient to meet
the application requirements, also scaled values are allowed. The CPU could be in low
power modes waiting for wake-up events.
1.10
Real-time clock (RTC) and backup registers
The STCOM embeds an integrated real-time clock (RTC). The RTC provides a hardware
calendar implementation, instead of a simple 32-bit free-running counter. The calendar can
be initialized to set the current time/date of the system and provide information on sub-
seconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month),
month, and year.
Software can program the daylight saving compensation; it can control two programmable
alarms (with interrupt function) that can be triggered by any combination of the calendar
fields.
Synchronization can be done with an external clock using the sub-second shift feature.
RTC maskable interrupts/events are:
Alarms: two alarms are present
Timestamps: two timestamps are present
Tamper: two tamper detection inputs are present
The RTC is clocked with a 32.768 kHz external crystal and has coarse calibration (periodic
digital calibration), smooth calibration (0.954 ppm) and analog calibration functionalities.The
1 Hz /512 Hz internal reference clock is optionally available on RTC_TAMPB for calibration.
The RTC has also twenty 32-bit backup registers (80 bytes), available for user defined data
storage. The possibility that backup registers are reset when a tamper detection event
occurs is selectable by software.
DocID028515 Rev 1
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58
Description
STCOM
1.11
Temperature sensors and overtemperature protection
The STCOM embeds an overtemperature protection mechanism, with fixed temperature
threshold, preventing the device from overheating. This automatic protection acts by
shutting down the PLC line driver when overheating occurs during PLC transmission. The
normal operation of the line driver is restored automatically as the overtemperature event
has ended.
In addition to the overtemperature automatic protection, information from two temperature
sensors is provided:
The line driver temperature sensor
The low power temperature sensor
The first sensor monitors the line driver temperature and can be used by the RTE to prevent
the line driver to be shut down abruptly by the overtemperature protection. The way to use
this information may depend on the protocol and on the version of the RTE firmware, so its
usage (if any) will be described within the specific firmware documentation released by
®
STMicroelectronics .
The second sensor monitors the temperature of the low power section of the device. It is
internally connected to the channel 8 of the general purpose 12-bit ADC (see Section :
General purpose analog-to-digital converter (ADC) on page 19 for further details) and it can
be used by the application for its own purposes.
The accuracy of the sensors is guaranteed by design. In case a higher accuracy is required
on the low power temperature sensor, the user shall adopt its own calibration procedure
during the application manufacturing.
1.12
Boot modes
The STCOM provides different security levels of protection:
1. Level 1: unsecure
The Cortex™-M4 is accessible through the JTAG and it's possible to download the
firmware in the embedded Flash using debugger plug-in or to load it from the external
NVM using the system boot functionality. It's also possible to download customer OTP
data such as cryptography keys. The shadow sector is not accessible.
2. Level 2: secure
The JTAG is blocked and it's not possible to access the embedded Flash for external
read or write operation. It's possible to load the ciphered firmware image from the
external NVM and upgrade the firmware thanks to the IAP functionality. Read access to
TM
the embedded Flash is possible to the Cortex -M4 code, including the shadow sector.
3. Level 3: secure and locked
The JTAG is blocked and it's not possible to access the embedded Flash for external
read or write operation. Some embedded Flash sectors are locked. It's possible to
upgrade the firmware thanks to the IAP functionality unless the new image tries to
change a locked area. Read access to the embedded Flash is possible to the
TM
Cortex -M4 code, including the shadow sector.
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DocID028515 Rev 1
STCOM
Description
4. Level 4: secure for customer loader
The JTAG is blocked and it is not possible to access the embedded Flash for the
external read or write operation via the JTAG, while the read and write access is
TM
allowed to the Cortex -M4 code (with the exception of the shadow sector). With
respect to the Level 2, there is no load or upgrade of the firmware image from the
external NVM. The firmware image shall be already present in the embedded Flash
(loaded in Level 1) and a customer application (secondary bootloader) can manage
upgrades.
5. Level 1*: secure erase and unlocking
The Cortex™-M4 is accessible through the JTAG and it's possible to download
firmware in the embedded Flash. Before the unlocking, the embedded Flash is fully
erased including the customer OTP data. The shadow sector is not accessible.
In order to respect these security requirements, the STCOM embeds a bootloader code.
The user can also configure the boot mode through the BOOT0/1 pins to select the proper
mode. The following boot modes are available:
1. Normal mode: this is the standard way of booting the code and eventually load (or
restore) a new image version from the external NVM.
2. Customer OTP write mode: in this mode the user can write its security keys and data
(e.g.: custom EUI48). After booting in this mode the security level is 2 (secure) or 4
(secure for customer loader) based on the selected option. In the security level 2 only
ciphered firmware can be loaded from an external memory while in the security level 4
the firmware upgrade is left to a customer bootloader.
3. Unlocking mode: this is the boot mode that enables again all the debug feature.
4. Low power mode: the minimal boot mode to guarantee low power operations. The
TM
RTE is not enabled and the Cortex -M4 code is executed as soon as possible at 24
MHz (the user can then scale the clock up or down).
The relationship between the security level and boot mode are shown in Table 5:
Table 5. Boot mode and security level relationship
Boot
mode
Level 1
Level 2
Level 3
Level 4
Level 1*
Yes
If lock option
selected for some
area → go to level 3
Yes, but no update
is performed on
locked sector
Yes
(no update is
performed)
Normal
mode
Yes
Yes
Customer
OTP write
mode
Yes → go to level
No
No
No
No
2 or 4
Unlocking Yes → go to level
Yes → go to level
Yes → go to level Yes → go to level Yes → go to level
mode
1*
1*
1*
1*
1*
Lowpower
mode
Yes
Yes
Yes
Yes
Yes
DocID028515 Rev 1
29/58
58
Description
STCOM
Table 6 shows the values of the boot pins for each boot mode.
Table 6. Boot modes and BOOT0/1 pin values
Boot mode
Boot mode value
BOOT1
BOOT0
Normal boot
Customer OTP write
Unlocking
0x2
0x0
0x1
0x3
1
0
0
1
0
0
1
1
Low power
1.13
System reprogrammability
The STCOM supports both in-system and in-application programming (ISP and IAP) modes
through the use of the embedded Flash and an external non-volatile memory (NVM). If the
external NVM contains two firmware copies, it's also possible to roll back to the previous
firmware version in case of firmware malfunctioning. The change of firmware to enable
different functionalities will require a complete reset of the device if the customer does not
implement its own bootloader.
1.13.1
1.13.2
In-system programming (ISP)
The ISP mode allows the user to erase and program the embedded Flash through the JTAG
port. This mode can be inhibited to enhance the security level of the device.
In-application programming (IAP)
The IAP mode allows the application on board to store in an external non-volatile memory
the firmware to be downloaded into the internal embedded Flash. The firmware image in the
NVM is copied into the internal embedded Flash at the power-on. The boot code inside the
device takes care of the integrity check, embedded Flash erasure and programming. IAP
can be done using the power line or by the local upgrade port. The customer can also write
its dedicated bootloader to perform IAP with the activation of a specific security level.
30/58
DocID028515 Rev 1
STCOM
Pinout and pin description
2
Pinout and pin description
2.1
Pin definition
Figure 7. TQFP176 pinout
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DocID028515 Rev 1
31/58
58
Pinout and pin description
STCOM
Table 7. Pin description
Type(1) Dir.(2) RS(3)
Pin
Pin name
Description
General purpose I/O, SPI1_MOSI, AT1_CH_1,
FSMC_PCAD_17
1
GPIO00_3
D
D
I/O
I/O
I
I
General purpose I/O, SPI1_SS, AT1_BKIN,
FSMC_PCAD_18, USART0_SCLK
2
GPIO00_2
3
GPIO00_1
DVDD_3 V3_IO
GPIO00_0
D
S
D
D
D
D
D
D
D
S
S
S
-
I/O
I
I
I
I
I
I
I
I
I
I
-
I
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I/O 3.3 V supply
4
I
5
I/O
General purpose I/O, USART0_RTS, FSMC_PCAD_20
USART0_RXD
6
USART0_RXD
USART0_TXD
SPI0_SSn
I
7
O
USART0_TXD
8
OD
SPI0_SSn
9
SPI0_SCLK
SPI0_MISO
O
SPI0_SCLK
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
I
O
I
SPI0_MISO
SPI0_MOSI
SPI0_MOSI
DVDD_1V2_FLASH
DGND
Embedded Flash memory 1.2 V supply
Embedded Flash memory ground
Embedded Flash memory 3.3 V supply
Reserved, tie to DGND
Boot mode selector pin 0
Boot mode selector pin 1
JTAG test reset - active low
JTAG test data input
-
DVDD_3 V3_FLASH
RESERVED
BOOT0
I
-
D
D
D
D
D
D
D
S
S
A
A
S
S
S
S
S
S
A
I
I
BOOT1
I
I
JTAG_TRSTn
JTAG_TDI
I
I
I
I
JTAG_TMS
I
I
JTAG test mode select input, SWIO
JTAG test clock input, SWCLK
JTAG test data output, SWV
24 MHz oscillator 1.2 V supply
I/O 3.3 V supply
JTAG_TCK
I
I
JTAG_TDO
O
I
I
DVDD_1V2_ MCLK
DVDD_3 V3_IO
MCLK_IN
I
I
I
-
-
24 MHz oscillator input
MCLK_OUT
DVDD_3 V3_REG
DVDD_1V2
-
-
24 MHz oscillator output
3.3 V input for the 1.2 V regulator
1.2 V regulator output / external supply input
QFS 1.2 V supply
I
I
I/O
I
I/O
DVDD_1V2_QFS
DVDD_3 V3_QFS
DGND
I
I
-
I
I
I
QFS 3.3 V supply
-
QFS ground
AVDD_5V_PGA
RX_INN
I
PGA 5 V supply
I
PGA negative input
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Pin
Pinout and pin description
Table 7. Pin description (continued)
Type(1) Dir.(2) RS(3)
Pin name
Description
34
35
36
RX_INP
AGND
ZC_IN
A
S
A
I
-
I
I
-
I
PGA positive input
PGA ground
Zero crossing comparator input
Zero crossing comparator ground reference - connect to
AGND
37
ZC_AGND_REF
A
I
I
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
AVDD_5V_AFE
PVCC
S
S
S
A
A
A
A
S
S
A
A
A
A
S
A
S
-
I
I
I
I
PLC AFE 5 V supply + receiver ADC supply
PA supply
PGND
-
-
PA ground
PA2_OUT
PA2_OUT
PA1_OUT
PA1_OUT
PGND
O
O
O
O
-
O
O
O
O
-
PA2 output
PA2 output
PA1 output
PA1 output
PA ground
PVCC
I
I
PA supply / 5 V regulator input voltage
PA1 inverting input
PA1_INN
I
I
PA1_INP
I
I
PA1 non-inverting input
PA2 non-inverting input
PA2 inverting input
PA2_INP
I
I
PA2_INN
I
I
AGND
-
-
5 V regulator ground
CSF
I/O
I/O
-
I/O
I/O
-
Current sense feedback
5 V regulator output / external supply input
Reserved - connect to AGND
Transmission predriver ground
Transmission predriver positive output
Transmission predriver negative output
Transmission predriver 5 V supply
Transmission DAC 3.3 V supply
Transmission DAC ground
Transmission DAC positive output
Transmission DAC negative output
I/O 3.3 V supply
AVDD_5V
RESERVED
AGND
S
A
A
S
S
S
A
A
S
-
-
TXDRV_OUTP
TXDRV_OUTN
AVDD_5V_TXDRV
AVDD_3 V3_DAC
AGND
O
O
I
O
O
I
I
I
-
-
DAC_OUTP
DAC_OUTN
DVDD_3 V3_IO
O
O
I
O
O
I
General purpose I/O, USART4_SCLK, AT0_BKIN,
SPI2_SSn, I2C2_SCL
64
65
GPIO10_7
GPIO10_6
D
D
I/O
I/O
I
I
General purpose I/O, USART4_TXD, AT0_CH_1,
SPI2_SCLK, I2C2_SDA
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58
Pinout and pin description
STCOM
Table 7. Pin description (continued)
Type(1) Dir.(2) RS(3)
Description
Pin
Pin name
General purpose I/O, USART4_RXD, AT0_CH_2,
SPI2_MISO, I2C0_SCL
66
GPIO10_5
D
D
D
D
I/O
I/O
I/O
I/O
I
I
I
I
General purpose I/O, USART4_CTS, AT0_CH_3,
SPI2_MOSI, I2C0_SDA
67
68
69
GPIO10_4
GPIO10_3
GPIO10_2
General purpose I/O, USART4_RTS, AT0_CH_4,
USART3_CTS, I2C2_SMBA
General purpose I/O, AT0_CHN_1, USART3_RTS,
I2C0_SMBA
70
71
72
73
74
75
GPIO10_1
GPIO10_0
D
D
S
S
D
D
I/O
I/O
I
I
I
General purpose I/O, AT0_CHN_2, USART3_RXD
General purpose I/O, AT0_CHN_3, USART3_TXD
3.3 V input for the 1.2 V regulator
DVDD_3 V3_REG
DVDD_1V2
RESETn
I
I/O
I/O
1.2 V regulator output / external supply input
Reset input, open drain output - active low
I/OD I/OD
GPIO09_7
I/O
I/O
I
I
General purpose I/O, AT0_ETR, ETM_SWO, SPI4_SCLK
General purpose I/O, USART3_SCLK, ETM_DATA_3,
SPI4_MISO
76
GPIO09_6
D
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
GPIO09_5
GPIO09_4
GPIO09_3
GPIO09_2
GPIO09_1
GPIO09_0
DVDD_3 V3_IO
N. C.
D
D
D
D
D
D
S
-
I/O
I
I
General purpose I/O, ETM_DATA_2, SPI4_MOSI
General purpose I/O, ETM_DATA_1, SPI4_SSn
General purpose I/O, ETM_DATA_0, USART2_CTS
General purpose I/O, ETM_CLKOUT, USART2_RTS
General purpose I/O, CAN1_RX, USART2_RXD
General purpose I/O, CAN1_TX, USART2_TXD
I/O 3.3 V supply
I/O
I/O
I
I/O
I
I/O
I
I/O
I
I
-
I
-
-
-
-
-
-
-
-
-
-
-
-
I
Not connected
N. C.
-
-
Not connected
N. C.
-
-
Not connected
N. C.
-
-
Not connected
N. C.
-
-
Not connected
N. C.
-
-
Not connected
N. C.
-
-
Not connected
N. C.
-
-
Not connected
N. C.
-
-
Not connected
N. C.
-
-
Not connected
N. C.
-
-
Not connected
N. C.
-
-
Not connected
RTC_TAMPB
D
I/O
Tamper input B, RTC clock output
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Pin
Pinout and pin description
Table 7. Pin description (continued)
Type(1) Dir.(2) RS(3)
Pin name
Description
97
98
RTC_TAMPA
VBAT
D
S
S
A
A
A
A
I
I
I
-
-
I
I
I
I
I
-
-
I
I
Tamper input A
2.0 to 3.6 V battery supply input
I/O 3.3 V supply
99
DVDD_3 V3_IO
OSC32_OUT
OSC32_IN
100
101
102
103
32 kHz oscillator output
32 kHz oscillator input
ADC_VREFN
ADC_VREFP
General purpose ADC negative reference voltage input
General purpose ADC positive reference voltage input
General purpose I/O, ADC_MUX_VIN_5, SPI3_SSn,
USART2_SCLK
104
105
106
GPIO08_5
GPIO08_4
GPIO08_3
D
D
D
I/O
I/O
I/O
I
I
I
General purpose I/O, ADC_MUX_VIN_4, SPI3_SCLK
General purpose I/O, ADC_MUX_VIN_3, USART1_CTS,
SPI3_MISO
General purpose I/O, ADC_MUX_VIN_2, USART1_RTS,
SPI3_MOSI
107
108
109
GPIO08_2
GPIO08_1
GPIO08_0
D
D
D
I/O
I/O
I/O
I
I
I
General purpose I/O, ADC_MUX_VIN_1, USART1_RXD,
I2C1_SCL
General purpose I/O, ADC_MUX_VIN_0, USART1_TXD,
I2C1_SDA, AT1_ETR
110
111
112
113
114
115
116
117
118
119
120
121
GPIO07_7
GPIO07_6
GPIO07_5
GPIO07_4
GPIO07_3
GPIO07_2
GPIO07_1
GPIO07_0
GPIO06_7
GPIO06_6
GPIO06_5
GPIO06_4
D
D
D
D
D
D
D
D
D
D
D
D
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
General purpose I/O, AT1_CHN_3, SPI1_SCLK
General purpose I/O, AT1_CHN_2, SPI1_MISO
General purpose I/O, AT1_CHN_1, SPI1_MOSI
General purpose I/O, AT1_CH_4, SPI1_SSn
General purpose I/O, AT1_CH_3
General purpose I/O, AT1_CH_2
General purpose I/O, AT1_CH_1, CAN0_RX
General purpose I/O, AT1_BKIN, CAN0_TX
General purpose I/O, SPI4_SSn, ETM_SWO
General purpose I/O, SPI4_SCLK, ETM_DATA_3
General purpose I/O, SPI4_MISO, ETM_DATA_2
General purpose I/O, SPI4_MOSI, ETM_DATA_1
General purpose I/O, USART3_CTS, I2C1_SCL,
ETM_DATA_0
122
123
124
GPIO06_3
GPIO06_2
GPIO06_1
D
D
D
I/O
I/O
I/O
I
I
I
General purpose I/O, USART3_RTS, I2C1_SDA,
ETM_CLKOUT
General purpose I/O, USART3_RXD, I2C1_SMBA,
I2C2_SCL
125
126
GPIO06_0
GPIO05_7
D
D
I/O
I/O
I
I
General purpose I/O, USART3_TXD, I2C2_SDA
General purpose I/O, USART3_SCLK, I2C2_SMBA
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58
Pinout and pin description
STCOM
Table 7. Pin description (continued)
Type(1) Dir.(2) RS(3)
Description
Pin
Pin name
127
128
129
130
131
132
GPIO05_6
GPIO05_5
D
D
D
S
D
D
I/O
I/O
I/O
I
I
I
I
I
I
I
General purpose I/O, USART0_CTS
General purpose I/O, USART0_RTS
General purpose I/O, MCO1
I/O 3.3 V supply
GPIO05_4
DVDD_3 V3_IO
GPIO05_3
I/O
I/O
General purpose I/O, FSMC_Ebar_1
GPIO05_2
General purpose I/O, USART2_SCLK, FSMC_Ebar_0
General purpose I/O, USART2_RXD, SPI2_SSn,
FSMC_BLn_0
133
GPIO05_1
D
I/O
I
General purpose I/O, USART2_TXD, SPI2_SCLK,
FSMC_BLn_1
134
135
136
GPIO05_0
DVDD_3 V3_IO
GPIO04_7
D
S
D
I/O
I
I
I
I
I/O 3.3 V supply
General purpose I/O, USART2_CTS, SPI2_MISO,
FSMC_PCDA_0
I/O
General purpose I/O, USART2_RTS, SPI2_MOSI,
FSMC_PCDA_1, MCO1
137
GPIO04_6
D
I/O
I
138
139
140
141
142
143
144
145
146
GPIO04_5
GPIO04_4
GPIO04_3
GPIO04_2
GPIO04_1
GPIO04_0
GPIO03_7
GPIO03_6
GPIO03_5
D
D
D
D
D
D
D
D
D
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
General purpose I/O, FSMC_PCDA_2
General purpose I/O, FSMC_PCDA_3
General purpose I/O, FSMC_PCDA_4
General purpose I/O, FSMC_PCDA_5
General purpose I/O, FSMC_PCDA_6
General purpose I/O, FSMC_PCDA_7
General purpose I/O, SPI3_SSn, FSMC_PCDA_8
General purpose I/O, SPI3_SCLK, FSMC_PCDA_9
General purpose I/O, SPI3_MISO, FSMC_PCDA_10
General purpose I/O, SPI3_MOSI, FSMC_PCDA_11,
USART3_SCLK
147
148
149
150
151
GPIO03_4
GPIO03_3
GPIO03_2
GPIO03_1
GPIO03_0
D
D
D
D
D
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
General purpose I/O, SPI2_SSn, USART3_CTS,
FSMC_PCDA_12
General purpose I/O, SPI2_SCLK, USART3_RTS,
FSMC_PCDA_13
General purpose I/O, SPI2_MISO, USART3_RXD,
FSMC_PCDA_14
General purpose I/O, SPI2_MOSI, USART3_TXD,
FSMC_PCDA_15
152
153
154
155
DVDD_1V2
DVDD_3 V3_REG
DVDD_3 V3_IO
RESERVED
S
S
S
-
I/O
I/O
1.2 V regulator output / external supply input
3.3 V input for the 1.2 V regulator
I/O 3.3 V supply
I
I
I
I
-
-
Reserved - connect to DGND
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Pinout and pin description
Table 7. Pin description (continued)
Type(1) Dir.(2) RS(3)
Description
Pin
Pin name
General purpose I/O, AT0_BKIN, FSMC_Lbar,
USART4_SCLK
156
GPIO02_7
D
D
D
D
I/O
I/O
I/O
I/O
I
I
I
I
General purpose I/O, AT0_CH_1, FSMC_PCWEn,
USART4_TXD
157
158
159
GPIO02_6
GPIO02_5
GPIO02_4
General purpose I/O, AT0_CHN_1, FSMC_PCOEn,
USART4_RXD
General purpose I/O, AT0_CH_2, FSMC_PCAD_0,
USART4_CTS
General purpose I/O, AT0_CHN_2, FSMC_PCAD_1,
USART4_RTS
160
161
162
GPIO02_3
GPIO02_2
GPIO02_1
D
D
D
I/O
I/O
I/O
I
I
I
General purpose I/O, AT0_CH_3, FSMC_PCAD_2
General purpose I/O, AT0_CHN_3, I2C2_SCL,
FSMC_PCAD_3
General purpose I/O, AT0_CH_4, I2C2_SDA,
FSMC_PCAD_4
163
164
165
166
167
168
169
170
171
172
173
GPIO02_0
GPIO01_7
GPIO01_6
GPIO01_5
GPIO01_4
GPIO01_3
GPIO01_2
GPIO01_1
GPIO01_0
GPIO00_7
GPIO00_6
D
D
D
D
D
D
D
D
D
D
D
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
General purpose I/O, AT0_ETR, I2C2_SMBA,
FSMC_PCAD_5, I2C1_SMBA
General purpose I/O, I2C1_SCL, CAN1_RX,
FSMC_PCAD_6
General purpose I/O, I2C1_SDA, CAN1_TX,
FSMC_PCAD_7
General purpose I/O, USART1_CTS, CAN0_RX,
FSMC_PCAD_8
General purpose I/O, USART1_RTS, CAN0_TX,
FSMC_PCAD_9
General purpose I/O, USART1_RXD, AT1_ETR,
FSMC_PCAD_10
General purpose I/O, USART1_TXD, AT1_CHN_3,
FSMC_PCAD_11
General purpose I/O, I2C0_SMBA, AT1_CHN_2,
FSMC_PCAD_12, USART1_SCLK
General purpose I/O, I2C0_SCL, AT1_CHN_1,
FSMC_PCAD_13
General purpose I/O, I2C0_SDA, AT1_CH_4,
FSMC_PCAD_14
General purpose I/O, SPI1_SCLK, AT1_CH_3,
FSMC_PCAD_15
174
175
GPIO00_5
D
S
I/O
I
I
I
DVDD_3 V3_IO
I/O 3.3 V supply
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58
Pinout and pin description
STCOM
Table 7. Pin description (continued)
Type(1) Dir.(2) RS(3)
Description
Pin
Pin name
General purpose I/O, SPI1_MISO, AT1_CH_2,
FSMC_PCAD_16
176
177
GPIO00_4
EXPAD
D
S
I/O
-
I
-
Exposed pad - DGND
1. Type: D = digital; A = analog; S = supply/ground.
2. Direction: I = input; O = output; I/O = input/output, OD = open drain.
3. Reset status: I = input, I/O = input/output, O = output.
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Pinout and pin description
2.2
GPIOs multiplexing scheme
In the STCOM, peripherals are connected to I/Os through a multiplexer. At a time one single
peripheral can control the I/Os. In this way, there is no conflict between peripherals sharing
the same I/O pins.
Thanks to a set of configuration registers, the user can select one of the 4 possible alternate
functions for each pin as described in Table 8.
Table 8. GPIOs multiplexing scheme
Pin name
Selection: 000
Selection: 001
Selection: 010
Selection: 011
GPIO00_0
GPIO00_1
GPIO00_2
GPIO00_3
GPIO00_4
GPIO00_5
GPIO00_6
GPIO00_7
GPIO01_0
GPIO01_1
GPIO01_2
GPIO01_3
GPIO01_4
GPIO01_5
GPIO01_6
GPIO01_7
GPIO02_0
GPIO02_1
GPIO02_2
GPIO02_3
GPIO02_4
GPIO02_5
GPIO02_6
GPIO02_7
GPIO03_0
GPIO03_1
GPIO03_2
GPIO03_3
GPIO03_4
USART0_RTS
USART0_CTS
SPI1_SS
FSMC_PCAD_20
FSMC_PCAD_19
FSMC_PCAD_18
FSMC_PCAD_17
FSMC_PCAD_16
FSMC_PCAD_15
FSMC_PCAD_14
FSMC_PCAD_13
FSMC_PCAD_12
FSMC_PCAD_11
FSMC_PCAD_10
FSMC_PCAD_9
FSMC_PCAD_8
FSMC_PCAD_7
FSMC_PCAD_6
FSMC_PCAD_5
FSMC_PCAD_4
FSMC_PCAD_3
FSMC_PCAD_2
FSMC_PCAD_1
FSMC_PCAD_0
FSMC_PCOEn
AT1_BKIN
AT1_CH_1
AT1_CH_2
AT1_CH_3
AT1_CH_4
AT1_CHN_1
AT1_CHN_2
AT1_CHN_3
AT1_ETR
USART0_SCLK
SPI1_MOSI
SPI1_MISO
SPI1_SCLK
I2C0_SDA
I2C0_SCL
I2C0_SMBA
USART1_TXD
USART1_RXD
USART1_RTS
USART1_CTS
I2C1_SDA
USART1_SCLK
CAN0_TX
CAN0_RX
CAN1_TX
CAN1_RX
I2C2_SMBA
I2C2_SDA
I2C2_SCL
I2C1_SCL
AT0_ETR
I2C1_SMBA
AT0_CH_4
AT0_CHN_3
AT0_CH_3
AT0_CHN_2
AT0_CH_2
AT0_CHN_1
AT0_CH_1
AT0_BKIN
USART4_RTS
USART4_CTS
USART4_RXD
USART4_TXD
USART4_SCLK
FSMC_PCWEn
FSMC_Lbar
SPI2_MOSI
SPI2_MISO
SPI2_SCLK
SPI2_SS
USART3_TXD
USART3_RXD
USART3_RTS
USART3_CTS
FSMC_PCDA_15
FSMC_PCDA_14
FSMC_PCDA_13
FSMC_PCDA_12
FSMC_PCDA_11
SPI3_MOSI
USART3_SCLK
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Pinout and pin description
STCOM
Table 8. GPIOs multiplexing scheme (continued)
Pin name
Selection: 000
Selection: 001
Selection: 010
Selection: 011
GPIO03_5
GPIO03_6
GPIO03_7
GPIO04_0
GPIO04_1
GPIO04_2
GPIO04_3
GPIO04_4
GPIO04_5
GPIO04_6
GPIO04_7
GPIO05_0
GPIO05_1
GPIO05_2
GPIO05_3
GPIO05_4
GPIO05_5
GPIO05_6
GPIO05_7
GPIO06_0
GPIO06_1
GPIO06_2
GPIO06_3
GPIO06_4
GPIO06_5
GPIO06_6
GPIO06_7
GPIO07_0
GPIO07_1
GPIO07_2
GPIO07_3
GPIO07_4
GPIO07_5
GPIO07_6
GPIO07_7
SPI3_MISO
SPI3_SCLK
SPI3_SS
FSMC_PCDA_10
FSMC_PCDA_9
FSMC_PCDA_8
FSMC_PCDA_7
FSMC_PCDA_6
FSMC_PCDA_5
FSMC_PCDA_4
FSMC_PCDA_3
FSMC_PCDA_2
FSMC_PCDA_1
FSMC_PCDA_0
FSMC_BLn_1
USART2_RTS
USART2_CTS
USART2_TXD
USART2_RXD
USART2_SCLK
SPI2_MOSI
SPI2_MISO
SPI2_SCLK
SPI2_SS
FSMC_BLn_0
FSMC_Ebar_0
FSMC_Ebar_1
MCO1
USART0_RTS
USART0_CTS
USART3_SCLK
USART3_TXD
USART3_RXD
USART3_RTS
USART3_CTS
SPI4_MOSI
SPI4_MISO
SPI4_SCLK
SPI4_SS
I2C2_SMBA
I2C2_SDA
I2C2_SCL
I2C1_SMBA
I2C1_SDA
I2C1_SCL
ETM_CLKOUT
ETM_DATA_0
ETM_DATA_1
ETM_DATA_2
ETM_DATA_3
ETM_SWO
AT1_BKIN
CAN0_TX
CAN0_RX
AT1_CH_1
AT1_CH_2
AT1_CH_3
AT1_CH_4
SPI1_SS
SPI1_MOSI
SPI1_MISO
SPI1_SCLK
AT1_CHN_1
AT1_CHN_2
AT1_CHN_3
40/58
DocID028515 Rev 1
STCOM
Pinout and pin description
Table 8. GPIOs multiplexing scheme (continued)
Pin name
Selection: 000
Selection: 001
Selection: 010
Selection: 011
GPIO08_0
GPIO08_1
GPIO08_2
GPIO08_3
GPIO08_4
GPIO08_5
GPIO09_0
GPIO09_1
GPIO09_2
GPIO09_3
GPIO09_4
GPIO09_5
GPIO09_6
GPIO09_7
GPIO10_0
GPIO10_1
GPIO10_2
GPIO10_3
GPIO10_4
GPIO10_5
GPIO10_6
GPIO10_7
ADC_CH_0
ADC_CH_1
ADC_CH_2
ADC_CH_3
ADC_CH_4
ADC_CH_5
USART1_TXD
USART1_RXD
USART1_RTS
USART1_CTS
I2C1_SDA
I2C1_SCL
AT1_ETR
SPI3_MOSI
SPI3_MISO
SPI3_SCLK
SPI3_SS
USART2_SCLK
USART2_TXD
USART2_RXD
USART2_RTS
USART2_CTS
SPI4_SS
CAN1_TX
CAN1_RX
ETM_CLKOUT
ETM_DATA_0
ETM_DATA_1
ETM_DATA_2
ETM_DATA_3
ETM_SWO
USART3_TXD
USART3_RXD
USART3_RTS
USART3_CTS
SPI2_MOSI
SPI2_MISO
SPI2_SCLK
SPI2_SS
1SPI4_MOSI
SPI4_MISO
USART3_SCLK
AT0_ETR
SPI4_SCLK
AT0_CHN_3
AT0_CHN_2
AT0_CHN_1
AT0_CH_4
AT0_CH_3
AT0_CH_2
AT0_CH_1
AT0_BKIN
I2C0_SMBA
I2C2_SMBA
I2C0_SDA
I2C0_SCL
I2C2_SDA
I2C2_SCL
USART4_RTS
USART4_CTS
USART4_RXD
USART4_TXD
USART4_SCLK
DocID028515 Rev 1
41/58
58
Memory map
STCOM
3
Memory map
Figure 8. Memory map
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42/58
DocID028515 Rev 1
STCOM
Electrical characteristics
4
Electrical characteristics
4.1
Absolute maximum ratings
Table 9. Absolute maximum ratings - voltage
Symbol
Parameter
Min.
Max.
Unit
PVCC
Line driver supply voltage range
PGND -0.3
AGND -0.3
20
V
V
AVDD_5V
5 V internal regulator voltage range
Min. (5.5, PVCC +0.3)
AVDD_5V_AFE,
5 V PLC AFE supply voltage range
AGND -0.3
Min. (5.5, PVCC +0.3)
V
AVDD_5V_PGA,
AVDD_5V_TXDRV
AVDD_3 V3_DAC 3.3 V PLC AFE supply voltage range
AGND -0.3
GND-0.3
5.2
5.2
5.2
2.4
2.4
V
V
V
V
V
V
DVDD_3 V3_IO,
I/O supply voltage range
DVD_3 V3_REG
DVDD_3 V3_QFS 3.3 V QFS supply voltage range
DGND -0.3
GND -0.3
GND -0.3
GND -0.3
DVDD_1V2,
1.2 V digital supply voltage range
DVDD_1V2_FLASH
DVDD_1V2_QFS
ADC_VREFP
1.2 V QFS supply voltage range
General purpose ADC positive reference
voltage range
Min. (5.2,
DVDD_3V3_IO + 0.3)
General purpose ADC negative
reference voltage range
Min. (5.2,
DVDD_3V3_IO + 0.3)
ADC_VREFN
GND -0.3
V
VBAT
DGND, AGND
PGND
VBAT voltage range
GND -0.3
GND -0.3
AGND -0.3
5.2
V
V
V
Variations between different ground pins
Variations between different ground pins
GND +0.3
AGND +0.3
Min. (5.2,
DVDD_3V3_IO + 0.3)
V(DIG_IN)
Input voltage range
GND -0.3
V
PA_OUT
PA_IN
PA output pins voltage range
PA input pins voltage range
RX_IN input pins voltage range
PGND -0.3
AGND -0.3
-5.5
Min. (20, PVCC +0.3)
Min. (20, PVCC +0.3)
9
V
V
V
RX_IN
Min. (5.5,
AVDD_5V_ AFE +0.3)
ZC_IN
ZC_IN voltage range
-5.5
V
V
Min. (5.2,
AVDD_5V_ AFE +0.3)
DAC_OUT
DAC output pins voltage range
AGND -0.3
Min (. 5.5,
AVDD_5V_ AFE +0.3)
TXDRV_OUT
CSF
TXDRV output voltage range
CSF pin voltage range
AGND -0.3
AGND-0.3
GND-0.3
V
V
V
AVDD_5V +0.3
Min. (5.2,
DVDD_3 V3_IO+0.3)
V(MCLK)
24 MHz oscillator pins voltage range
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Table 9. Absolute maximum ratings - voltage (continued)
Symbol
Parameter
Min.
Max.
Unit
Min. (5.2,
DVDD_3V3_IO + 0.3)
V(OSC32)
32 kHz oscillator pins voltage range
GND-0.3
V
Maximum withstanding voltage range
Test condition:
V(ESD)
ANSI-ESDA-JEDEC_JS-001 “human
body model” acceptance criteria: “normal
performance”
-2
+2
kV
Table 10. Absolute maximum ratings - current
Symbol
Parameter
Min.
Max.
Unit
I(PA_OUT)
PA repetitive RMS current
1.5
A rms
4.2
Thermal characteristics
Table 11. Thermal characteristics
Parameter Conditions
Junction temperature
Symbol
Min.
Max.
Unit
T(J)
125
85
°C
°C
°C
T(AMB)
T(STG)
Operating ambient temperature
Storage temperature
-40
-50
150
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Electrical characteristics
4.3
Operating conditions
T(AMB) = -40 to +85 °C, T(J) < 125 °C, PVCC = 18 V unless otherwise specified.
All typical values are referred to T(AMB) = 25 °C.
Power supply characteristics
Table 12. Analog supply characteristics
Symbol
Parameter(1)
Conditions
Min. Typ. Max. Unit
V(PVCC)
Line driver supply voltage
8
15
18
V
Line driver supply current
Rx mode
I(PVCC)_RX
No load on AVDD_5V
No load on AVDD_5V
500
A
40
20
mA
mA
Dual power amplifier
configuration
Line driver supply current
Tx mode, no load
I(PVCC)_TX
No load on AVDD_5V
Single power amplifier
configuration
Line driver supply voltage
turn-on threshold
V(PVCC)_TH
V(PVCC)_TL
7
V
V
Line driver supply voltage
turn-off threshold
6.5
Line driver supply voltage
hysteresis
V(PVCC)_HYST
V(AVDD_5V)
0.5
5
V
V
5 V regulator output
voltage , no load
4.5
5.5
5 V PLC AFE supply
voltage turn-on threshold
V(AVDD_5V_AFE)_TH
V(AVDD_5V_AFE)_TL
V(AVDD_5V_AFE)_HYST
4.33
4.26
60
V
5 V PLC AFE supply
voltage turn-off threshold
V
5 V PLC AFE supply
voltage hysteresis
mV
mA
See(2)
5 V PLC AFE supply
current Rx mode
54
PGA maximum gain
See(2)
I(5V)_RX
I(5V)_TX
5 V PLC AFE supply
current Rx active mode
PGA maximum gain
Rx in progress
61
mA
5 V PLC AFE supply
current Tx mode, no load
See(2)
9
1.6
6
mA
mA
mA
I(AVDD_3V3_DAC)
RX
3.3 V PLC AFE supply
current Rx mode
I(AVDD_3V3_DAC)
TX
DAC full scale current = 4 mA
Sine wave output f = 100 kHz
3.3 V PLC AFE supply
current Tx mode
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Electrical characteristics
STCOM
Table 12. Analog supply characteristics (continued)
Symbol
Parameter(1)
Conditions
Min. Typ. Max. Unit
V(DVDD_3V3_IO)
Digital I/O supply voltage
3.0
3.3
3.6
V
V
Digital I/O supply voltage
turn-on threshold
V(DVDD_3V3_IO)_TH
V(DVDD_3V3_IO)_TL
V(DVDD_3V3_IO)_HYST
V(DVDD_3V3_REG)
2.82
Digital I/O supply voltage
turn-off threshold
2.7
0.1
3.3
V
V
V
Digital I/O supply voltage
hysteresis
1.2 V regulator input
voltage
Low power mode
1.233
1.285
V
V
1.2 V regulator output
voltage
V(DVDD_1V2)
I(DVDD_1V2)
High power mode
Low power mode
High power mode
15
mA
1.2 V regulator output
current
300 mA
V
1.2 V supply voltage
turn-on threshold
V(DVDD_1V2)_TH
V(DVDD_1V2)_TL
Low and high power modes
Low and high power modes
1.11
1.2 V supply voltage
turn-off threshold
1.025
V
Low power mode
High power mode
86
86
mV
mV
1.2 V supply voltage
hysteresis
V(DVDD_1V2)_HYST
1. Based on characterization, not tested in production.
2. I(5 V) = I(AVDD_5V_AFE) + I(AVDD_5V_PGA) + I(AVDD_5V_TXDRV).
Table 13. Digital supply characteristics - RTE
Parameter(1)
Conditions
1.2 V digital supply current RTE frequency = 48 MHz see(2)
Symbol
Min. Typ. Max. Unit
I(DVDD_1V2)
I(DVDD_1V2)
29
68
mA
mA
(2)
1.2 V digital supply current RTE frequency = 120 MHz see
1. Based on characterization, not tested in production.
2. The tests are performed with the following enabled digital blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I2C, AES,
TRNG, QFS. Cortex™ frequency equals to 48 MHz and Cortex™ fetching by RAM. The value is calculated by measuring
the difference in the supply current with and without RTE enabled and running.
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Electrical characteristics
Table 14. Digital supply characteristics - Cortex™-M4 fetching from RAM
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
I(DVDD_1V2) 1.2 V digital supply current
I(DVDD_3V3) 3.3 V digital supply current
I(DVDD_1V2) 1.2 V digital supply current
I(DVDD_3V3) 3.3 V digital supply current
I(DVDD_1V2) 1.2 V digital supply current
I(DVDD_3V3) 3.3 V digital supply current
I(DVDD_1V2) 1.2 V digital supply current
I(DVDD_3V3) 3.3 V digital supply current
Cortex™ frequency = 24 MHz see(1)
Cortex™ frequency = 24 MHz see(1)
Cortex™ frequency = 48 MHz see(1)
Cortex™ frequency = 48 MHz see(1)
Cortex™ frequency = 72 MHz see(1)
Cortex™ frequency = 72 MHz see(1)
Cortex™ frequency = 96 MHz see(1)
Cortex™ frequency = 96 MHz see(1)
9.6
0.9
mA
mA
mA
mA
mA
mA
mA
mA
16.4
0.9
23.8
0.9
30.9
0.9
1. All the tests are performed with the following enabled digital blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I2C, AES,
TRNG, QFS.
Table 15. Digital supply characteristics - Cortex™-M4 fetching data from eFlash
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
I(DVDD_1V2) 1.2 V digital supply current
I(DVDD_3V3) 3.3 V digital supply current
I(DVDD_1V2) 1.2 V digital supply current
I(DVDD_3V3) 3.3 V digital supply current
I(DVDD_1V2) 1.2 V digital supply current
I(DVDD_3V3) 3.3 V digital supply current
I(DVDD_1V2) 1.2 V digital supply current
I(DVDD_3V3) 3.3 V digital supply current
Cortex™ frequency = 24 MHz see(1)
Cortex™ frequency = 24 MHz see(1)
Cortex™ frequency = 48 MHz see(1)
Cortex™ frequency = 48 MHz see(1)
Cortex™ frequency = 72 MHz see(1)
Cortex™ frequency = 72 MHz see(1)
Cortex™ frequency = 96 MHz see(1)
Cortex™ frequency = 96 MHz see(1)
11.2
3.5
mA
mA
mA
mA
mA
mA
mA
mA
17.6
3.6
24.2
3.7
30.6
3.8
1. All the tests are performed with the following enabled digital blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I2C, AES,
TRNG, QFS.
Table 16. Digital supply characteristics - DOZE (sleep)/deepsleep mode
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
I(DVDD_1V2) 1.2 V digital supply current
I(DVDD_3V3) 3.3 V digital supply current
I(DVDD_1V2) 1.2 V digital supply current
I(DVDD_3V3) 3.3 V digital supply current
Cortex™ in DOZE mode see(1)
Cortex™ in DOZE mode see(1)
Cortex™ in deepsleep mode see(1)
Cortex™ in deepsleep mode see(1)
6.5
0.9
6.5
0.9
mA
mA
mA
mA
1. The test is performed with the following enabled digital blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I2C, AES,
TRNG.
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58
Electrical characteristics
Symbol
STCOM
Table 17. Supply characteristics - QFS
Parameter
Conditions
Min. Typ. Max. Unit
QFS power consumption from 1.2 V
power supply
I(DVDD_1V2_QFS)
I(DVDD_3V3_QFS)
Master clock = 24 MHz see(1)
5.1
1.1
mA
mA
QFS power consumption from 3.3 V
power supply
Master clock = 24 MHz see(1)
1. The test is performed with the following enabled digital blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I2C, AES,
TRNG. The value is calculated by measuring the difference in the supply current with and without QFS enabled and running.
Table 18. 24 MHz oscillator
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
f(MCLK)
Crystal oscillator frequency
24
MHz
pF
External quartz crystal
Shunt capacitance
C0
ESR
CL
3.5
60
15
External quartz crystal ESR value
See(1)
See(1)
MCLK_IN , MCLK_OUT load
capacitance
10
pF
1. Guaranteed by design, not tested in production.
Table 19. 32 kHz oscillator
Parameter Conditions
Symbol
Min. Typ. Max. Unit
f(OSC32)
Crystal oscillator frequency
32.768
0.9
kHz
pF
External quartz crystal
Shunt capacitance
C0
ESR
CL
External quartz crystal ESR value See(1)
60
k
pF
External quartz crystal load
See(1)
12.5
capacitance
1. Guaranteed by design, not tested in production.
Table 20. Digital supply characteristics - I/O
Conditions
Symbol
Parameter
Min. Typ. Max. Unit
3.3 V I/O digital
supply current
I(DVDD_3V3_IO)
8 GPIO toggling at 0.5 MHz with Cext ~= 50 pF see(1)
8 GPIO toggling at 1 MHz with Cext ~= 50 pF see(1)
8 GPIO toggling at 8 MHz with Cext ~= 50 pF see(1)
23.0
24.9
49.4
mA
mA
mA
3.3 V I/O digital
supply current
I(DVDD_3V3_IO)
I(DVDD_3V3_IO)
3.3 V I/O digital
supply current
1. The tests are performed with the following enabled digital blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I2C, AES,
TRNG, QFS. Cortex™ frequency equals to 96 MHz and Cortex™ fetching by RAM. The values are calculated by measuring
the difference in the supply current with and without 8 GPIOs enabled and toggling at the given frequency.
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Electrical characteristics
Table 21. I/O characteristics
Parameter(1)
Symbol
I (I/O)
Conditions
Min. Typ. Max. Unit
Output current sunk by any I/Os and control pin
Output current source by any I/Os and control pin
See(1)
See(1)
8
mA
8
1. Guaranteed by design, not tested in production.
Table 22. Digital supply characteristics - power consumption under battery
Parameter Conditions Min. Typ. Max. Unit
I(DVDD_VBAT) Digital supply current under VBAT
Symbol
1.3
A
DocID028515 Rev 1
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58
Electrical characteristics
STCOM
4.4
PLC analog front-end (AFE) and line driver characteristics
4.4.1
Line driver characteristics
Table 23. Line driver characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Power amplifier output
Bias voltage
V(PAx_OUT)
BIAS
PVCC/2
V
- Rx mode
Power amplifier
GBWP
149
MHz
Gain-bandwidth product
I(PAx_OUT)
MAX
Power amplifier
Maximum output current
1000 mA rms
V(PAx_OUT) Power amplifier output
HD2
nd harmonic distortion
V(PAx_OUT) Power amplifier output
HD3
rd harmonic distortion
V(PAx_OUT) Power amplifier output
THD Total harmonic distortion
V(PAx_OUT) Power amplifier output
HD2
2nd harmonic distortion
V(PAx_OUT) Power amplifier output
HD3
rd harmonic distortion
V(PAx_OUT) Power amplifier output
THD Total harmonic distortion
-64
-67
-61
-57
-58
-54
dBc
dBc
dB
VCC = 18 V,
2
V(PA_OUT) = 13 Vpp,
Rload = 50 Ω,
3
f = 100 kHz
V(PA_OUT) DC = PVCC/2
dBc
dBc
dB
VCC = 18 V,
V(PA_OUT) = 13 Vpp,
Rload = 50 Ω,
3
f = 500 kHz
V(PA_OUT) DC = PVCC/2
PA_IN+ vs. VSS (see(1)
)
10
10
pF
pF
dB
dB
C(PAx_INP), Power amplifier Input
C(PAx_INN) capacitance
PA_IN- vs. VSS (see(1)
)
50 Hz
1 kHz
-100
-88
PSRR
Power supply rejection ratio
Ratio between PA_OUT and
CSF output current
CSF_RATIO
106
1. Not tested in production, guaranteed by design.
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DocID028515 Rev 1
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Electrical characteristics
4.4.2
Line driver test circuit
Figure 9. Line driver test circuit
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4.4.3
AFE characteristics
Transmission path characteristics
Table 24. DAC characteristics
Conditions
Symbol
Parameter
Min.
Typ.
Max. Unit
I(DAC_OUT)
CURRENT
Rx mode, current measured on both
outputs
DAC output current
0
mA
I(DAC_OUT)
CURRENT
Tx mode, current measured on both
outputs
DAC output current
4
1
mA
Vpp
dBc
V(DAC_OUT) Tx mode, differential
V(DAC_OUT) DAC output 2nd
Rload = 120 ± 1%
-76
HD2
harmonic distortion
R(DAC_OUT) = 120
Fclk = 20 MHz
V(DAC_OUT) DAC output 3rd
-83
-74
-74
-82
-73
dBc
dBc
dBc
dBc
dBc
HD3 harmonic distortion
Fout = 100 kHz
V(DAC_OUT) DAC output total
THD harmonic distortion
V(DAC_OUT) DAC output 2nd
HD2 harmonic distortion
R(DAC_OUT) = 120
Fclk = 20 MHz
V(DAC_OUT) DAC output 3rd
HD3 harmonic distortion
Fout = 500 kHz
V(DAC_OUT) DAC output total
THD harmonic distortion
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Electrical characteristics
STCOM
Table 25. Predriver characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max. Unit
Transmitter output bias
voltage
V(TX_OUT) BIAS
Rx mode
AVDD_5V_TXDRV/2
V
-
Predriver load impedance
1
k
dBc
Transmitter output 2nd
V(TX_OUT) HD2
-76
-83
-74
-74
-82
-73
harmonic distortion - see(1)
V(TX_OUT) = 4.7 V
pk-pk, no load,
Transmitter output 3rd
V(TX_OUT) HD3
V(TX_OUT) THD
V(TX_OUT) HD2
V(TX_OUT) HD3
V(TX_OUT) THD
dBc
dB
harmonic distortion see(1)
Fout = 100 KHz
Transmitter output total
harmonic distortion see(1)
Transmitter output 2nd
dBc
dBc
dB
harmonic distortion - see(1)
V(TX_OUT) = 4.7 V
pk-pk, no load,
Transmitter output 3rd
harmonic distortion see(1)
Fout = 500 KHz
Transmitter output total
harmonic distortion see(1)
1. DAC + predriver chain distortion.
Reception path characteristics
Table 26. Receiver input referred noise
Conditions
Symbol
Parameter
Min. Typ. Max. Unit
CENELEC-A (35 kHz to 95 kHz)
CENELEC -B (95 kHz to 125 kHz)
16
12
8
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
CENELEC -C (125 kHz to 140 kHz)
V(RX_INP -
RX_INN)
Receiver input referred noise CENELEC -D (140 kHz to 148 kHz)
ARIB STD-T84 (35 kHz to 400 kHz)
5
22
17
21
FCC-LOW (35 kHz to 125 kHz)
G3-FCC (150 kHz to 490 kHz)
Table 27. PLC PGA characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max. Unit
V(RX_INP),
V(RX_INN)
Receiver input maximum voltage
Single-ended mode
10
20
V p-p
V(RX_INP-
RX_INN)
Receiver input maximum voltage
Differential mode
V p-p
AVDDD_5
V_PGA/2
-
-
Receiver input bias voltage
Receiver input impedance
V
5.2
k
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Electrical characteristics
Table 27. PLC PGA characteristics
Symbol
GPGA(PLC)
Parameter
Conditions
Min.
Typ.
Max. Unit
PLC PGA minimum gain
PLC PGA maximum gain
-12
42
6
dB
dB
dB
GPGA(PLC)_Step PLC PGA gain step
Table 28. ADC characteristics
Conditions
Parameter
Min.
Typ.
Max. Unit
ADC input range
Resolution
Differential mode
5
V p-p
bit
12
Zero crossing comparator characteristics
Table 29. Zero crossing characteristics
Parameter Conditions
Symbol
Min.
Typ.
Max.
Unit
Zero crossing
Detection input
Voltage range
V(ZC_IN)
MAX
10
V p-p
Zero crossing
Detection input
Low threshold
V(ZC_IN)
TL
-6
mV
mV
Zero crossing
Detection input
High threshold
V(ZC_IN)
TH
+6
ZC_IN
d.c.
Zero crossing
Input duty cycle
50
%
ZC_IN delay Mains zero crossing to detection delay time
5.8
s
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58
Electrical characteristics
STCOM
4.5
Embedded Flash characteristics
Table 30. Flash memory characteristics
Symbol
Parameter(1)
Conditions
Min. Typ.(2) Max.(3) Max.(4) Unit
tDWPRG Double word program
Not including SW overhead
Not including SW overhead
Not including SW overhead
18
1.3
2.6
0.2
0.3
0.4
0.6
4.8
8
50
1.65
6.6
0.5
0.6
0.9
1.3
7.6
12.6
10
500
33
66
5.0
5.0
5.0
5.0
55
91
10
30
30
-
s
s
tMPRG Module program (512 kB)
tBKPRG Bank program (1056 KB)
s
tER16K Sector pre-program and erase (16 KB)
tER32K Sector pre-program and erase (32 KB)
tER64K Sector pre-program and erase (64 KB)
tER128K Sector pre-program and erase (128 KB)
tMKER Module erase (512 KB)
s
s
s
s
s
tBKER Bank erase (1056 KB)
s
tPABT Program abort latency
-
s
s
s
ms
tEABT Erase abort latency
-
30
tESUS Erase suspend latency
-
30
tESRT Erase suspend request rate
1. Based on characterization, not tested in production.
20
-
-
2. Assuming nominal supply values and operation at 25 °C, 0 cycles.
3. Assuming nominal supply values and operation at 25 °C, 100 cycles.
4. Assuming nominal supply values and operation at 125 °C, 100 Kcycles.
.
Table 31. Flash memory endurance and data retention
Parameter Conditions
Min.(1) Typ.
TA = -40 to +85 °C
Symbol
Max.
Unit
NEND
Endurance
1 K
15
Cycles
Years
Years
1 kcycle at TA = +85 °C(2)
tRET
Data retention
1 kcycles(2) at TA = +55 °C (see(2)
)
30
1. Based on characterization, not tested in production.
2. Cycling performed over the whole temperature range.
Table 32. Flash memory current consumption
Parameter Conditions
Symbol
Min. Typ. Max. Unit
Current consumption from 3.3 V During the erase of all the sectors -
supply source
I(Flash_VDD3V3)
1.6
mA
mA
see(1)
Current consumption from 1.2 V
supply source
I(Flash_VDD1V2)
During the erase of all the sectors(1)
12.3
1. During characterization, not tested in production. The values exclude the consumption from other pins.
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Package information
5
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
5.1
TQFP176 package information
Figure 10. TQFP176 (20 x 20 x 1 mm) package outline
74)3ꢁꢊꢉꢂ
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58
Package information
STCOM
Table 33. TQFP176 (20 x 20 x 1 mm) package mechanical data
Dimensions (millimeters)
Typ.
Symbol
Min.
Max.
A
A1
A2
b
1.20
0.127
1.05
0.05
0.95
1.00
0.18
0.13
0.23
c
0.09
0.20
D
21.80
19.80
22.00
20.00
8.70
22.20
20.20
D1
D2
D3
E
17.20
22.00
20.00
8.70
21.80
19.80
22.20
20.20
E1
E2
E3
e
17.20
0.40
L
0.45
0°
0.60
0.75
L1
k
1.00
3.5°
7°
ccc
0.08
5.2
Thermal data
Table 34. Thermal data
Typ.
value
Symbol
Parameter
Conditions
Unit
Mounted on a 2s2p PCB, with a dissipating
surface, connected through vias, on the bottom
side of the PCB.
Maximum thermal resistance junction
ambient steady state
RthJA
34
°C/W
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Ordering information
6
Ordering information
Table 35. Ordering information
Order code
Package
Packing
eFlash size
STCOM10
STCOM05
TQFP176 (20 x 20 x 1 mm)
TQFP176 (20 x 20 x 1 mm)
Tray
Tray
1 MB
640 kB
7
Revision history
Table 36. Document revision history
Date
Revision
Changes
15-Oct-2015
1
Initial release.
DocID028515 Rev 1
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58
STCOM
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
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