ST7232A(K2)TA/XXXRE [STMICROELECTRONICS]
8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP32, 7 X 7 MM, ROHS COMPLIANT, LQFP-32;
| 型号： | ST7232A(K2)TA/XXXRE |
| 厂家： | 
ST |
| 描述： | 8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP32, 7 X 7 MM, ROHS COMPLIANT, LQFP-32 时钟 外围集成电路 |
| 文件： | 总201页 (文件大小：3595K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST7232AK1-Auto ST7232AK2-Auto
ST7232AJ1-Auto ST7232AJ2-Auto
8-bit MCU for automotive, 16 Kbyte Flash/ROM,
10-bit ADC, 4 timers, SPI, SCI
Features
■ Memories
– 8K dual voltage high density Flash
LQFP32 7 x 7
LQFP44 10 x 10
(HDFlash) or ROM with read-out protection
capability. In-application programming and
in-circuit programming for HDFlash devices
– Main clock controller with: real time base,
beep and clock-out capabilities
– Configurable watchdog timer
– Two 16-bit timers with: 2 input captures, 2
output compares, PWM and pulse
generator modes
– 384 bytes RAM
– HDFlash endurance: 100 cycles, data
retention: 20 years at 55°C
■ Clock, reset and supply management
– Clock sources: crystal/ceramic resonator
oscillators and bypass for external clock
– PLL for 2x frequency multiplication
■ 2 communications interfaces
– SPI synchronous serianterface
– SCI asynchronous srial interface
– Four power saving modes: halt, active halt,
wait and slow
■ 1 analog peripheral (low current coupling)
– 10-bit ADC with up to 12 robust input ports
■ Interrupt management
■ Instruction set
– Nested interrupt controller
– 14 interrupt vectors plus TRAP and reset
– 6 external interrupt lines (on 4 vectors)
– 8bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
■ Up to 32 I/O ports
– 32/24 multifunctional bidirectional I/O lines
– 22/17 alternate function lines
– 12/10 high sink outputs
■ Development tools
– Full hardware/software development
package
– In-circuit testing capability
■ 4 timers
Table 1.
Device summary
Program memory - bytes RAM (stack) - bytes Operating volt. Temp. range Package
ST72F32AK1-Auto
ST72F32AK2-Auto
ST72F32AJ1-Auto
ST72F32AJ2-Auto
ST7232AK1-Auto
ST7232AK2-Auto
ST7232AJ1-Auto
ST7232AJ2-Auto
Flash 4K
LQFP32
Flash 8K
Flash 4K
Flash 8K
LQFP44
-40°C to
+125°C
384 (256)
3.8V to 5.5V
ROM 4K
ROM 8K
ROM 4K
ROM 8K
LQFP32
LQFP44
January 2008
Rev 1
1/201
www.st.com
1
Contents
ST7232Axx-Auto
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1
1.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Differences between ST7232A-Auto and ST7232A datasheets . . . . . . . . 15
1.2.1
1.2.2
1.2.3
Principal differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Minor content differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Editing and formatting differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2
3
4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1
4.2
4.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3.1
Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4
4.5
4.6
4.7
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
In-Circuit Programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5
6
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1
5.2
5.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1
6.2
6.3
6.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4.1
6.4.2
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2/201
ST7232Axx-Auto
Contents
6.5
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.5.1
6.5.2
6.5.3
6.5.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
External power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.6
System integrity management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2.1
7.2.2
7.2.3
7.2.4
Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Different interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Non-maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.3
7.4
7.5
7.6
7.7
Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Interrupt related instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.7.1
I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.8
7.9
External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 51
Nested interrupts register map and reset value . . . . . . . . . . . . . . . . . . . . 53
7.10 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.1
8.2
8.3
8.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Active halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.4.1
8.4.2
Active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.1
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3/201
Contents
ST7232Axx-Auto
9.2.1
9.2.2
9.2.3
Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.3
9.4
9.5
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.1.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.1.6 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.1.7 Using halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . 72
10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.1.9 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.1.10 Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . 73
10.2 Main clock controller with real-time clock and beeper (MCC/RTC) . . . . . 73
10.2.1 Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.2.2 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.3 Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.2.7 MCC/RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.2.8 MCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.3.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.3.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.3.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4/201
ST7232Axx-Auto
Contents
10.4 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
10.4.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.4.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
10.4.8 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
10.5 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
10.5.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.5.7 SCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.6 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.6.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.6.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.6.6 10-bit ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
11
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.1 CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.1.1 Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
11.1.2 Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
11.1.3 Direct instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.1.4 Indexed instructions (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . 147
11.1.5 Indirect instructions (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.1.6 Indirect indexed instructions (short, long) . . . . . . . . . . . . . . . . . . . . . . 148
11.1.7 Relative mode instructions (direct, indirect) . . . . . . . . . . . . . . . . . . . . . 149
11.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
11.3 Using a pre-byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5/201
Contents
ST7232Axx-Auto
12
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.2.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.2.2 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.2.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.4.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.4.2 Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.4.3 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.5.2 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12.5.3 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 162
12.5.4 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.7 Electromagnetic compatability (EMC) characteristics . . . . . . . . . . . . . . 165
12.7.1 Functional electromagnetic susceptibility (EMS) . . . . . . . . . . . . . . . . . 165
12.7.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 167
12.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.9.2 ICCSEL/V pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
PP
12.10 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.10.1 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6/201
ST7232Axx-Auto
Contents
12.11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 175
12.11.1 SPI (serial peripheral interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
12.12 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
12.12.1 Analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 179
12.12.2 General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
12.12.3 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
13
14
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
13.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
13.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
13.3 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Device configuration and ordering information . . . . . . . . . . . . . . . . . 185
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.2 Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.2.1 Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.2.2 Flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.3 ROM device ordering information and transfer of customer code . . . . . 188
14.4 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.2 Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.3 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.4 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.5 Socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 193
14.5 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
15
Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1 All Flash and ROM devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.1 Safe connection of OSC1/OSC2 pins . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.2 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.3 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
15.1.4 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 196
15.1.5 16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
15.1.6 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . 197
15.1.7 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
15.1.8 39-pulse ICC entry mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
7/201
Contents
ST7232Axx-Auto
15.2 ROM devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.2.1 I/O port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.2.2 External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
8/201
ST7232Axx-Auto
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
ST7 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CPU CC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ISPRx interrupt vector correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
EICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Active halt and halt power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DR register value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
I/O Port Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Port register configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
I/O interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Effect of low power modes on watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
WDGCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Effect of low power modes on MCC/RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
MCC/RTC interrupt control/wake-up capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
MCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
MCCBCR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
16-bit timer interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
CR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
CR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
CSR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Effect of low power modes on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
SPI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SPICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SPICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SCI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SCISR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SCICR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
9/201
List of tables
ST7232Axx-Auto
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
SCICR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
SCIBRR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SCIERPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SCIETPR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Baud rate selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Effect of low power modes on 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
ADCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
ADCDRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
ADCDRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
CPU addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
CPU addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 148
Short instructions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Relative mode instructions (direct and indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Supply current of clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Oscillator parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Examples of typical resonators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Characteristics of dual VOLTAGE HDFlash MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Electromagnetic test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Latch up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
I/O general port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
ICCSEL/V pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
PP
16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
ADC accuracy with V = 5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
DD
32-pin LQFP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
44-pin LQFP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Soldering compatibility (wave and reflow soldering process) . . . . . . . . . . . . . . . . . . . . . . 184
Flash option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 100. Option byte 0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
10/201
ST7232Axx-Auto
List of tables
Table 101. Option byte 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 102. Package selection (OPT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 103. Flash user programmable device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 104. FASTROM factory coded device types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 105. ROM factory coded device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 106. STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 107. Suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 108. Port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 109. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
11/201
List of figures
ST7232Axx-Auto
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
32-pin LQFP 7x7 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
44-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory map and sector addresses of the ST7232X family . . . . . . . . . . . . . . . . . . . . . . . . 28
Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Stack manipulation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 10. Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11. Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 15. Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 17. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 18. External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 19. Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 20. Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 21. Wait mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 22. Active halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 23. Active halt Mode Flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 24. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 25. Halt mode flow-chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 26. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 27. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 28. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 29. Approximate timeout duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 30. Exact timeout duration (t
and t
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
min
max
Figure 31. Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 32. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 33. 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 34. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 35. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 36. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 37. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 38. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 39. Output compare block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 40. Output compare timing diagram, f
Figure 41. Output compare timing diagram, f
= f
= f
/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
TIMER
CPU
TIMER
CPU
Figure 42. One pulse mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 43. One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 44. Pulse width modulation mode timing example with 2 output compare functions . . . . . . . . 91
Figure 45. Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 46. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 47. Single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 48. Generic SS timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
12/201
ST7232Axx-Auto
List of figures
Figure 49. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 50. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 51. Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 111
Figure 52. Single master/multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 53. SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 54. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 55. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 56. Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 57. ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 58. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 59. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 60.
f
max versus V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
CPU
DD
Figure 61. Typical I in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
DD
Figure 62. Typical I in slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
DD
Figure 63. Typical I in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
DD
Figure 64. Typ. I in slow wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
DD
Figure 65. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 66. Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 67. Integrated PLL jitter vs signal frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 68. Unused I/O pins configured as input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 69. Typical I vs. V with V = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
PU
DD
IN
SS
Figure 70. Typical V at V = 5V (std. ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
OL
DD
Figure 71. Typ. V at V = 5V (high-sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
OL
DD
Figure 72. Typical V at V = 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
OH
DD
Figure 73. Typical V vs. V (std. ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
OL
DD
Figure 74. Typical V vs. V (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
OL
DD
Figure 75. Typical V vs. V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
OH
DD
Figure 76. RESET pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 77. Two typical applications with ICCSEL/V pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
PP
Figure 78. SPI slave timing diagram with CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 79. SPI slave timing diagram with CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 80. SPI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 81.
R
max. vs f
with C
= 0pF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
AIN
ADC
AIN
Figure 82. Recommended C
and R
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
AIN
AIN
Figure 83. Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 84. Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 85. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 86. 32-pin LQFP outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 87. 44-pin LQFP outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 88. Flash commercial product code structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 89. FASTROM commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 90. ROM commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
13/201
Introduction
ST7232Axx-Auto
1
Introduction
1.1
Description
The ST7232AK1-Auto, ST7232AK2-Auto, ST7232AJ1-Auto, and ST7232AJ2-Auto devices
are members of the ST7 microcontroller family designed for the 5V operating range.
The 32 and 44-pin devices are designed for mid-range applications
All devices are based on a common industry-standard 8-bit core, featuring an enhanced
instruction set and are available with Flash or ROM program memory.
Under software control, all devices can be placed in wait, slow, active halt or halt mode,
reducing power consumption when the application is in idle or stand-by state.
The enhanced instruction set and addressing modes of the ST7 offer both power and
flexibility to software developers, enabling the design of highly efficient and compact
application code. In addition to standard 8-bit data management, all ST7 microcontrollers
feature true bit manipulation, 8 x 8 unsigned multiplication and indirect addressing modes.
Figure 1.
Device block diagram
8-bit core
ALU
Program
memory
(8K bytes)
RESET
Control
V
PP
RAM
(384 bytes)
V
V
SS
DD
Watchdog
Port A
OSC1
OSC2
OSC
MCC/RTC/beep
PORT F
Timer A
Beep
Port B
Port E
Port C
Timer B
SPI
SCI
Port D
10-bit ADC
V
AREF
V
SSA
14/201
ST7232Axx-Auto
Introduction
1.2
Differences between ST7232A-Auto and ST7232A datasheets
The differences between the ST7232A-Auto datasheet, version 1, released in January 2008
and the ST7232A datasheet, version 2, released in December 2005 are listed below.
Differences are categorised as follows:
●
●
●
Principal differences
Minor content differences
Editing and formatting differences
1.2.1
Principal differences
1. Changed root part number from ST7232A to ST7232AK1-Auto, ST7232AK2-Auto,
ST7232AJ1-Auto, and ST7232AJ2-Auto throughout document
2. Changed document title on page 1
3. Removed 1 and 5 suffix version temperatures ranges throughout the document
4. Features on page 1: Changed minimum value of data retention time (t
) to 20 years
RET
and changed the condition to T = 55°C
A
(5)
5. Table 2: Device pin description on page 21: Added footnote
6. Section 6.3: Phase locked loop (PLL) on page 36: Added caution regarding use of PLL
with an external clock
7. Reset vector fetch on page 38: Added a ‘caution’ about the reset vector when it is not
programmed
8. Section 9.2.1: Input modes on page 62: Amended note3 of this section
9. Section 9.3: I/O port implementation on page 66: Deleted I/O port implementation
tables
10. Output compare on page 85: Amended text in note 3
11. Figure 41: Output compare timing diagram, fTIMER = fCPU/4 on page 88: Removed
compare register i Latch from diagram
12. Section 10.6: 10-bit A/D converter (ADC) on page 139: Amended text concerning the
EOC bit in Starting the conversion
13. Table 70: Current characteristics on page 155:
–
–
Added data for the LQFP44 package to I
and I
VDD VSS
Updated max I values for standard I/O and high sink I/O
IO
14. Table 72: General operating conditions on page 156: Updated temperature ranges in
the ‘conditions’ column
15. Table 82: Characteristics of dual VOLTAGE HDFlash MEMORY on page 164:
–
–
Changed typical value of supply current (I ) to < 10µA
DD
Changed minimum value of data retention time (t
) to 20 years and changed the
RET
condition to T = 55°C
A
–
Changed the condition of write erase cycle (N ) to T = 85°C
RW A
16. Section 12.7.3: Absolute maximum ratings (electrical sensitivity) on page 167:
Removed text concerning dynamic latch-up
17. Electro-static discharge (ESD) on page 167: Replaced JESD22-A114A/A115A
standard with AEC-Q100-002/003/011 standard
15/201
Introduction
ST7232Axx-Auto
18. Table 85: ESD absolute maximum ratings on page 167:
–
–
Added test standards to conditions column
Changed max value of CDM from 250 V to: > 500 V to ≤ 750 V with corner pins >
750 V
–
Added ‘class’ information
19. Static latch-up on page 167: Added ‘AEC-Q100/004’ standard
20. Table 86: Latch up results on page 167:
–
–
–
–
–
Removed T = +25°C, +85°C and +105°C from latch-up conditions
A
Added AEC-Q100/004 test standard
Removed dynamic latch-up results
Changed ‘class’ information
Removed footnote 1 pertaining to class descriptions and JEDEC standards
21. Table 87: I/O general port pin characteristics on page 168:
(3)
(5)
–
–
Added footnote
Amended footnote
and
(4)
22. Figure 76: RESET pin protection on page 173: Removed EMC protective circuitry
(device works correctly without these components)
23. Table 92: SPI characteristics on page 175:
(1)
(2)
–
–
–
–
Added footnote
and
Updated max and unit information of t (MO)
v
Updated min values of t (MO)
h
Updated min and max values for ‘data output valid’ and ‘data output hold’ times
24. Figure 80: SPI master timing diagram on page 177: Modified figure to reflect changes
made in Table 92: SPI characteristics concerning t (MO) and t (MO)
v
h
25. Table 93: 10-bit ADC characteristics on page 178:
–
–
Removed word ‘positive’ from explanation of I parameter
lkg
(2)
Updated footnote
26. Figure 83: Typical A/D converter application on page 179: Changed I 1µA to I
L
lkg
27. Table 94: ADC accuracy with VDD = 5.0V on page 181:
–
–
Made the ‘conditions’ applicable for all parameters
(2)
Updated footnote
28. Table 97: Thermal characteristics on page 184:
(1)
(2)
–
–
Amended footnotes
and
Added a value for LQFP44
29. Table 99: Flash option bytes on page 185:
–
–
–
Changed bits 4 and 3 of option byte 0 to a default value of ‘1’
Changed the OSCRANGE bits [2:0] of option byte 1 from 111 to 011
Added footnote 1 concerning package selection
30. Updated Table 100: Option byte 0 description on page 186
31. Updated Table 101: Option byte 1 description on page 186
32. Added Table 102: Package selection (OPT7) on page 187
33. Section 15.1.2: External interrupt missed on page 194: Added section on ‘external
interrupt missed’ bug
16/201
ST7232Axx-Auto
Introduction
34. Section 15.1.6: TIMD set simultaneously with OC interrupt on page 197:
Added section concerning limitation of the 16-bit timer
Added ‘TBCR1’, ‘TBCSR I’ and ‘TBCSR &’ to the workaround subsection
–
–
1.2.2
Minor content differences
1. Removed all references to the SDIP32 and SDIP42 packages (which are unavailable in
automotive) thoughout document
2. Replaced TQFP by LQFP throughout document
3. Table 3: Hardware register map on page 25: Replaced ‘h’ with ‘b’ in the reset status
column for the SCICR1 register
4. System integrity control/status register (SICSR) on page 41: Replaced ‘h’ with ‘b’ in the
reset value cell of the SICSR register
5. Table 43: SPI register map and reset values on page 117: Changed the name of bit 5 in
the SPICSR register from OR to OVR
6. Break character on page 123: SPI replaced by SCI
7. Control register 1 (SCICR1) on page 133: Replaced ‘h’ with ‘b’ in the reset value cell of
the SCICR1 register
8. Changed I to I in Table 77: External clock source on page 161, Figure 65: Typical
L
lkg
application with an external clock source on page 161 and Table 90: ICCSEL/VPP pin
characteristics on page 174
9. Table 95: 32-pin LQFP mechanical data on page 182 and Table 96: 44-pin LQFP
mechanical data on page 183: Altered ‘inches’ data to four decimal places
10. Section 13.3: Soldering information on page 184:
–
–
–
Updated environmental information regarding ‘ECOPACK®’ packages
TM
Replaced ECOPACK with ECOPACK® throughout the document
Updated section on ECOPACK® soldering compatability
11. Table 98: Soldering compatibility (wave and reflow soldering process) on page 184:
Removed footnote on Pb package maximum temperature
12. Updated Table 103: Flash user programmable device types on page 187
13. Added Figure 88: Flash commercial product code structure on page 188
14. Updated Section 14.3: ROM device ordering information and transfer of customer code
on page 188
15. Added Table 104: FASTROM factory coded device types on page 189
16. Added Figure 89: FASTROM commercial product code structure on page 189
17. Added Table 105: ROM factory coded device types on page 190
18. Updated Figure 90: ROM commercial product code structure on page 190
19. Updated ST72P32A/ST7232A (3.8 to 5.5V) microcontroller option list on page 191
20. Updated Table 106: STMicroelectronics development tools on page 193
21. Section 14.4: Development tools on page 192:
–
–
–
Updated Introduction and Programming tools
Deleted Emulators and In-circuit debugging kit
Added Evaluation tools and starter kits and Development and debugging tools
22. Section 14.5: ST7 application notes on page 193: Removed list of ST7 application
notes
17/201
Introduction
ST7232Axx-Auto
1.2.3
Editing and formatting differences
1. Reformatted document
2. Converted register and bit decriptions to table format
3. Edited English throughout document
4. Correctly aligned footnotes of tables throughout document
18/201
ST7232Axx-Auto
Pin description
2
Pin description
Figure 2.
32-pin LQFP 7x7 package pinout
32 31 30 29 2827 2625
V
V
24
23
22
21
20
19
18
17
AREF
1
2
3
4
5
6
7
8
OSC1
OSC2
ei3 ei2
SSA
MCO/AIN8/PF0
V
_2
SS
ei1
Beep/(HS) PF1
OCMP1_A/AIN10/PF4
ICAP1_A/(HS) PF6
RESET
V
/ICCSEL
PP
PA7 (HS)
PA6 (HS)
PA4 (HS)
EXTCLK_A/(HS) PF7
ei0
9 10111213141516
AIN12/OCMP2_B/PC0
1. Legend: (HS) = 20mA high sink capability; eix = associated external interrupt vector
19/201
Pin description
Figure 3.
ST7232Axx-Auto
44-pin LQFP package pinout
44 43 42 41 40 39 38 37 36 35 34
RDI/PE1
PB0
V
V
1
2
3
4
5
6
7
8
33
SS_1
DD_1
32
PB1
PA3 (HS)
PC7/SS/AIN15
PC6/SCK/ICCCLK
PC5/MOSI/AIN14
PC4/MISO/ICCDATA
PC3 (HS)/ICAP1_B
PC2 (HS)/ICAP2_B
PC1/OCMP1_B/AIN13
PC0/OCMP2_B/AIN12
ei0 31
30
ei2
ei3
PB2
PB3
29
28
(HS) PB4
AIN0/PD0
AIN1/PD1
AIN2/PD2
AIN3/PD3
AIN4/PD4
27
26
25
9
ei1
10
11
24
23
12 13 14 15 16 17 18 19 20 21 22
1. Legend: (HS) = 20mA high sink capability; eix = associated external interrupt vector
For external pin connection guidelines, refer to Section 12: Electrical characteristics on
page 153.
In Table 2: Device pin description below, refer to Section 9: I/O ports on page 62 for more
details on the software configuration of the I/O ports. The RESET configuration of each pin
is shown in bold. This configuration is valid as long as the device is in reset state. For
external pin connection guidelines refer to Section 12: Electrical characteristics on
page 153.
20/201
ST7232Axx-Auto
Pin description
(1)
Table 2.
Device pin description
Pin
no.
Level
Port
Main
function
(after
Pin name
Alternate function
Input
Output
reset)
6
7
8
9
30 PB4 (HS)
31 PD0/AIN0
I/O CT HS
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
S
X
X
X
X
X
X
X
ei3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port B4
X
X
Port D0 ADC analog input 0
Port D1 ADC analog input 1
Port D2 ADC analog Input 2
Port D3 ADC analog Input 3
Port D4 ADC analog Input 4
Port D5 ADC analog Input 5
Analog reference voltage for ADC
Analog ground voltage
32 PD1/AIN1
X
X
X
X
X
X
X
X
X
X
(4)
-
PD2/AIN2
10 -(4) PD3/AIN3
11 -(4) PD4/AIN4
12 -(4) PD5/AIN5
(5)
13
14
1
2
VAREF
(5)
VSSA
S
Main clock
out (fCPU
ADC analog
input 8
15
3
PF0/MCO/AIN8
I/O CT
X
ei1
ei1
X
X
X
X
Port F0
)
16
4
PF1 (HS)/Beep
I/O CT HS
I/O CT HS
X
X
X
X
X
X
Port F1
Port F2
Beep signal output
17 -(4) PF2 (HS)
ei1
PF4/OCMP1_A/
AIN10
Timer A output ADC analog
compare 1
18
19
20
5
6
7
I/O CT
X
X
X
X
X
X
X
X
X
X
X
X
Port F4
Port F6
Port F7
input 10
PF6 (HS)/ICAP1_A I/O CT HS
Timer A input capture 1
PF7
I/O CT HS
(HS)/EXTCLK_A
Timer A external clock source
(5)
21
22
-
-
VDD_0
S
S
Digital main supply voltage
Digital ground voltage
(5)
VSS_0
PC0/OCMP2_B/
AIN12
Timer B output ADC analog
compare 2 input 12
23
24
8
9
I/O CT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port C0
Port C1
PC1/OCMP1_B/
AIN13
Timer B output ADC analog
compare 1 input 13
I/O CT
PC2
(HS)/ICAP2_B
25 10
26 11
27 12
I/O CT HS
I/O CT HS
I/O CT
Port C2 Timer B input capture 2
Port C3 Timer B input capture 1
PC3
(HS)/ICAP1_B
PC4/MISO/
ICCDATA
SPI master in/ ICC data
Port C4
slave out data input
SPI master out ADC analog
Port C5
28 13 PC5/MOSI/AIN14 I/O CT
29 14 PC6/SCK/ICCCLK I/O CT
X
/slave in data input 14
SPI serial
clock
ICC clock
output
Port C6
21/201
Pin description
ST7232Axx-Auto
(1)
Table 2.
Device pin description (continued)
Pin
no.
Level Port
Main
function
(after
Pin name
Alternate function
Input
Output
reset)
SPI slave
Port C7 select (active
low)
ADC analog
input 15
30 15 PC7/SS/AIN15
I/O CT
X
X
X
X
X
X
X
X
31 16 PA3 (HS)
I/O CT HS
S
ei0
Port A3
(5)
32
33
-
-
VDD_1
Digital main supply voltage
Digital ground voltage
Port A4
(5)
VSS_1
S
34 17 PA4 (HS)
35 -(4) PA5 (HS)
36 18 PA6 (HS)
37 19 PA7 (HS)
I/O CT HS
I/O CT HS
I/O CT HS
I/O CT HS
X
X
X
X
X
X
X
X
T
T
X
X
Port A5
Port A6
Port A7
Must be tied low. In the Flash
programming mode, this pin acts as the
programming voltage input VPP. See
Section 12.9.2 for more details. High
voltage must not be applied to ROM
devices.
38 20 VPP/ICCSEL
39 21 RESET
I
I/O CT
Top priority non maskable interrupt.
Digital ground voltage
(5)
40 22 VSS_2
S
41 23 OSC2(6)
O
Resonator oscillator inverter output
External clock input or resonator
oscillator inverter input
42 24 OSC1(6)
I
(5)
43 25 VDD_2
S
Digital main supply voltage
44 26 PE0/TDO
I/O CT
I/O CT
X
X
X
X
X
X
X
X
Port E0
Port E1
SCI transmit data out
SCI receive data in
1
27 PE1/RDI
Caution: Negative current
injection not allowed on this
pin(7)
2
28 PB0
I/O CT
X
ei2
X
X
Port B0
(4)
3
4
5
-
PB1
PB2
I/O CT
I/O CT
I/O CT
X
X
X
ei2
ei2
X
X
X
X
X
X
Port B1
Port B2
Port B3
(4)
-
29 PB3
ei2
1. Legend/abbreviations for Table 2:
Type: I = input, O = output, S = supply
Input level: CT = CMOS 0.3VDD/0.7VDD with input trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration inputs: float = floating, wpu = weak pull-up, int = interrupt, ana = analog ports
Port and control configuration outputs: OD = open drain, PP = push-pull
2. ‘eiX’ defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column
(int), then the I/O configuration is pull-up interrupt input; otherwise the configuration is floating interrupt input
22/201
ST7232Axx-Auto
Pin description
3. ‘T’ defines a true open drain I/O (P-buffer and protection diode to VDD are not implemented). See Section 9: I/O ports on
page 62 and Section 12.8: I/O port pin characteristics for more details
4. Each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The
configuration of these pads must be kept at reset state to avoid added current consumption.
5. It is mandatory to connect all available VDD and VAREF pins to the supply voltage and all VSS and VSSA pins to ground
6. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1:
Introduction and Section 12.5: Clock and timing characteristics for more details
7. For details refer to Section 12.8.1: General characteristics on page 168
23/201
Register and memory map
ST7232Axx-Auto
3
Register and memory map
As shown in <Blue HT>Figure 4, the MCU is capable of addressing 64K bytes of memories
and I/O registers.
The available memory locations consist of 128 bytes of register locations, up to 384 bytes of
RAM and up to 8 Kbytes of user program memory. The RAM space includes up to 256 bytes
for the stack from 0100h to 01FFh.
The highest address bytes contain the user reset and interrupt vectors.
Caution:
Memory locations marked as ‘reserved’ must never be accessed. Accessing a reserved
area can have unpredictable effects on the device.
Figure 4.
Memory map
0080h
Short addressing
RAM (zero page)
0000h
HW registers
(see Table 3)
00FFh
0100h
007Fh
0080h
256 bytes stack
Reserved
RAM
(384 bytes)
01FFh
0200h
047Fh
0480h
027Fh
or 047Fh
Reserved
E000h
E000h
Program memory
(4K or 8K)
8 Kbytes
4 Kbytes
FFDFh
FFE0h
F000h
FFFFh
Interrupt and reset vectors
(see Table 15)
FFFFh
24/201
ST7232Axx-Auto
Register and memory map
Reset status(1) Remarks(2)
Table 3.
Address
Hardware register map
Block
Register label
Register name
0000h
0001h
0002h
PADR
Port A data register
Port A data direction register
Port A option register
00h(4)
00h
00h
R/W
R/W
R/W
Port A(3) PADDR
PAOR
0003h
0004h
0005h
PBDR
Port B(3) PBDDR
PBOR
Port B data register
Port B data direction register
Port B option register
00h(4)
00h
00h
R/W
R/W
R/W
0006h
0007h
0008h
PCDR
PCDDR
PCOR
Port C data register
Port C data direction register
Port C option register
00h(4)
00h
00h
R/W
R/W
R/W
Port C
0009h
000Ah
000Bh
PDADR
Port D data register
Port D data direction register
Port D option register
00h(4)
00h
00h
R/W
R/W
R/W
Port D(3) PDDDR
PDOR
000Ch
000Dh
000Eh
PEDR
Port E(3) PEDDR
PEOR
Port E data register
Port E data direction register
Port E option register
00h(4)
00h
00h
R/W
R/W(3)
R/W(3)
000Fh
0010h
0011h
PFDR
Port F(3) PFDDR
PFOR
Port F data register
Port F data direction register
Port F option register
00h(4)
00h
00h
R/W
R/W
R/W
0012h to
0020h
Reserved area (15 bytes)
0021h
0022h
0023h
SPIDR
SPICR
SPICSR
SPI data I/O register
SPI control register
SPI control/status register
xxh
0xh
00h
R/W
R/W
R/W
SPI
0024h
0025h
0026h
0027h
ISPR0
ISPR1
ISPR2
ISPR3
Interrupt software priority register 0
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
ITC
0028h
0029h
EICR
External interrupt control register
Flash control/status register
Watchdog control register
Reserved area (1 byte)
00h
00h
7Fh
R/W
R/W
R/W
Flash
FCSR
002Ah Watchdog WDGCR
002Bh
002Ch
002Dh
MCCSR
MCCBCR
Main clock control/status register
Main clock controller: beep control register
00h
00h
R/W
R/W
MCC
002Eh to
0030h
Reserved area (3 bytes)
25/201
Register and memory map
ST7232Axx-Auto
Table 3.
Address
Hardware register map (continued)
Block
Register label
Register name
Reset status(1) Remarks(2)
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
Timer A control register 2
Timer A control register 1
Timer A control/status register
Timer A input capture 1 high register
Timer A input capture 1 low register
Timer A output compare 1 high register
Timer A output compare 1 low register
Timer A counter high register
00h
00h
xxxx x0xxb
xxh
R/W
R/W
R/W
Read only
Read only
R/W
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
R/W
Timer A TACHR
TACLR
Read only
Read only
Read only
Read only
Read only
Read only
R/W
Timer A counter low register
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A alternate counter high register
Timer A alternate counter low register
Timer A input capture 2 high register
Timer A input capture 2 low register
Timer A output compare 2 high register
Timer A output compare 2 low register
00h
R/W
0040h
Reserved area (1 byte)
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
Timer B control register 2
Timer B control register 1
Timer B control/status register
Timer B input capture 1 high register
Timer B input capture 1 low register
Timer B output compare 1 high register
Timer B output compare 1 low register
Timer B counter high register
00h
00h
xxxx x0xxb
xxh
R/W
R/W
R/W
Read only
Read only
R/W
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
TBOC1HR
TBOC1LR
Timer B TBCHR
TBCLR
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
Timer B counter low register
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B alternate counter high register
Timer B alternate counter low register
Timer B input capture 2 high register
Timer B input capture 2 low register
Timer B output compare 2 high register
Timer B output compare 2 low register
00h
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCI status register
SCI data register
SCI baud rate register
SCI control register 1
SCI control register 2
SCI extended receive prescaler register
Reserved area
C0h
xxh
00h
Read only
R/W
R/W
R/W
R/W
x000 0000b
00h
SCI
SCIERPR
00h
R/W
SCIETPR
SCI extended transmit prescaler register
00h
R/W
0058h to
006Fh
Reserved area (24 bytes)
0070h
0071h
0072h
ADCCSR
ADCDRH
ADCDRL
Control/status register
Data high register
Data low register
00h
00h
00h
R/W
Read only
Read only
ADC
0073h
007Fh
Reserved area (13 bytes)
1. x = undefined
2. R/W = read/write
3. The bits associated with unavailable pins must always keep their reset value
4. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents
26/201
ST7232Axx-Auto
Flash program memory
4
Flash program memory
4.1
Introduction
The ST7 dual voltage high density Flash (HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a byte-by-
byte basis using an external V supply.
PP
The HDFlash devices can be programmed and erased off-board (plugged in a programming
tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).
The array matrix organisation allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2
Main features
●
Three Flash programming modes:
–
–
–
Insertion in a programming tool. In this mode, all sectors including option bytes
can be programmed or erased
ICP (in-circuit programming). In this mode, all sectors including option bytes can
be programmed or erased without removing the device from the application board
IAP (in-application programming) In this mode, all sectors except sector 0, can be
programmed or erased without removing the device from the application board
and while the application is running
●
ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
●
●
Read-out protection
Register access security system (RASS) to prevent accidental programming or erasing
4.3
Structure
The Flash memory is organised in sectors and can be used for both code and data storage.
Depending on the overall Flash memory size in the microcontroller device, there are up to
three user sectors (see Table 4). Each of these sectors can be erased independently to
avoid unnecessary erasing of the whole Flash memory when only a partial erasing is
required.
The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the
upper part of the ST7 addressing space so the reset and interrupt vectors are located in
sector 0 (F000h-FFFFh).
Table 4.
Sectors available in Flash devices
Flash size (bytes)
Available sectors
4K
8K
Sector 0
Sectors 0,1
27/201
Flash program memory
ST7232Axx-Auto
4.3.1
Read-out protection
Read-out protection, when selected, provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.
In Flash devices, this protection is removed by reprogramming the option. In this case, the
entire program memory is first automatically erased and the device can be reprogrammed.
Read-out protection selection depends on the device type:
●
In Flash devices it is enabled and removed through the FMP_R bit in the option byte
In ROM devices it is enabled by mask option specified in the option list
●
Figure 5.
Memory map and sector addresses of the ST7232X family
4K
8K
10K
16K
24K
32K
48K
60K
Flash memory size
Sector 2
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
52 Kbytes
2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes
4 Kbytes
4 Kbytes
Sector 1
Sector 0
4.4
ICC interface
ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see
Figure 6). These pins are:
●
●
●
●
●
●
●
RESET: device reset
: device power supply ground
V
SS
ICCCLK: ICC output serial clock pin
ICCDATA: ICC input/output serial data pin
ICCSEL/V : programming voltage
PP
OSC1(or OSCIN): main clock input for external source (optional)
V
: application board power supply (optional, see Figure 6, footnote 3)
DD
28/201
ST7232Axx-Auto
Figure 6.
Flash program memory
Typical ICC interface
Programming tool
ICC connector
ICC cable
Application board
(3)
(See ‘caution’)
ICC connector
HE10 connector type
9
7
5
6
3
1
2
10
8
4
(2)
Application reset source
10kΩ
Application
power supply
C
C
L2
L1
(1)
Application I/O
ST7
1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is
necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in
progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by
the application, isolation such as a serial resistor has to implemented in case another device forces the
signal. Refer to the programming tool documentation for recommended resistor values.
2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts
between the programming tool and the application reset circuit if it drives more than 5mA at high level
(push pull output or pull-up resistor < 1K). A schottky diode can be used to isolate the application reset
circuit in this case. When using a classical RC network with R > 1K or a reset management IC with open
drain output and pull-up resistor > 1K, no additional components are needed. In all cases the user must
ensure that no external reset is generated by the application during the ICC session.
3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be
connected when using most ST programming tools (it is used to monitor the application power supply).
Please refer to the programming tool manual.
Caution:
External clock ICC entry mode is mandatory. Pin 9 must be connected to the OSC1 or
OSCIN pin of the ST7 and OSC2 must be grounded.
4.5
In-circuit programming (ICP)
To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM, Flash memory programming can be fully
customized (number of bytes to program, program locations, or selection serial
communication interface for downloading).
When using an STMicroelectronics or third-party programming tool that supports ICP and
the specific microcontroller device, the user needs only to implement the ICP hardware
interface on the application board (see Figure 6). For more details on the pin locations, refer
to the device pinout description.
29/201
Flash program memory
ST7232Axx-Auto
4.6
In-application programming (IAP)
This mode uses a Bootloader program previously stored in sector 0 by the user (in ICP
mode or by plugging the device in a programming tool).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored, ...). For example, it is possible
to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash sectors except sector 0, which is write/erase
protected to allow recovery in case errors occur during the programming operation.
4.7
Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash programming
reference manual and to the ST7 ICC protocol reference manual.
Flash control/status register (FCSR)
FCSR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
0
R/W
This register is reserved for use by programming tool software. It controls the Flash
programming and erasing operations.
Table 5.
Flash control/status register address and reset value
Address (Hex.) Register label
7
6
5
4
3
2
1
0
FCSR
0029h
Reset value
0
0
0
0
0
0
0
0
30/201
ST7232Axx-Auto
Central processing unit
5
Central processing unit
5.1
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient
8-bit data manipulation.
5.2
Main features
●
●
●
●
●
●
●
●
Enable executing 63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes (with indirect addressing mode)
Two 8-bit index registers
16-bit stack pointer
Low power halt and wait modes
Priority maskable hardware interrupts
Non-maskable software/hardware interrupts
5.3
CPU registers
The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are
accessed by specific instructions.
Figure 7.
CPU registers
7
0
Accumulator
Reset value = XXh
7
0
0
X index register
Y index register
Reset value = XXh
7
Reset value = XXh
15
PCH
8
7
PCL
0
Program counter
Reset value = reset vector @ FFFEh-FFFFh
7
0
Condition code register
1
1
1
1
I1 H I0 N
Z
X
C
X
Reset value =
8
1
X 1 X
15
7
0
Stack pointer
Reset value = stack higher address
1. X = undefined value
31/201
Central processing unit
ST7232Axx-Auto
Accumulator (A)
The accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
Index registers (X and Y)
These 8-bit registers are used to create effective addresses or as temporary storage areas
for data manipulation. (The cross-assembler generates a precede instruction (PRE) to
indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (program counter low which is
the LSB) and PCH (program counter high which is the MSB).
Condition code register (CC)
CC
Reset value: 111x 1xxx
7
6
5
4
3
2
1
Z
0
1
I1
H
I0
N
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The 8-bit condition code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
32/201
ST7232Axx-Auto
Central processing unit
Table 6.
CC register description
Bit name
Bit
Function
Interrupt management bits - interrupt
The combination of the I1 and I0 bits gives the current interrupt
software priority:
10: Interrupt software priority = level 0 (main)
01: Interrupt software priority = level 1
00: Interrupt software priority = level 2
5,3
I1, I0
11: Interrupt software priority = level 3 (= interrupt disable)
These two bits are set/cleared by hardware when entering in
interrupt. The loaded value is given by the corresponding bits in the
interrupt software priority registers (IxSPR). They can be also
set/cleared by software with the RIM, SIM, IRET, HALT, WFI and
PUSH/POP instructions. See Section 7: Interrupts for more details.
Arithmetic management bit -
Half carry
This bit is set by hardware when a carry occurs between bits 3 and 4
of the ALU during an ADD or ADC instructions. It is reset by
hardware during the same instructions.
4
H
0: No half carry has occurred
1: A half carry has occurred
This bit is tested using the JRH or JRNH instruction. The H bit is
useful in BCD arithmetic subroutines.
Arithmetic management bit - Negative
This bit is set and cleared by hardware. It is representative of the
result sign of the last arithmetic, logical or data manipulation. It’s a
copy of the result 7th bit.
0: The result of the last operation is positive or null
1: The result of the last operation is negative (i.e. the most significant
bit is a logic 1)
2
1
N
Z
This bit is accessed by the JRMI and JRPL instructions.
Arithmetic management bit - Zero
This bit is set and cleared by hardware. This bit indicates that the
result of the last arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero
1: The result of the last operation is zero
This bit is accessed by the JREQ and JRNE test instructions.
Arithmetic management bit -
Carry/borrow
This bit is set and cleared by hardware and software. It indicates an
overflow or an underflow has occurred during the last arithmetic
operation.
0
C
0: No overflow or underflow has occurred
1: An overflow or underflow has occurred
This bit is driven by the SCF and RCF instructions and tested by the
JRC and JRNC instructions. It is also affected by the ‘bit test and
branch’, shift and rotate instructions.
33/201
Central processing unit
ST7232Axx-Auto
Stack pointer register (SP)
SP
Reset value: 01 FFh
15
7
14
6
13
5
12
0
11
3
10
2
9
8
1
R/W
4
R/W
0
1
SP[7:0]
R/W
The stack pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 8).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU reset, or after a reset stack pointer instruction (RSP), the stack pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
The least significant byte of the stack pointer (called S) can be directly accessed by a LD
instruction.
Note:
When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 8.
●
When an interrupt is received, the SP is decremented and the context is pushed on the
stack
●
On return from interrupt, the SP is incremented and the context is popped from the
stack
A subroutine call occupies two locations and an interrupt five locations in the stack area.
34/201
ST7232Axx-Auto
Figure 8.
Central processing unit
Stack manipulation example
Call
subroutine
PUSH Y
POP Y
IRET
RET or RSP
Interrupt
event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
1. Legend: stack higher addres = 01FFh; stack lower address = 0100h
35/201
Supply, reset and clock management
ST7232Axx-Auto
6
Supply, reset and clock management
6.1
Introduction
The device includes a range of utility features for securing the application in critical situations (for
example in case of a power brown-out), and reducing the number of external components. An overview is
shown in Figure 10.
6.2
Main features
●
●
●
Optional PLL for multiplying the frequency by 2
Reset sequence manager (RSM)
Multi-oscillator clock management (MO)
–
5 crystal/ceramic resonator oscillators
6.3
Phase locked loop (PLL)
If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the
frequency by two to obtain an f of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is
OSC2
disabled, then f
f
/2.
OSC2 = OSC
Caution:
Caution:
The PLL is not recommended for applications where timing accuracy is required.
When the PLL is used with an external clock signal, the clock signal must be available on
the OSCIN pin before the reset signal is released.
Figure 9.
PLL block diagram
PLL x 2
/2
0
f
OSC
f
OSC2
1
PLL option bit
36/201
ST7232Axx-Auto
Supply, reset and clock management
Figure 10. Clock, reset and supply block diagram
f
OSC2
CPU
f
Main clock controller
with real-time clock
f
OSC
PLL
OSC2
Multi-oscillator
(option)
(MO)
(MCC/RTC)
OSC1
System integrity management
Watchdog timer
(WDG)
Reset sequence manager
(RSM)
RESET
SICSR
0
WDG
RF
0
0
0
V
SS
V
DD
6.4
Multi-oscillator (MO)
The main clock of the ST7 can be generated by two different source types coming from the
multi-oscillator block:
●
An external source
●
4 crystal or ceramic resonator oscillators
Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in
Table 7. Refer to Section 12: Electrical characteristics for more details.
Caution:
The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of failure
mode and effect analysis, it should be noted that if the OSC1 and/or OSC2 pins are left
unconnected, the ST7 main oscillator may start and, in this configuration, could generate an
f
clock frequency in excess of the allowed maximum (> 16MHz), putting the ST7 in an
OSC
unsafe/undefined state. The product behaviour must therefore be considered undefined
when the OSC pins are left unconnected.
6.4.1
6.4.2
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/ceramic oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main
clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges
has to be done by option byte in order to reduce consumption (refer to Section 14.2: Flash
devices on page 185 for more details on the frequency ranges). In this mode of the multi-
oscillator, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and start-up stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the reset phase to avoid losing time in the oscillator
start-up phase.
37/201
Supply, reset and clock management
ST7232Axx-Auto
Table 7.
ST7 clock source
Hardware configuration
ST7
OSC1
OSC2
External source
ST7
OSC1
OSC2
CL1
CL2
Load
capacitors
6.5
Reset sequence manager (RSM)
6.5.1
Introduction
The reset sequence manager includes two reset sources as shown in Figure 12:
●
External RESET source pulse
Internal watchdog reset
●
These sources act on the RESET pin and it is always kept low during the delay phase.
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic reset sequence consists of 3 phases as shown in Figure 11:
●
●
●
Active phase depending on the reset source
256 or 4096 CPU clock cycle delay (selected by option byte)
Reset vector fetch
Caution:
When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that
recovery has taken place from the reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application.
The reset vector fetch phase duration is 2 clock cycles.
38/201
ST7232Axx-Auto
Figure 11. Reset sequence phases
Supply, reset and clock management
Reset
Internal reset
Fetch vector
Active phase
256 or 4096 CLOCK CYCLES
6.5.2
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R weak pull-up
ON
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Section 12: Electrical
characteristics for more details.
A reset signal originating from an external source must have a duration of at least t
h(RSTL)in
in order to be recognized (see Figure 13). This detection is asynchronous and therefore the
MCU can enter reset state even in halt mode.
Figure 12. Reset block diagram
V
DD
R
ON
Internal reset
Filter
RESET
Pulse
generator
Watchdog reset
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
6.5.3
External power on reset
To start up the microcontroller correctly, the user must ensure by means of an external reset
circuit that the reset signal is held low until V is over the minimum level specified for the
DD
selected f
frequency.
OSC
A proper reset signal for a slow rising V supply can generally be provided by an external
DD
RC network connected to the RESET pin.
39/201
Supply, reset and clock management
ST7232Axx-Auto
6.5.4
Internal watchdog reset
The reset sequence generated by a internal watchdog counter overflow is shown in
Figure 13.
Starting from the watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least t
.
w(RSTL)out
Figure 13. Reset sequences
Watchdog
reset
External reset
Run
Run
Run
Active
phase
Active
phase
t
w(RSTL)out
t
h(RSTL)in
External
RESET
source
RESET pin
Watchdog
reset
Watchdog underflow
Internal reset (256 or 4096 T
Vector fetch
)
CPU
40/201
ST7232Axx-Auto
Supply, reset and clock management
6.6
System integrity management
System integrity control/status register (SICSR)
SICSR
7
Reset value: 0000 000x (00b)
6
5
4
3
2
1
0
Reserved
WDGRF
-
R/W
Table 8.
Bit
SICSR register description
Bit name
Function
7:1
Reserved, must be kept cleared
Watchdog reset flag
-
This bit indicates that the last reset was generated by the watchdog
peripheral. It is set by hardware (watchdog reset) and cleared by
software (writing zero).
0
WDGRF
41/201
Interrupts
ST7232Axx-Auto
7
Interrupts
7.1
Introduction
The ST7 enhanced interrupt management provides the following features:
●
●
●
Hardware interrupts
Software interrupt (TRAP)
Nested or concurrent interrupt management with flexible interrupt priority and level
management:
–
–
–
Up to 4 software programmable nesting levels
Up to 16 interrupt vectors fixed by hardware
2 non maskable events: reset, TRAP
This interrupt management is based on:
●
●
●
Bit 5 and bit 3 of the CPU CC register (I1:0)
Interrupt software priority registers (ISPRx)
Fixed interrupt vector addresses located at the high addresses of the memory map
(FFE0h to FFFFh) sorted by hardware priority order
This enhanced interrupt controller guarantees full upward compatibility with the standard
(not nested) ST7 interrupt controller.
7.2
Masking and processing flow
The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx
registers which give the interrupt software priority level of each interrupt vector (see
Table 9). The processing flow is shown in Figure 14.
When an interrupt request has to be serviced:
●
●
●
Normal processing is suspended at the end of the current instruction execution
The PC, X, A and CC registers are saved onto the stack
I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx
registers of the serviced interrupt vector
●
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to Table 15: Interrupt
mapping for vector addresses)
The interrupt service routine should end with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
Note:
As a consequence of the IRET instruction, the I1 and I0 bits are restored from the stack and
the program in the previous level is resumed.
42/201
ST7232Axx-Auto
Interrupts
I0
Table 9.
Interrupt software priority levels
Interrupt software priority
Level
I1
Level 0 (main)
Level 1
1
0
0
1
0
1
0
1
Low
Level 2
High
Level 3 (= interrupt disable)
Figure 14. Interrupt processing flowchart
Pending
interrupt
Y
Y
Reset
TRAP
N
Interrupt has the same or a
lower software priority
than current one
N
I1:0
Fetch next
instruction
The interrupt
stays pending
Y
Interrupt has a higher
software priority
than current one
‘IRET’
N
Restore PC, X, A, CC
from stack
Execute
instruction
Stack PC, X, A, CC
Load I1:0 from interrupt SW register
Load PC from interrupt vector
43/201
Interrupts
ST7232Axx-Auto
7.2.1
Servicing pending interrupts
As several interrupts can be pending at the same time, the interrupt to be taken into account
is determined by the following two-step process:
●
the highest software priority interrupt is serviced
●
if several interrupts have the same software priority then the interrupt with the highest
hardware priority is serviced first
Figure 15 describes this decision process.
Figure 15. Priority decision process
Pending
interrupts
Different
Same
Software
priority
Highest software
priority serviced
Highest hardware
priority serviced
When an interrupt request is not serviced immediately, it is latched and then processed
when its software priority combined with the hardware priority becomes the highest one.
Note:
1
2
The hardware priority is exclusive while the software one is not. This allows the previous
process to succeed with only one interrupt.
Reset and TRAP can be considered as having the highest software priority in the decision
process.
7.2.2
Different interrupt vector sources
Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable
type (reset, TRAP) and the maskable type (external or from internal peripherals).
44/201
ST7232Axx-Auto
Interrupts
7.2.3
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see Figure 14). After stacking the PC, X, A and CC registers (except for reset), the
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to
disable interrupts (level 3). These sources allow the processor to exit halt mode.
●
TRAP (non maskable software interrupt)
This software interrupt is serviced when the TRAP instruction is executed. It is serviced
according to the flowchart in Figure 14.
●
Reset
The reset source has the highest priority in the ST7. This means that the first current routine
has the highest software priority (level 3) and the highest hardware priority. See Section 6.5:
Reset sequence manager (RSM).
7.2.4
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled
and if its own interrupt software priority (in ISPRx registers) is higher than the one currently
being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt
is latched and thus remains pending.
●
External interrupts
External interrupts allow the processor to exit from halt low power mode. External
interrupt sensitivity is software selectable through the external interrupt control register
(EICR).
External interrupt triggered on edge is latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
If several input pins of a group connected to the same interrupt line are selected
simultaneously, these are logically ORed.
●
Peripheral interrupts
Usually the peripheral interrupts cause the MCU to exit from halt mode except those
mentioned in Table 15: Interrupt mapping . A peripheral interrupt occurs when a
specific flag is set in the peripheral status registers and if the corresponding enable bit
is set in the peripheral control register.
The general sequence for clearing an interrupt is based on an access to the status register
followed by a read or write to an associated register.
Note:
The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be
serviced) is therefore lost if the clear sequence is executed.
45/201
Interrupts
ST7232Axx-Auto
7.3
Interrupts and low power modes
All interrupts allow the processor to exit the wait low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the halt modes (see
column ‘exit from halt’ in Table 15: Interrupt mapping). When several pending interrupts are
present while exiting halt mode, the first one serviced can only be an interrupt with exit from
halt mode capability and it is selected through the same decision process shown in
Figure 15.
Note:
If an interrupt, that is not able to exit from halt mode, is pending with the highest priority
when exiting halt mode, this interrupt is serviced after the first one serviced.
7.4
Concurrent and nested management
Figure 16 and Figure 17 show two different interrupt management modes. The first is called
concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode
in Figure 17. The interrupt hardware priority is given in this order from the lowest to the
highest: MAIN, IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt.
Warning: A stack overflow may occur without notifying the software of
the failure.
Figure 16. Concurrent interrupt management
Software priority level
I1
I0
TRAP
3
1
1
1
1
1
1
1
1
1
1
1
1
IT0
3
IT1
IT1
3
IT2
3
IT3
3
RIM
IT4
3
MAIN
11/10
MAIN
10
3/0
46/201
ST7232Axx-Auto
Figure 17. Nested interrupt management
Interrupts
Software priority level
I1
I0
TRAP
3
1
1
1
0
1
1
1
IT0
3
1
0
0
1
1
IT1
IT1
2
IT2
IT2
1
IT3
3
RIM
IT4
IT4
3
MAIN
11/10
MAIN
10
3/0
7.5
Interrupt registers
CPU CC register interrupt bits
CPU CC
Reset value: 111x 1010 (xAh)
7
6
5
4
3
2
1
Z
0
1
I1
H
I0
R/W
N
C
R/W
R/W
R/W
R/W
R/W
R/W
Table 10. CPU CC register description
Bit
Bit name
Function
Software interrupt priority
These two bits indicate the current interrupt software priority:
10: Interrupt software priority = level 0 (main)
01: Interrupt software priority = level 1
00: Interrupt software priority = level 2
11: Interrupt software priority = level 3 (= interrupt disable(1)
These two bits are set/cleared by hardware when entering in
)
5, 3
I1, I0
interrupt. The loaded value is given by the corresponding bits in the
interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT,
WFI, IRET and PUSH/POP instructions (see Table 12: Dedicated
interrupt instruction set).
1. TRAP and reset events can interrupt a level 3 program.
47/201
Interrupts
ST7232Axx-Auto
Interrupt software priority registers (ISPRX)
ISPR0
Reset value: 1111 1111 (FFh)
7
6
5
4
3
2
1
0
I1_3
I0_3
I1_2
I0_2
I1_1
I0_1
I1_0
I0_0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ISPR1
Reset value: 1111 1111 (FFh)
7
6
5
4
3
2
1
0
I1_7
I0_7
I1_6
I0_6
I1_5
I0_5
I1_4
I0_4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ISPR2
Reset value: 1111 1111 (FFh)
7
6
5
4
3
2
1
0
I1_11
I0_11
I1_10
I0_10
I1_9
I0_9
I1_8
I0_8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ISPR3
Reset value: 1111 1111 (FFh)
7
1
6
1
5
1
4
1
3
2
1
0
I1_13
I0_13
I1_12
I0_12
R
R
R
R
R/W
R/W
R/W
R/W
These four registers contain the interrupt software priority of each interrupt vector.
●
Each interrupt vector (except reset and TRAP) has corresponding bits in the ISPRx
registers where its own software priority is stored. This correspondance is shown in
Table 11.
●
●
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1
and I0 bits in the CC register.
Level 0 can not be written (I1_x = 1, I0_x = 0). In this case, the previously stored value
is kept (example, previous = CFh, write = 64h, result = 44h).
Table 11. ISPRx interrupt vector correspondence
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
-
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
-
FFE1h-FFE0h
I1_13 and I0_13 bits
The reset, and TRAP vectors have no software priorities. When one is serviced, the I1 and
I0 bits of the CC register are both set.
Caution:
If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour
has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered.
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).
48/201
ST7232Axx-Auto
Interrupts
7.6
Interrupt related instructions
(1)
Table 12. Dedicated interrupt instruction set
Instruction
New description
Function/example
I1
H
I0
N
Z
C
HALT
IRET
JRM
Entering halt mode
1
0
Interrupt routine return
Jump if I1:0 = 11 (level 3)
Jump if I1:0 <> 11
Pop CC, A, X, PC
I1:0 = 11 ?
I1
H
I0
N
Z
C
JRNM
POP CC
RIM
I1:0 <> 11 ?
Pop CC from the stack
Mem => CC
I1
1
1
1
1
H
I0
0
N
Z
C
Enable interrupt (level 0 set) Load 10 in I1:0 of CC
Disable interrupt (level 3 set) Load 11 in I1:0 of CC
SIM
1
TRAP
WFI
Software TRAP
Wait for interrupt
Software NMI
1
0
1. During the execution of an interrupt routine, the HALT, POP CC, RIM, SIM and WFI instructions change
the current software priority up to the next IRET instruction or one of the previously mentioned instructions.
7.7
External interrupts
7.7.1
I/O port interrupt sensitivity
The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR
register (Figure 18). This control allows up to 4 fully independent external interrupt source
sensitivities.
Each external interrupt source can be generated on four (or five) different events on the pin:
●
●
●
●
●
Falling edge
Rising edge
Falling and rising edge
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity bits in the EICR register can be modified
only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that
interrupts must be disabled before changing sensitivity.
The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits
of the EICR.
49/201
Interrupts
ST7232Axx-Auto
Figure 18. External interrupt control bits
EICR
IS20 IS21
Port A3 interrupt
PAOR.3
PADDR.3
ei0 interrupt source
Sensitivity
PA3
control
IPA bit
EICR
Port F [2:0] interrupts
IS21
IS20
PFOR.2
PFDDR.2
PF2
Sensitivity
control
ei1 interrupt source
ei2 interrupt source
ei3 interrupt source
PF2
PF1
PF0
EICR
Port B [3:0] interrupts
IS10
IS11
PBOR.3
PBDDR.3
PB3
PB2
PB1
PB0
Sensitivity
control
PB3
IPB bit
EICR
Port B [7:4] interrupts
IS11
IS10
PBOR.7
PBDDR.7
PB7
Sensitivity
control
PB7
PB6
PB5
PB4
50/201
ST7232Axx-Auto
Interrupts
7.8
External interrupt control register (EICR)
EICR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
IS1[1:0]
R/W
IPB
IS2[1:0]
R/W
IPA
Reserved
-
R/W
R/W
Table 13. EICR register description
Bit
Bit name
Function
Interrupt sensitivity (ei2 and ei3)
The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to
the following external interrupts:
External interrupt ei2 (port B[3:0]):
00: External interrupt sensitivity = falling edge and low level
(IPB bit = 0) and rising edge and high level (IPB bit = 1)
01: External interrupt sensitivity = rising edge only (IPB bit = 0) and
falling edge only (IPB bit = 1)
10: External interrupt sensitivity = falling edge only (IPB bit = 0) and
rising edge only (IPB bit = 1)
7:6
IS1[1:0]
11: External interrupt sensitivity = rising and falling edge
(IPB bit = 0 and 1)
External interrupt ei3 (port B[4]):
00: external interrupt sensitivity = falling edge and low level
01: external interrupt sensitivity = rising edge only
10: external interrupt sensitivity = falling edge only
11: external interrupt sensitivity = rising and falling edge
These 2 bits can be written only when I1 and I0 of the CC register
are both set to 1 (level 3).
Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B [3:0] external
interrupts. It can be set and cleared by software only when I1 and I0
of the CC register are both set to 1 (level 3).
0: No sensitivity inversion
5
IPB
1: Sensitivity inversion
51/201
Interrupts
ST7232Axx-Auto
Table 13. EICR register description (continued)
Bit
Bit name
Function
Interrupt sensitivity (ei0 and ei1)
The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to
the following external interrupts:
External interrupt ei0 (port A[3:0]):
00: External interrupt sensitivity = falling edge and low level
(IPA bit = 0) and rising edge and high level (IPA bit = 1)
01: External interrupt sensitivity = rising edge only (IPA bit = 0) and
falling edge only (IPA bit = 1)
10: External interrupt sensitivity = falling edge only (IPA bit = 0) and
rising edge only (IPA bit = 1)
4:3
IS2[1:0]
11: External interrupt sensitivity = rising and falling edge
(IPA bit = 0 and 1)
External interrupt ei1 port ([F2:0]):
00: External interrupt sensitivity = falling edge and low level
01: External interrupt sensitivity = rising edge only
10: External interrupt sensitivity = falling edge only
11: External interrupt sensitivity = rising and falling edge
These 2 bits can be written only when I1 and I0 of the CC register
are both set to 1 (level 3).
Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A [3:0] external
interrupts. It can be set and cleared by software only when I1 and I0
of the CC register are both set to 1 (level 3).
0: No sensitivity inversion
2
IPA
-
1: Sensitivity inversion
1:0
Reserved, must always be kept cleared
52/201
ST7232Axx-Auto
Interrupts
7.9
Nested interrupts register map and reset value
Table 14. Nested interrupts register map and reset values
Address (Hex.)
Register label
7
6
5
4
3
2
1
0
ei1
SPI
AVD
ei0
MCC + SI
I1_1 I0_1
ISPR0
Reset value
0024h
I1_3
1
I0_3
1
I1_2
1
I0_2
1
1
1
1
1
ei3
ei2
ISPR1
Reset value
0025h
0026h
I1_7
1
I0_7
1
I1_6
1
I0_6
1
I1_5
1
I0_5
1
I1_4
1
I0_4
1
SCI
Timer B
Timer A
ISPR2
Reset value
I1_11
1
I0_11
1
I1_10
1
I0_10
1
I1_9
1
I0_9
1
I1_8
1
I0_8
1
ISPR3
Reset value
I1_13
1
I0_13
1
I1_12
1
I0_12
1
0027h
0028h
1
1
1
1
EICR
Reset value
IS11
0
IS10
0
IPB
0
IS21
0
IS20
0
IPA
0
0
0
7.10
Interrupt mapping
Table 15. Interrupt mapping
Source
Register Priority Exitfrom
Exit from
active halt
No.
Description
Address vector
block
label
order
halt
Reset
TRAP
Reset
Yes
No
Yes
No
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
N/A
Software interrupt
0
1
Not used
Main clock controller time
base interrupt
Higher
priority
MCC/RTC
MCCSR
Yes
Yes
FFF8h-FFF9h
2
3
ei0
ei1
ei2
ei3
External interrupt port A[3:0]
External interrupt port F[2:0]
External interrupt port B[3:0]
External interrupt port B[7:4]
Not used
Yes
Yes
Yes
Yes
No
No
No
No
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
N/A
4
5
6
Not used
7
SPI
SPI peripheral interrupts
SPICSR
TASR
Yes(1)
No
No
No
No
No
8
Timer A Timer A peripheral interrupts
Timer B Timer B peripheral interrupts
9
TBSR
No
10
11
SCI
SCI peripheral interrupts
Not used
SCISR
No
Lower
priority
1. Unexpected exit from halt may occur when SPI is in slave mode.
53/201
Power saving modes
ST7232Axx-Auto
8
Power saving modes
8.1
Introduction
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 19): slow, wait (slow
wait), active halt and halt.
After a reset the normal operating mode is selected by default (RUN mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided or multiplied by 2 (f
).
OSC2
From RUN mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
Figure 19. Power saving mode transitions
High
Run
Slow
Wait
Slow wait
Active halt
Halt
Low
Power consumption
8.2
Slow mode
This mode has two targets:
●
To reduce power consumption by decreasing the internal clock in the device
To adapt the internal clock frequency (f ) to the available supply voltage
●
CPU
Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or
disables slow mode and two CPx bits which select the internal slow frequency (f ).
CPU
In this mode, the master clock frequency (f
) can be divided by 2, 4, 8 or 16. The CPU
OSC2
and peripherals are clocked at this lower frequency (f
).
CPU
Note:
Slow wait mode is activated when entering the wait mode while the device is already in slow
mode.
54/201
ST7232Axx-Auto
Figure 20. Slow mode clock transitions
Power saving modes
f
/2
f
/4
f
OSC2
OSC2
OSC2
f
CPU
f
OSC2
00
01
CP1:0
SMS
Normal run mode request
New slow
frequency request
8.3
Wait mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During wait mode, the I[1:0] bits of the CC register are forced
to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU
remains in wait mode until an interrupt or reset occurs, whereupon the program counter
branches to the starting address of the interrupt or reset service routine. The MCU remains
in wait mode until a reset or an interrupt occurs, causes it to wake up.
Refer to Figure 21.
55/201
Power saving modes
Figure 21. Wait mode flow-chart
ST7232Axx-Auto
Oscillator
Peripherals
CPU
ON
ON
OFF
10
WFI instruction
I[1:0] bits
N
Reset
Y
N
Interrupt
Y
Oscillator
Peripherals
CPU
ON
OFF
ON
10
I[1:0] bits
256 OR 4096 CPU clock
cycle delay
Oscillator
Peripherals
CPU
ON
ON
ON
(1)
I[1:0] bits
XX
Fetch reset vector or
service interrupt
1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
8.4
Active halt and halt modes
Active halt and halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in active
halt or halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR
register).
Table 16. Active halt and halt power saving modes
MCCSR
Power saving mode entered when HALT instruction is executed
OIE bit
0
1
Halt mode
Active halt mode
56/201
ST7232Axx-Auto
Power saving modes
8.4.1
Active halt mode
Active halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the main clock
controller status register (MCCSR) is set (see Section 10.2: Main clock controller with real-
time clock and beeper (MCC/RTC) on page 73 for more details on the MCCSR register).
The MCU can exit active halt mode on reception of either an MCC/RTC interrupt, a specific
interrupt (see Table 15: Interrupt mapping on page 53) or a reset. When exiting active halt
mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes
operation by servicing the interrupt or by fetching the reset vector which woke it up (see
Figure 23).
When entering active halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In active halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
The safeguard against staying locked in active halt mode is provided by the oscillator
interrupt.
Note:
As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set),
entering active halt mode while the watchdog is active does not generate a reset. This
means that the device cannot spend more than a defined delay in this power saving mode.
Caution:
When exiting active halt mode following an interrupt, OIE bit of MCCSR register must not be
cleared before t
after the interrupt occurs (t
= 256 or 4096 t
delay depending
DELAY
DELAY
CPU
on option byte). Otherwise, the ST7 enters halt mode for the remaining t
period.
DELAY
Figure 22. Active halt timing overview
Active
halt
256 OR 4096 CPU
cycle delay
Run
Run
(1)
Reset or interrupt
HALT
instruction
Fetch
vector
[MCCSR.OIE = 1]
1. This delay occurs only if the MCU exits active halt mode by means of a reset
57/201
Power saving modes
Figure 23. Active halt mode flow-chart
ST7232Axx-Auto
Oscillator
Peripherals
CPU
ON
OFF
OFF
10
(1)
HALT instruction
(MCCSR.OIE = 1)
I[1:0] bits
N
Reset
Y
N
(2)
Interrupt
Oscillator
Peripherals
CPU
ON
OFF
ON
Y
(3)
I[1:0] bits
XX
256 OR 4096 CPU clock
cycle delay
Oscillator
Peripherals
CPU
ON
ON
ON
(3)
I[1:0] bits
XX
Fetch reset vector or
service interrupt
1. Peripheral clocked with an external clock source can still be active
2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from active halt mode (such as
external interrupt). Refer to Table 15: Interrupt mapping on page 53 for more details.
3. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and restored when the CC register is
popped.
8.4.2
Halt mode
The halt mode is the lowest power consumption mode of the MCU. It is entered by executing
the ‘HALT’ instruction when the OIE bit of the main clock controller status register (MCCSR)
is cleared (see Section 10.2: Main clock controller with real-time clock and beeper
(MCC/RTC) on page 73 for more details on the MCCSR register).
The MCU can exit halt mode on reception of either a specific interrupt (see Table 15:
Interrupt mapping on page 53) or a reset. When exiting halt mode by means of a reset or an
interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is
used to stabilize the oscillator. After the start up delay, the CPU resumes operation by
servicing the interrupt or by fetching the reset vector which woke it up (see Figure 25).
When entering halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
58/201
ST7232Axx-Auto
Power saving modes
The compatibility of watchdog operation with halt mode is configured by the ‘WDGHALT’
option bit of the option byte. The HALT instruction when executed while the watchdog
system is enabled, can generate a watchdog reset (see Section 14.2 on page 185) for more
details.
Figure 24. Halt timing overview
256 OR 4096 CPU
Run
Halt
Run
cycle delay
Reset or interrupt
HALT
instruction
Fetch
vector
[MCCSR.OIE = 1]
59/201
Power saving modes
Figure 25. Halt mode flow-chart
ST7232Axx-Auto
HALT instruction
(MCCSR.OIE = 0)
Enable
Watchdog
Disable
0
(1)
WDGHALT
1
Oscillator
OFF
OFF
OFF
10
Watchdog reset
(2)
Peripherals
CPU
I[1:0] bits
N
Reset
Y
N
(3)
Interrupt
Oscillator
Peripherals
CPU
ON
OFF
ON
Y
(4)
I[1:0] bits
XX
256 or 4096 CPU clock
cycle delay
Oscillator
ON
ON
ON
Peripherals
CPU
(4)
I[1:0] bits
XX
Fetch reset vector or
service interrupt
1. WDGHALT is an option bit. See Section 14.2: Flash devices for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from halt mode (such as external interrupt). Refer to
Table 15: Interrupt mapping on page 53 for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
60/201
ST7232Axx-Auto
Power saving modes
Halt mode recommendations
●
Make sure that an external event is available to wake up the microcontroller from halt
mode
●
When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as ‘input pull-up with interrupt’ before executing the HALT instruction.
The main reason for this is that the I/O may be wrongly configured due to external
interference or by an unforeseen logical condition.
●
●
For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
The opcode for the HALT instruction is 0 x 8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
●
As the HALT instruction clears the interrupt mask in the CC register to allow interrupts,
the user may choose to clear all pending interrupt bits before executing the HALT
instruction. This avoids entering other peripheral interrupt routines after executing the
external interrupt routine corresponding to the wake up event (reset or external
interrupt).
61/201
I/O ports
ST7232Axx-Auto
9
I/O ports
9.1
Introduction
The I/O ports offer different functional modes:
●
Transfer of data through digital inputs and outputs
For specific pins they offer different functional modes:
●
●
External interrupt generation
Alternate signal input/output for the on-chip peripherals
An I/O port contains up to 8 pins. Each pin can be programmed independently as digital
input (with or without interrupt generation) or digital output.
9.2
Functional description
Each port has 2 main registers:
●
Data register (DR)
●
Data direction register (DDR)
Each port also has one optional register:
Option register (OR)
●
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR
registers: bit X corresponding to pin X of the port. The same correspondence is used for the
DR register.
The following description takes into account the OR register, (for specific ports which do not
provide this register refer to Section 9.3: I/O port implementation on page 66). The generic
I/O block diagram is shown in Figure 26.
9.2.1
Input modes
The input configuration is selected by clearing the corresponding DDR register bit. In this
case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
Note:
1
Writing the DR register modifies the latch value but does not affect the pin status.
2
When switching from input to output mode, the DR register has to be written first to drive the
correct level on the pin as soon as the port is configured as an output.
3
Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this
might corrupt the DR content for I/Os configured as input."
62/201
ST7232Axx-Auto
I/O ports
External interrupt function
When an I/O is configured as input with interrupt, an event on this I/O can generate an
external interrupt request to the CPU.
Each pin can independently generate an interrupt request. The interrupt sensitivity is
independently programmable using the sensitivity bits in the EICR register.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see Section 2:
Pin description and Section 7: Interrupts). If several input pins are selected simultaneously
as interrupt sources, these are first detected according to the sensitivity bits in the EICR
register and then logically ORed.
The external interrupts are hardware interrupts, which means that the request latch (not
accessible directly by the application) is automatically cleared when the corresponding
interrupt vector is fetched. To clear an unwanted pending interrupt by software, the
sensitivity bits in the EICR register must be modified.
9.2.2
Output modes
The output configuration is selected by setting the corresponding DDR register bit. In this
case, writing the DR register applies this digital value to the I/O pin through the latch. Then
reading the DR register returns the previously stored value.
Two different output modes can be selected by software through the OR register: Output
push-pull and open-drain.
See Table 17 for the DR register value and output pin status.
Table 17. DR register value and output pin status
DR
Push-pull
Open-drain
0
1
VSS
VDD
Vss
Floating
9.2.3
Alternate functions
When an on-chip peripheral is configured to use a pin, the alternate function is automatically
selected. This alternate function takes priority over the standard I/O programming.
When the signal is coming from an on-chip peripheral, the I/O pin is automatically
configured in output mode (push-pull or open drain according to the peripheral).
When the signal is going to an on-chip peripheral, the I/O pin must be configured in input
mode. In this case, the pin state is also digitally readable by addressing the DR register.
Note:
Input pull-up configuration can cause unexpected value at the input of the alternate
peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to
be configured in input floating mode.
63/201
I/O ports
ST7232Axx-Auto
Figure 26. I/O port general block diagram
1
0
Register
access
Alternate
output
V
DD
P-buffer (see Table below)
Pull-up (see Table below)
Alternate
enable
DR
DDR
OR
V
DD
Pull-up
condition
Pad
If implemented
OR SEL
DDR SEL
DR SEL
N-buffer
Diodes
(see Table below)
Analog input
CMOS
Schmitt trigger
1
0
Alternate input
External interrupt
source (ei )
x
Table 18. I/O port mode options
Configuration mode
Diodes
Pull-up
P-buffer
to VDD
to VSS
Floating with/without interrupt
Input
Off(1)
On(2)
Off(1)
Pull-up with/without interrupt
On(2)
Push-pull
On(2)
Off(1)
NI(3)
On(2)
Off(1)
NI(3)
Output
Open drain (logic level)
True open drain
NI(4)
1. Implemented not activated
2. Implemented and activated
3. Not implemented
4. The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VSS is
implemented to protect the device against positive stress.
64/201
ST7232Axx-Auto
I/O ports
Table 19. I/O port configurations
Hardware configuration
DR register access
W
Not implemented in
true open drain
I/O ports
V
DD
Pull-up condition
R
PU
DR
register
Data bus
Pad
R
Alternate input
External interrupt source (ei )
x
Interrupt condition
Analog input
Not implemented in
true open drain
I/O ports
DR register access
V
DD
R
PU
R/W
DR
register
Data bus
Pad
Alternate
output
Alternate
enable
Not implemented in
true open drain
I/O ports
DR register access
R/W
V
DD
R
PU
DR
register
Data bus
Pad
Alternate
output
Alternate
enable
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR
register reads the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate
function reads the pin status given by the DR register content.
Caution:
The alternate function must not be activated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious interrupts.
65/201
I/O ports
ST7232Axx-Auto
Analog alternate function
When the pin is used as an ADC input, the I/O must be configured as floating input. The
analog multiplexer (controlled by the ADC registers) switches the analog voltage present on
the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level or loading on any port pin while
conversion is in progress. Furthermore it is recommended not to have clocking pins located
close to a selected analog pin.
Warning: The analog input voltage level must be within the limits
stated in the absolute maximum ratings.
9.3
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 27
Other transitions are potentially risky and should be avoided, since they are likely to present
unwanted side-effects such as spurious interrupt generation. The I/O port register
configurations are summarized in Table 20 below.
Figure 27. Interrupt I/O port state transitions
01
00
10
11
Input
floating/pull-up
interrupt
Input
floating
(reset state)
Output
open-drain
Output
push-pull
= DDR, OR
XX
66/201
ST7232Axx-Auto
I/O ports
Table 20. Port register configurations
Input (DDR = 0)
Output (DDR = 1)
Port
Pin name
OR = 0
OR = 1
OR = 0
OR = 1
PA[7:6]
PA[5:4]
PA[3]
Floating
True open-drain
Port A
Port B
Pull-up
Floating interrupt
Pull-up interrupt
PB[3]
PB[4]
PB[2:0]
Port C
Port D
Port E
PC[7:0]
PD[5:0]
PE[1:0]
Floating
Open drain
Push-pull
Pull-up
PF[7:6]
PF[4]
Port F
PF[2]
Floating interrupt
Pull-up interrupt
PF[1:0]
9.4
9.5
Low power modes
Table 21. Effect of low power modes on I/O ports
Mode Description
Wait
Halt
No effect on I/O ports. External interrupts cause the device to exit from wait mode.
No effect on I/O ports. External interrupts cause the device to exit from halt mode.
Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and the interrupt mask in the CC register is not active
(RIM instruction).
Table 22. I/O interrupt control/wake-up capability
Interrupt event
Event flag Enable control bit Exit from wait Exit from halt
External interrupt on selected
external event
DDRx
ORx
-
Yes
67/201
I/O ports
ST7232Axx-Auto
Table 23. I/O port register map and reset values
Address (Hex.) Register label
7
6
5
4
3
2
1
0
Reset value of all I/O port registers
0
0
0
0
0
0
0
0
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
PADR
PADDR
PAOR
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
PEDDR
PEOR
PFDR
PFDDR
PFOR
68/201
ST7232Axx-Auto
On-chip peripherals
10
On-chip peripherals
10.1
Watchdog timer (WDG)
10.1.1
Introduction
The watchdog timer is used to detect the occurrence of a software fault, usually generated
by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The watchdog circuit generates an MCU reset on
expiry of a programmed time period, unless the program refreshes the counter’s contents
before the T6 bit becomes cleared.
10.1.2
10.1.3
Main features
●
●
●
●
●
Programmable free-running downcounter
Programmable reset
Reset (if watchdog activated) when the T6 bit reaches zero
Optional reset on HALT instruction (configurable by option byte)
Hardware watchdog selectable by option byte
Functional description
The counter value stored in the watchdog control register (WDGCR bits T[6:0]), is
decremented every 16384 f
cycles (approx.), and the length of the timeout period can
OSC2
be programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling the reset pin low
for typically 30µs.
The application program must write in the WDGCR register at regular intervals during
normal operation to prevent an MCU reset. This downcounter is free-running: it counts down
even if the watchdog is disabled. The value to be stored in the WDGCR register must be
between FFh and C0h:
●
●
●
The WDGA bit is set (watchdog enabled)
The T6 bit is set to prevent generating an immediate reset
The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset (see Figure 29: Approximate timeout duration).
The timing varies between a minimum and a maximum value due to the unknown
status of the prescaler when writing to the WDGCR register (see Figure 30).
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
If the watchdog is activated, the HALT instruction generates a reset.
69/201
On-chip peripherals
Figure 28. Watchdog block diagram
ST7232Axx-Auto
Reset
f
OSC2
MCC/RTC
Watchdog control register (WDGCR)
DIV 64
WDGA T6
T5
T4
T3
T2
T1
T0
6-bit downcounter (CNT)
12-bit MCC
RTC counter
WDG prescaler DIV 4
TB[1:0] bits (MCCSR register)
MSB
LSB
0
6 5
11
10.1.4
How to program the watchdog timeout
Figure 29 shows the linear relationship between the 6-bit value to be loaded in the watchdog
counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a
quick calculation without taking the timing variations into account. If more precision is
needed, use the formulae in Figure 30.
Caution:
When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 29. Approximate timeout duration
3F
38
30
28
20
18
10
08
00
1.5
18
34
50
65
82
98
114
128
Watchdog timeout (ms) @ 8 MHz. f
OSC2
70/201
ST7232Axx-Auto
On-chip peripherals
Figure 30. Exact timeout duration (t
and t
)
min
max
Where:
t
t
t
= (LSB + 128) x 64 x t
OSC2
min0
= 16384 x t
max0
OSC2
OSC2
= 125ns if f
= 8 MHz
OSC2
CNT = value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register.
TB1 bit (MCCSR reg.)
TB0 bit (MCCSR reg.)
Selected MCCSR timebase
MSB
LSB
0
0
1
1
0
1
0
1
2ms
4ms
4
8
59
53
35
54
10ms
25ms
20
49
To calculate the minimum watchdog timeout (t ):
min
MSB
4
If
Then
Else
t
= tmin0 + 16384 × CNT × t
-------------
CNT <
min
osc2
4CNT
----------------
4CNT
----------------
⎛
⎞
⎠
t
= t
+
16384 × CNT –
+ (192 + LSB) × 64 ×
× t
osc2
min
min0
⎝
MSB
MSB
To calculate the maximum watchdog timeout (t
):
max
MSB
4
If
-------------
Then
CNT ≤
t
= tmax0 + 16384 × CNT × t
max
osc2
4CNT
----------------
4CNT
----------------
⎛
⎞
Else
t
= t
+
16384 × CNT –
+ (192 + LSB) × 64 ×
× t
osc2
max
max0
⎝
⎠
MSB
MSB
Note: In the above formulae, division results must be rounded down to the next integer value.
Example: With 2ms timeout selected in MCCSR register
Value of T[5:0] bits in WDGCR register
(Hex.)
Min. watchdog timeout (ms)
Max. watchdog timeout (ms)
tmax
tmin
00
3F
1.496
128
2.048
128.552
71/201
On-chip peripherals
ST7232Axx-Auto
10.1.5
Low power modes
Table 24. Effect of low power modes on watchdog timer
Mode Description
Slow
Wait
No effect on watchdog.
No effect on watchdog.
OIE bit in
MCCSR
register
WDGHALT
bit in option
byte
No watchdog reset is generated. The MCU enters halt mode.
The watchdog counter is decremented once and then stops
counting and is no longer able to generate a watchdog reset
until the MCU receives an external interrupt or a reset.
0
0
If an external interrupt is received, the watchdog restarts
counting after 256 or 4096 CPU clocks. If a reset is generated,
the watchdog is disabled (reset state) unless hardware
watchdog is selected by option byte. For application
recommendations see Section 10.1.7 below.
Halt
0
1
1
x
A reset is generated
No reset is generated. The MCU enters active halt mode. The
watchdog counter is not decremented. It stops counting. When
the MCU receives an oscillator interrupt or external interrupt,
the watchdog restarts counting immediately. When the MCU
receives a reset the watchdog restarts counting after 256 or
4096 CPU clocks.
10.1.6
10.1.7
Hardware watchdog option
If hardware watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to Section 14.2: Flash devices.
Using halt mode with the WDG (WDGHALT option)
The following recommendation applies if halt mode is used when the watchdog is enabled:
Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected
WDG reset immediately after waking up the microcontroller.
10.1.8
Interrupts
None
72/201
ST7232Axx-Auto
On-chip peripherals
10.1.9
Control register (WDGCR)
WDGCR
7
Reset value: 0111 1111 (7Fh)
6
5
4
3
2
1
0
WDGA
R/W
T[6:0]
R/W
Table 25. WDGCR register description
Bit
Bit name
Function
Activation bit(1)
This bit is set by software and only cleared by hardware after a reset.
When WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
7
WDGA
1: Watchdog enabled
7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter. They are
decremented every 16384 fOSC2 cycles (approx.). A reset is
produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
6:0
T[6:0]
1. The WDGA bit is not used if the hardware watchdog option is enabled by option byte.
10.1.10 Watchdog timer register map and reset values
Table 26. Watchdog timer register map and reset values
Address(Hex.) Register label
7
6
5
4
3
2
1
0
WDGCR
002Ah
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
Reset value
10.2
Main clock controller with real-time clock and beeper
(MCC/RTC)
The main clock controller consists of three different functions:
●
A programmable CPU clock prescaler
●
A clock-out signal to supply external devices
●
A real-time clock timer with interrupt capability
Each function can be used independently and simultaneously.
10.2.1
Programmable CPU clock prescaler
The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal
peripherals. It manages slow power saving mode (see Section 8.2: Slow mode for more
details).
The prescaler selects the f
main clock frequency and is controlled by three bits in the
CPU
MCCSR register: CP[1:0] and SMS.
73/201
On-chip peripherals
ST7232Axx-Auto
10.2.2
Clock-out capability
The clock-out capability is an alternate function of an I/O port pin that outputs a f
to drive external devices. It is controlled by the MCO bit in the MCCSR register.
clock
OSC2
Caution:
When selected, the clock out pin suspends the clock during active halt mode.
10.2.3
Real-time clock timer (RTC)
The counter of the real-time clock timer allows an interrupt to be generated based on an
accurate real-time clock. Four different time bases depending directly on f are available.
OSC2
The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and
OIF.
When the RTC interrupt is enabled (OIE bit set), the ST7 enters active halt mode when the
HALT instruction is executed. See Section 8.4: Active halt and halt modes for more details.
10.2.4
Beeper
The beep function is controlled by the MCCBCR register. It can output three selectable
frequencies on the BEEP pin (I/O port alternate function).
Figure 31.
Main clock controller (MCC/RTC) block diagram
BC1 BC0
MCCBCR
Beep signal
selection
Beep
MCO
To watchdog timer
MCC/RTC interrupt
12-bit MCC RTC
counter
DIV 64
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
MCCSR
f
OSC2
DIV 2, 4, 8, 16
1
0
CPU clock
to CPU and
peripherals
f
CPU
74/201
ST7232Axx-Auto
On-chip peripherals
10.2.5
Low power modes
Table 27. Effect of low power modes on MCC/RTC
Mode
Description
No effect on MCC/RTC peripheral
MCC/RTC interrupt causes the device to exit from wait mode
Wait
No effect on MCC/RTC counter (OIE bit is set), the registers are frozen
MCC/RTC interrupt causes the device to exit from active halt mode
Active halt
Halt
MCC/RTC counter and registers are frozen
MCC/RTC operation resumes when the MCU is woken up by an interrupt with
‘exit from halt’ capability
10.2.6
Interrupts
The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is
set and the interrupt mask in the CC register is not active (RIM instruction).
Table 28. MCC/RTC interrupt control/wake-up capability
Interrupt event
Event flag Enable control bit Exit from wait
OIF OIE Yes
Exit from halt
Time base overflow event
No(1)
1. The MCC/RTC interrupt wakes up the MCU from active halt mode, not from halt mode.
75/201
On-chip peripherals
ST7232Axx-Auto
10.2.7
MCC/RTC registers
MCC control/status register (MCCSR)
MCCSR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
MCO
CP[1:0]
R/W
SMS
OIE
OIF
TB[1:0]
R/W
R/W
R/W
R/W
R/W
Table 29. MCCSR register description
Bit
Bit name
Function
Main clock out selection
This bit enables the MCO alternate function on the PF0 I/O port. It is
set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
7
MCO
1: MCO alternate function enabled (fCPU on I/O port)
Note: To reduce power consumption, the MCO function is not active
in active halt mode.
CPU clock prescaler
These bits select the CPU clock prescaler which is applied in the
different slow modes. Their action is conditioned by the setting of the
SMS bit. These two bits are set and cleared by software.
00: fCPU in slow mode = fOSC2/2
6:5
CP[1:0]
01: fCPU in slow mode = fOSC2/4
10: fCPU in slow mode = fOSC2/8
11: fCPU in slow mode = fOSC2/16
Slow mode select
This bit is set and cleared by software.
0: Normal mode, fCPU = fOSC2
4
SMS
1: Slow mode, fCPU is given by CP1, CP0; see Section 8.2: Slow
mode and Section 10.2: Main clock controller with real-time clock
and beeper (MCC/RTC) for more details.
Time base control
These bits select the programmable divider time base. They are set
and cleared by software:
00: Time base (for counter prescaler 16000) = 4ms (fOSC2 = 4MHz)
and 2ms (fOSC2 = 8MHz)
01: Time base (for counter prescaler 32000) = 8ms (fOSC2 = 4MHz)
and 4ms (fOSC2 = 8MHz)
10: Time base (for counter prescaler 80000) = 20ms (fOSC2 = 4MHz)
and 10ms (fOSC2 = 8MHz)
3:2
TB[1:0]
11: Time base (for counter prescaler 200000) = 50ms
(fOSC2 = 4MHz) and 25ms (fOSC2 = 8MHz)
A modification of the time base is taken into account at the end of the
current period (previously set) to avoid an unwanted time shift. This
allows use of this time base as a real-time clock.
76/201
ST7232Axx-Auto
Table 29. MCCSR register description (continued)
On-chip peripherals
Bit
Bit name
Function
Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from active halt mode. When this
bit is set, calling the ST7 software HALT instruction enters the active
1
0
OIE
halt power saving mode
.
Oscillator interrupt flag
This bit is set by hardware and cleared by software reading the
MCCSR register. It indicates when set that the main oscillator has
reached the selected elapsed time (TB1:0).
OIF
0: Timeout not reached
1: Timeout reached
Caution: The BRES and BSET instructions must not be used on the
MCCSR register to avoid unintentionally clearing the OIF bit.
MCC beep control register (MCCBCR)
MCCBCR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
Reserved
-
BC[1:0]
R/W
Table 30. MCCBCR register description
Bit
Bit name
Function
7:2
-
Reserved, must be kept cleared
Beep control
These 2 bits select the PF1 pin beep capability:
00: Beep mode (with fOSC2 = 8MHz) = off
01: Beep mode (with fOSC2 = 8MHz) = ~2-KHz (output beep
signal ~ 50% duty cycle)
1:0
BC[1:0]
10: Beep mode (with fOSC2 = 8MHz) = ~1-KHz (output beep
signal ~ 50% duty cycle)
11: beep mode (with fOSC2 = 8MHz) = ~500-Hz (output beep
signal ~ 50% duty cycle)
The beep output signal is available in active halt mode but has to be
disabled to reduce the consumption.
77/201
On-chip peripherals
ST7232Axx-Auto
10.2.8
MCC register map and reset values
Table 31. Main clock controller register map and reset values
Address(Hex.) Register label
7
6
5
4
3
2
1
0
MCCSR
002Ch
MCO CP1 CP0 SMS TB1 TB0
OIE
0
OIF
0
Reset value
0
0
0
0
0
0
MCCBCR
002Dh
BC1 BC0
Reset value
0
0
0
0
0
0
0
0
10.3
16-bit timer
10.3.1
Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler.
It may be used for a variety of purposes, including pulse length measurement of up to two
input signals (input capture) or generation of up to two output waveforms (output compare
and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the CPU clock prescaler.
Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and
do not share any resources. They are synchronized after a MCU reset as long as the timer
clock frequencies are not modified.
This description covers one or two 16-bit timers. In ST7 devices with two timers, register
names are prefixed with TA (Timer A) or TB (Timer B).
10.3.2
Main features
●
●
●
Programmable prescaler: f
divided by 2, 4 or 8
CPU
Overflow status flag and maskable interrupt
External clock input (must be at least 4 times slower than the CPU clock speed) with
the choice of active edge
●
1 or 2 output compare functions each with:
–
–
–
–
2 dedicated 16-bit registers
2 dedicated programmable signals
2 dedicated status flags
1 dedicated maskable interrupt
●
1 or 2 input capture functions each with:
–
–
–
–
2 dedicated 16-bit registers
2 dedicated active edge selection signals
2 dedicated status flags
1 dedicated maskable interrupt
●
●
Pulse width modulation mode (PWM
One pulse mode
78/201
ST7232Axx-Auto
On-chip peripherals
●
●
Reduced power mode
5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)
(a)
The block diagram is shown in Figure 32.
10.3.3
Functional description
Counter
The main block of the programmable timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
Counter register (CR)
●
Counter high register (CHR) is the most significant byte (MS byte)
Counter low register (CLR) is the least significant byte (LS byte)
●
Alternate counter register (ACR)
●
Alternate counter high register (ACHR) is the most significant byte (MS byte)
Alternate counter low register (ACLR) is the least significant byte (LS byte)
●
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the
status register, (SR), (see 16-bit read sequence (from either the counter register or alternate
counter register) on page 81).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value.
Both counters have a reset value of FFFCh (this is the only value which is reloaded in the
16-bit timer). The reset value of both counters is also FFFCh in one pulse mode and PWM
mode.
The timer clock depends on the clock control bits (bits 3 and 2) of the CR2 register, as
illustrated in Table 36: CR2 register description. The value in the counter register repeats
every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The
timer frequency can be f
/2, f
/4, f
/8 or an external frequency.
CPU
CPU
CPU
Caution:
In Flash devices, Timer A functionality has the following restrictions:
●
●
●
TAOC2HR and TAOC2LR registers are write only
Input capture 2 is not implemented
The corresponding interrupts cannot be used (ICF2, OCF2 forced by hardware to zero)
a. Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pinout
description. When reading an input signal on a non-bonded pin, the value is always ‘1’.
79/201
On-chip peripherals
ST7232Axx-Auto
Figure 32. Timer block diagram
ST7 internal bus
f
CPU
MCU-peripheral interface
8 high
8 low
8-bit
buffer
8
8
8
8
8
8
8
8
High
Low
High
Low
High
Low
High
Low
EXEDG
16
1/2
Output
Output
compare
register
2
Input
capture
register
2
Input
capture
register
1
Counter register
compare
register
1
1/4
1/8
EXTCLK
pin
Alternate counter
register
16
16
16
CC[1:0]
Timer internal bus
16 16
Overflow detect
circuit
Edge detect circuit 1
Edge detect circuit 2
Output compare circuit
ICAP1
pin
6
ICAP2
pin
Latch1
Latch2
OCMP1
pin
0
ICF1 OCF1 TOF ICF2 OCF2
0
TIMD
OCMP2
pin
CSR (control/status register)
EXEDG
OPM PWM CC1 CC0 IEDG2
OC2E
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
CR1 (control register 1)
OC1E
CR2 (control register 2)
(1)
Timer interrupt
1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (see Table 15: Interrupt mapping on page 53).
80/201
ST7232Axx-Auto
16-bit read sequence (from either the counter register or alternate counter register)
Figure 33. 16-bit read sequence
On-chip peripherals
Beginning of the sequence
Read MS byte
At t0
LS byte is buffered
Other
instructions
Returns buffered LS byte
value at t0
At t0 +∆t
Read LS byte
Sequence completed
The user must read the MS byte first, then the LS byte value is buffered automatically.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MS byte several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LS byte of the count value at the time of the read.
Whatever the timer mode used (input capture, output compare, one pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:
●
The TOF bit of the SR register is set
●
A timer interrupt is generated if the TOIE bit of the CR1 register is set and the I bit of the
CC register is cleared
If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done in two steps:
1. Reading the SR register while the TOF bit is set
2. An access (read or write) to the CLR register
Note:
The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by wait mode.
In halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (MCU awakened by an interrupt) or from the reset count (MCU
awakened by a reset).
81/201
On-chip peripherals
ST7232Axx-Auto
External clock
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that triggers the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 34. Counter timing diagram, internal clock divided by 2
CPU clock
Internal reset
Timer clock
FFFD FFFE FFFF 0000 0001 0002 0003
Counter register
Timer overflow flag (TOF)
Figure 35. Counter timing diagram, internal clock divided by 4
CPU clock
Internal reset
Timer clock
FFFD
FFFC
0000
0001
Counter register
Timer overflow flag (TOF)
Figure 36. Counter timing diagram, internal clock divided by 8
CPU clock
Internal reset
Timer clock
FFFC
FFFD
0000
Counter register
Timer overflow flag (TOF)
Note:
The MCU is in reset state when the internal reset signal is high, when it is low the MCU is
running.
82/201
ST7232Axx-Auto
On-chip peripherals
Input capture
In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the
16-bit timer.
The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the
free running counter after a transition is detected on the ICAPi pin (see below).
MSB
LSB
ICiR
ICiHR
ICiLR
ICiR register is a read-only register.
The active transition is software programmable through the IEDGi bit of Control Registers
(CRi).
Timing resolution is one count of the free running counter: (fCPU/CC[1:0]).
Procedure
To use the input capture function select the following in the CR2 register:
●
The timer clock (CC[1:0]) (see Table 36: CR2 register description)
●
The edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with pull-up without interrupt if this
configuration is available).
Select the following in the CR1 register:
●
Set the ICIE bit to generate an interrupt after an input capture coming from either the
ICAP1 pin or the ICAP2 pin.
●
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1pin must be configured as floating input or input with pull-up without interrupt if
this configuration is available).
When an input capture occurs:
●
ICFi bit is set
●
The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see Figure 38).
●
A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC
register. Otherwise, the interrupt remains pending until both conditions become true.
Clearing the input capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:
1. By reading the SR register while the ICFi bit is set
2. By accessing (reading or writing) the ICiLR register
83/201
On-chip peripherals
ST7232Axx-Auto
Note:
1
2
3
After reading the ICiHR register, transfer of input capture data is inhibited and ICFi is never
set until the ICiLR register is also read.
The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
The 2 input capture functions can be used together even if the timer also uses the 2 output
compare functions.
4
5
In one pulse mode and PWM mode only input capture 2 can be used.
The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any
transitions on these pins activates the input capture function.
Moreover if one of the ICAPi pins is configured as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the ICiHR
(see note 1).
6
7
The TOF bit can be used with interrupt generation in order to measure events that go
beyond the timer range (FFFFh).
In Flash devices, the ICAP2 registers (TAIC2HR, TAIC2LR) are not available on Timer A.
The corresponding interrupts cannot be used (ICF2 is forced by hardware to 0).
Figure 37. Input capture block diagram
ICAP1
pin
CR1 (control register 1)
Edge detect
circuit 2
Edge detect
circuit 1
ICIE
IEDG1
ICAP2
pin
SR (status register)
IC2R register
ICF1
ICF2
0
0
0
IC1R register
CR2 (control register 2)
CC1 CC0 IEDG2
16-bit
16-bit free running counter
84/201
ST7232Axx-Auto
Figure 38. Input capture timing diagram
On-chip peripherals
Timer clock
FF01
FF02
FF03
Counter register
ICAPi pin
ICAPi flag
FF03
ICAPi register
1. The rising edge is the active edge.
Output compare
In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in
the 16-bit timer.
This function can be used to control an output waveform or indicate when a period of time
has elapsed.
When a match is found between the output compare register and the free running counter,
the output compare function:
●
●
●
Assigns pins with a programmable value if the OCiE bit is set
Sets a flag in the status register
Generates an interrupt if enabled
Two 16-bit registers, output compare register 1 (OC1R) and output compare register 2
(OC2R) contain the value to be compared to the counter register each timer clock cycle (see
below).
MSB
LSB
OCiR
OCiHR
OCiLR
These registers are readable and writable and are not affected by the timer hardware. A
reset event changes the OCiR value to 8000h.
Timing resolution is one count of the free running counter: (fCPU/
).
CC[1:0]
Procedure
To use the output compare function, select the following in the CR2 register:
●
Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output
compare i signal.
●
Select the timer clock (CC[1:0]) (see Table 36: CR2 register description)
Select the following in the CR1 register:
●
Select the OLVLi bit to applied to the OCMPi pins after the match occurs
●
Set the OCIE bit to generate an interrupt if it is needed
85/201
On-chip peripherals
When a match is found between OCRi register and CR register:
ST7232Axx-Auto
●
●
●
OCFi bit is set
The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset)
A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is
cleared in the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using
the following formula:
∆t * fCPU
PRESC
∆ OCiR =
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
f
CPU
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 36: CR2
register description)
If the timer clock is an external clock, the formula is:
∆ OCiR = ∆t * fEXT
Where:
∆t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is set
2. Accessing (reading or writing) the OCiLR register
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OCiR register:
●
Write to the OCiHR register (further compares are inhibited)
●
Read the SR register (first step of the clearance of the OCFi bit, which may be already
set)
●
Write to the OCiLR register (enables the output compare function and clears the OCFi
bit)
86/201
ST7232Axx-Auto
On-chip peripherals
Note:
1
2
3
After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit does not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see Figure 40 on page 88 for an example with f
/2 and
CPU
Figure 41 on page 88 for an example with f
PWM mode.
/4). This behavior is the same in OPM or
CPU
4
5
The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
The value in the 16-bit OCiR register and the OLVi bit should be changed after each
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
6
In Flash devices, the TAOC2HR, TAOC2LR registers are ‘write only’ in Timer A. The
corresponding event cannot be generated (OCF2 is forced by hardware to 0).
Forced compare output capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
The FOLVLi bits have no effect in both one pulse mode and PWM mode.
Figure 39. Output compare block diagram
16 bit free running counter
OC1E OC2E
CC1 CC0
CR2 (control register 2)
16-bit
CR1 (control register 1)
Output compare circuit
OCIE
FOLV2 FOLV1 OLVL2
OLVL1
Latch
OCMP1
pin
1
16-bit
OC1R register
16-bit
Latch
2
OCMP2
pin
OCF1
OCF2
0
0
0
OC2R register
SR (status register)
87/201
On-chip peripherals
Figure 40. Output compare timing diagram, f
ST7232Axx-Auto
= f
/2
CPU
TIMER
Internal CPU clock
Timer clock
2ECF 2ED0 2ED1 2ED2 2ED3 2ED4
2ED3
Counter register
Output compare register i (OCRi)
Output compare flag i (OCFi)
OCMPi pin (OLVLi = 1)
Figure 41. Output compare timing diagram, f
= f
/4
CPU
TIMER
Internal CPU clock
Timer clock
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
Counter register
Output compare register i (OCRi)
Output compare flag i (OCFi)
OCMPi pin (OLVLi = 1)
88/201
ST7232Axx-Auto
On-chip peripherals
One pulse mode
One pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one pulse mode uses the input capture1 function and the output compare1 function.
Procedure
To use one pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse using
the appropriate formula below according to the timer clock source used
2. Select the following in the CR1 register:
–
–
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input)
3. Select the following in the CR2 register:
–
Set the OC1E bit (the OCMP1 pin is then dedicated to the output compare 1
function)
–
–
Set the OPM bit
Select the timer clock CC[1:0] (see Table 36: CR2 register description)
Figure 42. One pulse mode sequence
One pulse mode cycle
ICR1 = counter
When event occurs
on ICAP1
OCMP1 = OLVL2
Counter is reset to FFFCh
ICF1 bit is set
When
counter = OCIR
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R
register.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the input capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set
2. Accessing (reading or writing) the ICiLR register
89/201
On-chip peripherals
ST7232Axx-Auto
The OC1R register value required for a specific timing application can be calculated using
the following formula:
t
* fCPU
- 5
OCiR value =
PRESC
Where:
t
f
= Pulse period (in seconds)
= CPU clock frequency (in hertz)
CPU
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 36: CR2
register description)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
t
f
= Pulse period (in seconds)
= External timer clock frequency (in hertz)
EXT
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin, (see Figure 43).
Note:
1
2
The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate
an output compare interrupt.
When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
3
4
If OLVL1 = OLVL2 a continuous signal is seen on the OCMP1 pin.
The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
5
6
When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the one pulse mode.
In Flash devices, Timer A OCF2 bit is forced by hardware to 0.
90/201
ST7232Axx-Auto
Figure 43. One pulse mode timing example
On-chip peripherals
01F8
2ED3
IC1R
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
01F8
Counter
ICAP1
OLVL2
OLVL2
OLVL1
OCMP1
Compare1
1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
Figure 44. Pulse width modulation mode timing example with 2 output compare
functions
2ED0 2ED1 2ED2
OLVL1
34E2 FFFC
OLVL2
FFFC FFFD FFFE
OLVL2
Counter
OCMP1
34E2
Compare1
Compare2
Compare2
1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
91/201
On-chip peripherals
ST7232Axx-Auto
Pulse width modulation mode
Pulse width modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.
Pulse width modulation mode uses the complete output compare 1 function plus the OC2R
register, and so this functionality can not be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are taken into account only at the end of the
PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using
the appropriate formula below according to the timer clock source used
2. Load the OC1R register with the value corresponding to the period of the pulse if
(OLVL1 = 0 and OLVL2 = 1) using the appropriate formula below according to the timer
clock source used
3. Select the following in the CR1 register:
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC1R register
–
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC2R register
4. Select the following in the CR2 register:
–
–
–
Set OC1E bit (the OCMP1 pin is then dedicated to the output compare 1 function)
Set the PWM bit
Select the timer clock (CC[1:0]) (see Table 36: CR2 register description)
Figure 45. Pulse width modulation cycle
Pulse width modulation cycle
When
counter = OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
Counter is reset to FFFCh
ICF1 bit is set
When
counter = OC2R
If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1 = OLVL2 a continuous signal is seen on the OCMP1 pin.
92/201
ST7232Axx-Auto
On-chip peripherals
The OCiR register value required for a specific timing application can be calculated using
the following formula::
t
* fCPU
- 5
OCiR value =
PRESC
Where:
t
f
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
CPU
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 36)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
t
f
= Signal or pulse period (in seconds)
= External timer clock frequency (in hertz)
EXT
The output compare 2 event causes the counter to be initialized to FFFCh (see Figure 44)
Note:
1
2
3
4
After a write instruction to the OCiHR register, the output compare function is inhibited until
the OCiLR register is also written.
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the output
compare interrupt is inhibited.
The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
5
When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
93/201
On-chip peripherals
ST7232Axx-Auto
10.3.4
Low power modes
Table 32. Effect of low power modes on 16-bit timer
Mode Description
No effect on 16-bit timer.
Timer interrupts cause the device to exit from wait mode.
Wait
16-bit timer registers are frozen.
In halt mode, the counter stops counting until halt mode is exited. Counting resumes from
the previous count when the MCU is woken up by an interrupt with ‘exit from halt mode’
capability or from the counter reset value when the MCU is woken up by a reset.
Halt
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is
armed. Consequently, when the MCU is woken up by an interrupt with ‘exit from halt mode’
capability, the ICFi bit is set, and the counter value present when exiting from halt mode is
captured into the ICiR register.
10.3.5
Interrupts
(1)
Table 33. 16-bit timer interrupt control/wake-up capability
Interrupt event
Event flag Enable control bit Exit from wait Exit from halt
Input capture 1 event/counter
reset in PWM mode
ICF1
ICIE
Input capture 2 event
ICF2
Output compare 1 event
(not available in PWM mode)
OCF1
Yes
No
OCIE
TOIE
Output compare 2 event
(not available in PWM mode)
OCF2
TOF
Timer overflow event
1. The 16-bit timer interrupt events are connected to the same interrupt vector (see Section 7: Interrupts).
These events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
94/201
ST7232Axx-Auto
On-chip peripherals
10.3.6
Summary of timer modes
Table 34. Summary of timer modes
Timer resources
Input Output
Modes
Input
Output compare
capture 1
capture 2
compare 1
2
Input capture(1)and/or(2)
Yes
Yes(2)
Yes
Yes
Yes
Output compare(1)and/or(2)
Not
One pulse mode
No
Partially(2)
No
recommended(1)
No
Not
PWM mode
recommended(3)
1. See note 4 in One pulse mode on page 89
2. See note 5 and 6 in One pulse mode on page 89
3. See note 4 in Pulse width modulation mode on page 92
10.3.7
16-bit timer registers
Each timer is associated with three control and status registers, and with six pairs of data
registers (16-bit values) relating to the two input captures, the two output compares, the
counter and the alternate counter.
Control register 1 (CR1)
CR1
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
ICIE
R/W
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 35. CR1 register description
Bit
Bit name
Function
Input capture interrupt enable
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the
SR register is set
7
ICIE
Output compare interrupt enable
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of
the SR register is set
6
5
OCIE
TOIE
Timer overflow interrupt enable
0: Interrupt is inhibited
1: A timer interrupt is enabled whenever the TOF bit of the SR
register is set
95/201
On-chip peripherals
Table 35. CR1 register description (continued)
ST7232Axx-Auto
Bit
Bit name
Function
Forced output compare 2
This bit is set and cleared by software.
0: No effect on the OCMP2 pin
4
FOLV2
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E
bit is set and even if there is no successful comparison
Forced output compare 1
This bit is set and cleared by software.
0: No effect on the OCMP1 pin
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is
set and even if there is no successful comparison
3
2
FOLV1
OLVL2
Output level 2
This bit is copied to the OCMP2 pin whenever a successful
comparison occurs with the OC2R register and OCxE is set in the
CR2 register. This value is copied to the OCMP1 pin in one pulse
mode and pulse width modulation mode.
Input edge 1
This bit determines which type of level transition on the ICAP1 pin
triggers the capture.
0: A falling edge triggers the capture
1: A rising edge triggers the capture
1
0
IEDG1
OLVL1
Output level 1
The OLVL1 bit is copied to the OCMP1 pin whenever a successful
comparison occurs with the OC1R register and the OC1E bit is set in
the CR2 register.
96/201
ST7232Axx-Auto
On-chip peripherals
Control register 2 (CR2)
CR2
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
OC1E
R/W
OC2E
OPM
PWM
CC[1:0]
R/W
IEDG2
EXEDG
R/W
R/W
R/W
R/W
R/W
Table 36. CR2 register description
Bit
Bit name
Function
Output compare 1 pin enable
This bit is used only to output the signal from the timer on the
OCMP1 pin (OLV1 in output compare mode, both OLV1 and OLV2 in
PWM and one-pulse mode). Whatever the value of the OC1E bit, the
output compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for
general-purpose I/O)
7
OCIE
1: OCMP1 pin alternate function enabled
Output compare 2 pin enable
This bit is used only to output the signal from the timer on the
OCMP2 pin (OLV2 in output compare mode). Whatever the value of
the OC2E bit, the output compare 2 function of the timer remains
active.
6
OC2E
0: OCMP2 pin alternate function disabled (I/O pin free for general-
purpose I/O)
1: OCMP2 pin alternate function enabled
One pulse mode
0: One pulse mode is not active
1: One pulse mode is active, the ICAP1 pin can be used to trigger
one pulse on the OCMP1 pin; the active transition is given by the
IEDG1 bit. The length of the generated pulse depends on the
contents of the OC1R register.
5
4
OPM
PWM
Pulse width modulation
0: PWM mode is not active
1: PWM mode is active, the OCMP1 pin outputs a programmable
cyclic signal; the length of the pulse depends on the value of OC1R
register; the period depends on the value of OC2R register.
Clock control
The timer clock mode depends on the following bits:
00: timer clock = fCPU/4
01: timer clock = fCPU/2
10: timer clock = fCPU/8
3:2
CC[1:0]
11: timer clock = external clock (where available)
Note: If the external clock pin is not available, programming the
external clock configuration stops the counter.
97/201
On-chip peripherals
Table 36. CR2 register description (continued)
ST7232Axx-Auto
Bit
Bit name
Function
Input edge 2
This bit determines which type of level transition on the ICAP2 pin
triggers the capture.
1
IEDG2
0: A falling edge triggers the capture
1: A rising edge triggers the capture
External clock edge
This bit determines which type of level transition on the external
clock pin EXTCLK triggers the counter register.
0: A falling edge triggers the counter register
0
EXEDG
1: A rising edge triggers the counter register
Control/status register (CSR)
CSR
Reset value: xxxx x0xx (xxh)
7
6
5
4
3
2
1
0
ICF1
OCF1
TOF
ICF2
OCF2
TIMD
Reserved
-
R
R
R
R
R
R/W
Table 37. CSR register description
Bit
Bit name
Function
Input capture flag 1
0: No input capture (reset value)
1: An input capture has occurred on the ICAP1 pin or the counter
has reached the OC2R value in PWM mode. To clear this bit, first
read the SR register, then read or write the low byte of the IC1R
(IC1LR) register.
7
ICF1
Output compare flag 1
0: No match (reset value)
6
5
4
OCF1
TOF
1: The content of the free running counter has matched the content
of the OC1R register. To clear this bit, first read the SR register, then
read or write the low byte of the OC1R (OC1LR) register.
Timer overflow flag
0: No timer overflow (reset value)
1: The free running counter rolled over from FFFFh to 0000h. To
clear this bit, first read the SR register, then read or write the low
byte of the CR (CLR) register.
Note: Reading or writing the ACLR register does not clear TOF
Input capture flag 2
0: No input capture (reset value)
ICF2
1: An input capture has occurred on the ICAP2 pin. To clear this bit,
first read the SR register, then read or write the low byte of the IC2R
(IC2LR) register.
98/201
ST7232Axx-Auto
Table 37. CSR register description (continued)
On-chip peripherals
Bit
Bit name
Function
Output compare flag 2
0: No match (reset value)
3
OCF2
1: The content of the free running counter has matched the content
of the OC2R register. To clear this bit, first read the SR register, then
read or write the low byte of the OC2R (OC2LR) register.
Timer disable
This bit is set and cleared by software. When set, it freezes the timer
prescaler and counter and disables the output functions (OCMP1
and OCMP2 pins) to reduce power consumption. Access to the timer
registers is still available, allowing the timer configuration to be
changed, or the counter reset, while it is disabled.
0: Timer enabled
2
TIMD
1: Timer prescaler, counter and outputs disabled
1:0
-
Reserved, must be kept cleared
Input capture 1 high register (IC1HR)
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the input capture 1 event).
IC1HR
7
Reset value: undefined
6
5
4
3
2
1
0
MSB
LSB
R
R
R
R
R
R
R
R
Input capture 1 low register (IC1LR)
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the input capture 1 event).
IC1LR
7
Reset value: undefined
6
5
4
3
2
1
0
MSB
LSB
R
R
R
R
R
R
R
R
Output compare 1 high register (OC1HR)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
OC1HR
7
Reset value: 1000 0000 (80h)
6
5
4
3
2
1
0
MSB
LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
99/201
On-chip peripherals
ST7232Axx-Auto
Output compare 1 low register (OC1LR)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
OC1LR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
MSB
LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output compare 2 high register (OC2HR)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
OC2HR
7
Reset value: 1000 0000 (80h)
6
5
4
3
2
1
0
MSB
LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output compare 2 low register (OC2LR)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
OC2LR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
MSB
LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Counter high register (CHR)
This is an 8-bit register that contains the high part of the counter value.
CHR Reset value: 1111 1111 (FFh)
7
6
5
4
3
2
1
0
MSB
R
LSB
R
R
R
R
R
R
R
100/201
ST7232Axx-Auto
On-chip peripherals
Counter low register (CLR)
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after accessing the CSR register clears the
TOF bit.
CLR
Reset value: 1111 1100 (FCh)
7
6
5
4
3
2
1
0
MSB
R
LSB
R
R
R
R
R
R
R
Alternate counter high register (ACHR)
This is an 8-bit register that contains the high part of the counter value.
ACHR
7
Reset value: 1111 1111 (FFh)
6
5
4
3
2
1
0
MSB
LSB
R
R
R
R
R
R
R
R
Alternate counter low register (ACLR)
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after an access to CSR register does not clear
the TOF bit in the CSR register.
ACLR
7
Reset value: 1111 1100 (FCh)
6
5
4
3
2
1
0
MSB
LSB
R
R
R
R
R
R
R
R
Input capture 2 high register (IC2HR)
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the input capture 2 event).
IC2HR
7
Reset value: undefined
6
5
4
3
2
1
0
MSB
LSB
R
R
R
R
R
R
R
R
101/201
On-chip peripherals
ST7232Axx-Auto
Input capture 2 low register (IC2LR)
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the input capture 2 event).
IC2LR
7
Reset value: undefined
6
5
4
3
2
1
0
MSB
LSB
R
R
R
R
R
R
R
R
16-bit timer register map and reset values
Table 38. 16-bit timer register map and reset values
Address (Hex.) Register label
7
6
5
4
3
2
1
0
Timer A: 32
Timer B: 42
CR1
Reset value
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
0
0
0
0
0
0
0
0
Timer A: 31
Timer B: 41
CR2
Reset value
OC1E OC2E OPM PWM
CC1
0
CC0 IEDG2 EXEDG
0
0
0
0
0
0
0
Timer A: 33
Timer B: 43
CSR
Reset value
ICF1 OCF1 TOF ICF2 OCF2 TIMD
-
x
-
x
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
x
0
0
0
0
1
1
1
1
x
x
0
x
x
0
0
0
0
1
1
1
1
x
x
Timer A: 34
Timer B: 44
IC1HR
Reset value
MSB
x
LSB
x
x
x
0
0
0
0
1
0
1
0
x
x
Timer A: 35
Timer B: 45
IC1LR
Reset value
MSB
x
LSB
x
Timer A: 36
Timer B: 46
OC1HR
Reset value
MSB
1
LSB
0
Timer A: 37
Timer B: 47
OC1LR
Reset value
MSB
0
LSB
0
Timer A: 3E
Timer B: 4E
OC2HR
Reset value
MSB
1
LSB
0
Timer A: 3F
Timer B: 4F
OC2LR
Reset value
MSB
0
LSB
0
Timer A: 38
Timer B: 48
CHR
Reset value
MSB
1
LSB
1
Timer A: 39
Timer B: 49
CLR
Reset value
MSB
1
LSB
0
Timer A: 3A
Timer B: 4A
ACHR
Reset value
MSB
1
LSB
1
Timer A: 3B
Timer B: 4B
ACLR
Reset value
MSB
1
LSB
0
Timer A: 3C
Timer B: 4C
IC2HR
Reset value
MSB
x
LSB
x
Timer A: 3D
Timer B: 4D
IC2LR
Reset value
MSB
x
LSB
x
102/201
ST7232Axx-Auto
On-chip peripherals
10.4
Serial peripheral interface (SPI)
10.4.1
Introduction
The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves
however the SPI interface can not be a master in a multi-master system.
10.4.2
Main features
●
●
●
●
●
●
●
●
●
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
Six master mode frequencies (f
/4 max.)
CPU
f
/2 max. slave mode frequency (see note below)
CPU
SS management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag.
Write collision, master mode fault and overrun flags
Note:
In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
10.4.3
General description
Figure 46 shows the serial peripheral interface (SPI) block diagram. There are 3 registers:
●
●
●
SPI control register (SPICR)
SPI control/status register (SPICSR)
SPI data register (SPIDR)
The SPI is connected to external devices through 4 pins:
●
●
●
●
MISO: master in/slave out data
MOSI: master out / slave in data
SCK: serial clock out by SPI masters and input by SPI slaves
SS: Slave select:
This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves
individually and to avoid contention on the data lines. Slave SS inputs can be driven by
standard I/O ports on the master MCU.
103/201
On-chip peripherals
ST7232Axx-Auto
Figure 46. Serial peripheral interface block diagram
Data/address bus
Read
SPIDR
Read buffer
Interrupt request
MOSI
7
SPICSR
0
MISO
8-bit shift register
SPIF WCOL OVR MODF
0
SOD SSM
SSI
Write
SOD bit
1
SS
0
SCK
SPI state control
SPICR
7
0
MSTR
SPR0
CPOL CPHA SPR1
SPIE SPE SPR2
Master control
Serial clock generator
SS
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in Figure 47.
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node ( in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see Figure 50) but master and
slave must be programmed with the same timing mode.
104/201
ST7232Axx-Auto
Figure 47. Single master/single slave application
On-chip peripherals
Master
Slave
MSbit
LSbit
MSbit
LSbit
MISO
MOSI
MISO
MOSI
8-bit shift register
8-bit shift register
SCK
SS
SCK
SS
SPI clock
generator
+5V
Not used if SS is managed by software
Slave select management
As an alternative to using the SS pin to control the slave select signal, the application can
choose to manage the slave select signal by software. This is configured by the SSM bit in
the SPICSR register (see Figure 49)
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
In master mode:
●
SS internal must be held high continuously
In slave mode:
There are two cases depending on the data/clock timing relationship (see Figure 48):
If CPHA = 1 (data latched on 2nd clock edge):
●
SS internal must be held low during the entire transmission. This implies that in single
slave applications the SS pin either can be tied to V , or made free for standard I/O by
SS
managing the SS function by software (SSM = 1 and SSI = 0 in the in the SPICSR
register)
If CPHA = 0 (data latched on 1st clock edge):
●
SS internal must be held low during byte transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS is not pulled high, a write
collision error occurs when the slave writes to the shift register (see Write collision error
(WCOL) on page 110).
105/201
On-chip peripherals
Figure 48. Generic SS timing diagram
ST7232Axx-Auto
MOSI/MISO
Master SS
Byte 2
Byte 1
Byte 3
Slave SS
if CPHA = 0
Slave SS
if CPHA = 1
Figure 49. Hardware/software slave select management
SSM bit
SSI bit
1
SS internal
0
SS external pin
Master mode operation
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
Note:
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
To operate the SPI in master mode, perform the following steps in order:
1. Write to the SPICR register:
–
–
Select the clock frequency by configuring the SPR[2:0] bits
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
Figure 50 shows the four possible configurations.
Note: The slave must have the same CPOL and CPHA settings as the master.
2. Write to the SPICSR register:
Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin
high for the complete byte transmit sequence.
3. Write to the SPICR register:
Set the MSTR and SPE bits
–
–
Note:
1
2
If the SPICSR register is not written first, the SPICR register setting (MSTR bit) may be not
taken into account.
MSTR and SPE bits remain set only if SS is high).
The transmit sequence begins when software writes a byte in the SPIDR register.
106/201
ST7232Axx-Auto
On-chip peripherals
Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the most significant bit of the MOSI pin first.
When data transfer is complete:
●
The SPIF bit is set by hardware
●
An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SPICSR register while the SPIF bit is set
2. A read to the SPIDR register
Note:
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the following actions:
–
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see Figure 50)
Note: The slave must have the same CPOL and CPHA settings as the master.
–
Manage the SS pin as described in Slave select management on page 105 and
Figure 48. If CPHA = 1 SS must be held low continuously. If CPHA = 0 SS must be
held low during byte transmission and pulled up between each byte to let the slave
write in the shift register.
2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
Slave mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the most significant bit of the MISO pin first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
●
The SPIF bit is set by hardware
●
An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SPICSR register while the SPIF bit is set
2. A write or a read to the SPIDR register
Note:
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
107/201
On-chip peripherals
ST7232Axx-Auto
The SPIF bit can be cleared during a second transmission; however, it must be cleared
before the second SPIF bit in order to prevent an overrun condition (see Overrun condition
(OVR) on page 110).
10.4.4
Clock phase and clock polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits (see Figure 50).
Note:
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
capture clock edge
Figure 50, shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the
MISO pin, the MOSI pin are directly connected between the master and the slave device.
Note:
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
108/201
ST7232Axx-Auto
On-chip peripherals
Figure 50. Data clock timing diagram
CPHA = 1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MSbit
MSbit
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSbit
LSbit
MOS1
(from slave)
SS
(to slave)
Capture strobe
CPHA = 0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MSbit
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSbit
LSbit
MOS1
(from slave)
MSbit
SS
(to slave)
Capture strobe
1. This figure should not be used as a replacement for parametric information. Refer to Section 12: Electrical characteristics.
109/201
On-chip peripherals
ST7232Axx-Auto
10.4.5
Error flags
Master mode fault (MODF)
Master mode fault occurs when the master device has its SS pin pulled low.
When a master mode fault occurs:
●
The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set
●
The SPE bit is reset. This blocks all output from the device and disables the SPI
peripheral.
●
The MSTR bit is reset, thus forcing the device into slave mode
Clearing the MODF bit is done through a software sequence:
1. A read access to the SPICSR register while the MODF bit is set
2. A write to the SPICR register
Note:
To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high
during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their
original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set
except in the MODF bit clearing sequence.
Overrun condition (OVR)
An overrun condition occurs, when the master device has sent a data byte and the slave
device has not cleared the SPIF bit issued from the previously transmitted byte.
When an overrun occurs, the OVR bit is set and an interrupt request is generated if the SPIE
bit is set.
In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A
read to the SPIDR register returns this byte. All other bytes are lost.
The OVR bit is cleared by reading the SPICSR register.
Write collision error (WCOL)
A write collision occurs when the software tries to write to the SPIDR register while a data
transfer is taking place with an external device. When this happens, the transfer continues
uninterrupted and the software write is unsuccessful.
Write collisions can occur both in master and slave mode. See also Slave select
management on page 105.
Note:
A‘read collision’ never occurs since the received data byte is placed in a buffer in which
access is always synchronous with the MCU operation.
The WCOL bit in the SPICSR register is set if a write collision occurs.
No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software sequence (see Figure 51).
110/201
ST7232Axx-Auto
On-chip peripherals
Figure 51. Clearing the WCOL bit (write collision flag) software sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st step
Read SPICSR
Result
SPIF = 0
WCOL = 0
2nd step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st step
2nd step
Read SPICSR
Read SPIDR
Result
WCOL = 0
1. Writing to the SPIDR register instead of reading it does not reset the WCOL bits.
Single master systems
A typical single master system may be configured, using an MCU as the master and four
MCUs as slaves (see Figure 52).
The master device selects the individual slave devices by using four pins of a parallel port to
control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports are forced to be
inputs at that time, thus disabling the slave devices.
Note:
To prevent a bus conflict on the MISO line the master allows only one active slave device
during a transmission.
For more security, the slave device may respond to the master with the received data byte.
Then the master receives the previous byte back from the slave device if all MISO and MOSI
pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes with
command fields.
111/201
On-chip peripherals
Figure 52. Single master/multiple slave configuration
ST7232Axx-Auto
SS
SS
SS
SS
SCK
SCK
SCK
SCK
Slave MCU
Slave MCU
Slave MCU
Slave MCU
MOSI
MISO
MOSI
MISO
MOSI
MISO
MISO
MOSI
MISO
MOSI
SCK
Master
MCU
5V
SS
10.4.6
Low power modes
Table 39. Effect of low power modes on SPI
Mode
Description
No effect on SPI.
Wait
SPI interrupt events cause the device to exit from wait mode.
SPI registers are frozen.
In halt mode, the SPI is inactive. SPI operation resumes when the MCU is
woken up by an interrupt with ‘exit from halt mode’ capability. The data received
is subsequently read from the SPIDR register when the software is running
(interrupt vector fetching). If several data are received before the wake up event,
then an overrun error is generated. This error can be detected after the fetch of
the interrupt routine that woke up the device.
Halt
Using the SPI to wakeup the MCU from halt mode
In slave configuration, the SPI is able to wakeup the ST7 device from halt mode through a
SPIF interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
Note:
When waking up from halt mode, if the SPI remains in slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from halt mode state to normal
state. If the SPI exits from slave mode, it returns to normal state immediately.
Caution:
The SPI can wake up the ST7 from halt mode only if the slave select signal (external SS pin
or the SSI bit in the SPICSR register) is low when the ST7 enters halt mode. So if slave
selection is configured as external (see Slave select management on page 105), make sure
the master drives a low level on the SS pin when the slave enters halt mode.
112/201
ST7232Axx-Auto
On-chip peripherals
10.4.7
Interrupts
(1)
Table 40. SPI interrupt control/wake-up capability
Interrupt event
Event flag
Enable control bit
Exit from wait
Exit from halt
SPI end of transfer event
Master mode fault event
Overrun error
SPIF
MODF
OVR
Yes
SPIE
Yes
No
1. The SPI interrupt events are connected to the same interrupt vector (see Section 7: Interrupts). They
generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the CC register
is reset (RIM instruction).
10.4.8
SPI registers
Control register (SPICR)
SPICR
7
Reset value: 0000 xxxx (0xh)
6
5
4
3
2
1
0
SPIE
R/W
SPE
SPR2
MSTR
CPOL
CPHA
SPR[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
Table 41. SPICR register description
Bit
Bit name
Function
Serial peripheral interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
7
SPIE
1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or
OVR = 1 in the SPICSR register
Serial peripheral output enable
This bit is set and cleared by software. It is also cleared by hardware
when, in master mode, SS = 0 (see Master mode fault (MODF) on
page 110). The SPE bit is cleared by reset, so the SPI peripheral is
not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
6
5
SPE
Divider enable
This bit is set and cleared by software and is cleared by reset. It is
used with the SPR[1:0] bits to set the baud rate (see bits [1:0]
below).
SPR2
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: The SPR2 bit has no effect in slave mode
113/201
On-chip peripherals
Table 41. SPICR register description (continued)
ST7232Axx-Auto
Bit
Bit name
Function
Master mode
This bit is set and cleared by software. It is also cleared by hardware
when, in master mode, SS = 0 (see Master mode fault (MODF) on
page 110).
4
MSTR
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input
to an output and the functions of the MISO and MOSI pins are
reversed.
Clock polarity
This bit is set and cleared by software. This bit determines the idle
state of the serial clock. The CPOL bit affects both the master and
slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
3
2
CPOL
CPHA
Note: If CPOL is changed at the communication byte boundaries, the
SPI must be disabled by resetting the SPE bit.
Clock phase
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge
1: The second clock transition is the first capture edge
Note: The slave must have the same CPOL and CPHA settings as
the master.
Serial clock frequency
These bits are set and cleared by software. Used with the SPR2 bit,
they select the baud rate of the SPI serial clock SCK output by the SPI
in master mode:
100: serial clock = fCPU/4
000: serial clock = fCPU/8
1:0
SPR[1:0]
001: serial clock = fCPU/16
110: serial clock = fCPU/32
010: serial clock = fCPU/64
011: serial clock = fCPU/128
Note: These 2 bits have no effect in slave mode.
114/201
ST7232Axx-Auto
On-chip peripherals
Control/status register (SPICSR)
SPICSR
7
Reset value: 0000 0000 (00h)
6
5
4
3
-
2
1
0
SPIF
R
WCOL
OVR
MODF
SOD
SSM
SSI
R
R
R
R/W
R/W
R/W
R/W
Table 42. SPICSR register description
Bit
Bit name
Function
Serial peripheral data transfer flag
This bit is set by hardware when a transfer has been completed. An
interrupt is generated if SPIE = 1 in the SPICR register. It is cleared
by a software sequence (an access to the SPICSR register followed
by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared
1: Data transfer between the device and an external device has been
completed
7
SPIF
Note: While the SPIF bit is set, all writes to the SPIDR register are
inhibited until the SPICSR register is read.
Write collision status
This bit is set by hardware when a write to the SPIDR register is
done during a transmit sequence. It is cleared by a software
sequence (see Figure 51).
0: No write collision occurred
1: A write collision has been detected
6
5
WCOL
SPI overrun error
This bit is set by hardware when the byte currently being received in
the shift register is ready to be transferred into the SPIDR register
while SPIF = 1 (see Overrun condition (OVR) on page 110). An
interrupt is generated if SPIE = 1 in SPICR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
OVR
1: Overrun error detected
Mode fault flag
This bit is set by hardware when the SS pin is pulled low in master
mode (see Master mode fault (MODF) on page 110). An SPI
interrupt can be generated if SPIE = 1 in the SPICSR register. This
bit is cleared by a software sequence (an access to the SPICR
register while MODF = 1 followed by a write to the SPICR register).
0: No master mode fault detected
4
MODF
1: A fault in master mode has been detected
3
2
-
Reserved, must be kept cleared.
SPI output disable
This bit is set and cleared by software. When set, it disables the
alternate function of the SPI output (MOSI in master mode/MISO in
slave mode).
SOD
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
115/201
On-chip peripherals
Table 42. SPICSR register description (continued)
ST7232Axx-Auto
Bit
Bit name
Function
SS management
This bit is set and cleared by software. When set, it disables the
alternate function of the SPI SS pin and uses the SSI bit value
instead. See Slave select management on page 105.
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit.
External SS pin free for general-purpose I/O)
1
SSM
SS internal mode
This bit is set and cleared by software. It acts as a ‘chip select’ by
controlling the level of the SS slave select signal when the SSM bit is
set.
0
SSI
0 : Slave selected
1 : Slave deselected
Data I/O register (SPIDR)
SPIDR
Reset value: undefined
7
6
5
4
3
2
1
0
D[7:0]
R/W
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register initiates transmission/reception of another byte.
Note:
1
2
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Warning: A write to the SPIDR register places data directly into the
shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see Figure 46).
116/201
ST7232Axx-Auto
On-chip peripherals
SPI register map and reset values
Table 43. SPI register map and reset values
Addres (Hex.) Register label
7
6
5
4
3
2
1
0
SPIDR
0021h
MSB
x
LSB
x
Reset value
x
x
x
x
x
x
SPICR
0022h
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Reset value
0
0
0
0
x
x
x
x
SPICSR
0023h
SPIF WCOL OVR MODF
SOD
0
SSM
0
SSI
0
Reset value
0
0
0
0
0
10.5
Serial communications interface (SCI)
10.5.1
Introduction
The serial communications interface (SCI) offers a flexible means of full-duplex data
exchange with external equipment requiring an industry standard NRZ asynchronous serial
data format. The SCI offers a very wide range of baud rates using two baud rate generator
systems.
10.5.2
Main features
●
●
●
●
●
●
●
Full duplex, asynchronous communications
NRZ standard format (mark/space)
Dual baud rate generator systems
Independently programmable transmit and receive baud rates up to 500K baud
Programmable data word length (8 or 9 bits)
Receive buffer full, transmit buffer empty and end of transmission flags
Two receiver wake up modes:
–
–
Address bit (MSB)
Idle line
●
●
●
Muting function for multiprocessor configurations
Separate enable bits for transmitter and receiver
Four error detection flags:
–
–
–
–
Overrun error
Noise error
Frame error
Parity error
●
Five interrupt sources with flags:
–
–
–
–
–
Transmit data register empty
Transmission complete
Receive data register full
Idle line received
Overrun error detected
117/201
On-chip peripherals
ST7232Axx-Auto
●
Parity control:
–
–
Transmits parity bit
Checks parity of received data byte
●
Reduced power consumption mode
10.5.3
General description
The interface is externally connected to another device by two pins (see Figure 54):
●
TDO: Transmit data output. When the transmitter and the receiver are disabled, the
output pin returns to its I/O port configuration. When the transmitter and/or the receiver
are enabled and nothing is to be transmitted, the TDO pin is at high level.
●
RDI: Receive data input is the serial data input. Oversampling techniques are used for
data recovery by discriminating between valid incoming data and noise.
Through these pins, serial data is transmitted and received as frames comprising:
●
●
●
●
An idle line prior to transmission or reception
A start bit
A data word (8 or 9 bits) least significant bit first
A stop bit indicating that the frame is complete
This interface uses two types of baud rate generator:
●
A conventional type for commonly-used baud rates
●
An extended type with a prescaler offering a very wide range of baud rates even with
non-standard oscillator frequencies.
118/201
ST7232Axx-Auto
On-chip peripherals
Figure 53. SCI block diagram
Write
Read
DR (data register)
Received data register (RDR)
Received shift register
Transmit data register (TDR)
Transmit shift register
TDO
RDI
CR1
R8
T8 SCID
M
WAKE PCE PS PIE
Wake up
unit
Receiver clock
Transmit control
Receiver control
CR2
TIE TCIE RIE ILIE
SR
TE
RE RWU SBK
TDRE TC RDRF IDLE OR NF
FE PE
SCI interrupt control
Transmitter clock
Transmitter rate control
f
/16
/PR
CPU
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
Receiver rate control
Conventional baud rate generator
119/201
On-chip peripherals
ST7232Axx-Auto
10.5.4
Functional description
The block diagram of the serial control interface, is shown in Figure 53. It contains 6
dedicated registers:
●
●
●
●
●
Two control registers (SCICR1 and SCICR2)
A status register (SCISR)
A baud rate register (SCIBRR)
An extended prescaler receiver register (SCIERPR)
An extended prescaler transmitter register (SCIETPR)
Refer to the register descriptions in Section 10.5.7 for the definitions of each bit.
Serial data format
Word length may be selected as being either 8 or 9 bits by programming the M bit in the
SCICR1 register (see Figure 53).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An idle character is interpreted as an entire frame of ‘1’s followed by the start bit of the next
frame which contains data.
A break character is interpreted on receiving ‘0’s for some multiple of the frame period. At
the end of the last break frame the transmitter inserts an extra ‘1’ bit to acknowledge the
start bit.
Transmission and reception are driven by their own baud rate generator.
120/201
ST7232Axx-Auto
Figure 54. Word length programming
On-chip peripherals
9-bit word length (M bit is set)
Possible
parity bit
Data frame
Bit2
Next data frame
Next
Start
bit
start
Stop
bit
Bit0
Bit1
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
bit
Start
Bit
Idle frame
Start
Extra
Break frame
bit
’1’
8-bit word length (M bit is reset)
Data frame
Possible
parity bit
Next data frame
Next
start
Start
bit
Stop
bit
Bit2
bit
Bit1
Bit3
Bit4
Bit5
Bit6
Bit7
Bit0
Start
bit
Idle frame
Start
bit
Extra
’1’
Break frame
Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the
T8 bit in the SCICR1 register.
Character transmission
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this
mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the
transmit shift register (see Figure 53).
Procedure
●
●
●
Select the M bit to define the word length
Select the desired baud rate using the SCIBRR and the SCIETPR registers
Set the TE bit to assign the TDO pin to the alternate function and to send an idle frame
as first transmission
●
Access the SCISR register and write the data to send in the SCIDR register (this
sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.
Clearing the TDRE bit is always performed by the following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
121/201
On-chip peripherals
The TDRE bit is set by hardware and it indicates:
ST7232Axx-Auto
●
●
●
The TDR register is empty
The data transfer is beginning
The next data can be written in the SCIDR register without overwriting the previous
data
This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR
register.
When a transmission is taking place, a write instruction to the SCIDR register stores the
data in the TDR register and which is copied in the shift register at the end of the current
transmission.
When no transmission is taking place, a write instruction to the SCIDR register places the
data directly in the shift register, the data transmission starts, and the TDRE bit is
immediately set.
When a frame transmission is complete (after the stop bit) the TC bit is set and an interrupt
is generated if the TCIE is set and the I bit is cleared in the CCR register.
Clearing the TC bit is performed by the following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note:
The TDRE and TC bits are cleared by the same software sequence.
Break characters
Setting the SBK bit loads the shift register with a break character. The break frame length
depends on the M bit (see Figure 54).
As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this
bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the
recognition of the start bit of the next frame.
Idle characters
Setting the TE bit drives the SCI to send an idle frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the
current word.
Note:
Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in
the SCIDR.
122/201
ST7232Axx-Auto
On-chip peripherals
Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9
bits and the MSB is stored in the R8 bit in the SCICR1 register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this
mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the
received shift register (see Figure 53).
Procedure
●
●
●
Select the M bit to define the word length
Select the desired baud rate using the SCIBRR and the SCIERPR registers
Set the RE bit, this enables the receiver which begins searching for a start bit
When a character is received:
●
The RDRF bit is set. It indicates that the content of the shift register is transferred to the
RDR.
●
●
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register
The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.
Clearing the RDRF bit is performed by the following software sequence done by:
1. An access to the SCISR register
2. A read to the SCIDR register
The RDRF bit must be cleared before the end of the reception of the next character to avoid
an overrun error.
Break character
When a break character is received, the SCI handles it as a framing error.
Idle character
When an idle frame is detected, there is the same procedure as a data received character
plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.
Overrun error
An overrun error occurs when a character is received when RDRF has not been reset. Data
can not be transferred from the shift register to the RDR register as long as the RDRF bit is
not cleared.
When an overrun error occurs:
●
●
●
●
The OR bit is set
The RDR content is not lost
The shift register is overwritten
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register
The OR bit is reset by an access to the SCISR register followed by a SCIDR register read
operation.
123/201
On-chip peripherals
Noise error
ST7232Axx-Auto
Oversampling techniques are used for data recovery by discriminating between valid
incoming data and noise. Normal data bits are considered valid if three consecutive samples
(8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit
detection, the NF flag is set on the basis of an algorithm combining both valid edge
detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set
during start bit reception, there should be a valid edge detection as well as three valid
samples.
When noise is detected in a frame:
●
●
●
The NF flag is set at the rising edge of the RDRF bit
Data is transferred from the shift register to the SCIDR register
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The NF flag is reset by a SCISR register read operation followed by a SCIDR register read
operation.
During reception, if a false start bit is detected (example, 8th, 9th, 10th samples are
011,101,110), the frame is discarded and the receiving sequence is not started for this
frame. There is no RDRF bit set for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid
frame is received.
Note:
If the application start bit is not long enough to match the above requirements, then the NF
flag may get set due to the short start bit. In this case, the NF flag may be ignored by the
application software when the first valid byte is received.
See also Noise error causes on page 129.
124/201
ST7232Axx-Auto
On-chip peripherals
Figure 55. SCI baud rate and extended prescaler block diagram
Transmitter clock
Extended prescaler transmitter rate control
SCIETPR
Extended transmitter prescaler register
SCIERPR
Extended receiver prescaler register
Receiver clock
Extended prescaler receiver rate control
Extended prescaler
f
CPU
Transmitter rate control
/16
/PR
SCIBRR
SCP1
SCT2
SCT1 SCT0 SCR2 SCR1 SCR0
SCP0
Receiver rate control
Conventional baud rate generator
125/201
On-chip peripherals
ST7232Axx-Auto
Framing error
A framing error is detected when:
●
The stop bit is not recognized on reception at the expected time, following either a de-
synchronization or excessive noise.
●
A break is received
When the framing error is detected:
●
●
●
the FE bit is set by hardware
Data is transferred from the Shift register to the SCIDR register
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The FE bit is reset by a SCISR register read operation followed by a SCIDR register read
operation.
Conventional baud rate generation
The baud rate for the receiver and transmitter (Rx and Tx) are set independently and
calculated as follows:
fCPU
fCPU
Rx =
Tx =
(16*PR)*RR
(16*PR)*TR
where:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits).
All these bits are in the SCIBRR register (see Baud rate register (SCIBRR) on page 136).
Example: If f is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and
CPU
receive baud rates are 38400 baud.
Note:
The baud rate registers MUST NOT be changed while the transmitter or the receiver is
enabled.
Extended baud rate generation
The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value
prescaler, whereas the conventional baud rate generator retains industry standard software
compatibility.
The extended baud rate generator block diagram is described in Figure 55.
The output clock rate sent to the transmitter or to the receiver is the output from the 16
divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR
register.
Note:
The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value
other than zero.
126/201
ST7232Axx-Auto
The baud rates are calculated as follows:
On-chip peripherals
fCPU
16*ERPR*(PR*RR)
fCPU
16*ETPR*(PR*TR)
Rx =
Tx =
where:
ETPR = 1,..,255 (see Extended transmit prescaler division register (SCIETPR) on
page 137)
ERPR = 1,.. 255 (see Extended receive prescaler division register (SCIERPR) on page 137)
Receiver muting and wake up feature
In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant SCI
service overhead for all non addressed receivers.
The non addressed devices may be placed in sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in sleep mode:
None of the reception status bits can be set.
All the receive interrupts are inhibited.
A muted receiver may be awakened by one of the following two ways:
●
by idle line detection if the WAKE bit is reset
by address mark detection if the WAKE bit is set
●
Receiver wakes-up by idle line detection when the receive line has recognised an idle frame.
Then the RWU bit is reset by hardware but the IDLE bit is not set.
Receiver wakes-up by address mark detection when it received a ‘1’ as the most significant
bit of a word, thus indicating that the message is an address. The reception of this particular
word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the
receiver to receive this word normally and to use it as an address word.
Caution:
In mute mode, do not write to the SCICR2 register. If the SCI is in mute mode during the
read operation (RWU = 1) and an address mark wake up event occurs (RWU is reset)
before the write operation, the RWU bit is set again by this write operation. Consequently
the address byte is lost and the SCI is not woken up from mute mode.
Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length
defined by the M bit, the possible SCI frame formats are as listed in Table 44.
127/201
On-chip peripherals
ST7232Axx-Auto
(1)
Table 44. Frame formats
M bit
PCE bit
SCI frame
0
0
1
1
0
1
0
1
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
1. Legend: SB = start bit, STB = stop bit, PB = parity bit.
Note:
In case of wake up by an address mark, the MSB bit of the data is taken into account and
not the parity bit
Even parity
The parity bit is calculated to obtain an even number of ‘1s’ inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example, data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit = 0).
Odd parity
The parity bit is calculated to obtain an odd number of ‘1s’ inside the frame made of the 7 or
8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example, data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit = 1).
Transmission mode
If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted
but is changed by the parity bit.
Reception mode
If the PCE bit is set then the interface checks if the received data byte has an even number
of ‘1s’ if even parity is selected (PS = 0) or an odd number of ‘1s’ if odd parity is selected
(PS = 1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is
generated if PIE is set in the SCICR1 register.
SCI clock tolerance
During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th
samples is considered as the bit value. For a valid bit detection, all the three samples should
have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and
10th samples are 0, 1 and 1 respectively, then the bit value is ‘1’, but the noise flag bit is set
because the three samples values are not the same.
Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples
have the desired bit value. This means the clock frequency should not vary more than 6/16
(37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when
receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed
3.75%.
128/201
ST7232Axx-Auto
Note:
On-chip peripherals
The internal sampling clock of the microcontroller samples the pin value on every falling
edge. Therefore, the internal sampling clock and the time the application expects the
sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit
length is 64µs), then the 8th, 9th and 10th samples are at 28µs, 32µs and 36µs respectively
(the first sample starting ideally at 0µs). But if the falling edge of the internal clock occurs
just before the pin value changes, the samples would then be out of sync by ~4µs. This
means the entire bit length must be at least 40µs (36µs for the 10th sample + 4µs for
synchronization with the internal sampling clock).
Clock deviation causes
The causes which contribute to the total deviation are:
●
D
: Deviation due to transmitter error (local oscillator error of the transmitter or the
TRA
transmitter is transmitting at a different baud rate).
●
●
D
D
: Error due to the baud rate quantisation of the receiver
QUANT
: Deviation of the local oscillator of the receiver. This deviation can occur during
REC
the reception of one complete SCI message assuming that the deviation has been
compensated at the beginning of the message.
●
D
: Deviation due to the transmission line (generally due to the transceivers)
TCL
All the deviations of the system should be added and compared to the SCI clock tolerance:
+ D + D + D < 3.75%
D
TRA
QUANT
REC
TCL
Noise error causes
See also description of noise error in Receiver on page 123.
Start bit
The noise flag (NF) is set during start bit reception if one of the following conditions occurs:
1. A valid falling edge is not detected. A falling edge is considered to be valid if the 3
consecutive samples before the falling edge occurs are detected as '1' and, after the
falling edge occurs, during the sampling of the 16 samples, if one of the samples
numbered 3, 5 or 7 is detected as a ‘1’.
2. During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is
detected as a ‘1’.
Therefore, a valid start bit must satisfy both the above conditions to prevent the noise flag
getting set.
Data bits
The noise flag (NF) is set during normal data bit reception if the following condition occurs:
During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the
same. The majority of the 8th, 9th and 10th samples is considered as the bit value.
Therefore, a valid data bit must have samples 8, 9 and 10 at the same value to prevent the
noise flag being set.
129/201
On-chip peripherals
Figure 56. Bit sampling in reception mode
ST7232Axx-Auto
RDI line
Sampled values
Sample clock
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6/16
7/16
7/16
One bit time
10.5.5
Low power modes
Table 45. Effect of low power modes on SCI
Mode
Description
No effect on SCI.
Wait
SCI interrupts cause the device to exit from wait mode.
SCI registers are frozen.
Halt
In halt mode, the SCI stops transmitting/receiving until halt mode is
exited.
10.5.6
Interrupts
Table 46. SCI interrupt control/wake-up capability
Interrupt event
Event flag Enable control bit Exit from wait Exit from halt
Transmit data register empty
Transmission complete
Received data ready to be read
Overrun error detected
Idle line detected
TDRE
TC
TIE
TCIE
RDRF
OR
RIE
Yes
No
IDLE
PE
ILIE
PIE
Parity error
The SCI interrupt events are connected to the same interrupt vector.
These events generate an interrupt if the corresponding enable control bit is set and the
interrupt mask in the CC register is reset (RIM instruction).
130/201
ST7232Axx-Auto
On-chip peripherals
10.5.7
SCI registers
Status register (SCISR)
SCISR
Reset value: 1100 0000 (C0h)
7
6
5
4
3
2
1
0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PE
R
R
R
R
R
R
R
R
Table 47. SCISR register description
Bit
Bit name
Function
Transmit data register empty
This bit is set by hardware when the content of the TDR register has
been transferred into the shift register. An interrupt is generated if the
TIE bit = 1 in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register followed by a write to the
SCIDR register).
7
TDRE
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: Data are not transferred to the shift register unless the TDRE
bit is cleared.
Transmission complete
This bit is set by hardware when transmission of a frame containing
data is complete. An interrupt is generated if TCIE = 1 in the SCICR2
register. It is cleared by a software sequence (an access to the
SCISR register followed by a write to the SCIDR register).
0: Transmission is not complete
6
TC
1: Transmission is complete
Note: TC is not set after the transmission of a preamble or a break.
Received data ready flag
This bit is set by hardware when the content of the RDR register has
been transferred to the SCIDR register. An interrupt is generated if
RIE = 1 in the SCICR2 register. It is cleared by a software sequence
(an access to the SCISR register followed by a read to the SCIDR
register).
5
RDRF
0: Data are not received
1: Received data are ready to be read
Idle line detect
This bit is set by hardware when an idle line is detected. An interrupt
is generated if the ILIE = 1 in the SCICR2 register. It is cleared by a
software sequence (an access to the SCISR register followed by a
read to the SCIDR register).
4
IDLE
0: No idle line is detected
1: Idle line is detected
Note: The IDLE bit is not set again until the RDRF bit is set (i.e. a
new idle line occurs).
131/201
On-chip peripherals
Table 47. SCISR register description (continued)
ST7232Axx-Auto
Bit
Bit name
Function
Overrun error
This bit is set by hardware when the word currently being received in
the shift register is ready to be transferred into the RDR register
while RDRF = 1. An interrupt is generated if RIE = 1 in the SCICR2
register. It is cleared by a software sequence (an access to the
SCISR register followed by a read to the SCIDR register).
0: No overrun error
3
OR
1: Overrun error is detected
Note: When the IDLE bit is set the RDR register content is not lost
but the shift register is overwritten.
Noise flag
This bit is set by hardware when noise is detected on a received
frame. It is cleared by a software sequence (an access to the SCISR
register followed by a read to the SCIDR register).
0: No noise is detected
2
NF
1: Noise is detected
Note: The NF bit does not generate an interrupt as it appears at the
same time as the RDRF bit which itself generates an interrupt.
Framing error
This bit is set by hardware when a de-synchronization, excessive
noise or a break character is detected. It is cleared by a software
sequence (an access to the SCISR register followed by a read to the
SCIDR register).
1
FE
0: No framing error is detected
1: Framing error or break character is detected
Note: The FE bit does not generate an interrupt as it appears at the
same time as the RDRF bit which itself generates an interrupt. If the
word currently being transferred causes both frame error and
overrun error, it is transferred and only the OR bit is set.
Parity error
This bit is set by hardware when a parity error occurs in receiver
mode. It is cleared by a software sequence (a read to the status
register followed by an access to the SCIDR data register). An
interrupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
0
PE
1: Parity error
132/201
ST7232Axx-Auto
On-chip peripherals
Control register 1 (SCICR1)
SCICR1
7
Reset value: x000 0000 (x0b)
6
5
4
3
2
1
0
R8
T8
SCID
M
WAKE
PCE
PS
PIE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 48. SCICR1 register description
Bit
Bit name
Function
Receive data bit 8
7
R8
This bit is used to store the 9th bit of the received word when M = 1.
Transmit data bit 8
6
5
T8
This bit is used to store the 9th bit of the transmitted word when
M = 1.
Disabled for low power consumption
When this bit is set the SCI prescalers and outputs are stopped at
the end of the current byte transfer in order to reduce power
consumption.This bit is set and cleared by software.
0: SCI enabled
SCID
1: SCI prescaler and outputs disabled
Word length
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note: The M bit must not be modified during a data transfer (both
transmission and reception).
4
3
M
Wake up method
This bit determines the SCI wake up method, it is set or cleared by
software.
WAKE
0: Idle line
1: Address mark
Parity control enable
This bit selects the hardware parity control (generation and
detection). When the parity control is enabled, the computed parity is
inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and
parity is checked on the received data. This bit is set and cleared by
software. Once it is set, PCE is active after the current byte (in
reception and in transmission).
2
PCE
0: Parity control disabled
1: Parity control enabled
133/201
On-chip peripherals
Table 48. SCICR1 register description (continued)
ST7232Axx-Auto
Bit
Bit name
Function
Parity selection
This bit selects the odd or even parity when the parity
generation/detection is enabled (PCE bit set). It is set and cleared by
software. The parity is selected after the current byte.
0: Even parity
1
PS
1: Odd parity
Parity interrupt enable
This bit enables the interrupt capability of the hardware parity control
when a parity error is detected (PE bit set). It is set and cleared by
software.
0
PIE
0: Parity error interrupt disabled
1: Parity error interrupt enabled
Control register 2 (SCICR2)
SCICR2
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 49. SCICR2 register description
Bit
Bit name
Function
Transmitter interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
7
TIE
1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR
register
Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1 in the SCISR
register
6
5
4
TCIE
RIE
Receiver interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in
the SCISR register
Idle line interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
ILIE
1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR
register
134/201
ST7232Axx-Auto
Table 49. SCICR2 register description (continued)
On-chip peripherals
Bit
Bit name
Function
Transmitter enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Note 1: During transmission, an ‘0’ pulse on the TE bit (‘0’ followed
by ‘1’) sends a preamble (idle line) after the current word.
Note 2: When TE is set there is a 1 bit-time delay before the
transmission starts.
3
TE
Caution The TDO pin is free for general purpose I/O only when the
TE and RE bits are both cleared (or if TE is never set).
Receiver enable
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
2
1
RE
Receiver wake up
This bit determines if the SCI is in mute mode or not. It is set and
cleared by software and can be cleared by hardware when a wake
up sequence is recognized.
RWU
0: Receiver in active mode
1: Receiver in mute mode
Note: Before selecting mute mode (setting the RWU bit), the SCI
must receive some data first, otherwise it cannot function in mute
mode with wakeup by idle line detection.
Send break
This bit set is used to send break characters. It is set and cleared by
software.
0: No break character is transmitted
0
SBK
1: Break characters are transmitted
Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter sends
a BREAK word at the end of the current word.
Data register (SCIDR)
Contains the received or transmitted data character, depending on whether it is read from or
written to.
SCIDR
7
Reset value: undefined
6
5
4
3
2
1
0
DR[7:0]
R/W
The data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 53).
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 53).
135/201
On-chip peripherals
ST7232Axx-Auto
Baud rate register (SCIBRR)
SCIBRR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
SCP[1:0]
R/W
SCT[2:0]
SCR[2:0]
R/W
R/W
Table 50. SCIBRR register description
Bit
Bit name
Function
First SCI prescaler
These 2 prescaling bits allow several standard clock division ranges:
00: PR prescaling factor = 1
01: PR prescaling factor = 3
7:6
SCP[1:0]
10: PR prescaling factor = 4
11: PR prescaling factor = 13
SCI transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and SCP0 bits define the
total division applied to the bus clock to yield the transmit rate clock
in conventional baud rate generator mode:
000: TR dividing factor = 1
001: TR dividing factor = 2
010: TR dividing factor = 4
5:3
SCT[2:0]
011: TR dividing factor = 8
100: TR dividing factor = 16
101: TR dividing factor = 32
110: TR dividing factor = 64
111: TR dividing factor = 128
SCI receiver rate divisor
These 3 bits, in conjunction with the SCP[1:0] bits define the total
division applied to the bus clock to yield the receive rate clock in
conventional baud rate generator mode:
000: RR dividing factor = 1
001: RR dividing factor = 2
010: RR dividing factor = 4
2:0
SCR[2:0]
011: RR dividing factor = 8
100: RR dividing factor = 16
101: RR dividing factor = 32
110: RR dividing factor = 64
111: RR dividing factor = 128
136/201
ST7232Axx-Auto
On-chip peripherals
Extended receive prescaler division register (SCIERPR)
Allows setting of the extended prescaler rate division factor for the receive circuit.
SCIERPR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
ERPR[7:0]
R/W
Table 51. SCIERPR register description
Bit
Bit name
Function
8-bit extended receive prescaler register
The extended baud rate generator is activated when a value different
from 00h is stored in this register. Therefore the clock frequency
issued from the 16 divider (see Figure 55) is divided by the binary
factor set in the SCIERPR register (in the range 1 to 255).
The extended baud rate generator is not used after a reset.
7:0
ERPR[7:0]
Extended transmit prescaler division register (SCIETPR)
Allows setting of the external prescaler rate division factor for the transmit circuit.
SCIETPR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
ETPR[7:0]
R/W
Table 52. SCIETPR register description
Bit
Bit name
Function
8-bit extended transmit prescaler register
The extended baud rate generator is activated when a value different
from 00h is stored in this register. Therefore the clock frequency
issued from the 16 divider (see Figure 55) is divided by the binary
factor set in the SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not used after a reset.
7:0
ETPR[7:0]
137/201
On-chip peripherals
ST7232Axx-Auto
Baud rate selection
Table 53. Baud rate selection
Conditions
Accuracy
Symbol
Parameter
Standard Baud rate Unit
fCPU
vs.
Prescaler
standard
Conventional mode
TR (or RR)=128, PR=13
TR (or RR)= 32, PR=13
TR (or RR)= 16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 16, PR= 13
TR (or RR)= 2, PR=13
TR (or RR)= 1, PR=13
300
~300.48
1200 ~1201.92
2400 ~2403.84
4800 ~4807.69
9600 ~9615.38
10400 ~10416.67
19200 ~19230.77
38400 ~38461.54
~0.16%
~0.79%
fTx
fRx
Communication
frequency
8MHz
Hz
Extended mode
ETPR (or ERPR) = 35,
TR (or RR) = 1, PR = 1
14400 ~14285.71
SCI register map and reset values
Table 54. SCI register map and reset values
Address (Hex.) Register label
7
6
5
4
3
2
1
0
SCISR
0050h
TDRE TC
RDRF IDLE
OR
0
NF
0
FE
0
PE
0
Reset value
1
1
0
0
SCIDR
0051h
MSB
x
LSB
x
Reset value
x
x
x
x
x
x
SCIBRR
0052h
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
Reset value
0
0
0
0
0
0
0
0
SCICR1
0053h
R8
x
T8
0
SCID
0
M
0
WAKE PCE
PS
0
PIE
0
Reset value
0
0
SCICR2
0054h
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU SBK
Reset value
0
0
0
0
SCIERPR
0055h
MSB
0
LSB
0
Reset value
0
0
0
0
0
0
0
0
0
0
SCIPETPR
0057h
MSB
0
LSB
0
Reset value
138/201
ST7232Axx-Auto
On-chip peripherals
10.6
10-bit A/D converter (ADC)
10.6.1
Introduction
The on-chip analog to digital converter (ADC) peripheral is a 10-bit, successive
approximation converter with internal sample and hold circuitry. This peripheral has up to 16
multiplexed analog input channels (refer to device pin out description) that allow the
peripheral to convert the analog voltage levels from up to 16 different sources.
The result of the conversion is stored in a 10-bit data register. The A/D converter is
controlled through a control/status register.
10.6.2
Main features
●
●
●
●
●
●
10-bit conversion
Up to 16 channels with multiplexed input
Linear successive approximation
Data register (DR) which contains the results
Conversion complete status flag
On/off bit (to reduce consumption)
The block diagram is shown in Figure 57.
Figure 57. ADC block diagram
f
CPU
DIV 4
DIV 2
0
1
f
ADC
SPE AD
ED ON
EOC
0
CH3 CH2 CH1 CH0 ADCCSR
4
AIN0
AIN1
Analog
MUX
Analog to digital converter
AINx
ADCDRH
D9
D8
D7
D6
D5
D4
D3
D2
ADCDRL
0
0
0
0
0
0
D1
D0
139/201
On-chip peripherals
ST7232Axx-Auto
10.6.3
Functional description
The conversion is monotonic, meaning that the result never decreases if the analog input
does not decrease and never increases if the analog input does not increase.
If the input voltage (V ) is greater than V
(high-level voltage reference) then the
AIN
AREF
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (V ) is lower than V
(low-level voltage reference) then the
SSA
AIN
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in Section 12:
Electrical characteristics.
R
is the maximum recommended impedance for an analog input signal. If the impedance
AIN
is too high, this results in a loss of accuracy due to leakage and sampling not being
completed in the alloted time.
A/D converter configuration
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to
Section 9: I/O ports. Using these pins as analog inputs does not affect the ability of the port
to be read as a logic input.
In the ADCCSR register select the CS[3:0] bits to assign the analog channel to convert.
Starting the conversion
In the ADCCSR register set the ADON bit to enable the A/D converter and to start the
conversion. From this time on, the ADC performs a continuous conversion of the selected
channel.
When a conversion is complete:
●
The EOC bit is set by hardware
●
The result is in the ADCDR register
A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit.
To read the 10 bits, perform the following steps:
1. Poll the EOC bit
2. Read the ADCDRL register
3. Read the ADCDRH register. This clears EOC automatically
Note:
The data is not latched, so both the low and the high data register must be read before the
next conversion is complete, so it is recommended to disable interrupts while reading the
conversion result.
To read only 8 bits, perform the following steps:
1. Poll the EOC bit
2. Read the ADCDRH register. This clears EOC automatically
140/201
ST7232Axx-Auto
On-chip peripherals
Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
10.6.4
Low power modes
Note:
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed.
Table 55. Effect of low power modes on 10-bit ADC
Mode
Description
Wait
No effect on A/D converter
A/D converter disabled.
After wakeup from halt mode, the A/D converter requires a stabilization time
Halt
t
STAB (see Section 12: Electrical characteristics) before accurate conversions
can be performed.
10.6.5
10.6.6
Interrupts
None.
10-bit ADC registers
Control/status register (ADCCSR)
ADCCSR
Reset value: 0000 0000 (00h)
7
6
5
4
0
3
2
1
0
EOC
SPEED
ADON
CH[3:0]
R/W
R
R/W
R/W
-
Table 56. ADCCSR register description
Bit
Bit name
Function
End of conversion
This bit is set by hardware. It is cleared by hardware when software
reads the ADCDRH register or writes to any bit of the ADCCSR
register.
7
EOC
0: Conversion is not complete
1: Conversion complete
ADC clock selection
This bit is set and cleared by software.
0: fADC = fCPU/4
1: fADC = fCPU/2
6
5
SPEED
ADON
A/D converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
141/201
On-chip peripherals
Table 56. ADCCSR register description (continued)
ST7232Axx-Auto
Bit
Bit name
Function
Reserved, must be kept cleared.
Channel selection
4
0
These bits are set and cleared by software. They select the analog
input to convert:
0000: channel pin = AIN0
0001: channel pin = AIN1
0010: channel pin = AIN2
0011: channel pin = AIN3
0100: channel pin = AIN4
0101: channel pin = AIN5
0110: channel pin = AIN6
0111: channel pin = AIN7
3:0
CH[3:0]
1000: channel pin = AIN8
1001: channel pin = AIN9
1010: channel pin = AIN10
1011: channel pin = AIN11
1100: channel pin = AIN12
1101: channel pin = AIN13
1110: channel pin = AIN14
1111: channel pin = AIN15
Note: The number of channels is device dependent. Refer to the
Section 2: Pin description.
Data register (ADCDRH)
ADCDRH
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
D[9:2]
R
Table 57. ADCDRH register description
Bit
Bit name
Function
7:0
D[9:2]
MSB of converted analog value
Data register (ADCDRL)
ADCDRL
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
0
-
D[1:0]
R
142/201
ST7232Axx-Auto
On-chip peripherals
Table 58. ADCDRL register description
Bit
Bit name
Function
Reserved, must be kept cleared
LSB of converted analog value
7:2
1:0
0
D[1:0]
ADC register map and reset value
Table 59. ADC register map and reset values
Address (Hex.) Register label
7
6
5
4
3
2
1
0
ADCCSR
0070h
EOC SPEED ADON
CH3 CH2
CH1
0
CH0
0
Reset value
0
0
0
0
0
0
ADCDRH
0071h
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
Reset value
ADCDRL
0072h
D1
0
D0
0
Reset value
0
0
0
0
0
0
143/201
Instruction set
ST7232Axx-Auto
11
Instruction set
11.1
CPU addressing modes
The CPU features 17 different addressing modes which can be classified in 7 main groups
(see Table 60).
Table 60. CPU addressing mode groups
Addressing mode
Example
Inherent
Immediate
Direct
nop
ld A,#$55
ld A,$55
Indexed
Indirect
ld A,($55,X)
ld A,([$55],X)
jrne loop
Relative
Bit operation
bset byte,#5
The CPU instruction set is designed to minimize the number of bytes required per
instruction. To do so, most of the addressing modes may be subdivided in two sub-modes
called long and short:
●
Long addressing mode is more powerful because it can use the full 64 Kbyte address
space, however it uses more bytes and more CPU cycles.
●
Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 assembler optimizes the use of long and short addressing modes.
144/201
ST7232Axx-Auto
Instruction set
Table 61. CPU addressing mode overview
Pointer
address
Pointer
size
Length
(bytes)
Mode
Syntax
Destination
Inherent
nop
+ 0
+ 1
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 2
+ 2
Immediate
Short
ld A,#$55
ld A,$10
Direct
Direct
Direct
Direct
Direct
Indirect
Indirect
00..FF
Long
ld A,$1000
0000..FFFF
00..FF
No offset
Short
Indexed ld A,(X)
Indexed ld A,($10,X)
00..1FE
Long
Indexed ld A,($1000,X) 0000..FFFF
Short
ld A,[$10]
00..FF
0000..FFFF 00..FF
00..1FE 00..FF
00..FF
byte
Long
ld A,[$10.w]
word
byte
Short
Indirect Indexed ld A,([$10],X)
ld
Indirect Indexed
A,([$10.w],X)
Long
0000..FFFF 00..FF
PC+/-127
word
+ 2
Relative
Relative
Bit
Direct
jrne loop
+ 1
+ 2
+ 1
+ 2
Indirect
Direct
jrne [$10]
PC+/-127
00..FF
00..FF
byte
byte
bset $10,#7
bset [$10],#7
Bit
Indirect
00..FF
00..FF
btjt
$10,#7,skip
Bit
Bit
Direct
Relative
00..FF
00..FF
+ 2
+ 3
btjt
Indirect Relative
00..FF
byte
[$10],#7,skip
145/201
Instruction set
ST7232Axx-Auto
11.1.1
Inherent instructions
All inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.
Table 62. Inherent instructions
Inherent instruction
Function
NOP
No operation
S/W interrupt
TRAP
WFI
Wait for interrupt (low power mode)
Halt oscillator (lowest power mode)
Sub-routine return
HALT
RET
IRET
SIM
Interrupt sub-routine return
Set interrupt mask (level 3)
Reset interrupt mask (level 0)
Set carry flag
RIM
SCF
RCF
Reset carry flag
RSP
Reset stack pointer
Load
LD
CLR
Clear
PUSH/POP
INC/DEC
TNZ
Push/pop to/from the stack
Increment/decrement
Test negative or zero
1 or 2 complement
CPL, NEG
MUL
Byte multiplication
SLL, SRL, SRA, RLC, RRC
SWAP
Shift and rotate operations
Swap nibbles
11.1.2
Immediate instructions
Immediate instructions have two bytes, the first byte contains the opcode, the second byte
contains the operand value.
Table 63. Immediate instructions
Immediate Instruction
Function
LD
Load
CP
Compare
BCP
Bit compare
Logical operations
Arithmetic operations
AND, OR, XOR
ADC, ADD, SUB, SBC
146/201
ST7232Axx-Auto
Instruction set
11.1.3
Direct instructions
In direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two sub-modes:
●
Direct instructions (short)
The address is a byte, thus requires only one byte after the opcode, but only allows
00 - FF addressing space.
●
Direct instructions (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes
after the opcode.
11.1.4
Indexed instructions (no offset, short, long)
In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three sub-modes:
●
●
●
Indexed (no offset)
There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing
space.
Indexed (short)
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE
addressing space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes
after the opcode.
11.1.5
Indirect instructions (short, long)
The required data byte to do the operation is found by its memory address, located in
memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two sub-
modes:
●
Indirect (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF
addressing space, and requires 1 byte after the opcode.
●
Indirect (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte
addressing space, and requires 1 byte after the opcode.
147/201
Instruction set
ST7232Axx-Auto
11.1.6
Indirect indexed instructions (short, long)
This is a combination of indirect and short indexed addressing modes. The operand is
referenced by its memory address, which is defined by the unsigned addition of an index
register value (X or Y) with a pointer value located in memory. The pointer address follows
the opcode.
The indirect indexed addressing mode consists of two sub-modes:
●
Indirect indexed (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE
addressing space, and requires 1 byte after the opcode.
●
Indirect indexed (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte
addressing space, and requires 1 byte after the opcode.
Table 64. Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes
Long and short instructions
Function
LD
CP
Load
Compare
AND, OR, XOR
ADC, ADD, SUB, SBC
BCP
Logical operations
Arithmetic addition/substraction operations
Bit compare
Table 65. Short instructions and functions
Short instructions only
Function
CLR
Clear
INC, DEC
Increment/decrement
Test negative or zero
1 or 2 complement
Bit operations
TNZ
CPL, NEG
BSET, BRES
BTJT, BTJF
SLL, SRL, SRA, RLC, RRC
SWAP
Bit test and jump operations
Shift and rotate operations
Swap nibbles
CALL, JP
Call or jump subroutine
148/201
ST7232Axx-Auto
Instruction set
11.1.7
Relative mode instructions (direct, indirect)
This addressing mode is used to modify the PC register value, by adding an 8-bit signed
offset to it.
Table 66. Relative mode instructions (direct and indirect)
Available relative direct/indirect instructions
Function
JRxx
Conditional jump
Call relative
CALLR
The relative addressing mode consists of two sub-modes:
●
Relative (direct)
The offset is following the opcode.
Relative (indirect)
●
The offset is defined in memory, which address follows the opcode.
11.2
Instruction groups
The ST7 family devices use an instruction set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:
Table 67. Instruction groups
Load and transfer
LD
CLR
Stack operation
PUSH POP
RSP
Increment/decrement
Compare and tests
INC
CP
DEC
TNZ
OR
BCP
XOR
Logical operations
AND
CPL NEG
Bit operation
BSET BRES
BTJT BTJF
Conditional bit test and branch
Arithmetic operations
Shift and rotates
ADC
SLL
ADD
SRL
JRT
SUB
SRA
JRF
SBC MUL
RLC RRC SWAP SLA
Unconditional jump or call
Conditional branch
JRA
JRxx
JP
CALL CALLR NOP RET
Interruption management
Condition code flag modification
TRAP WFI
SIM RIM
HALT IRET
SCF RCF
149/201
Instruction set
ST7232Axx-Auto
11.3
Using a pre-byte
The instructions are described with one to four opcodes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes:
PC-2
PC-1
PC
End of previous instruction
Prebyte
Opcode
PC+1
Additional word (0 to 2) according to the number of bytes required to compute
the effective address
These prebytes enable instructions in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instructions in X or the instructions using
direct addressing mode. The prebytes are:
PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one
PIX 92
PIY 91
Replace an instruction using direct, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect addressing mode
It also changes an instruction using X indexed addressing mode to an instruction
using indirect X indexed addressing mode
Replace an instruction using X indirect indexed addressing mode by a Y one
150/201
ST7232Axx-Auto
Instruction set
Table 68. Instruction set overview
Mnemo
Description
Add with carry
Function/example
Dst
Src
I1
H
I0
N
Z
C
ADC
A = A + M + C
A = A + M
A
A
M
M
M
M
H
H
N
N
N
N
Z
Z
Z
Z
C
C
ADD
Addition
AND
Logical And
A = A . M
A
BCP
Bit compare A, memory
Bit reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
C
C
CALLR Call subroutine relative
CLR
CP
Clear
reg, M
reg
0
N
N
N
1
Z
Z
Z
Arithmetic compare
One complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
DEC
HALT
IRET
INC
reg, M
reg, M
Halt
1
0
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
I1
H
I0
N
N
Z
Z
C
reg, M
JP
Absolute jump
jp [TBL.w]
JRA
Jump relative always
Jump relative
JRT
JRF
Never jump
jrf *
JRIH
JRIL
JRH
JRNH
JRM
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
JRNC
Jump if ext. INT pin = 1
Jump if ext. INT pin = 0
Jump if H = 1
(ext. INT pin high)
(ext. INT pin low)
H = 1 ?
Jump if H = 0
H = 0 ?
Jump if I1:0 = 11
Jump if I1:0 <> 11
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
I1:0 = 11 ?
I1:0 <> 11 ?
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
Jump if C = 0
C = 0 ?
JRULT Jump if C = 1
JRUGE Jump if C = 0
Unsigned <
Jmp if unsigned >=
151/201
Instruction set
ST7232Axx-Auto
Table 68. Instruction set overview (continued)
Mnemo
Description
Function/example
Dst
Src
I1
H
I0
N
Z
C
JRUGT Jump if (C + Z = 0)
JRULE Jump if (C + Z = 1)
Unsigned >
Unsigned <=
dst <= src
X, A = X * A
neg $10
LD
Load
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
N
N
N
N
Z
Z
Z
Z
MUL
NEG
NOP
OR
Multiply
0
0
Negate (2's compl)
No operation
OR operation
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
M
reg
CC
M
POP
Pop from the stack
M
I1
1
H
I0
0
C
0
PUSH
RCF
RET
RIM
Push onto the stack
Reset carry flag
Subroutine return
Enable interrupts
Rotate left true C
Rotate right true C
Reset stack pointer
Substract with carry
Set carry flag
reg, CC
I1:0 = 10 (level 0)
C <= A <= C
C => A => C
S = Max allowed
A = A - M - C
C = 1
RLC
RRC
RSP
SBC
SCF
SIM
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable interrupts
Shift left arithmetic
Shift left logic
I1:0 = 11 (level 3)
C <= A <= 0
C <= A <= 0
0 => A => C
A7 => A => C
A = A - M
1
1
SLA
SLL
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SRL
SRA
SUB
Shift right logic
Shift right arithmetic
Substraction
N
N
N
N
M
M
SWAP SWAP nibbles
A7-A4 <=> A3-A0 reg, M
tnz lbl1
TNZ
Test for neg and zero
TRAP
WFI
S/W trap
S/W interrupt
1
1
1
0
Wait for interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
152/201
ST7232Axx-Auto
Electrical characteristics
12
Electrical characteristics
12.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
12.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25°C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3σ).
12.1.2
12.1.3
12.1.4
Typical values
Unless otherwise specified, typical data are based on T = 25°C, V = 5V. They are given
only as design guidelines and are not tested.
A
DD
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 58.
Figure 58. Pin loading conditions
ST7 pin
C
L
153/201
Electrical characteristics
ST7232Axx-Auto
12.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 59.
Figure 59. Pin input voltage
ST7 pin
VIN
12.2
Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
12.2.1
Voltage characteristics
Table 69. Voltage characteristics
Symbol
VDD - VSS
Ratings
Maximum value Unit
Supply voltage
6.5
13
VPP - VSS
Programming voltage
V
Input voltage on true open drain pin
Input voltage on any other pin
VSS - 0.3 to 6.5
(1)(2)
VIN
VSS - 0.3 to
VDD + 0.3
|∆VDDx| and |∆VSSx| Variations between different digital power pins
50
mV
50
|VSSA - VSSx
VESD(HBM)
VESD(MM)
|
Variations between digital and analog ground pins
Electro-static discharge voltage (human body model)
Electro-static discharge voltage (machine model)
See Section 12.7.3 on
page 167
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional
internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a
corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up
or pull-down resistor (typical: 4.7kΩfor RESET, 10kΩfor I/Os). For the same reason, unused I/O pins must
not be directly tied to VDD or VSS
.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
154/201
ST7232Axx-Auto
Electrical characteristics
Maximum value Unit
12.2.2
Current characteristics
Table 70. Current characteristics
Symbol
Ratings
32-pin device
75
150
75
150
20
40
- 25
5
Total current into VDD power lines
IVDD
mA
mA
(source(1)
)
44-pin device
32-pin device
44-pin device
Total current out of VSS ground lines
(sink)(1)
IVSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on VPP pin
IIO
Injected current on RESET pin
5
mA
(2)(3)
IINJ(PIN)
Injected current on OSC1 and OSC2 pins
Injected current on Flash device pin PB0
Injected current on any other pin(4)(5)
5
+5
5
Total injected current (sum of all I/O and control pins)(4)
25
(2)
ΣIINJ(PIN)
1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected
3. Negative injection disturbs the analog performance of the device. See note 3 in Section 12.12.3: ADC
accuracy on page 181.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterisation with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
5. True open drain I/O port pins do not accept positive injection.
12.2.3
Thermal characteristics
Table 71. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
-65 to +150
°C
Maximum junction temperature (see Section 13.2: Thermal characteristics)
155/201
Electrical characteristics
ST7232Axx-Auto
12.3
Operating conditions
Table 72. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fCPU
Internal clock frequency
0
8
MHz
Operating voltage
(except Flash write/erase)
3.8
4.5
5.5
5.5
VDD
V
Operating voltage for Flash
write/erase
VPP = 11.4 to 12.6V
A suffix version
B suffix version
C suffix version
-40
-40
-40
85
TA
Ambient temperature range
105
125
°C
Figure 60. f
max versus V
DD
CPU
f
[MHz]
CPU
8
6
4
2
Functionality not
guaranteed in this area
Functionality guaranteed
in this area (unless otherwise
specified in the tables
of parametric data)
1
0
3.5
3.8 4.0
4.5
5.5
Supply voltage [V]
1. Some temperature ranges are only available with a specific package and memory size. Refer to
Section 14: Device configuration and ordering information.
Warning: Do not connect 12V to V before V is powered on, as this
PP
DD
may damage the device.
156/201
ST7232Axx-Auto
Electrical characteristics
12.4
Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added (except for halt mode
for which the clock is stopped).
12.4.1
Current consumption
Table 73. Current consumption
Flash
ROM
devices
devices
Symbol
Parameter
Conditions
Unit
Typ Max(1) Typ Max(1)
fOSC = 2MHz, fCPU = 1MHz
Supply current in run fOSC = 4MHz, fCPU = 2MHz
1
2.3
3.5
5.3
7.0
1.3
2.0
3.6
7.1
2.0
3.0
5
1.4
2.4
4.4
mA
mA
mA
mode(2)
fOSC = 8MHz, fCPU = 4MHz
fOSC = 16MHz, fCPU = 8MHz
10
fOSC = 2MHz, fCPU = 62.5kHz 0.48
Supply current in slow fOSC = 4MHz, fCPU = 125kHz 0.53
1
0.6
0.7
0.8
1.1
1.8
2.1
2.4
3.0
1.1
1.2
1.4
mode(2)
fOSC = 8MHz, fCPU = 250kHz 0.63
fOSC = 16MHz, fCPU = 500kHz 0.80
fOSC = 2MHz, fCPU = 1MHz
Supply current in wait fOSC = 4MHz, fCPU = 2MHz
0.6
0.9
1.3
2.3
1.8
2.2
2.6
3.6
1
1.3
2.0
3.3
6
1.5
2.5
4.5
mode(2)
fOSC = 8MHz, fCPU = 4MHz
fOSC = 16MHz, fCPU = 8MHz
IDD
fOSC = 2MHz, fCPU = 62.5kHz 430
950
70
200
300
600
Supply current in slow fOSC = 4MHz, fCPU = 125kHz
470 1000 100
530 1050 200
µA
µA
µA
wait mode(2)
fOSC = 8MHz, fCPU = 250kHz
fOSC = 16MHz, fCPU = 500kHz 660 1200 350 1200
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
<1
5
10
50
<1
<1
10
50
Supply current in halt
mode(3)
fOSC = 2MHz
fOSC = 4MHz
fOSC = 8MHz
60
160
200
300
500
22
44
86
30
60
120
300
Supply current in
active halt mode(4)
100
180
340
f
OSC = 16MHz
170
1. Data based on characterization results, tested in production at VDD max. and fCPU max.
2. Measurements are done in the following conditions:
- Progam executed from RAM, CPU running with RAM access. The increase in consumption when
executing from Flash is 50%.
- All I/O pins in input mode with a static value at VDD or VSS (no load)
- All peripherals in reset state.
- Clock input (OSC1) driven by external square wave.
- In slow and slow wait mode, fCPU is based on fOSC divided by 32.
To obtain the total current consumption of the device, add the clock source (Section 12.5.3) and the
peripheral power consumption (Section 12.4.3).
3. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load). Data based
on characterization results, tested in production at VDD max. and fCPU max.
4. Data based on characterisation results, not tested in production. All I/O pins in push-pull 0 mode (when
applicable) with a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave.
To obtain the total current consumption of the device, add the clock source consumption (Section 12.5.3).
157/201
Electrical characteristics
ST7232Axx-Auto
Power consumption vs fCPU: Flash devices
Figure 61. Typical I in run mode
DD
6
5
4
3
2
1
0
2MHZ
4MHz
8MHz
16MHz
Vdd (V)
Figure 62. Typical I in slow mode
DD
1.2
1
0.8
0.6
0.4
0.2
0
2MHZ
4MHz
8MHz
16MHz
Vdd (V)
158/201
ST7232Axx-Auto
Figure 63. Typical I in wait mode
Electrical characteristics
DD
3.5
3
2.5
2
2MHZ
4MHz
8MHz
16MHz
1.5
1
0.5
0
Vdd (V)
Figure 64. Typ. I in slow wait mode
DD
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2MHZ
4MHz
8MHz
16MHz
Vdd (V)
12.4.2
Supply and clock managers
The previous current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added (except for halt mode).
Table 74. Supply current of clock sources
Symbol
Parameter
Conditions
Typ
Max
Unit
Supply current of resonator
oscillator(1)(2)
see Section 12.5.3
IDD(RES)
µA
µA
on page 162
IDD(PLL) PLL supply current
VDD = 5V
360
1. Data based on characterization results done with the external components specified in Section 12.5.3 , not
tested in production.
2. As the oscillator is based on a current source, the consumption does not depend on the voltage.
159/201
Electrical characteristics
ST7232Axx-Auto
12.4.3
On-chip peripherals
Table 75. On-chip peripherals
Symbol Parameter
Conditions
Typ Unit
IDD(TIM) 16-bit timer supply current(1)
IDD(SPI) SPI supply current(2)
50
TA = 25°C, fCPU = 4MHz, VDD = 5.0V
µA
IDD(SCI) SCI supply current(3)
400
IDD(ADC) ADC supply current when converting(4)
1. Data based on a differential IDD measurement between reset configuration (timer counter running at
fCPU/4) and timer counter stopped (only TIMD bit set). Data valid for one timer.
2. Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent
SPI master communication at maximum speed (data sent equal to 55h). This measurement includes the
pad toggling consumption.
3. Data based on a differential IDD measurement between SCI low power state (SCID=1) and a permanent
SCI data transmit sequence.
4. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions.
12.5
Clock and timing characteristics
Subject to general operating conditions for V , f
, and T .
A
DD CPU
12.5.1
General timings
Table 76. General timings
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Unit
2
3
12
1500
22
tCPU
ns
tc(INST) Instruction cycle time
fCPU = 8MHz
250
10
375
Interrupt reaction time(2)
tv(IT)
tCPU
µs
tv(IT) = ∆tc(INST) + 10
fCPU = 8MHz
1.25
2.75
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles
needed to finish the current instruction execution.
160/201
ST7232Axx-Auto
Electrical characteristics
12.5.2
External clock source
Table 77. External clock source
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOSC1H
VOSC1L
tw(OSC1H)
OSC1 input pin high level voltage
OSC1 input pin low level voltage
VDD - 1
VSS
VDD
V
VSS + 1
OSC1 high or low time(1)
5
see Figure 65
tw(OSC1L)
ns
tr(OSC1)
tf(OSC1)
OSC1 rise or fall time(1)
15
1
Ilkg
OSC1 Input leakage current
VSS ≤ VIN ≤ VDD
µA
1. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 65. Typical application with an external clock source
90%
V
OSC1H
OSC1L
10%
V
t
t
w(OSC1H)
t
t
w(OSC1L)
f(OSC1)
r(OSC1)
OSC2
Not connected internally
f
OSC
I
lkg
External clock source
OSC1
ST72XXX
161/201
Electrical characteristics
ST7232Axx-Auto
12.5.3
Crystal and ceramic resonator oscillators
The ST7 internal clock can be supplied with four different crystal/ceramic resonator
oscillators. All the information given in this paragraph are based on characterization results
with specified typical external components. In the application, the resonator and the load
capacitors have to be placed as close as possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, package, accuracy...).
Table 78. Oscillator parameters
Symbol
Parameter
Conditions
Min
Max Unit
LP: Low power oscillator
1
2
MP: Medium power oscillator >2
MS: Medium speed oscillator >4
4
fOSC
Oscillator frequency(1)
Feedback resistor(2)
MHz
8
HS: High speed oscillator
>8
16
RF
20
40
kΩ
RS = 200Ω LP oscillator
RS = 200Ω MP oscillator
RS = 200Ω MS oscillator
RS = 100ΩHS oscillator
22
22
18
15
56
46
33
33
Recommended load capacitance
versus equivalent serial resistance of
the crystal or ceramic resonator (RS)
CL1
CL2
pF
VIN = VSS
LP oscillator
MP oscillator
MS oscillator
HS oscillator
80
150
250
460
910
i2
OSC2 driving current
160
310
610
µA
1. The oscillator selection can be optimized in terms of supply current using a high quality resonator with
small RS value. Refer to crystal/ceramic resonator manufacturer for more details.
2. Data based on characterisation results, not tested in production.
Figure 66. Typical application with a crystal or ceramic resonator
i
2
When resonator with integrated capacitors
f
OSC
C
L1
OSC1
OSC2
Resonator
R
F
C
L2
ST72XXX
162/201
ST7232Axx-Auto
Electrical characteristics
Table 79. Examples of typical resonators
CL1 CL2 tSU(osc)
[pF] [pF] [ms](3)
Oscil.
Reference(1)
Freq.
Characteristic(2)
∆fOSC
=
LP
MP
MS
HS
CSA2.00MG
CSA4.00MG
CSA8.00MTZ
2MHz
4MHz
8MHz
16MHz
22 22
22 22
33 33
33 33
4
2
[ 0.5%tolerance, 0.3%∆Ta
,
,
,
,
0.3%aging
0.3%aging
0.3%aging
0.3%aging
,
,
,
,
x.x%correl
x.x%correl
x.x%correl
x.x%correl
]
]
]
]
∆fOSC
=
[ 0.5%tolerance, 0.3%∆Ta
∆fOSC
=
1
[ 0.5%tolerance, 0.5%∆Ta
CSA16.00MXZ040
∆fOSC
=
0.7
(4)
[ 0.5%tolerance, 0.3%∆Ta
1. Resonators all have different characteristics. Contact the manufacturer to obtain the appropriate values of external
components and to verify oscillator performance.
2. Resonator characteristics given by the ceramic resonator manufacturer.
3. tSU(OSC) is the typical oscillator start-up time measured between VDD = 2.8V and the fetch of the first instruction (with a
quick VDD ramp-up from 0 to 5V (< 50µs).
4. 3rd overtone resonators require specific validation by the resonator manufacturer.
12.5.4
PLL characteristics
Table 80. PLL characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fOSC
PLL input frequency range
2
4
2
MHz
%
∆ fCPU/fCPU Instantaneous PLL jitter(1)
fOSC = 4 MHz.
0.7
1. Data characterized but not tested.
The user must take the PLL jitter into account in the application (for example in serial
communication or sampling of high frequency signals). The PLL jitter is a periodic effect,
which is integrated over several CPU cycles. Therefore the longer the period of the
application signal, the less it is impacted by the PLL jitter.
Figure 67 shows the PLL jitter integrated on application signals in the range 125kHz to
2MHz. At frequencies of less than 125KHz, the jitter is negligible.
Figure 67. Integrated PLL jitter vs signal frequency
+/-Jitter
(%)
1.2
1
max
typ
0.8
0.6
0.4
0.2
0
4
2
1
500 250 125
MHz MHz MHz kHz kHz kHz
Application Frequency
1. Measurement conditions: fCPU = 8MHz.
163/201
Electrical characteristics
ST7232Axx-Auto
12.6
Memory characteristics
12.6.1
RAM and hardware registers
Table 81. RAM and hardware registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VRM
Data retention mode(1)
Halt mode (or reset)
1.6
V
1. Minimum VDD supply voltage without losing data stored in RAM (in halt mode or under reset) or in
hardware registers (only in halt mode). Not tested in production.
12.6.2
Flash memory
Table 82.
Characteristics of dual voltage HDFlash memory
Dual voltage HDFlash memory
Symbol
Parameter
Conditions
Read mode
Min(1) Typ Max(1) Unit
0
1
8
8
fCPU
Operating frequency
MHz
Write/erase mode
4.5V ≤VDD ≤5.5V
Write/erase
VPP
IDD
Programming voltage(2)
Supply current(3)
11.4
12.6
V
µA
<10
10
Read (VPP = 12V)
Write/erase
200
30
µA
IPP
VPP current(3)
mA
tVPP
tRET
NRW
Internal VPP stabilization time
Data retention time
µs
TA = 55°C
TA = 85°C
20
Years
Cycles
Write erase cycles
100
TPROG Programming or erasing
TERASE temperature range
-40
25
85
°C
1. Data based on characterization results, not tested in production.
2. VPP must be applied only during the programming or erasing operation and not permanently for reliability
reasons.
3. Data based on simulation results, not tested in production.
164/201
ST7232Axx-Auto
Electrical characteristics
12.7
Electromagnetic compatability (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
12.7.1
Functional electromagnetic susceptibility (EMS)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electro magnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the
IEC 1000 - 4 - 2 standard.
●
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
DD
SS
through a 100pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000 - 4 - 4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behaviour is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
165/201
Electrical characteristics
ST7232Axx-Auto
Table 83. Electromagnetic test results
Symbol
Parameter
Conditions
Level/class
ROM device, VDD = 5V, TA = +25°C,
4A
Voltage limits to be applied on
VFESD any I/O pin to induce a
functional disturbance
fOSC = 8MHz conforms to IEC 1000 - 4 - 2
Flash device, VDD = 5V, TA = +25°C,
fOSC = 8MHz conforms to IEC 1000 - 4 - 2
4B
4A
Fast transient voltage burst
limits to be applied through
VDD = 5V, TA = +25°C, fOSC = 8MHz
100pF on VDD and VDD pins to conforms to IEC 1000 - 4 - 4
induce a functional disturbance
VFFTB
12.7.2
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling two LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
(1)
Table 84. EMI emissions
Max vs. [fOSC/fCPU
]
Monitored
frequency band
Sym. Parameter
Cond.
Device/package
Unit
8/4MHz 16/8MHz
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI level
25
30
18
3.0
25
30
18
3.0
12
19
15
3
27
36
23
3.5
27
36
23
3.5
18
25
22
3.5
15
26
20
3.5
dBµV
Flash/LQFP32
-
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI level
dBµV
ROM/LQFP32(3)
8K Flash/LQFP44
8K ROM/LQFP44
-
Peak
SEMI
level(2)
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI level
dBµV
-
dBµV
-
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI level
12
23
15
3.0
1. Refer to Application Note AN1709 for data on other package types
2. Data based on characterization results, not tested in production
3. Under completion
166/201
ST7232Axx-Auto
Electrical characteristics
12.7.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the device
is stressed in order to determine its performance in terms of electrical sensitivity.
Electro-static discharge (ESD)
Electro-static discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the AEC-Q100-002/003/011 standard. For more details, refer to the application
note AN1181.
Table 85. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
TA = +25°C
conforming to AEC-Q100-
002
Electro-static discharge voltage
(human body model)
VESD(HBM)
H1C
2000
TA = +25°C
conforming to AEC-Q100-
003
Electro-static discharge voltage
(machine model)
VESD(MM)
M2
200
V
> 500 to ≤
750 with
corner
TA = +25°C
conforming to AEC-Q100-
011
Electro-static discharge voltage
(charged device model)
VESD(CDM)
C3B
pins > 750
1. Data based on characterization results, not tested in production
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
●
A current injection is applied to each input, output and configurable I/0 pin
These tests are compliant with EIA/JESD 78A and AEC-Q100/004 IC latch-up standards.
Table 86. Latch up results
Symbol
Parameter
Conditions
Class
TA = +125°C
conforming to JESD 78A and AEC-Q100/004
LU
Static latch-up class
II level A
167/201
Electrical characteristics
ST7232Axx-Auto
12.8
I/O port pin characteristics
12.8.1
General characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
Table 87. I/O general port pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input low level voltage
VIL
0.3 x VDD
V
(standard voltage devices)(1)
VIH
Input high level voltage(1)
0.7 x VDD
V
Vhys
Schmitt trigger voltage hysteresis(2)
0.7
Injected current on Flash device pin
PB0
0
+4
4
(3)
IINJ(PIN)
Injected current on other I/O pins
VDD = 5V
mA
Total injected current
(sum of all I/O and control pins)
(3)
ΣIINJ(PIN)
±25
1
Ilkg
IS
Input leakage current
VSS ≤VIN ≤VDD
µA
Static current consumption induced by
each floating input pin
Floating input mode(4)(5)
VIN = VSS, VDD = 5V
200
RPU
CIO
Weak pull-up equivalent resistor(6)
50
120
5
250
kΩ
I/O pin capacitance
pF
tf(IO)out
tr(IO)out
tw(IT)in
Output high to low level fall time(1)
Output low to high level rise time(1)
External interrupt pulse time(7)
25
25
CL = 50pF between
10% and 90%
ns
1
tCPU
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specification. A
positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. Refer to Section 12.2.2 on
page 155 for more details.
4. Static peak current value taken at a fixed VIN value, based on design simulation and technology characteristics, not tested
in production. This value depends on VDD and temperature values.
5. The Schmitt trigger that is connected to every I/O port is disabled for analog inputs only when ADON bit is ON and the
particular ADC channel is selected (with port configured in input floating mode). When the ADON bit is OFF, static current
consumption may result. This can be avoided by keeping the input voltage of this pin close to VDD or VSS.
6. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described
in Figure 69).
7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
168/201
ST7232Axx-Auto
Figure 68. Unused I/O pins configured as input
Electrical characteristics
V
DD
ST7XXX
Unused I/O port
10kΩ
Unused I/O port
ST7XXX
10kΩ
1. I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC
robustness and lower cost.
Figure 69. Typical I vs. V with V = V
PU
DD
IN
SS
90
80
70
60
50
40
30
20
10
0
Ta=140°C
Ta=95°C
Ta=25°C
Ta=-45°C
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
169/201
Electrical characteristics
ST7232Axx-Auto
12.8.2
Output driving current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Table 88. Output driving current
Symbol
Parameter
Conditions
IIO = +5mA
IIO = +2mA
Min
Max Unit
1.2
Output low level voltage for a standard
I/O pin when 8 pins are sunk at same
time (see Figure 70)
0.5
(1)
VOL
IIO = +20mA,
TA ≤ 85°C
TA > 85°C
1.3
1.5
V
Output low level voltage for a high sink
I/O pin when 4 pins are sunk at same
time (see Figure 71 and Figure 73)
IIO = +8mA
0.6
I
IO = -5mA,
VDD - 1.4
VDD - 1.6
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 72 and Figure 75)
TA ≤ 85°C
TA > 85°C
(2)
VOH
IIO = -2mA
VDD - 0.7
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the
sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and
the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins do not have VOH
.
Figure 70. Typical V at V = 5V (std. ports)
OL
DD
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Ta=140°C "
Ta=95°C
Ta=25°C
Ta=-45°C
5
10
15
I
(mA)
IO
170/201
ST7232Axx-Auto
Figure 71. Typ. V at V = 5V (high-sink ports)
Electrical characteristics
OL
DD
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Ta= 140°C
Ta=95°C
Ta=25°C
Ta=-45°C
10
20
(mA)
30
I
IO
Figure 72. Typical V at V = 5V
OH
DD
5.5
5
4.5
4
3.5
3
Vdd=5V 140°C min
Vdd=5v 95°C min
Vdd=5v 25°C min
Vdd=5v -45°C min
2.5
2
-10
-8
-6
-4
-2
0
I
(mA)
IO
Figure 73. Typical V vs. V (std. ports)
OL
DD
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.45
0.4
Ta= -45°C
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
Ta=25°C
Ta=95°C
Ta=140°C
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
Vdd(V)
171/201
Electrical characteristics
ST7232Axx-Auto
Figure 74. Typical V vs. V (high-sink ports)
OL
DD
1.6
1.4
1.2
1
0.6
Ta= 140°C
Ta=95°C
0.5
Ta=25°C
Ta=-45°C
0.4
0.3
0.2
0.8
0.6
0.4
0.2
0
Ta= 140°C
Ta=95°C
Ta=25°C
Ta=-45°C
0.1
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
V dd(V )
Vdd(V )
Figure 75. Typical V vs. V
OH
DD
5.5
5
6
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
5
4
3
2
1
0
4.5
4
3.5
3
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
2.5
2
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
Vdd(V)
172/201
ST7232Axx-Auto
Electrical characteristics
12.9
Control pin characteristics
12.9.1
Asynchronous RESET pin
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD CPU
A
Table 89. Asynchronous RESET pin
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vhys
VIL
Schmitt trigger voltage hysteresis(1)
Input low level voltage(2)
2.5
0.16 x VDD
0.5
VIH
VOL
IIO
Input high level voltage(2)
0.85 x VDD
V
Output low level voltage(3)
VDD = 5V IIO = +2mA
0.2
2
Driving current on RESET pin
Weak pull-up equivalent resistor
mA
kΩ
µs
RON
VDD = 5V
20
20
30
30
120
tw(RSTL)out Generated reset pulse duration
th(RSTL)in External reset pulse hold time (5)
tg(RSTL)in Filtered glitch duration(6)
Internal reset sources
42(4)
2.5
µs
200
ns
1. Hysteresis voltage between Schmitt trigger switching levels.
2. Data based on characterization results, not tested in production.
3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O
ports and control pins) must not exceed IVSS
.
4. Data guaranteed by design, not tested in production.
5. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the
RESET pin with a duration below th(RSTL)in can be ignored.
6. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy
environments.
Figure 76. RESET pin protection
V
ST72XXX
DD
R
ON
User external
reset circuit
Internal reset
Watchdog
Filter
0.01µF
Pulse generator
Required
1. The reset network protects the device against parasitic resets.
2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (watchdog).
3. 3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the VIL max. level specified in Section 12.9.1 . Otherwise the reset is not taken into account internally.
4. 4. Because the reset circuit is designed to allow the internal reset to be output in the RESET pin, the user must ensure that
the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value specified
for IINJ(RESET) in Section 12.2.2 on page 155.
173/201
Electrical characteristics
ST7232Axx-Auto
12.9.2
ICCSEL/V pin
PP
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD CPU
A
Table 90. ICCSEL/V pin characteristics
PP
Symbol
Parameter
Conditions
Min
Max
Unit
Flash versions
ROM versions
Flash versions
ROM versions
VIN = VSS
VSS
VSS
0.2
0.3 x VDD
12.6
VIL
Input low level voltage(1)
V
VDD - 0.1
0.7 x VDD
VIH
Ilkg
Input high level voltage(1)
Input leakage current
VDD
1
uA
1. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 77. Two typical applications with ICCSEL/V pin
PP
ICCSEL/V
V
PP
PP
Programming
tool
10kΩ
ST72XXX
ST72XXX
1. When ICC mode is not required by the application ICCSEL/VPP pin must be tied to VSS
.
12.10
Timer peripheral characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Refer to Section 9: I/O ports for more details on the input/output alternate function
characteristics (output compare, input capture, external clock, PWM output...).
Data based on design simulation and/or characterisation results, not tested in production.
12.10.1 16-bit timer
Table 91. 16-bit timer
Symbol Parameter
Conditions
Min
Typ
Max
Unit
tw(ICAP)in Input capture pulse time
tres(PWM) PWM resolution time
1
2
tCPU
ns
fCPU = 8MHz
250
0
fEXT
Timer external clock frequency
PWM repetition rate
fCPU/4
fCPU/4
16
MHz
bit
fPWM
0
ResPWM PWM resolution
174/201
ST7232Axx-Auto
Electrical characteristics
12.11
Communication interface characteristics
12.11.1 SPI (serial peripheral interface)
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Data based on design simulation and/or characterisation results, not tested in production.
When no communication is on-going the data output line of the SPI (MOSI in master mode,
MISO in slave mode) has its alternate function capability released. In this case, the pin
status depends on the I/O port configuration. Refer to Section 9: I/O ports for more details
on the input/output alternate function characteristics (SS, SCK, MOSI, MISO).
Table 92. SPI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Master fCPU = 8MHz
Slave fCPU = 8MHz
fCPU/128 = 0.0625 fCPU/4 = 2
fSCK
1/tc(SCK)
SPI clock frequency
MHz
0
fCPU/2 = 4
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
see Table 2: Device pin description
(1)
tsu(SS)
SS setup time(2)
120
120
Slave
(1)
th(SS)
SS hold time
(1)
tw(SCKH)
tw(SCKL)
Master
Slave
100
90
SCK high and low time
Data input setup time
Data input hold time
(1)
(1)
tsu(MI)
tsu(SI)
Master
Slave
100
100
(1)
(1)
th(MI)
th(SI)
Master
Slave
100
100
ns
(1)
Data output access
time
(1)
ta(SO)
0
120
Slave
Data output disable
time
(1)
tdis(SO)
240
90
(1)
tv(SO)
th(SO)
tv(MO)
th(MO)
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave (after enable
edge)
(1)
0
0
(1)
(1)
120
Master (after enable
edge)
1. Data based on design simulation and/or characterization results, not tested in production
2. Depends on fCPU. For example, if fCPU = 8 MHz, then tCPU = 1/fCPU = 125ns and tsu(SS) = 175ns.
175/201
Electrical characteristics
ST7232Axx-Auto
Figure 78. SPI slave timing diagram with CPHA = 0
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
t
t
w(SCKH)
w(SCKL)
t
t
h(SO)
t
v(SO)
t (SO)
dis(SO)
t
t
a
r(SCK)
f(SCK)
MISO
see note 2
MSB OUT
BIT6 OUT
LSB OUT
see note 2
OUTPUT
t
h(SI)
t
su(SI)
MOSI
INPUT
MSB IN
BIT1 IN
LSB IN
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD
.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends of the I/O port configuration.
Figure 79. SPI slave timing diagram with CPHA = 1
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
t
t
w(SCKH)
w(SCKL)
t
t
dis(SO)
v(SO)
t
t
t
h(SO)
t
r(SCK)
f(SCK)
a(SO)
MISO
HZ
MSB OUT
BIT6 OUT
LSB OUT
OUTPUT
see note 2
see note 2
t
h(SI)
t
su(SI)
MOSI
MSB IN
BIT1 IN
LSB IN
INPUT
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD
.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends of the I/O port configuration.
176/201
ST7232Axx-Auto
Figure 80. SPI master timing diagram
Electrical characteristics
SS
INPUT
t
c(SCK)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CPHA=1
CPOL=0
CPHA = 1
CPOL = 1
t
w(SCKH)
t
t
r(SCK)
w(SCKL)
t
f(SCK)
t
h(MI)
t
su(MI)
MISO
INPUT
MSB IN
BIT6 IN
LSB IN
t
t
v(MO)
h(MO)
MOSI
see note 2
see note 2
OUTPUT
MSB OUT
BIT6 OUT
LSB OUT
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD
.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends of the I/O port
configuration.
177/201
Electrical characteristics
ST7232Axx-Auto
12.12
10-bit ADC characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD CPU
A
Table 93. 10-bit ADC characteristics
Symbol
Parameter
ADC clock frequency
Conditions
Min Typ
Max
Unit
fADC
0.4
2
VDD
VAREF
250
1
MHz
VAREF Analog reference voltage
0.7 * VDD ≤ VAREF ≤ VDD 3.8
VSSA
V
VAIN
Conversion voltage range(1)
-40°C ≤ TA ≤ +85°C
+85°C < TA ≤ +125°C
nA
µA
kΩ
pF
Hz
pF
Ilkg
Input leakage current for analog input (2)
RAIN
CAIN
fAIN
External input impedance
see Figure 81
and Figure 82
External capacitor on analog input
Variation freq. of analog input signal
CADC Internal sample and hold capacitor
12
Conversion time (sample + hold)
tADC
7.5
µs
fCPU = 8MHz, SPEED = 0 fADC = 2MHz
– No of sample capacitor loading cycles
tADC
4
1/fADC
– No. of hold conversion cycles
11
1. Any added external serial resistor downgrades the ADC accuracy (especially for resistance greater than 10kΩ). Data based
on characterization results, not tested in production.
2. Injecting negative current on adjacent pins may result in increased leakage currents. Software filtering of the converted
analog value is recommended.
Figure 81. R
max. vs f
with C = 0pF
AIN
AIN
ADC
45
40
35
30
25
2 M Hz
1 M H z
20
15
10
5
0
0
10
30
70
CPARASITIC (pF)
1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad
capacitance (3pF). A high CPARASITIC value downgrades conversion accuracy. To remedy this, fADC should be reduced.
178/201
ST7232Axx-Auto
Figure 82. Recommended C
Electrical characteristics
and R
values
AIN
AIN
Cain 10 nF
1000
Cain 22 nF
Cain 47 nF
100
10
1
0.1
0.01
0.1
1
10
fAIN(KHz)
1. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization
time and decreased to allow the use of a larger serial resistor (RAIN)
.
Figure 83. Typical A/D converter application
ST72XXX
V
DD
V
T
0.6V
R
2kΩ(max)
AIN
AINx
10-bit A/D
conversion
V
AIN
C
V
T
0.6V
AIN
C
12pF
I
ADC
lkg
12.12.1 Analog power supply and reference pins
Depending on the MCU pin count, the package may feature separate V
and V
SSA
AREF
analog power supply pins. These pins supply power to the A/D converter cell and function
as the high and low reference voltages for the conversion. In some packages, V and
AREF
V
pins are not available (refer to Section 2: Pin description on page 19). In this case the
SSA
analog supply and reference pads are internally bonded to the V and V pins.
DD
SS
Separation of the digital and analog power pins allow board designers to improve A/D
performance. Conversion accuracy can be impacted by voltage drops and noise in the event
of heavily loaded or badly decoupled power supply lines (see Section 12.12.2: General PCB
design guidelines on page 180).
179/201
Electrical characteristics
ST7232Axx-Auto
12.12.2 General PCB design guidelines
To obtain best results, some general design and layout rules should be followed when
designing the application PCB to shield the noise-sensitive, analog physical interface from
noise-generating CMOS logic signals.
●
Use separate digital and analog planes. The analog ground plane should be connected
to the digital ground plane via a single point on the PCB.
●
Filter power to the analog power planes. It is recommended to connect capacitors, with
good high frequency characteristics, between the power and ground lines, placing
0.1µF and optionally, if needed 10pF capacitors as close as possible to the ST7 power
supply pins and a 1 to 10µF capacitor close to the power source (see Figure 84).
●
●
The analog and digital power supplies should be connected in a star nework. Do not
use a resistor, as V
is used as a reference voltage by the A/D converter and any
AREF
resistance would cause a voltage drop and a loss of accuracy.
Properly place components and route the signal traces on the PCB to shield the analog
inputs. Analog signals paths should run over the analog ground plane and be as short
as possible. Isolate analog signals from digital signals that may switch while the analog
inputs are being sampled by the A/D converter. Do not toggle digital outputs on the
same I/O port as the A/D input being converted.
Figure 84. Power supply filtering
ST72XXX
1 to 10µF
0.1µF
V
V
SS
DD
ST7 digital noise
filtering
V
DD
Power
source supply
0.1µF
V
AREF
External noise
filtering
V
SSA
180/201
ST7232Axx-Auto
Electrical characteristics
12.12.3 ADC accuracy
Table 94. ADC accuracy with V = 5.0V
DD
Symbol
Parameter
Conditions
Typ Max(1) Unit
|ET|
|EO|
|EG|
|ED|
|EL|
Total unadjusted error (2)
4
6
(2)
Offset error
3
5
(2)
Gain error
CPU in run mode @ fADC = 2 MHz.
0.5
1.5
1.5
4.5
4.5
4.5
LSB
(2)
Differential linearity error
(2)
Integral linearity error
1. Data based on characterization results, monitored in production to guarantee 99.73% within max value
from -40°C to 125°C ( 3σ distribution limits).
2. ADC accuracy vs. negative injection current: Injecting negative current may reduce the accuracy of the
conversion being performed on another analog input. Any positive injection current within the limits
specified for IINJ(PIN) and ΣIINJ(PIN) in Section 12.8 does not affect the ADC accuracy.
Figure 85. ADC accuracy characteristics
Digital result ADCDR
E
G
1023
1022
1021
V
– V
AREF
SSA
1LSB
= --------------------------------------------
IDEAL
1024
(2)
(1) = Example of an actual transfer curve
E
T
(3)
7
6
5
4
3
2
1
(2) = Ideal transfer curve
(1)
(3) = End point correlation line
E
O
E
L
E
D
1 LSB
IDEAL
V
(LSB
)
IDEAL
in
0
1
2
3
4
5
6
7
10211022 1023 1024
V
V
AREF
SSA
1. Legend:
ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves
EO = Offset error: deviation between the first actual transition and the first ideal one
E
G = Gain error: deviation between the last ideal transition and the last actual one
ED = Differential linearity error: maximum deviation between actual steps and the ideal one
EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation
line
181/201
Package characteristics
ST7232Axx-Auto
13
Package characteristics
13.1
Package mechanical data
Figure 86. 32-pin LQFP outline
D
A
D1
A2
A1
e
E
E1
b
c
L1
L
h
Table 95. 32-pin LQFP mechanical data
mm
inches
Typ
Dim.
Min
Typ
Max
Min
Max
A
A1
A2
b
1.600
0.150
1.450
0.450
0.200
0.0630
0.0059
0.0571
0.0177
0.0079
0.050
1.350
0.300
0.090
0.0020
0.0531
0.0118
0.0035
1.400
0.370
0.0551
0.0146
C
D
9.000
7.000
9.000
7.000
0.800
3.5°
0.3543
0.2756
0.3543
0.2756
0.0315
3.5°
D1
E
E1
e
θ
0°
7°
0°
7°
L
0.450
0.600
1.000
0.750
0.0177
0.0236
0.0394
0.0295
L1
182/201
ST7232Axx-Auto
Figure 87. 44-pin LQFP outline
Package characteristics
A
D
D1
A2
A1
b
e
E1
E
L
c
L1
h
Table 96. 44-pin LQFP mechanical data
mm
inches
Typ
Dim.
Min
Typ
Max
Min
Max
A
A1
A2
b
1.600
0.150
1.450
0.450
0.200
0.0630
0.0059
0.0571
0.0177
0.0079
0.050
1.350
0.300
0.090
0.0020
0.0531
0.0118
0.0035
1.400
0.370
0.0551
0.0146
0.000
C
D
12.000
10.000
12.000
10.000
0.800
3.5°
0.4724
0.3937
0.4724
0.3937
0.0315
3.5°
D1
E
E1
e
θ
0°
7°
0°
7°
L
0.450
0.600
1.000
0.750
0.0177
0.0236
0.0236
0.0295
L1
183/201
Package characteristics
ST7232Axx-Auto
13.2
Thermal characteristics
Table 97. Thermal characteristics
Symbol
Ratings
Value
Unit
Package thermal resistance (junction to ambient)
LQFP32
LQFP44
70
52
RthJA
°C/W
PD
Power dissipation(1)
500
150
mW
°C
TJmax
Maximum junction temperature(2)
1. The maximum power dissipation is obtained from the formula PD = (TJ-TA)/RthJA. The power dissipation of
an application can be defined by the user with the formula: PD = PINT + PPORT where PINT is the chip
internal power (IDD x VDD) and PPORT is the port power dissipation depending on the ports used in the
application.
2. The maximum chip-junction temperature is based on technology characteristics.
13.3
Soldering information
In order to meet environmental requirements, ST offers these devices in ECOPACK® pack-
ages. These packages have a lead-free second level interconnect. The category of second
level interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK® specifications are available at www.st.com.
Compatibility
ECOPACK® LQFP packages are fully compatible with Lead (Pb) containing soldering
process (see application note AN2034).
Table 98. Soldering compatibility (wave and reflow soldering process)
Package
LQFP32
LQFP44
Plating material devices
Pb solder paste Pb-free solder paste
NiPdAu (Nickel-Palladium-Gold)
Sn (pure Tin)
Yes Yes
184/201
ST7232Axx-Auto
Device configuration and ordering information
14
Device configuration and ordering information
14.1
Introduction
Each device is available for production in user programmable versions (Flash) as well as in factory coded
versions (ROM/FASTROM).
ST7232A-Auto are ROM versions. ST72P32A-Auto devices are factory advanced service technique
ROM (FASTROM) versions: they are factory-programmed HDFlash devices.
Flash devices are shipped to customers with a default content (FFh), while ROM factory coded parts
contain the code supplied by the customer. This implies that Flash devices have to be configured by the
customer using the option bytes while the ROM devices are factory-configured.
14.2
Flash devices
14.2.1
Flash configuration
Table 99. Flash option bytes
Static option byte 0
Static option byte 1
7
6
5
4
3
2
1
1
0
7
6
5
4
3
2
1
0
WDG
HALT SW
OSCTYPE
OSCRANGE
PLL
OFF
Reserved
FMP_R PKG1 RSTC
See
1
1
0
0
2
1
1
0
Default
1
1
1
1
1
1
1
note
1
1
0
1
1
1. Depends on device type as defined in Table 102: Package selection (OPT7) on page 187
The option bytes allows the hardware configuration of the microcontroller to be selected. They have no
address in the memory map and can be accessed only in programming mode (for example using a
standard ST7 programming tool). The default content of the Flash is fixed to FFh. To program directly the
Flash devices using ICP, Flash devices are shipped to customers with an internal clock source selected.
In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see option list).
185/201
Device configuration and ordering information
Table 100. Option byte 0 description
ST7232Axx-Auto
Bit
Bit name
Function
Watchdog reset on halt
This option bit determines if a reset is generated when entering halt mode while the
watchdog is active.
7
WDG HALT
0: No reset generation when entering halt mode
1: Reset generation when entering halt mode
Hardware or software watchdog
This option bit selects the watchdog type
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
6
WDG SW
-
5:1
Reserved, must be kept at default value
Flash memory read-out protection
Read-out protection, when selected, provides a protection against program
memory content extraction and against write access to Flash memory.
Erasing the option bytes when the FMP_R option is selected causes the whole
user memory to be erased first, and the device can be reprogrammed. Refer to
Section 4.3.1: Read-out protection on page 28 and the ST7 Flash programming
reference manual for more details.
0
FMP_R
0: Read-out protection enabled
1: Read-out protection disabled
Table 101. Option byte 1 description
Bit
Bit name
Function
Pin package selection bit
This option bit selects the package (see Table 102)
7
PKG1
Note: On the chip, each I/O port has 8 pads. Pads that are not bonded to external
pins are in input pull-up configuration after reset. The configuration of these pads
must be kept at reset state to avoid added current consumption.
Reset clock cycle selection
This option bit selects the number of CPU cycles applied during the reset phase
and when exiting halt mode. For resonator oscillators, it is advised to select 4096
due to the long crystal stabilization time.
6
RSTC
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
Oscillator type
These option bits select the ST7 main clock source type:
00: Clock source = Resonator oscillator
01: Reserved
5:4
OSCTYPE[1:0]
10: Reserved
11: Clock source = External source
186/201
ST7232Axx-Auto
Device configuration and ordering information
Function
Table 101. Option byte 1 description (continued)
Bit
Bit name
Oscillator range
When the resonator oscillator is selected, these option bits select the resonator
oscillator current source corresponding to the frequency range of the used
resonator. Otherwise, these bits are used to select the normal frequency range.
000: Typ. frequency range (LP) = >1~2MHz
3:1
OSCRANGE[2:0]
001: Typ. frequency range (MP) = >2~4MHz)
010: Typ. frequency range (MS) = >4~8MHz)
011: Typ. frequency range (HS) = >8~16MHz)
PLL activation
This option bit activates the PLL which allows multiplication by two of the main
input clock frequency. The PLL must not be used with the internal RC oscillator.
The PLL is guaranteed only with an input frequency between 2 and 4MHz.
0: PLL x2 enabled
0
PLL OFF
1: PLL x2 disabled
Caution: The PLL can be enabled only if the ‘OSC RANGE’ (OPT3:1) bits are
configured to ‘MP - 2~4MHz’. Otherwise, the device functionality is not
guaranteed.
Caution 2: When the PLL is used with an external clock signal, the clock signal
must be available on the OSCIN pin before the reset signal is released.
Table 102. Package selection (OPT7)
Version
Selected package
PKG1
J
LQFP44
LQFP32
1
0
K
14.2.2
Flash ordering information
The following Table 103 serves as a guide for ordering.
Table 103. Flash user programmable device types
Order code(1)
Package
Flash memory (Kbytes)
Temperature range
ST72F32AK1TARE
ST72F32AK1TCRE
ST72F32AK2TARE
ST72F32AK2TCRE
ST72F32AJ1TARE
40°C +85°C
40°C +125°C
40°C +85°C
40°C +125°C
40°C +85°C
40°C +125°C
40°C +85°C
40°C +125°C
4K
LQFP32
8K
4K8
8K
ST72F32AJ1TCRE
ST72F32AJ2TARE
LQFP44
ST72F32AJ2TCRE
1. R = Tape and reel (left blank if tray)
187/201
Device configuration and ordering information
Figure 88. Flash commercial product code structure
ST7232Axx-Auto
DEVICE PINOUT PROG MEM PACKAGE TEMP RANGE
R
E
E = Lead-free (ECOPACK®)
Conditioning options
R = Tape and reel (left blank if tray)
A = -40 to +85°C
C = -40 to +125°C
T = Low profile quad flat pack
1 = 4 Kbytes
2 = 8 Kbytes
K = 32 pins
J = 44 pins
ST72F32A
14.3
ROM device ordering information and transfer of customer
code
Customer code is made up of the ROM/FASTROM contents and the list of the selected
options (if any). The ROM/FASTROM contents are to be sent with the S19 hexadecimal file
generated by the development tool. All unused bytes must be set to FFh. Complete the
appended ST72P32A/ST7232A (3.8 to 5.5V) microcontroller option list on page 191 to
communicate the selected options to STMicroelectronics.
Refer to application note AN1635 for information on the counter listing returned by ST after
code has been transferred.
Table 104: FASTROM factory coded device types on page 189 and Table 105: ROM factory
coded device types on page 190 serve as guides for ordering. The STMicroelectronics
Sales Organization will be pleased to provide detailed information on contractual points.
Caution:
The readout protection binary value is inverted between ROM and Flash products. The
option byte checksum differs between ROM and Flash.
188/201
ST7232Axx-Auto
Device configuration and ordering information
Table 104. FASTROM factory coded device types
Order code(1)
Package
Flash memory (Kbytes)
Temperature range
ST72P32A(K1)TAxxxRE
ST72P32A(K1)TCxxxRE
ST72P32A(K2)TAxxxRE
ST72P32A(K2)TCxxxRE
ST72P32A(J1)TAxxxRE
ST72P32A(J1)TCxxxRE
ST72P32A(J2)TAxxxRE
ST72P32A(J2)TCxxxRE
40°C +85°C
40°C +125°C
40°C +85°C
40°C +125°C
40°C +85°C
40°C +125°C
40°C +85°C
40°C +125°C
4K
LQFP32
8K
4K
8K
LQFP44
1. The two characters in parentheses which represent the pinout and program memory size are for reference
only and are not visible in the final commercial product order code.
‘xxx’ represents the code name defined by STMicroelectronics: It denotes the ROM code, pinout and
program memory size.
R = Tape and Reel (left blank if Tray)
Figure 89. FASTROM commercial product code structure
DEVICE PACKAGE TEMP RANGE xxx R E
E = Lead-free (ECOPACK®)
Conditioning options:
R = Tape and reel (left blank if tray)
Code name (defined by STMicroelectronics)
(denotes ROM code, pinout and program memory size)
A = -40 to +85°C
B = -40 to +105°C
C = -40 to +125°C
T = Low profile quad flat pack
ST72P32A
189/201
Device configuration and ordering information
Table 105. ROM factory coded device types
ST7232Axx-Auto
Temperature range
Order code(1)
Package
Flash memory (Kbytes)
ST7232A(K1)TA/xxxRE
ST7232A(K1)TC/xxxRE
ST7232A(K2)TA/xxxRE
ST7232A(K2)TC/xxxRE
ST7232A(J1)TA/xxxRE
ST7232A(J1)TC/xxxRE
ST7232A(J2)TA/xxxRE
ST7232A(J2)TC/xxxRE
40°C +85°C
40°C +125°C
40°C +85°C
40°C +125°C
40°C +85°C
40°C +125°C
40°C +85°C
40°C +125°C
4K
LQFP32
8K
4K
8K
LQFP44
1. The two characters in parentheses which represent the pinout and program memory size are for reference
only and are not visible in the final commercial product order code.
‘xxx’ represents the code name defined by STMicroelectronics: It denotes the ROM code, pinout and
program memory size.
R = Tape and Reel (left blank if Tray)
Figure 90. ROM commercial product code structure
DEVICE PACKAGE TEMP RANGE
xxx
R E
/
E = Lead-free (ECOPACK®)
Conditioning options:
R = Tape and reel (left blank if tray)
Code name (defined by STMicroelectronics)
(denotes ROM code, pinout and program memory size)
A = -40 to +85°C
B = -40 to +105°C
C = -40 to +125°C
T = Low profile quad flat pack
ST7232A
190/201
ST7232Axx-Auto
Device configuration and ordering information
ST72P32A/ST7232A (3.8 to 5.5V) microcontroller option list
(Last update: September 2007)
Customer:
Address:
.....................................................................
.....................................................................
.....................................................................
.....................................................................
Contact:
Phone No: .....................................................................
Reference/ROM or FASTROM code: ...............................
The FASTROM/ROM code name is assigned by STMicroelectronics.
FASTROM/ROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
----------------------------------------------------------------------------------------------------------------------------------------------
ROM
4K
8K
----------------------------------------------------------------------------------------------------------------------------------------------
LQFP32:
LQFP44:
[ ] ST7232A(K1)T
[ ] ST7232A(J1)T
[ ] ST7232A(K2)T
[ ] ST7232A(J2)T
----------------------------------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------
FASTROM
4K
8K
----------------------------------------------------------------------------------------------------------------------------------------------
LQFP32:
LQFP44:
[ ] ST72P32A(K1)T
[ ] ST72P32A(J1)T
[ ] ST72P32A(K2)T
[ ] ST72P32A(J2)T
----------------------------------------------------------------------------------------------------------------------------------------------
Conditioning (check only one option):
LQFP packaged product
Temperature range:
Special marking:
[ ] Tape and reel
[ ] A (-40°C to +85°C)
[ ] No
[ ] Tray
[ ] B (-40°C to +105°C)
[ ] C (-40°C to +125°C)
[ ] Yes ".........................." (LQFP32 7 char., other pkg. 10 char. max)
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Clock source selection:
[ ] Resonator
[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
(1)
[ ] External clock
[ ] Disabled
(1)(2)
PLL
:
[ ] Enabled
Reset delay:
[ ] 256 cycles
[ ] 4096 cycles
[ ] Hardware activation
[ ] No reset
Watchdog selection:
[ ] Software activation
[ ] Reset
Watchdog reset on halt:
(3)
Readout protection
:
[ ] Disabled
[ ] Enabled
Date
Signature
............................
.............................
1. PLL not supported with external clock source
2. The PLL can be enabled only if the resonator is configured to ‘Medium power: 2~4MHz’
3. The readout protection binary value is inverted between ROM and Flash products. The option byte
checksum differs between ROM and Flash.
191/201
Device configuration and ordering information
ST7232Axx-Auto
14.4
Development tools
14.4.1
Introduction
Development tools for the ST7 microcontrollers include a complete range of hardware
systems and software tools from STMicroelectronics and third-party tool suppliers. The
range of tools includes solutions to help you evaluate microcontroller peripherals, develop
and debug your application, and program your microcontrollers.
14.4.2
14.4.3
Evaluation tools and starter kits
ST offers complete, affordable starter kits and full-featured evaluation boards that allow you
to evaluate microcontroller features and quickly start developing ST7 applications. Starter
kits are complete, affordable hardware/software tool packages that include features and
samples to help you quickly start developing your application. ST evaluation boards are
open-design, embedded systems, which are developed and documented to serve as
references for your application design. They include sample application software to help you
demonstrate, learn about and implement your ST7’s features.
Development and debugging tools
Application development for ST7 is supported by fully optimizing C compilers and the ST7
assembler-linker toolchain, which are all seamlessly integrated in the ST7 integrated
development environments in order to facilitate the debugging and fine-tuning of your
application. The cosmic C compiler is available in a free version that outputs up to 16 Kbytes
of code.
The range of hardware tools includes cost effective ST7-DVP3 series emulators. These
tools are supported by the ST7 Toolset from STMicroelectronics, which includes the STVD7
integrated development environment (IDE) with high-level language debugger, editor,
project manager and integrated programming interface.
14.4.4
Programming tools
During the development cycle, the ST7-DVP3 and ST7-EMU3 series emulators and the
RLink provide in-circuit programming capability for programming the Flash microcontroller
on your application board.
ST also provides dedicated a low-cost dedicated in-circuit programmer, the ST7-STICK, as
well as ST7 socket boards which provide all the sockets required for programming any of the
devices in a specific ST7 subfamily on a platform that can be used with any tool with in-
circuit programming capability for ST7.
For production programming of ST7 devices, ST’s third-party tool partners also provide a
complete range of gang and automated programming solutions, which are ready to integrate
into your production environment.
For additional ordering codes for spare parts, accessories and tools available for the ST7
(including from third party manufacturers), refer to the online product selector at
www.st.com/mcu.
192/201
ST7232Axx-Auto
Device configuration and ordering information
Table 106. STMicroelectronics development tools
Emulation
Programming
Supported
products
ST7 DVP3 series
Emulator Connection kit
ST7 EMU3 series
ICC socket
board
Active probe
Emulator
and TEB
ST7232AJ,
ST72F32AJ
ST7MDT20-
DVP3
ST7MDT20-
T44/DVP
ST7MDT20
J-EMU3
ST7MDT20
J-TEB
ST7SB20
J/xx(1)
ST7232AK,
ST72F32AK
ST7MDT20-
DVP3
ST7MDT20-
T32/DVP
1. Add suffix /EU, /UK, /US for the power supply of your region.
14.4.5
Socket and emulator adapter information
For information on the type of socket that is supplied with the emulator, refer to the
suggested list of sockets in Table 107.
Note:
Before designing the board layout, it is recommended to check the overall dimensions of the
socket as they may be greater than the dimensions of the device.
For footprint and other mechanical information about these sockets and adapters, refer to
the manufacturer’s datasheet (www.ironwoodelectronics.com for LQFP32 7 x 7).
Table 107. Suggested list of socket types
Socket
Emulator adapter
(supplied with ST7MDT20J-EMU3)
Device
(supplied with ST7MDT20J-EMU3)
LQFP32 7 X 7
IRONWOOD SF-QFE32SA-L-01
IRONWOOD SK-UGA06/32A-01
YAMAICHI ICP-044-5
LQFP44 10 X10 YAMAICHI IC149-044-*52-*5
14.5
ST7 application notes
For all revelant application notes, refer to www.st.com.
193/201
Known limitations
ST7232Axx-Auto
15
Known limitations
15.1
All Flash and ROM devices
15.1.1
Safe connection of OSC1/OSC2 pins
The OSC1 and/or OSC2 pins must not be left unconnected otherwise the ST7 main
oscillator may start and, in this configuration, could generate an f clock frequency in
OSC
excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state.
Refer to Section 6.4: Multi-oscillator (MO) on page 37.
15.1.2
External interrupt missed
To avoid any risk of generating a parasitic interrupt, the edge detector is automatically
disabled for one clock cycle during an access to either DDR and OR. Any input signal edge
during this period is not detected and does not generate an interrupt.
This case can typically occur if the application refreshes the port configuration registers at
intervals during runtime.
Workaround
The workaround is based on software checking the level on the interrupt pin before and after
writing to the PxOR or PxDDR registers. If there is a level change (depending on the
sensitivity programmed for this pin) the interrupt routine is invoked using the call instruction
with three extra PUSH instructions before executing the interrupt routine (this is to make the
call compatible with the IRET instruction at the end of the interrupt service routine).
But detection of the level change does not make sure that edge occurs during the critical
one cycle duration and the interrupt has been missed. This may lead to occurrence of same
interrupt twice (one hardware and another with software call).
To avoid this, a semaphore is set to ‘1’ before checking the level change. The semaphore is
changed to level '0' inside the interrupt routine. When a level change is detected, the
semaphore status is checked and if it is ‘1’ this means that the last interrupt has been
missed. In this case, the interrupt routine is invoked with the call instruction.
There is another possible case that is, if writing to PxOR or PxDDR is done with global
interrupts disabled (interrupt mask bit set). In this case, the semaphore is changed to ‘1’
when the level change is detected. Detecting a missed interrupt is done after the global
interrupts are enabled (interrupt mask bit reset) and by checking the status of the
semaphore. If it is ‘1’ this means that the last interrupt was missed and the interrupt routine
is invoked with the call instruction.
To implement the workaround, the following software sequence is to be followed for writing
into the PxOR/PxDDR registers. The example is for Port PF1 with falling edge interrupt
sensitivity. The software sequence is given for both cases (global interrupt
disabled/enabled).
194/201
ST7232Axx-Auto
Case 1: Writing to PxOR or PxDDR with global interrupts enabled:
Known limitations
LD A,#01
LD sema,A; set the semaphore to '1'
LD A,PFDR
AND A,#02
LD X,A; store the level before writing to PxOR/PxDDR
LD A,#$90
LD PFDDR,A ; Write to PFDDR
LD A,#$ff
LD PFOR,A ; Write to PFOR
LD A,PFDR
AND A,#02
LD Y,A; store the level after writing to PxOR/PxDDR
LD A,X; check for falling edge
cp A,#02
jrne OUT
TNZ Y
jrne OUT
LD A,sema ; check the semaphore status if edge is detected
CP A,#01
jrne OUT
call call_routine ; call the interrupt routine
OUT:LD A,#00
LD sema,A
.call_routine ; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt ; entry to interrupt routine
LD A,#00
LD sema,A
IRET
Case 2: Writing to PxOR or PxDDR with global interrupts disabled:
SIM ; set the interrupt mask
LD A,PFDR
AND A,#$02
LD X,A ; store the level before writing to PxOR/PxDDR
LD A,#$90
LD PFDDR,A ; Write into PFDDR
LD A,#$ff
LD PFOR,A ; Write to PFOR
LD A,PFDR
AND A,#$02
LD Y,A ; store the level after writing to PxOR/PxDDR
LD A,X ; check for falling edge
cp A,#$02
jrne OUT
TNZ Y
jrne OUT
LD A,#$01
LD sema,A ; set the semaphore to '1' if edge is detected
195/201
Known limitations
RIM ; reset the interrupt mask
ST7232Axx-Auto
LD A,sema ; check the semaphore status
CP A,#$01
jrne OUT
call call_routine ; call the interrupt routine
RIM
OUT:RIM
JP while_loop
.call_routine ; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt ; entry to interrupt routine
LD A,#$00
LD sema,A
IRET
15.1.3
Unexpected reset fetch
If an interrupt request occurs while a ‘POP CC’ instruction is executed, the interrupt
controller does not recognise the source of the interrupt and, by default, passes the reset
vector address to the CPU.
Workaround
To solve this issue, a ‘POP CC’ instruction must always be preceded by a ‘SIM’ instruction.
15.1.4
Clearing active interrupts outside interrupt routine
When an active interrupt request occurs at the same time as the related flag is being
cleared, an unwanted reset may occur.
Note:
Clearing the related interrupt mask does not generate an unwanted reset.
Concurrent interrupt context
The symptom does not occur when the interrupts are handled normally, i.e. when:
●
●
●
The interrupt flag is cleared within its own interrupt routine
The interrupt flag is cleared within any interrupt routine
The interrupt flag is cleared in any part of the code while this interrupt is disabled
If these conditions are not met, the symptom can be avoided by implementing the following
sequence:
Perform SIM and RIM operation before and after resetting an active interrupt request.
Example:
SIM
Reset interrupt flag
RIM
196/201
ST7232Axx-Auto
Known limitations
Nested interrupt context
The symptom does not occur when the interrupts are handled normally, i.e. when:
●
The interrupt flag is cleared within its own interrupt routine
●
The interrupt flag is cleared within any interrupt routine with higher or identical priority
leve
●
The interrupt flag is cleared in any part of the code while this interrupt is disabled
If these conditions are not met, the symptom can be avoided by implementing the following
sequence:
PUSH CC
SIM
Reset interrupt flag
POP CC
15.1.5
15.1.6
16-bit timer PWM mode
In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R
register (OC1HR, OC1LR). It leads to either full or no PWM during a period, depending on
the OLVL1 and OLVL2 settings.
TIMD set simultaneously with OC interrupt
Description
If the 16-bit timer is disabled at the same time as the output compare event occurs, then the
output compare flag gets locked and cannot be cleared before the timer is enabled again.
Impact on the application
If output compare interrupt is enabled, then the output compare flag cannot be cleared in the
timer interrupt routine. Consequently the interrupt service routine is called repeatedly and
the application gets stuck which causes the watchdog reset if enabled by the application.
Workaround
Disable the timer interrupt before disabling the timer. While enabling, first enable the timer,
then the timer interrupts.
Perform the following to disable the timer:
●
TACR1 or TBCR1 = 0x00h; // Disable the compare interrupt
TACSR | or TBCSR | = 0x40; // Disable the timer
●
Perform the following to enable the timer again:
●
TACSR & or TBCSR & = ~0x40; // Enable the timer
●
TACR1 or TBCR1 = 0x40; // Enable the compare interrup
197/201
Known limitations
ST7232Axx-Auto
15.1.7
SCI wrong break duration
Description
A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.
In some cases, the break character may have a longer duration than expected:
- 20 bits instead of 10 bits if M = 0
- 22 bits instead of 11 bits if M = 1.
In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.
This may lead to generate one break more than expected.
Occurrence
The occurrence of the problem is random and proportional to the baudrate. With a transmit
frequency of 19200 baud (f
occurrence is around 1%.
= 8MHz and SCIBRR = 0xC9), the wrong break duration
CPU
Workaround
If this wrong duration is not compliant with the communication protocol in the application,
software can request that an idle line be generated before the break character. In this case,
the break duration is always correct assuming the application is not doing anything between
the idle and the break. This can be ensured by temporarily disabling interrupts.
The exact sequence is:
●
●
●
●
Disable interrupts
Reset and set TE (IDLE request)
Set and reset SBK (break request)
Re-enable interrupts
15.1.8
39-pulse ICC entry mode
For Flash devices, ICC mode entry using ST7 application clock (39 pulses) is not supported.
External clock mode must be used (36 pulses). Refer to the ST7 Flash Programming
Reference Manual.
198/201
ST7232Axx-Auto
Known limitations
15.2
ROM devices only
15.2.1
I/O port A and F configuration
When using an external quartz crystal or ceramic resonator, a few f
clock periods may
OSC2
be lost when the signal pattern in Table 108 occurs . This is because this pattern causes the
device to enter test mode and return to user mode after a few clock periods. User program
execution and I/O status are not changed, only a few clock cycles are lost.
This happens with either one of the following configurations (see also Table 108):
PA3 = 0, PF4 = 1, PF1 = 0 while PLL option is disabled and PF0 is toggling.
PA3 = 0, PF4 = 1, PF1 = 0, PF0 = 1 while PLL option is enabled.
Table 108. Port A and F configuration
PLL
PA3
PF4
PF1
PF0
Clock disturbance
Max. 2 clock cycles lost at each rising or
falling edge of PF0
OFF
ON
0
0
1
1
0
0
Toggling
1
Max. 1 clock cycle lost out of every 16
As a consequence, for cycle-accurate operations, these configurations are prohibited in
either input or output mode.
Workaround
To avoid this occurring, it is recommended to connect one of these pins to GND (PF4 or
PF0) or V (PA3 or PF1).
DD
15.2.2
External clock source with PLL
PLL is not supported with external clock source.
199/201
Revision history
ST7232Axx-Auto
16
Revision history
Table 109. Document revision history
Date
Revision
Changes
28-Jan-2008
1
Initial release
200/201
ST7232Axx-Auto
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2008 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
201/201
相关型号：
ST7232A(K2)TC/XXXRE
8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP32, 7 X 7 MM, ROHS COMPLIANT, LQFP-32
STMICROELECTR
ST7232AJ1B1
8-BIT MICROCONTROLLER WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
STMICROELECTR
ST7232AJ1B5
8-BIT MICROCONTROLLER WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
STMICROELECTR
ST7232AJ1B6A
8-BIT MICROCONTROLLER WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
STMICROELECTR
ST7232AJ1BB
8-BIT MICROCONTROLLER WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
STMICROELECTR
ST7232AJ1BC
8-BIT MICROCONTROLLER WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
STMICROELECTR
ST7232AJ1BC/XXX
8-BIT, MROM, 8MHz, MICROCONTROLLER, PDIP42, 0.600 INCH, SHRINK, PLASTIC, DIP-42
STMICROELECTR
ST7232AJ1T1
8-BIT MICROCONTROLLER WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
STMICROELECTR
ST7232AJ1T5
8-BIT MICROCONTROLLER WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
STMICROELECTR
ST7232AJ1T6A
8-BIT MICROCONTROLLER WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
STMICROELECTR
ST7232AJ1TB
8-BIT MICROCONTROLLER WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
STMICROELECTR
ST7232AJ1TC
8-BIT MICROCONTROLLER WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明