M95640-WDW6TP_技术文档

M95640

M95320

64Kbit and 32Kbit Serial SPI Bus EEPROM

With High Speed Clock

FEATURES SUMMARY

■ Compatible with SPI Bus Serial Interface

Figure 1. Packages

(Positive Clock SPI Modes)

■ Single Supply Voltage:

– 4.5 to 5.5V for M95xxx

– 2.5 to 5.5V for M95xxx-W

– 1.8 to 5.5V for M95xxx-R

8

■ 10MHz, 5MHz or 2MHz clock rate (depending

on ordering options)

1

■ 5ms or 10ms Write Time (depending on

ordering options)

PDIP8 (BN)

0.25 mm frame

■ Status Register

■ Hardware Protection of the Status Register

■ BYTE and PAGE WRITE (up to 32 Bytes)

■ Self-Timed Programming Cycle

■ Adjustable Size Read-Only EEPROM Area

■ Enhanced ESD Protection

8

1

■ More than 100,000 or 1 million Erase/Write

SO8 (MN)

150 mil width

Cycles (depending on ordering options)

■ More than 40 Year Data Retention

TSSOP8 (DW)

169 mil width

TSSOP14 (DL)

169 mil width

November 2003

1/39

M95640, M95320

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. DIP and SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. TSSOP14 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

CONNECTING TO THE SPI BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Bus Master and Memory Devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power On Reset: VCC Lock-Out Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Active Power and Stand-by Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Protection and Protocol Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. Write-Protected Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 8. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2/39

M95640, M95320

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 9. Write Enable (WREN) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 10. Write Disable (WRDI) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 11. Read Status Register (RDSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 12. Write Status Register (WRSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6. Address Range Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 13. Read from Memory Array (READ) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 14. Byte Write (WRITE) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Write to Memory Array (WRITE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 15. Page Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

POWER-UP AND DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Power-up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 8. Operating Conditions (M95xxx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 9. Operating Conditions (M95xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10. Operating Conditions (M95xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 16. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. DC Characteristics (M95xxx, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 14. DC Characteristics (M95xxx, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 15. DC Characteristics (M95xxx-W, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 16. DC Characteristics (M95xxx-W, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17. DC Characteristics (M95xxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 18. AC Characteristics (M95xxx, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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M95640, M95320

Table 19. AC Characteristics (M95xxx, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 20. AC Characteristics (M95xxx-W, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 21. AC Characteristics (M95xxx-W, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 22. AC Characteristics (M95xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 17. Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 18. Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 19. Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 20. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 33

Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data. . . . . . . . . . 33

Figure 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline. . . . 34

Table 24. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data

34

Figure 22. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 35

Table 25. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 35

Figure 23. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . 36

Table 26. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . 36

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 28. How to Identify Current and Forthcoming Products by the Process Identification Letter 37

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 38

4/39

M95640, M95320

SUMMARY DESCRIPTION

These electrically erasable programmable memo-

ry (EEPROM) devices are accessed by a high

speed SPI-compatible bus. The memory array is

organized as 8192 x 8 bit (M95640), and 4096 x 8

bit (M95320).

The device is accessed by a simple serial interface

that is SPI-compatible. The bus signals are C, D

and Q, as shown in Table 1 and Figure 2.

Figure 3. DIP and SO Connections

M95xxx

S

Q

1

8

V

CC

HOLD

2

3

4

7

The device is selected when Chip Select (S) is tak-

en Low. Communications with the device can be

interrupted using Hold (HOLD).

W

6

5

C

D

V

SS

AI01790D

Figure 2. Logic Diagram

V

CC

Note: 1. See page 33 (onwards) for package dimensions, and how

to identify pin-1.

Figure 4. TSSOP14 Connections

D

C

S

Q

M95xxx

S

Q

1

2

3

4

5

6

7

14

V

CC

W

13 HOLD

12 NC

11 NC

10 NC

NC

W

HOLD

9

8

C

D

V

SS

V

SS

AI01789C

AI02346C

Note: 1. See page 33 (onwards) for package dimensions, and how

to identify pin-1.

2. NC = Not Connected

Table 1. Signal Names

C

Serial Clock

Serial Data Input

Serial Data Output

Chip Select

Write Protect

Hold

D

Q

S

W

HOLD

V

Supply Voltage

Ground

CC

V

SS

5/39

M95640, M95320

SIGNAL DESCRIPTION

During all operations, V must be held stable and

(Q) is at high impedance. Unless an internal Write

cycle is in progress, the device will be in the Stand-

by mode. Driving Chip Select (S) Low enables the

device, placing it in the active power mode.

After Power-up, a falling edge on Chip Select (S)

is required prior to the start of any instruction.

CC

within the specified valid range: V (min) to

CC

V

(max).

CC

All of the input and output signals must be held

High or Low (according to voltages of V , V , V

IH OH IL

or V , as specified in Tables 13 to 17). These sig-

OL

nals are described next.

Hold (HOLD). The Hold (HOLD) signal is used to

pause any serial communications with the device

without deselecting the device.

During the Hold condition, the Serial Data Output

(Q) is high impedance, and Serial Data Input (D)

and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be se-

lected, with Chip Select (S) driven Low.

Write Protect (W). The main purpose of this in-

put signal is to freeze the size of the area of mem-

ory that is protected against Write instructions (as

specified by the values in the BP1 and BP0 bits of

the Status Register).

Serial Data Output (Q). This output signal is

used to transfer data serially out of the device.

Data is shifted out on the falling edge of Serial

Clock (C).

Serial Data Input (D). This input signal is used to

transfer data serially into the device. It receives in-

structions, addresses, and the data to be written.

Values are latched on the rising edge of Serial

Clock (C).

Serial Clock (C). This input signal provides the

timing of the serial interface. Instructions, address-

es, or data present at Serial Data Input (D) are

latched on the rising edge of Serial Clock (C). Data

on Serial Data Output (Q) changes after the falling

edge of Serial Clock (C).

This pin must be driven either High or Low, and

must be stable during all write operations.

Chip Select (S). When this input signal is High,

the device is deselected and Serial Data Output

6/39

M95640, M95320

CONNECTING TO THE SPI BUS

These devices are fully compatible with the SPI

protocol.

All instructions, addresses and input data bytes

are shifted in to the device, most significant bit

first. The Serial Data Input (D) is sampled on the

first rising edge of the Serial Clock (C) after Chip

Select (S) goes Low.

(Q) is latched on the first falling edge of the Serial

Clock (C) after the instruction (such as the Read

from Memory Array and Read Status Register in-

structions) have been clocked into the device.

Figure 5 shows three devices, connected to an

MCU, on a SPI bus. Only one device is selected at

a time, so only one device drives the Serial Data

Output (Q) line at a time, all the others being high

impedance.

All output data bytes are shifted out of the device,

most significant bit first. The Serial Data Output

Figure 5. Bus Master and Memory Devices on the SPI Bus

SDO

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

SDI

SCK

C

Q

D

C

Q

D

C Q D

Bus Master

(ST6, ST7, ST9,

ST10, Others)

SPI Memory

Device

SPI Memory

Device

SPI Memory

Device

CS3 CS2 CS1

S

W

HOLD

W

HOLD

W

AI03746D

Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

SPI Modes

is available from the falling edge of Serial Clock

(C).

The difference between the two modes, as shown

in Figure 6, is the clock polarity when the bus mas-

ter is in Stand-by mode and not transferring data:

– C remains at 0 for (CPOL=0, CPHA=0)

– C remains at 1 for (CPOL=1, CPHA=1)

These devices can be driven by a microcontroller

with its SPI peripheral running in either of the two

following modes:

– CPOL=0, CPHA=0

– CPOL=1, CPHA=1

For these two modes, input data is latched in on

the rising edge of Serial Clock (C), and output data

7/39

M95640, M95320

Figure 6. SPI Modes Supported

CPOL CPHA

C

0

1

0

1

D

MSB

Q

MSB

AI01438B

8/39

M95640, M95320

OPERATING FEATURES

Power-up

Active Power and Stand-by Power Modes

When the power supply is turned on, V

rises

When Chip Select (S) is Low, the device is en-

abled, and in the Active Power mode. The device

CC

from V to V

.

SS

CC

consumes I , as specified in Tables 13 to 17.

CC

During this time, the Chip Select (S) must be al-

lowed to follow the V voltage. It must not be al-

When Chip Select (S) is High, the device is dis-

abled. If an Erase/Write cycle is not currently in

progress, the device then goes in to the Stand-by

Power mode, and the device consumption drops

CC

lowed to float, but should be connected to V via

CC

a suitable pull-up resistor.

As a built in safety feature, Chip Select (S) is edge

sensitive as well as level sensitive. After Power-

up, the device does not become selected until a

falling edge has first been detected on Chip Select

(S). This ensures that Chip Select (S) must have

been High, prior to going Low to start the first op-

eration.

to I

.

CC1

Hold Condition

The Hold (HOLD) signal is used to pause any se-

rial communications with the device without reset-

ting the clocking sequence.

During the Hold condition, the Serial Data Output

(Q) is high impedance, and Serial Data Input (D)

and Serial Clock (C) are Don’t Care.

Power On Reset: V Lock-Out Write Protect

CC

In order to prevent data corruption and inadvertent

Write operations during Power-up, a Power On

Reset (POR) circuit is included. The internal reset

To enter the Hold condition, the device must be

selected, with Chip Select (S) Low.

is held active until V

has reached the POR

CC

Normally, the device is kept selected, for the whole

duration of the Hold condition. Deselecting the de-

vice while it is in the Hold condition, has the effect

of resetting the state of the device, and this mech-

anism can be used if it is required to reset any pro-

cesses that had been in progress.

The Hold condition starts when the Hold (HOLD)

signal is driven Low at the same time as Serial

Clock (C) already being Low (as shown in Figure

7).

threshold value, and all operations are disabled –

the device will not respond to any command. In the

same way, when V

drops from the operating

CC

voltage, below the POR threshold value, all oper-

ations are disabled and the device will not respond

to any command.

A stable and valid V must be applied before ap-

CC

plying any logic signal.

Power-down

At Power-down, the device must be deselected.

Chip Select (S) should be allowed to follow the

The Hold condition ends when the Hold (HOLD)

signal is driven High at the same time as Serial

Clock (C) already being Low.

voltage applied on V

.

CC

Figure 7 also shows what happens if the rising and

falling edges are not timed to coincide with Serial

Clock (C) being Low.

Figure 7. Hold Condition Activation

C

HOLD

Hold

Condition

AI02029D

9/39

M95640, M95320

Status Register

Figure 8 shows the position of the Status Register

in the control logic of the device. The Status Reg-

ister contains a number of status and control bits

that can be read or set (as appropriate) by specific

instructions.

■ Write and Write Status Register instructions are

checked that they consist of a number of clock

pulses that is a multiple of eight, before they are

accepted for execution.

■ All instructions that modify data must be

preceded by a Write Enable (WREN) instruction

to set the Write Enable Latch (WEL) bit . This bit

is returned to its reset state by the following

events:

WIP bit. The Write In Progress (WIP) bit indicates

whether the memory is busy with a Write or Write

Status Register cycle.

WEL bit. The Write Enable Latch (WEL) bit indi-

cates the status of the internal Write Enable Latch.

– Power-up

BP1, BP0 bits. The Block Protect (BP1, BP0) bits

are non-volatile. They define the size of the area to

be software protected against Write instructions.

– Write Disable (WRDI) instruction completion

– Write Status Register (WRSR) instruction

completion

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware

Protected mode. In this mode, the non-volatile bits

of the Status Register (SRWD, BP1, BP0) become

read-only bits.

– Write (WRITE) instruction completion

■ The Block Protect (BP1, BP0) bits allow part of

the memory to be configured as read-only. This

is the Software Protected Mode (SPM).

■ The Write Protect (W) signal allows the Block

Protect (BP1, BP0) bits to be protected. This is

the Hardware Protected Mode (HPM).

Table 2. Status Register Format

For any instruction to be accepted, and executed,

Chip Select (S) must be driven High after the rising

edge of Serial Clock (C) for the last bit of the in-

struction, and before the next rising edge of Serial

Clock (C).

b7

b0

SRWD

0

BP1 BP0 WEL WIP

Two points need to be noted in the previous sen-

tence:

– The ‘last bit of the instruction’ can be the eighth

bit of the instruction code, or the eighth bit of a

data byte, depending on the instruction (except

for Read Status Register (RDSR) and Read

(READ) instructions).

Status Register Write Protect

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

– The ‘next rising edge of Serial Clock (C)’ might

(or might not) be the next bus transaction for

some other device on the SPI bus.

Data Protection and Protocol Control

Non-volatile memory devices can be used in envi-

ronments that are particularly noisy, and within ap-

plications that could experience problems if

memory bytes are corrupted. Consequently, the

device features the following data protection

mechanisms:

Table 3. Write-Protected Block Size

Status Register Bits

Protected Block

Array Addresses Protected

BP1

BP0

M95640

none

M95320

none

0

1

0

1

0

1

none

Upper quarter

Upper half

1800h - 1FFFh

1000h - 1FFFh

0000h - 1FFFh

0C00h - 0FFFh

0800h - 0FFFh

0000h - 0FFFh

Whole memory

10/39

M95640, M95320

MEMORY ORGANIZATION

The memory is organized as shown in Figure 8.

Figure 8. Block Diagram

HOLD

High Voltage

Generator

W

S

Control Logic

C

D

Q

I/O Shift Register

Address Register

and Counter

Data

Register

Status

Register

Size of the

Read only

EEPROM

area

1 Page

X Decoder

AI01272C

11/39

M95640, M95320

INSTRUCTIONS

Each instruction starts with a single-byte code, as

summarized in Table 4.

If an invalid instruction is sent (one not contained

in Table 4), the device automatically deselects it-

self.

Table 4. Instruction Set

Instruc

Instruction

Format

Description

tion

WREN Write Enable

0000 0110

0000 0100

0000 0101

0000 0001

0000 0011

0000 0010

WRDI

RDSR

Write Disable

Read Status Register

WRSR Write Status Register

READ Read from Memory Array

WRITE Write to Memory Array

Figure 9. Write Enable (WREN) Sequence

S

0

1

2

3

4

5

6

7

C

D

Q

Instruction

High Impedance

AI02281E

Write Enable (WREN)

As shown in Figure 9, to send this instruction to the

device, Chip Select (S) is driven Low, and the bits

of the instruction byte are shifted in, on Serial Data

Input (D). The device then enters a wait state. It

waits for a the device to be deselected, by Chip

Select (S) being driven High.

The Write Enable Latch (WEL) bit must be set pri-

or to each WRITE and WRSR instruction. The only

way to do this is to send a Write Enable instruction

to the device.

12/39

M95640, M95320

Figure 10. Write Disable (WRDI) Sequence

S

0

1

2

3

4

5

6

7

C

Instruction

D

High Impedance

Q

AI03750D

Write Disable (WRDI)

The device then enters a wait state. It waits for a

the device to be deselected, by Chip Select (S) be-

ing driven High.

The Write Enable Latch (WEL) bit, in fact, be-

comes reset by any of the following events:

One way of resetting the Write Enable Latch

(WEL) bit is to send a Write Disable instruction to

the device.

As shown in Figure 10, to send this instruction to

the device, Chip Select (S) is driven Low, and the

bits of the instruction byte are shifted in, on Serial

Data Input (D).

– Power-up

– WRDI instruction execution

– WRSR instruction completion

– WRITE instruction completion.

13/39

M95640, M95320

Figure 11. Read Status Register (RDSR) Sequence

S

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

C

D

Instruction

Status Register Out

High Impedance

Q

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

AI02031E

Read Status Register (RDSR)

BP1, BP0 bits. The Block Protect (BP1, BP0) bits

are non-volatile. They define the size of the area to

be software protected against Write instructions.

These bits are written with the Write Status Regis-

ter (WRSR) instruction. When one or both of the

Block Protect (BP1, BP0) bits is set to 1, the rele-

vant memory area (as defined in Table 2) be-

comes protected against Write (WRITE)

instructions. The Block Protect (BP1, BP0) bits

can be written provided that the Hardware Protect-

ed mode has not been set.

The Read Status Register (RDSR) instruction al-

lows the Status Register to be read. The Status

Register may be read at any time, even while a

Write or Write Status Register cycle is in progress.

When one of these cycles is in progress, it is rec-

ommended to check the Write In Progress (WIP)

bit before sending a new instruction to the device.

It is also possible to read the Status Register con-

tinuously, as shown in Figure 11.

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware

Protected mode (when the Status Register Write

Disable (SRWD) bit is set to 1, and Write Protect

(W) is driven Low). In this mode, the non-volatile

bits of the Status Register (SRWD, BP1, BP0) be-

come read-only bits and the Write Status Register

(WRSR) instruction is no longer accepted for exe-

cution.

The status and control bits of the Status Register

are as follows:

WIP bit. The Write In Progress (WIP) bit indicates

whether the memory is busy with a Write or Write

Status Register cycle. When set to 1, such a cycle

is in progress, when reset to 0 no such cycle is in

progress.

WEL bit. The Write Enable Latch (WEL) bit indi-

cates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is

set, when set to 0 the internal Write Enable Latch

is reset and no Write or Write Status Register in-

struction is accepted.

14/39

M95640, M95320

Figure 12. Write Status Register (WRSR) Sequence

S

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

C

Instruction

Status

Register In

7

6

5

4

3

2

0

1

D

Q

High Impedance

MSB

AI02282D

Write Status Register (WRSR)

(WIP) bit. The Write In Progress (WIP) bit is 1 dur-

ing the self-timed Write Status Register cycle, and

is 0 when it is completed. When the cycle is com-

pleted, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction al-

lows the user to change the values of the Block

Protect (BP1, BP0) bits, to define the size of the

area that is to be treated as read-only, as defined

in Table 2.

The Write Status Register (WRSR) instruction also

allows the user to set or reset the Status Register

Write Disable (SRWD) bit in accordance with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware

Protected Mode (HPM). The Write Status Register

(WRSR) instruction is not executed once the Hard-

ware Protected Mode (HPM) is entered.

The contents of the Status Register Write Disable

(SRWD) and Block Protect (BP1, BP0) bits are fro-

zen at their current values from just before the

start of the execution of Write Status Register

(WRSR) instruction. The new, updated, values

take effect at the moment of completion of the ex-

ecution of Write Status Register (WRSR) instruc-

tion.

The Write Status Register (WRSR) instruction al-

lows new values to be written to the Status Regis-

ter. Before it can be accepted, a Write Enable

(WREN) instruction must previously have been ex-

ecuted. After the Write Enable (WREN) instruction

has been decoded and executed, the device sets

the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is

entered by driving Chip Select (S) Low, followed

by the instruction code and the data byte on Serial

Data Input (D).

The instruction sequence is shown in Figure 12.

The Write Status Register (WRSR) instruction has

no effect on b6, b5, b4, b1 and b0 of the Status

Register. b6, b5 and b4 are always read as 0.

Chip Select (S) must be driven High after the rising

edge of Serial Clock (C) that latches in the eighth

bit of the data byte, and before the next rising edge

of Serial Clock (C). Otherwise, the Write Status

Register (WRSR) instruction is not executed. As

soon as Chip Select (S) is driven High, the self-

timed Write Status Register cycle (whose duration

is t ) is initiated. While the Write Status Register

W

cycle is in progress, the Status Register may still

be read to check the value of the Write In Progress

15/39

M95640, M95320

Table 5. Protection Modes

Memory Content

W

Signal

SRWD

Bit

Write Protection of the

Status Register

Mode

1

Protected Area

Unprotected Area

1

0

Status Register is

Writable (if the WREN

Software instruction has set the

Protected WEL bit)

Ready to accept Write

instructions

Write Protected

(SPM)

The values in the BP1

and BP0 bits can be

changed

1

0

1

Status Register is

Hardware Hardware write protected

Protected The values in the BP1

Ready to accept Write

instructions

Write Protected

(HPM)

and BP0 bits cannot be

changed

Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 3.

The protection features of the device are summa-

rized in Table 3.

Block Protect (BP1, BP0) bits of the Status Reg-

ister, are also hardware protected against data

modification.

When the Status Register Write Disable (SRWD)

bit of the Status Register is 0 (its initial delivery

state), it is possible to write to the Status Register

provided that the Write Enable Latch (WEL) bit has

previously been set by a Write Enable (WREN) in-

struction, regardless of the whether Write Protect

(W) is driven High or Low.

When the Status Register Write Disable (SRWD)

bit of the Status Register is set to 1, two cases

need to be considered, depending on the state of

Write Protect (W):

Regardless of the order of the two events, the

Hardware Protected Mode (HPM) can be entered:

– by setting the Status Register Write Disable

(SRWD) bit after driving Write Protect (W) Low

– or by driving Write Protect (W) Low after setting

the Status Register Write Disable (SRWD) bit.

The only way to exit the Hardware Protected Mode

(HPM) once entered is to pull Write Protect (W)

High.

If Write Protect (W) is permanently tied High, the

Hardware Protected Mode (HPM) can never be

activated, and only the Software Protected Mode

(SPM), using the Block Protect (BP1, BP0) bits of

the Status Register, can be used.

– If Write Protect (W) is driven High, it is possible

to write to the Status Register provided that the

Write Enable Latch (WEL) bit has previously

been set by a Write Enable (WREN) instruction.

– If Write Protect (W) is driven Low, it is not pos-

sible to write to the Status Register even if the

Write Enable Latch (WEL) bit has previously

been set by a Write Enable (WREN) instruction.

(Attempts to write to the Status Register are re-

jected, and are not accepted for execution). As

a consequence, all the data bytes in the memo-

ry area that are software protected (SPM) by the

Table 6. Address Range Bits

Device

M95640

M95320

Address Bits

A12-A0

A11-A0

Note: 1. b15 to b13 are Don’t Care on the M95640.

b15 to b12 are Don’t Care on the M95320.

16/39

M95640, M95320

Figure 13. Read from Memory Array (READ) Sequence

S

0

1

2

3

4

5

6

7

8

9

10

20 21 22 23 24 25 26 27 28 29 30 31

C

Instruction

16-Bit Address

15 14 13

MSB

3

2

1

0

D

Q

Data Out 1

Data Out 2

High Impedance

2

7

6

5

4

3

1

7

0

MSB

AI01793D

Note: Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.

Read from Memory Array (READ)

When the highest address is reached, the address

counter rolls over to zero, allowing the Read cycle

to be continued indefinitely. The whole memory

can, therefore, be read with a single READ instruc-

tion.

The Read cycle is terminated by driving Chip Se-

lect (S) High. The rising edge of the Chip Select

(S) signal can occur at any time during the cycle.

As shown in Figure 13, to send this instruction to

the device, Chip Select (S) is first driven Low. The

bits of the instruction byte and address bytes are

then shifted in, on Serial Data Input (D). The ad-

dress is loaded into an internal address register,

and the byte of data at that address is shifted out,

on Serial Data Output (Q).

If Chip Select (S) continues to be driven Low, the

internal address register is automatically incre-

mented, and the byte of data at the new address is

shifted out.

The first byte addressed can be any byte within

any page.

The instruction is not accepted, and is not execut-

ed, if a Write cycle is currently in progress.

17/39

M95640, M95320

Figure 14. Byte Write (WRITE) Sequence

S

0

1

2

3

4

5

6

7

8

9

10

20 21 22 23 24 25 26 27 28 29 30 31

C

Instruction

16-Bit Address

Data Byte

15 14 13

3

2

1

0

7

6

5

4

3

2

0

1

D

Q

High Impedance

AI01795D

Note: Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.

Write to Memory Array (WRITE)

Each time a new data byte is shifted in, the least

significant bits of the internal address counter are

incremented. If the number of data bytes sent to

the device exceeds the page boundary, the inter-

nal address counter rolls over to the beginning of

the page, and the previous data there are overwrit-

ten with the incoming data. (The page size of

these devices is 32 bytes).

The instruction is not accepted, and is not execut-

ed, under the following conditions:

– if the Write Enable Latch (WEL) bit has not been

set to 1 (by executing a Write Enable instruction

just before)

As shown in Figure 14, to send this instruction to

the device, Chip Select (S) is first driven Low. The

bits of the instruction byte, address byte, and at

least one data byte are then shifted in, on Serial

Data Input (D).

The instruction is terminated by driving Chip Se-

lect (S) High at a byte boundary of the input data.

In the case of Figure 14, this occurs after the

eighth bit of the data byte has been latched in, in-

dicating that the instruction is being used to write

a single byte. The self-timed Write cycle starts,

and continues for a period t

(as specified in Ta-

WC

bles 18 to 22), at the end of which the Write in

Progress (WIP) bit is reset to 0.

– if a Write cycle is already in progress

– if the device has not been deselected, by Chip

Select (S) being driven High, at a byte boundary

(after the eighth bit, b0, of the last data byte that

has been latched in)

– if the addressed page is in the region protected

by the Block Protect (BP1 and BP0) bits.

If, though, Chip Select (S) continues to be driven

Low, as shown in Figure 15, the next byte of input

data is shifted in, so that more than a single byte,

starting from the given address towards the end of

the same page, can be written in a single internal

Write cycle.

18/39

M95640, M95320

Figure 15. Page Write (WRITE) Sequence

S

0

1

2

3

4

5

6

7

8

9

10

20 21 22 23 24 25 26 27 28 29 30 31

C

D

Instruction

16-Bit Address

Data Byte 1

15 14 13

3

2

1

0

7

6

5

4

3

2

0

1

S

C

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Data Byte 2

Data Byte 3

Data Byte N

7

6

5

4

3

2

0

7

6

5

4

3

2

0

6

5

4

3

2

0

1

D

AI01796D

Note: Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.

19/39

M95640, M95320

POWER-UP AND DELIVERY STATE

Power-up State

After Power-up, the device is in the following state:

– Stand-by mode

the SRWD, BP1 and BP0 bits of the Status Regis-

ter are unchanged from the previous power-down

(they are non-volatile bits).

– deselected (after Power-up, a falling edge is re-

quired on Chip Select (S) before any instruc-

tions can be started).

INITIAL DELIVERY STATE

– not in the Hold Condition

– the Write Enable Latch (WEL) is reset to 0

– Write In Progress (WIP) is reset to 0

The device is delivered with the memory array set

at all 1s (FFh). The Status Register Write Disable

(SRWD) and Block Protect (BP1 and BP0) bits are

initialized to 0.

20/39

M95640, M95320

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings" table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 7. Absolute Maximum Ratings

Symbol

Parameter

Min.

Max.

Unit

T

STG

Storage Temperature

–65

150

°C

2

PDIP

SO

260

1

3

T_LEAD

°C

Lead Temperature during Soldering

260

3

TSSOP

260

V_O

V_I

Output Voltage

Input Voltage

Supply Voltage

–0.45

–0.3

V_CC+0.6

6.5

V

6.5

CC

4

V_ESD

–4000

4000

Electrostatic Discharge Voltage (Human Body model)

®

Note: 1. Compliant with the ECOPACK 7191395 specifiication for lead-free soldering processes

2. No longer than 10 seconds

3. Not exceeding 250°C for more than 30 seconds, and peaking at 260°C

4. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

21/39

M95640, M95320

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. Designers should check that the operating

conditions in their circuit match the measurement

conditions when relying on the quoted parame-

ters.

Table 8. Operating Conditions (M95xxx)

Symbol

Parameter

Min.

4.5

Max.

5.5

Unit

V

CC

Supply Voltage

Ambient Operating Temperature (range 6)

–40

85

°C

T_A

Ambient Operating Temperature (range 3)

125

Table 9. Operating Conditions (M95xxx-W)

Symbol

Min.

Max.

Unit

Parameter

V

Supply Voltage

2.5

–40

5.5

85

V

CC

Ambient Operating Temperature (range 6)

Ambient Operating Temperature (range 3)

°C

T_A

125

Table 10. Operating Conditions (M95xxx-R)

1

Symbol

Min.

1.8

Max.

5.5

Unit

V

Parameter

V

CC

Supply Voltage

Ambient Operating Temperature

T_A

–40

85

°C

Note: 1. This product is under development. For more information, please contact your nearest ST sales office.

Table 11. AC Measurement Conditions

Symbol

Parameter

Min.

Max.

Unit

pF

ns

V

C

Load Capacitance

100

L

Input Rise and Fall Times

50

0.2V to 0.8V

Input Pulse Voltages

CC

0.3V to 0.7V

Input and Output Timing Reference Voltages

V

CC

Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 16. AC Measurement I/O Waveform

Input Levels

Input and Output

Timing Reference Levels

0.8V

0.2V

CC

0.7V

CC

0.3V

CC

AI00825B

22/39

M95640, M95320

Table 12. Capacitance

Symbol

C_OUT

Parameter

Test Condition

= 0V

Min.

Max.

Unit

pF

Output Capacitance (Q)

Input Capacitance (D)

V

8

6

OUT

C_IN

V

IN

= 0V

pF

Input Capacitance (other pins)

V

pF

Note: Sampled only, not 100% tested, at T =25°C and a frequency of 5 MHz.

A

Table 13. DC Characteristics (M95xxx, temperature range 6)

Symbol

Parameter

Test Condition

V_IN= V_SSor V_CC

Min.

Max.

± 2

Unit

I_LI

Input Leakage Current

Output Leakage Current

µA

I_LO

S = V_CC, V_OUT= V_SSor V_CC

± 2

C = 0.1V_CC/0.9V_CCat 5MHz,

4

mA

µA

2

V_CC= 5 V, Q = open, Current Product

I_CC

Supply Current

C = 0.1V_CC/0.9V_CCat 10MHz,

5

3

V

_CC= 5 V, Q = open, New Product

S = V_CC, V_CC= 5 V,

10

2

V_IN= V_SSor V_CC, Current Product

Supply Current

(Stand-by)

I_CC1

S = V_CC, V_CC= 5 V,

µA

2

3

V

_IN= V_SSor V_CC, New Product

V_IL

V_IH

Input Low Voltage

Input High Voltage

Output Low Voltage

–0.45

0.3 V_CC

V_CC+1

0.4

V

0.7 V_CC

1

I_OL= 2 mA, V_CC= 5 V

I_OH= –2 mA, V_CC= 5 V

V_OL

1

Output High Voltage

0.8 V_CC

V

V_OH

Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.

2. Current product: identified by Process Identification letter S.

3. New product: identified by Process Identification letter V.

23/39

M95640, M95320

Table 14. DC Characteristics (M95xxx, temperature range 3)

Symbol

Parameter

Test Condition

V_IN= V_SSor V_CC

Min.

Max.

± 2

Unit

µA

I_LI

Input Leakage Current

Output Leakage Current

I_LO

S = V_CC, V_OUT= V_SSor V_CC

± 2

µA

C = 0.1V_CC/0.9V_CCat 2 MHz,

2

mA

µA

2

V_CC= 5 V, Q = open, Current Product

I_CC

Supply Current

C = 0.1V_CC/0.9V_CCat 5 MHz,

4

3

V_CC= 5 V, Q = open, New Product

S = V_CC, V_CC= 5 V,

20

2

V_IN= V_SSor V_CC, Current Product

Supply Current

(Stand-by)

I_CC1

S = V_CC, V_CC= 5 V,

µA

5

3

V_IN= V_SSor V_CC, New Product

V_IL

V_IH

0.3 V_CC

V_CC+1

0.4

Input Low Voltage

Input High Voltage

Output Low Voltage

–0.45

V

0.7 V_CC

1

I_OL= 2 mA, V_CC= 5 V

I_OH= –2 mA, V_CC= 5 V

V_OL

1

Output High Voltage

0.8 V_CC

V

V_OH

Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.

2. Current product: identified by Process Identification letter S.

3. New product: identified by Process Identification letter B.

Table 15. DC Characteristics (M95xxx-W, temperature range 6)

Symbol

Parameter

Test Condition

V_IN= V_SSor V_CC

Min.

Max.

± 2

Unit

µA

I_LI

Input Leakage Current

Output Leakage Current

I_LO

S = V_CC, V_OUT= V_SSor V_CC

± 2

µA

C = 0.1V_CC/0.9V_CCat 2 MHz,

2

mA

µA

1

V

_CC= 2.5 V, Q = open, Current Product

I_CC

Supply Current

C = 0.1V_CC/0.9V_CCat 5 MHz,

3

2

V_CC= 2.5 V, Q = open, New Product

S = V_CC, V_CC= 2.5 V,

1

V_IN= V_SSor V_CC, Current Product

Supply Current

(Stand-by)

I_CC1

S = V_CC, V_CC= 2.5 V

µA

1

2

V_IN= V_SSor V_CC, New Product

V_IL

V_IH

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

–0.45

0.3 V_CC

V_CC+1

0.4

V

0.7 V_CC

V_OL

V_OH

I

_OL= 1.5 mA, V_CC= 2.5 V

I_OH= –0.4 mA, V_CC= 2.5 V

0.8 V_CC

Note: 1. Current product: identified by Process Identification letter S.

2. New product: identified by Process Identification letter V.

24/39

M95640, M95320

Table 16. DC Characteristics (M95xxx-W, temperature range 3)

Symbol

Parameter

Unit

µA

Test Condition

V_IN= V_SSor V_CC

Min.

Max.

± 2

I_LI

Input Leakage Current

Output Leakage Current

I_LO

S = V_CC, V_OUT= V_SSor V_CC

± 2

µA

C = 0.1V_CC/0.9V_CCat 5 MHz,

V_CC= 2.5 V, Q = open

I_CC

Supply Current

mA

µA

3

2

Supply Current

(Stand-by)

I_CC1

S = V_CC, V_CC= 2.5 V, V_IN= V_SSor V_CC

V_IL

V_IH

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

–0.45

0.3 V_CC

V_CC+1

0.4

V

0.7 V_CC

V_OL

V_OH

I

_OL= 1.5 mA, V_CC= 2.5 V

I_OH= –0.4 mA, V_CC= 2.5 V

0.8 V_CC

Note: New product: identified by Process Identification letter B.

Table 17. DC Characteristics (M95xxx-R)

1

2

Symbol

Parameter

Unit

µA

Test Condition

Min.

Max.

I_LI

Input Leakage Current

Output Leakage Current

V_IN= V_SSor V_CC

± 2

I_LO

S = V_CC, V_OUT= V_SSor V_CC

µA

C = 0.1V_CC/0.9V_CCat 2 MHz,

V_CC= 1.8 V, Q = open

I_CC

Supply Current

mA

µA

1

Supply Current

(Stand-by)

I_CC1

S = V_CC, V_IN= V_SSor V_CC, V_CC= 1.8 V

V_IL

V_IH

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

–0.45

0.3 V_CC

V_CC+1

0.3

V

0.7 V_CC

V_OL

V_OH

I

_OL= 0.15 mA, V_CC= 1.8 V

I

_OH= –0.1 mA, V_CC= 1.8 V

0.8 V_CC

Note: 1. This product is under qualification. For more infomation, please contact your nearest ST sales office.

2. Preliminary data.

25/39

M95640, M95320

Table 18. AC Characteristics (M95xxx, temperature range 6)

Test conditions specified in Table 11 and Table 8

3

4

Symbol

Alt.

Parameter

Unit

MHz

ns

Min.

D.C.

90

Max.

Min.

Max.

f

C

f

Clock Frequency

5

D.C.

15

10

SCK

CSS1

CSS2

t

S Active Setup Time

S Not Active Setup Time

S Deselect Time

SLCH

t

90

15

ns

SHCH

t

100

90

40

ns

SHSL

CS

t

CSH

S Active Hold Time

S Not Active Hold Time

Clock High Time

25

ns

CHSH

t

90

15

ns

CHSL

1

t

90

40

ns

t

CLH

CH

1

t

Clock Low Time

Clock Rise Time

40

ns

t

CL

CLL

2

t

1

µs

t

RC

CLCH

2

t

Clock Fall Time

1

µs

ns

t

FC

CHCL

t

DSU

Data In Setup Time

20

30

70

40

60

15

20

30

DVCH

t

Data In Hold Time

CHDX

DH

t

Clock Low Hold Time after HOLD not Active

Clock Low Hold Time after HOLD Active

Clock High Set-up Time before HOLD Active

HHCH

t

HLCH

t

CHHL

Clock High Set-up Time before HOLD not

Active

t

60

30

ns

CHHH

2

t

Output Disable Time

Clock Low to Output Valid

Output Hold Time

100

60

25

ns

t

DIS

SHQZ

t

CLQV

V

t

HO

0

CLQX

2

t

Output Rise Time

50

20

25

5

ns

ms

t

RO

QLQH

2

t

Output Fall Time

t

FO

QHQL

2

t

HOLD High to Output Low-Z

HOLD Low to Output High-Z

Write Time

50

t

LZ

HHQX

2

t

100

10

t

HZ

HLQZ

t

WC

W

Note: 1. t + t ≥ 1 / f .

CH

CL

C

2. Value guaranteed by characterization, not 100% tested in production.

3. Current product: identified by Process Identification letter S.

4. New product: identified by Process Identification letter V.

26/39

M95640, M95320

Table 19. AC Characteristics (M95xxx, temperature range 3)

Test conditions specified in Table 11 and Table 8

3

4

Symbol

Alt.

Parameter

Unit

MHz

ns

Min.

D.C.

200

Max.

Min.

Max.

f

C

f

Clock Frequency

2

D.C.

90

5

SCK

CSS1

CSS2

t

S Active Setup Time

S Not Active Setup Time

S Deselect Time

SLCH

t

90

ns

SHCH

t

100

90

ns

SHSL

CS

t

CSH

S Active Hold Time

S Not Active Hold Time

Clock High Time

ns

CHSH

t

90

ns

CHSL

1

t

200

90

ns

t

CLH

CH

1

t

Clock Low Time

Clock Rise Time

90

ns

t

CL

CLL

2

t

1

µs

t

RC

CLCH

2

t

Clock Fall Time

1

µs

ns

t

FC

CHCL

t

DSU

Data In Setup Time

40

50

20

30

70

40

70

DVCH

t

Data In Hold Time

CHDX

DH

t

Clock Low Hold Time after HOLD not Active

Clock Low Hold Time after HOLD Active

Clock High Set-up Time before HOLD Active

140

90

HHCH

t

HLCH

t

120

CHHL

Clock High Set-up Time before HOLD not

Active

t

120

70

ns

CHHH

2

t

Output Disable Time

Clock Low to Output Valid

Output Hold Time

250

150

100

60

ns

t

DIS

SHQZ

t

CLQV

V

t

HO

0

CLQX

2

t

Output Rise Time

100

250

10

50

100

5

ns

ms

t

RO

QLQH

2

t

Output Fall Time

t

FO

QHQL

2

t

HOLD High to Output Low-Z

HOLD Low to Output High-Z

Write Time

t

LZ

HHQX

2

t

HZ

HLQZ

t

WC

W

Note: 1. t + t ≥ 1 / f .

CH

CL

C

2. Value guaranteed by characterization, not 100% tested in production.

3. Current product: identified by Process Identification letter S.

4. New product: identified by Process Identification letter B.

27/39

M95640, M95320

Table 20. AC Characteristics (M95xxx-W, temperature range 6)

Test conditions specified in Table 11 and Table 9

3

4

Symbol

Alt.

Parameter

Unit

MHz

ns

Min.

D.C.

200

Max.

Min.

Max.

f

C

f

Clock Frequency

2

D.C.

90

5

SCK

CSS1

CSS2

t

S Active Setup Time

S Not Active Setup Time

S Deselect Time

SLCH

t

90

ns

SHCH

t

100

90

ns

SHSL

CS

t

CSH

S Active Hold Time

S Not Active Hold Time

Clock High Time

ns

CHSH

t

90

ns

CHSL

1

t

200

90

ns

t

CLH

CH

1

t

Clock Low Time

Clock Rise Time

90

ns

t

CL

CLL

2

t

1

µs

t

RC

CLCH

2

t

Clock Fall Time

1

µs

ns

t

FC

CHCL

t

DSU

Data In Setup Time

40

50

20

30

70

40

60

DVCH

t

Data In Hold Time

CHDX

DH

t

Clock Low Hold Time after HOLD not Active

Clock Low Hold Time after HOLD Active

Clock High Set-up Time before HOLD Active

140

90

HHCH

t

HLCH

t

120

CHHL

Clock High Set-up Time before HOLD not

Active

t

120

60

ns

CHHH

2

t

Output Disable Time

Clock Low to Output Valid

Output Hold Time

250

150

100

60

ns

t

DIS

SHQZ

t

CLQV

V

t

HO

0

CLQX

2

t

Output Rise Time

100

250

10

50

100

5

ns

ms

t

RO

QLQH

2

t

Output Fall Time

t

FO

QHQL

2

t

HOLD High to Output Low-Z

HOLD Low to Output High-Z

Write Time

t

LZ

HHQX

2

t

HZ

HLQZ

t

WC

W

Note: 1. t + t ≥ 1 / f .

CH

CL

C

2. Value guaranteed by characterization, not 100% tested in production.

3. Current product: identified by Process Identification letter S.

4. New product: identified by Process Identification letter V.

28/39

M95640, M95320

Table 21. AC Characteristics (M95xxx-W, temperature range 3)

Test conditions specified in Table 11 and Table 9

Symbol

Alt.

Parameter

Unit

MHz

ns

Min.

D.C.

90

Max.

f

Clock Frequency

5

C

SCK

CSS1

CSS2

t

S Active Setup Time

S Not Active Setup Time

S Deselect Time

SLCH

t

90

ns

SHCH

t

100

90

ns

SHSL

CS

t

CSH

S Active Hold Time

S Not Active Hold Time

Clock High Time

ns

CHSH

t

90

ns

CHSL

1

t

90

ns

t

CLH

CH

1

t

Clock Low Time

Clock Rise Time

ns

t

CLL

CL

2

t

1

µs

t

RC

CLCH

2

t

Clock Fall Time

1

µs

ns

t

FC

CHCL

t

DSU

Data In Setup Time

20

30

70

40

60

DVCH

t

DH

Data In Hold Time

CHDX

t

Clock Low Hold Time after HOLD not Active

Clock Low Hold Time after HOLD Active

Clock High Set-up Time before HOLD Active

Clock High Set-up Time before HOLD not Active

Output Disable Time

HHCH

t

HLCH

t

CHHL

t

CHHH

2

t

100

60

t

DIS

SHQZ

t

Clock Low to Output Valid

Output Hold Time

CLQV

V

t

0

CLQX

HO

RO

2

t

Output Rise Time

50

100

5

t

QLQH

QHQL

HHQX

2

t

FO

Output Fall Time

ns

ms

t

HOLD High to Output Low-Z

HOLD Low to Output High-Z

Write Time

t

LZ

t

HZ

t

HLQZ

t

W

t

WC

Note: 1. t + t ≥ 1 / f .

CH

CL

C

2. Value guaranteed by characterization, not 100% tested in production.

3. New product: identified by Process Identification letter B.

29/39

M95640, M95320

Table 22. AC Characteristics (M95xxx-R)

Test conditions specified in Table 11 and Table 10

3

Symbol

Alt.

Parameter

Unit

MHz

ns

Min.

Max.

f

Clock Frequency

D.C.

200

2

C

SCK

CSS1

CSS2

t

S Active Setup Time

S Not Active Setup Time

S Deselect Time

SLCH

t

ns

SHCH

t

ns

SHSL

CS

t

CSH

S Active Hold Time

S Not Active Hold Time

Clock High Time

ns

CHSH

t

ns

CHSL

1

t

ns

t

CLH

CH

1

t

Clock Low Time

Clock Rise Time

200

ns

t

CLL

CL

2

t

1

µs

t

RC

CLCH

2

t

Clock Fall Time

1

µs

ns

t

FC

CHCL

t

DSU

Data In Setup Time

40

50

DVCH

t

DH

Data In Hold Time

CHDX

t

Clock Low Hold Time after HOLD not Active

Clock Low Hold Time after HOLD Active

Clock High Set-up Time before HOLD Active

Clock High Set-up Time before HOLD not Active

Output Disable Time

140

90

HHCH

t

HLCH

t

120

CHHL

t

CHHH

2

t

250

150

t

DIS

SHQZ

t

Clock Low to Output Valid

Output Hold Time

CLQV

V

t

0

CLQX

HO

RO

2

t

Output Rise Time

100

250

10

t

QLQH

QHQL

HHQX

2

t

FO

Output Fall Time

ns

ms

t

HOLD High to Output Low-Z

HOLD Low to Output High-Z

Write Time

t

LZ

t

HZ

t

HLQZ

t

W

t

WC

Note: 1. t + t ≥ 1 / f .

CH

CL

C

2. Value guaranteed by characterization, not 100% tested in production.

3. Preliminary data: this product is under qualification. For more infomation, please contact your nearest ST sales office.

30/39

M95640, M95320

Figure 17. Serial Input Timing

tSHSL

S

tCHSL

tSLCH

tCHSH

tSHCH

C

tDVCH

tCHCL

tCHDX

tCLCH

MSB IN

LSB IN

D

Q

High Impedance

AI01447C

Figure 18. Hold Timing

S

tHLCH

tCHHL

tHHCH

C

tCHHH

tHLQZ

tHHQX

Q

D

HOLD

AI02032

31/39

M95640, M95320

Figure 19. Output Timing

S

tCH

C

tCLQV

tCL

tSHQZ

tCLQX

LSB OUT

Q

D

tQLQH

tQHQL

ADDR.LSB IN

AI01449D

32/39

M95640, M95320

PACKAGE MECHANICAL

Figure 20. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline

E

b2

A2

A1

A

L

c

b

e

eA

eB

D

8

1

E1

PDIP-B

Notes: 1. Drawing is not to scale.

Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data

mm

inches

Min.

Symb.

Typ.

Min.

Max.

Typ.

Max.

A

A1

A2

b

5.33

0.210

0.38

2.92

0.36

1.14

0.20

9.02

7.62

6.10

–

0.015

0.115

0.014

0.045

0.008

0.355

0.300

0.240

–

3.30

0.46

1.52

0.25

9.27

7.87

6.35

2.54

7.62

4.95

0.56

1.78

0.36

10.16

8.26

7.11

–

0.130

0.018

0.060

0.010

0.365

0.310

0.250

0.100

0.300

0.195

0.022

0.070

0.014

0.400

0.325

0.280

–

b2

c

D

E

E1

e

eA

eB

L

–

10.92

3.81

0.430

0.150

3.30

2.92

0.130

0.115

33/39

M95640, M95320

Figure 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline

h x 45˚

A

C

B

CP

e

D

N

E

H

1

A1

α

L

SO-a

Note: Drawing is not to scale.

Table 24. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data

mm

Min.

1.35

0.10

0.33

0.19

4.80

3.80

–

inches

Min.

0.053

0.004

0.013

0.007

0.189

0.150

–

Symb.

Typ.

Max.

1.75

0.25

0.51

0.25

5.00

4.00

–

Typ.

Max.

0.069

0.010

0.020

0.010

0.197

0.157

–

A

A1

B

C

D

E

e

1.27

0.050

H

h

5.80

0.25

0.40

0°

6.20

0.50

0.90

8°

0.228

0.010

0.016

0°

0.244

0.020

0.035

8°

L

α

N

CP

8

0.10

0.004

34/39

M95640, M95320

Figure 22. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline

D

8

5

c

E1

E

1

4

α

A1

L

A

A2

L1

CP

b

e

TSSOP8AM

Notes: 1. Drawing is not to scale.

Table 25. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data

mm

inches

Symbol

Typ.

Min.

Max.

1.200

0.150

1.050

0.300

0.200

0.100

3.100

–

Typ.

Min.

Max.

0.0472

0.0059

0.0413

0.0118

0.0079

0.0039

0.1220

–

A

A1

A2

b

0.050

0.800

0.190

0.090

0.0020

0.0315

0.0075

0.0035

1.000

0.0394

c

CP

D

3.000

0.650

6.400

4.400

0.600

1.000

2.900

–

0.1181

0.0256

0.2520

0.1732

0.0236

0.0394

0.1142

–

e

E

6.200

4.300

0.450

6.600

4.500

0.750

0.2441

0.1693

0.0177

0.2598

0.1772

0.0295

E1

L

L1

α

0°

8°

0°

8°

35/39

M95640, M95320

Figure 23. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Outline

D

14

8

c

E1

E

1

7

α

A1

L

A

A2

L1

CP

b

e

TSSOP14-M

Notes: 1. Drawing is not to scale.

Table 26. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Mechanical Data

mm

inches

Min.

Symbol

Typ.

Min.

Max.

1.200

0.150

1.050

0.300

0.200

0.100

5.100

–

Typ.

Max.

0.0472

0.0059

0.0413

0.0118

0.0079

0.0039

0.2008

–

A

A1

A2

b

0.050

0.800

0.190

0.090

0.0020

0.0315

0.0075

0.0035

1.000

0.0394

c

CP

D

5.000

0.650

6.400

4.400

0.600

1.000

4.900

–

0.1969

0.0256

0.2520

0.1732

0.0236

0.0394

0.1929

–

e

E

6.200

4.300

0.500

6.600

4.500

0.750

0.2441

0.1693

0.0197

0.2598

0.1772

0.0295

E1

L

L1

α

0°

8°

0°

8°

36/39

M95640, M95320

PART NUMBERING

Table 27. Ordering Information Scheme

Example:

M95320

–

W

MN

6

T

P

Device Type

M95 = SPI serial access EEPROM

1

Device Function

640 = 64 Kbit (8192 x 8)

320 = 32 Kbit (4096 x 8)

Operating Voltage

blank = V = 4.5 to 5.5V

CC

W = V = 2.5 to 5.5V

CC

R = V = 1.8 to 5.5V

CC

Package

BN = PDIP8

MN = SO8 (150 mil width)

DW = TSSOP8 (169 mil width)

DL = TSSOP14 (169 mil width)

Temperature Range

6 = –40 to 85 °C

3 = –40 to 125 °C

Option

blank = Standard Packing

T = Tape & Reel Packing

Plating Technology

blank = Standard SnPb plating

P = Pb-free plating

G = Green pack

Note: 1. Devices bearing the process identification letter “B” or “V” in the package marking (on the top side of the package, on the right side),

guarantee more than 1 million Erase/Write cycle endurance (see Table 28, below). For more information about these devices, and

their device identification, please contact your nearest ST sales office, and ask for the Product Change Notice.

For a list of available options (speed, package,

etc.) or for further information on any aspect of this

device, please contact your nearest ST Sales Of-

fice.

Table 28. How to Identify Current and Forthcoming Products by the Process Identification Letter

1

Markings on Current Products

Markings on New Products

95640 6 (or 95640W6)

xxxxS

xxxxV

95640 3

95640 3 (or 95640W3)

xxxxS

xxxxB

Note: 1. For further information, please ask your ST Sales Office for Process Change Notice PCN MPG/EE/0053 (PCEE0053) and MPG/

EE/0054 (PCEE0054).

37/39

M95640, M95320

REVISION HISTORY

Table 29. Document Revision History

Date

Rev.

Description of Revision

Human Body Model meets JEDEC std (Table 2). Minor adjustments on pp 1,11,15. New clause

on p7. Addition of TSSOP8 package on pp 1, 2, Ordering Info, Mechanical Data

13-Jul-2000

1.2

Test condition added I and I , and specification of t

and t

removed.

LI

LO

DLDH

DHDL

t

, t

and t

changed to 50ns for the -V range.

CLCH CHCL DLDH

DHDL

“-V” Voltage range changed to “2.7V to 3.6V” throughout.

Maximum lead soldering time and temperature conditions updated.

16-Mar-2001

1.3

Instruction sequence illustrations updated.

“Bus Master and Memory Devices on the SPI bus” illustration updated.

Package Mechanical data updated.

19-Jul-2001

06-Dec-2001

18-Dec-2001

08-Feb-2002

1.4 M95160 and M95080 devices removed to their own data sheet

Endurance increased to 1M write/erase cycles

Instruction sequence illustrations updated

1.5

2.0 Document reformatted using the new template. No parameters changed.

Announcement made of planned upgrade to 10 MHz clock for the 5V, –40 to 85°C, range.

Endurance set to 100K write/erase cycles

2.1

10MHz, 5MHz, 2MHz clock; 5ms, 10ms Write Time; 100K, 1M erase/write cycles distinguished

on front page, and in the DC and AC Characteristics tables

18-Dec-2002

2.2

26-Mar-2003

26-Jun-2003

15-Oct-2003

21-Nov-2003

2.3 Process indentification letter corrected in footnote to AC Characteristics table for temp. range 3

2.4 -S voltage range upgraded by removing it and inserting -R voltage range in its place

Table of contents, and Pb-free options added. V (min) improved to -0.45V.

3.0

3.1

IL

V (min) and V (min) corrected (improved) to -0.45V.

I

O

38/39

M95640, M95320

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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39/39


型号：	M95640-WDW6TP
厂家：	ST
描述：	64Kbit and 32Kbit Serial SPI Bus EEPROM With High Speed Clock 为64Kbit和32Kbit串行SPI总线的EEPROM采用高速时钟存储内存集成电路光电二极管 PC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件：	总39页 (文件大小：553K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M95640-WDW6TP [STMICROELECTRONICS]

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