M95160-WDW3TP/SC [STMICROELECTRONICS]
2KX8 SPI BUS SERIAL EEPROM, PDSO8, 0.169 INCH, HALOGEN FREE AND ROHS COMPLIANT, TSSOP-8;
| 型号： | M95160-WDW3TP/SC |
| 厂家： | 
ST |
| 描述： | 2KX8 SPI BUS SERIAL EEPROM, PDSO8, 0.169 INCH, HALOGEN FREE AND ROHS COMPLIANT, TSSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总35页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M95160-W4
M95160-W3
16 Kbit serial SPI bus EEPROM
with high speed clock
Custom data
Features
■ Compatible with SPI bus serial interface
(positive clock SPI modes)
■ Extended operating temperature range:
– Device grade 3: –40 °C to +125 °C
– Device grade 4: –40 °C to +145 °C
■ Single supply voltage:
– 2.5 V to 5.5 V
TSSOP8 (DW)
169 mil width
■ High speed: 5 MHz
■ Status Register
■ Hardware protection of the Status Register
■ Byte and page write (up to 32 bytes)
■ Self-timed programming cycle
■ Adjustable size read-only EEPROM area
■ Enhanced ESD protection
■ More than 1 million write cycles
■ More than 40-year data retention
■ Package
®
– ECOPACK2 (RoHS compliant and
Halogen-free)
June 2011
Doc ID 14520 Rev 7
1/35
This is a document intended for a specific customer. It must not be released without first contacting Division marketing.
www.st.com
1
Contents
M95160-W3, M95160-W4
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
4
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1
4.1.2
4.1.3
4.1.4
Operating supply voltage V
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
4.3
4.4
4.5
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
6.2
6.3
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Contents
6.3.2
6.3.3
6.3.4
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4
6.5
6.6
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9
10
11
12
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List of tables
M95160-W3, M95160-W4
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating conditions (M95160-W3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating conditions (M95160-W4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 32
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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M95160-W3, M95160-W4
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TSSOP8-lead package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 15. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 32
Doc ID 14520 Rev 7
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Description
M95160-W3, M95160-W4
1
Description
The M95160-W3 and M95160-W4 are electrically erasable programmable memory
(EEPROM) devices. They are accessed by a high-speed SPI-compatible bus. The memory
array is organized as 2048 × 8 bits.
The M95160-W3 and M95160-W4 are the first EEPROM devices in TSSOP package
qualified at 145°C.
The M95160-W3 and M95160-W4 devices are designed to be compliant with the very high
level of reliability defined by the Automotive standard AEC-Q100 grade 0.
Figure 1.
Logic diagram
V
CC
D
C
S
Q
M95xxx
W
HOLD
V
SS
AI01789C
Table 1.
Signal names
Signal name
Function
Direction
C
Serial Clock
Input
Input
Output
Input
Input
Input
D
Serial Data input
Serial Data output
Chip Select
Write Protect
Hold
Q
S
W
HOLD
VCC
VSS
Supply voltage
Ground
6/35
Doc ID 14520 Rev 7
M95160-W3, M95160-W4
Figure 2.
Description
TSSOP8-lead package connections (top view)
M95xxx
S
Q
1
2
3
4
8
V
CC
HOLD
7
W
6
5
C
D
V
SS
AI01790D
1. See Package mechanical data section for package dimensions, and how to identify pin-1.
Doc ID 14520 Rev 7
7/35
Signal description
M95160-W3, M95160-W4
2
Signal description
During all operations, V must be held stable and within the specified valid range:
CC
V
(min) to V (max).
CC
CC
All of the input and output signals must be held high or low (according to voltages of V ,
IH
V
, V or V , as specified in Table 11. These signals are described next.
OH
IL OL
2.1
2.2
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
2.3
2.4
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
8/35
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M95160-W3, M95160-W4
Signal description
2.6
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all write instructions.
2.7
2.8
VCC supply voltage
V
is the supply voltage.
CC
VSS ground
V
is the reference for the V supply voltage.
SS
CC
Doc ID 14520 Rev 7
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Connecting to the SPI bus
M95160-W3, M95160-W4
3
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such
as the Read from Memory Array and Read Status Register instructions) have been clocked
into the device.
Figure 3. shows three devices, connected to an MCU, on an SPI bus. Only one device is
selected at a time, so only one device drives the Serial Data output (Q) line at a time, all the
others being high impedance.
Figure 3.
Bus master and memory devices on the SPI bus
633
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3#+
6##
6##
6##
#
1
$
#
1
$
# 1 $
633
633
633
30) BUS MASTER
30) MEMORY
DEVICE
30) MEMORY
DEVICE
30) MEMORY
DEVICE
2
2
2
#3ꢃ #3ꢁ #3ꢀ
3
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3
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1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 3 shows an example of three memory devices connected to an MCU, on an SPI bus.
Only one memory device is selected at a time, so only one memory device drives the Serial
Data output (Q) line at a time, the other memory devices are high impedance.
The pull-up resistor R (represented in Figure 3) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may be in a state where all input/output SPI buses are
high impedance at the same time (for example, if the Bus Master is reset during the
transmission of an instruction), the clock line (C) must be connected to an external pull-
down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high): this ensures that S and C do not become high at the same
time, and so, that the t
requirement is met. The typical value of R is 100 kΩ.
SHCH
10/35
Doc ID 14520 Rev 7
M95160-W3, M95160-W4
Connecting to the SPI bus
3.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
CPOL=0, CPHA=0
CPOL=1, CPHA=1
●
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4., is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
●
Figure 4.
SPI modes supported
CPOL CPHA
C
0
1
0
1
C
D
MSB
Q
MSB
AI01438B
Doc ID 14520 Rev 7
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Operating features
M95160-W3, M95160-W4
4
Operating features
4.1
Supply voltage (VCC)
4.1.1
Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied (see Table 9). This voltage
CC
CC
must remain stable and valid until the end of the transmission of the instruction and, for a
Write instruction, until the completion of the internal write cycle (t ).
W
In order to secure a stable DC supply voltage, it is recommended to decouple the V line
CC
with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V /V
CC SS
package pins.
4.1.2
Device reset
In order to prevent inadvertent write operations during power-up, a power on reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until V
CC
reaches the internal reset threshold voltage (this threshold is lower than the minimum V
CC
operating voltage defined in Table 9).
When V passes over the POR threshold, the device is reset and in the following state:
CC
●
in Standby Power mode
●
deselected (note that, to be executed, an instruction must be preceded by a falling
edge on Chip Select (S))
●
Status Register value:
–
–
–
the Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)
When V passes over the POR threshold, the device is reset and enters the Standby
CC
Power mode. The device must not be accessed until V reaches a valid and stable V
CC
CC
voltage within the specified [V (min), V (max)] range defined in Table 9.
CC
CC
4.1.3
Power-up conditions
When the power supply is turned on, V rises continuously from V to V . During this
CC
SS
CC
time, the Chip Select (S) line is not allowed to float but should follow the V voltage, it is
CC
therefore recommended to connect the S line to V via a suitable pull-up resistor (see
CC
Figure 3).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The V voltage has to rise continuously from 0 V up to the minimum V operating voltage
CC
CC
defined in Table 9 and the rise time must not vary faster than 1 V/µs.
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Operating features
4.1.4
Power-down
During power-down (continuous decrease of V below the minimum V operating voltage
CC
CC
defined in Table 9), the device must be:
●
deselected (Chip Select S should be allowed to follow the voltage applied on V
)
CC
●
in Standby Power mode (there should not be any internal write cycle in progress).
4.2
Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes I , as specified in Table 11.
CC
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to I
.
CC1
4.3
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low.
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
4.4
Status Register
Figure 5. shows the position of the Status Register in the control logic of the device. The
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits
Doc ID 14520 Rev 7
13/35
Operating features
M95160-W3, M95160-W4
4.5
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
●
Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write (WRITE) instruction completion
●
●
The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status
Register to be protected.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
●
The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
●
The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2.
Write-protected block size
Status Register bits
Protected array addresses
M95160-W3 and M95160-W4
Protected block
BP1
BP0
0
0
1
1
0
1
0
1
none
none
Upper quarter
Upper half
Whole memory
0600h - 07FFh
0400h - 07FFh
0000h - 07FFh
14/35
Doc ID 14520 Rev 7
M95160-W3, M95160-W4
Memory organization
5
Memory organization
The memory is organized as shown in Figure 5.
Figure 5.
Block diagram
HOLD
W
High voltage
generator
Control logic
S
C
D
Q
I/O shift register
Address register
and counter
Data
register
Status
Register
Size of the
read-only
EEPROM
area
1 page
X decoder
AI01272d
Doc ID 14520 Rev 7
15/35
Instructions
M95160-W3, M95160-W4
6
Instructions
Each instruction starts with a single-byte code, as summarized in Table 3.
If an invalid instruction is sent (one not contained in Table 3.), the device automatically
deselects itself.
Table 3.
Instruction set
Instruction
Description
Write Enable
Instruction format
WREN
WRDI
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Write Disable
RDSR
WRSR
READ
WRITE
Read Status Register
Write Status Register
Read from Memory Array
Write to Memory Array
6.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 6., to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.
Figure 6.
Write Enable (WREN) sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI02281E
16/35
Doc ID 14520 Rev 7
M95160-W3, M95160-W4
Instructions
6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 7., to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
●
●
●
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure 7.
Write Disable (WRDI) sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03750D
Doc ID 14520 Rev 7
17/35
Instructions
M95160-W3, M95160-W4
6.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 8.
The status and control bits of the Status Register are as follows:
6.3.1
6.3.2
6.3.3
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 4.) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 4.
Status Register format
b7
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status register write protect
Block protect bits
Write enable latch bit
Write in progress bit
18/35
Doc ID 14520 Rev 7
M95160-W3, M95160-W4
Instructions
Figure 8.
Read Status Register (RDSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031E
Doc ID 14520 Rev 7
19/35
Instructions
M95160-W3, M95160-W4
6.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code, the data byte on Serial Data input (D) and the Chip Select
(S) driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C)
that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock
(C). Otherwise, the Write Status Register (WRSR) instruction is not executed.
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed write cycle that takes t to complete (as specified in Table 13).
W
The instruction sequence is shown in Figure 9.
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit: the WIP bit is 1 during the self-timed write
cycle t , and is 0 when the write cycle is complete. The WEL bit (Write Enable Latch) is also
W
reset at the end of the write cycle t .
W
The Write Status Register (WRSR) instruction allows the user to change the values of the
BP1, BP0 bits and the SRWD bit:
●
The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read only, as defined in Table 5.
●
The SRWD bit (Status Register Write Disable bit), in accordance with the signal read
on the Write Protect pin (W), allows the user to set or reset the write protection mode of
the Status Register itself. When in Write-protected mode, the Write Status Register
(WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the t Write cycle.
W
The Write Status Register (WRSR) instruction has no effect on bits b6, b5, b4, b1, b0 of the
Status Register. Bits b6, b5, b4 are always read as 0.
Table 5.
Protection modes
Memory content
W
signal
SRWD Write protection of the
Mode
bit
Status Register
Protected area(1) Unprotected area(1)
1
0
0
0
Status Register is
Writable (if the WREN
Software- instruction has set the
protected WEL bit)
Ready to accept
Write-protected
Write instructions
(SPM)
The values in the BP1
and BP0 bits can be
changed
1
0
1
1
Status Register is
Hardware- Hardware write protected
protected The values in the BP1
Ready to accept
Write-protected
Write instructions
(HPM)
and BP0 bits cannot be
changed
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 4.
20/35
Doc ID 14520 Rev 7
M95160-W3, M95160-W4
The protection features of the device are summarized in Table 2.
Instructions
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of whether Write Protect (W) is driven high or low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
●
●
If Write Protect (W) is driven high, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,
are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
●
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
low
●
or by driving Write Protect (W) low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W) high.
If Write Protect (W) is permanently tied high, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
(1)
Table 6.
Address range bits
Device
M95160-W3 and M95160-W4
Address bits
A10-A0
1. b15 to b11 are Don’t Care.
Doc ID 14520 Rev 7
21/35
Instructions
M95160-W3, M95160-W4
Figure 9.
Write Status Register (WRSR) sequence
S
C
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
22/35
Doc ID 14520 Rev 7
M95160-W3, M95160-W4
Instructions
6.5
Read from Memory Array (READ)
As shown in Figure 10., to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 10. Read from Memory Array (READ) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
AI01793D
1. Depending on the memory size, as shown in Table 6., the most significant address bits are Don’t Care.
Doc ID 14520 Rev 7
23/35
Instructions
M95160-W3, M95160-W4
6.6
Write to Memory Array (WRITE)
As shown in Figure 11., to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a
period t (as specified in Table 13), at the end of which the Write in Progress (WIP) bit is
W
reset to 0.
In the case of Figure 11., Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte. If,
though, Chip Select (S) continues to be driven low, as shown in Figure 12., the next byte of
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
●
●
if a Write cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
●
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Figure 11. Byte Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
Data Byte
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
Q
High Impedance
AI01795D
1. Depending on the memory size, as shown in Table 6., the most significant address bits are Don’t Care.
24/35
Doc ID 14520 Rev 7
M95160-W3, M95160-W4
Figure 12. Page Write (WRITE) sequence
Instructions
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
Data Byte 1
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
S
C
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
0
7
6
5
4
3
2
0
6
5
4
3
2
0
1
1
1
D
AI01796D
1. Depending on the memory size, as shown in Table 6., the most significant address bits are Don’t Care.
Doc ID 14520 Rev 7
25/35
Delivery state
M95160-W3, M95160-W4
7
Delivery state
7.1
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
8
Maximum rating
Stressing the device outside the ratings listed in Table 7. may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 7.
Symbol
Absolute maximum ratings
Parameter
Min.
Max.
Unit
TA
TSTG
TLEAD
VO
Ambient operating temperature
Storage temperature
–40
–65
150
150
°C
°C
°C
V
Lead temperature during soldering
Output voltage
See note (1)
–0.50
–0.50
–0.50
–4000
VCC+0.6
6.5
VI
Input voltage
V
VCC
VESD
Supply voltage
6.5
V
Electrostatic discharge voltage (human body model)(2)
4000
V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω)
26/35
Doc ID 14520 Rev 7
M95160-W3, M95160-W4
DC and AC parameters
9
DC and AC parameters
This section summarizes the operating and measurement conditions, and the dc and ac
characteristics of the device. The parameters in the dc and ac characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 8.
Symbol
Operating conditions (M95160-W3)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
2.5
5.5
V
Ambient operating temperature (device grade 4)
–40
125
°C
Table 9.
Symbol
Operating conditions (M95160-W4)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
2.5
5.5
V
Ambient operating temperature (device grade 4)
–40
145
°C
Table 10. AC measurement conditions
Symbol
Parameter
Load capacitance
Min.
30 or 100
Typ.
Max.
Unit
CL
pF
ns
V
Input rise and fall times
50
Input pulse voltages
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
Input and output(1) timing reference voltages
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 13. AC measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
0.3V
CC
CC
0.2V
CC
AI00825B
(1)
Table 11. Capacitance
Symbol
Parameter
Test condition
Min.
Max.
Unit
COUT
Output capacitance (Q)
Input capacitance (D)
VOUT = 0 V
VIN = 0 V
VIN = 0 V
8
8
6
pF
pF
pF
CIN
Input capacitance (other pins)
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.
Doc ID 14520 Rev 7
27/35
DC and AC parameters
M95160-W3, M95160-W4
(1)
Table 12. DC characteristics
Test conditions (in addition to those
specified in Table 8, Table 9 and
Table 10)
Symbol
Parameter
Min.
Max.
Unit
Input leakage
current
ILI
VIN = VSS or VCC
2
2
µA
µA
Output leakage
current
ILO
ICC
S = VCC, VOUT = VSS or VCC
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open
Supply current
2
mA
S = VCC, VCC = 2.5 V, VIN = VSS or VCC
S = VCC, VCC = 5.5 V, VIN = VSS or VCC
10
10
µA
µA
V
Supply current
(Standby)
ICC1
VIL
VIH
Input low voltage
Input high voltage
–0.45
0.3 VCC
0.7 VCC VCC+1
0.4
V
VOL
VOH
Output low voltage IOL = 1.5 mA, VCC = 2.5 V
Output high voltage IOH = –0.4 mA, VCC = 2.5 V
V
0.8 VCC
V
1. Preliminary data.
28/35
Doc ID 14520 Rev 7
M95160-W3, M95160-W4
DC and AC parameters
Table 13. AC characteristics
Test conditions specified in Table 8, Table 9 and Table 10
Symbol
Alt.
Parameter
Min.
Max. Unit
fC
fSCK
Clock frequency
D.C.
60
60
90
60
60
75
75
5
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S active setup time
tCSS2 S not active setup time
tCS S deselect time
tCSH S active hold time
S not active hold time
(1)
tCH
tCLH
tCLL
tRC
Clock high time
Clock low time
Clock rise time
Clock fall time
(1)
tCL
(2)
tCLCH
1
1
(2)
tCHCL
tFC
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU Data in setup time
20
20
60
60
0
tDH
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low setup time before HOLD active
Clock low setup time before HOLD not active
Output disable time
0
(2)
tSHQZ
tDIS
tV
80
55
80
Clock low to output valid (CL = 30 pF)
Clock low to output valid (CL = 100 pF)
Output hold time
(3)
tCLQV
tCLQX
tHO
tRO
tFO
tLZ
0
(2)
tQLQH
Output rise time
80
80
80
80
5
(2)
tQHQL
Output fall time
tHHQV
HOLD high to output valid
HOLD low to output high-Z
Write time
(2)
tHLQZ
tHZ
tWC
tW
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). See also Note 3.
2. Value guaranteed by characterization, not 100% tested in production.
3. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU
=
0 ns, tCL can be equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than)
t
CLQV+tSU.
Doc ID 14520 Rev 7
29/35
DC and AC parameters
Figure 14. Serial input timing
M95160-W3, M95160-W4
tSHSL
tSHCH
S
C
tCHSL
tSLCH
tCH
tCHSH
tDVCH
tCHCL
tCHDX
tCL
tCLCH
MSB IN
LSB IN
D
Q
High impedance
AI01447d
Figure 15. Hold timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHHQV
tHLQZ
Q
HOLD
AI01448c
30/35
Doc ID 14520 Rev 7
M95160-W3, M95160-W4
DC and AC parameters
Figure 16. Serial output timing
S
tCH
tSHSL
C
tCLQV
tCLQX
tCLCH
tCHCL
tCL
tSHQZ
Q
D
tQLQH
tQHQL
ADDR
LSB IN
AI01449f
Doc ID 14520 Rev 7
31/35
Package mechanical data
M95160-W3, M95160-W4
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 17. TSSOP8 – 8-lead thin shrink small outline, package outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 14. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters
inches(1)
Symbol
Typ
Min
Max
Typ
Min
Max
A
1.2
0.15
1.05
0.3
0.2
0.1
3.1
-
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.122
A1
0.05
0.8
0.002
0.0315
0.0075
0.0035
A2
1
0.0394
b
0.19
0.09
c
CP
D
3
0.65
6.4
4.4
0.6
1
2.9
-
0.1181
0.0256
0.252
0.1142
-
e
-
E
6.2
4.3
0.45
6.6
4.5
0.75
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
0.1732
0.0236
0.0394
L
L1
α
0°
8
8°
0°
8
8°
N (number of leads)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Doc ID 14520 Rev 7
M95160-W3, M95160-W4
Part numbering
11
Part numbering
Table 15. Ordering information scheme
Example:
M95160
–
W DW 4
T
P /SC
Device type
M95 = SPI serial access EEPROM
Device function
160 = 16 Kbit (2048 × 8)
Operating voltage
W = VCC = 2.5 to 5.5 V
Package
DW = TSSOP8
Device grade
3 = Device tested with high reliability certified flow(1)
Automotive temperature range (–40 to 125 °C)
.
4 = Device tested with high reliability certified flow(1)
Automotive temperature range (–40 to 145 °C)
.
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
G or P = ECOPACK2® (RoHS compliant and Hallogen-free)
Process
/SC = F6SP36%
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Doc ID 14520 Rev 7
33/35
Revision history
M95160-W3, M95160-W4
12
Revision history
Table 16. Document revision history
Date
Revision
Changes
07-Mar-2008
1
Initial release.
Year of Revision 1 corrected in Table 16: Document revision history.
M95080-W4 part number removed.
Load capacitance value modified and Note 1 moved in Table 10: AC
measurement conditions.
17-Jun-2008
2
Table 13: AC characteristics updated and Note 3 added.
Figure 14: Serial input timing, Figure 15: Hold timing and Figure 16: Serial
output timing modified.
Section 6.4: Write Status Register (WRSR) modified.
ICC1 modified in Table 12: DC characteristics.
05-Jan-2009
03-Sep-2009
3
4
Section 4.1: Supply voltage (VCC) updated.
CL can be 30 or 100 pF in Table 10: AC measurement conditions.
tCH, tCL and tCLQV modified in Table 13: AC characteristics.
Device grade 3 added:
– M95160-W3 part number added
14-Jan-2010
5
– Table 8: Operating conditions (M95160-W3) added
– Table 15: Ordering information scheme updated
21-Jan-2010
27-Jun-2011
6
7
Process corrected in Table 15: Ordering information scheme.
Updated Section 1: Description.
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Doc ID 14520 Rev 7
M95160-W3, M95160-W4
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Doc ID 14520 Rev 7
35/35
相关型号：
M95160-WDW6TG
2KX8 SPI BUS SERIAL EEPROM, PDSO8, HALOGEN FREE AND ROHS COMPLIANT, TSSOP-8
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