M95160-RMB3T/W [STMICROELECTRONICS]
IC,SERIAL EEPROM,2KX8,CMOS,LLCC,8PIN,PLASTIC;型号: | M95160-RMB3T/W |
厂家: | ST |
描述: | IC,SERIAL EEPROM,2KX8,CMOS,LLCC,8PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
文件: | 总39页 (文件大小:714K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M95160
M95080
16Kbit and 8Kbit Serial SPI Bus EEPROM
With High Speed Clock
FEATURES SUMMARY
■
Compatible with SPI Bus Serial Interface
Figure 1. Packages
(Positive Clock SPI Modes)
■
Single Supply Voltage:
–
–
–
–
4.5 to 5.5V for M95xxx
8
2.5 to 5.5V for M95xxx-W
1.8 to 5.5V for M95xxx-R
1.65V to 5.5V for M95xxx-S
1
■
High Speed
SO8 (MN)
150 mil width
–
20MHz Clock Rate, 5ms Write Time
■
■
■
■
■
■
■
■
Status Register
Hardware Protection of the Status Register
BYTE and PAGE WRITE (up to 32 Bytes)
Self-Timed Programming Cycle
Adjustable Size Read-Only EEPROM Area
Enhanced ESD Protection
TSSOP8 (DW)
169 mil width
More than 1 Million Erase/Write Cycles
More than 40-Year Data Retention
TSSOP8 (DS)
3x3mm² body size (MSOP)
UFDFPN8 (MB)
2x3mm² (MLP)
Table 1. Product List
Reference
Part Number
M95160
M95160-W
M95160-R
M95160-S
M95080
M95160
M95080-W
M95080-R
M95080-S
M95080
September 2005
1/39
M95160, M95080
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
CONNECTING TO THE SPI BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Device Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Protection and Protocol Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DELIVERY STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/39
M95160, M95080
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3/39
M95160, M95080
SUMMARY DESCRIPTION
These electrically erasable programmable memo-
ry (EEPROM) devices are accessed by a high
speed SPI-compatible bus. The memory array is
organized as 2048 x 8 bit (M95160), and 1024 x 8
bit (M95080).
Figure 3. 8-pin Package Connections
(Top View)
The device is accessed by a simple serial interface
that is SPI-compatible. The bus signals are C, D
and Q, as shown in Table 2. and Figure 2.
The device is selected when Chip Select (S) is tak-
en Low. Communications with the device can be
interrupted using Hold (HOLD).
M95xxx
S
Q
1
2
3
4
8
V
CC
HOLD
7
W
6
5
C
D
V
SS
Figure 2. Logic Diagram
AI01790D
V
CC
Note: See PACKAGE MECHANICAL section for package dimen-
sions, and how to identify pin-1.
D
C
S
Q
Table 2. Signal Names
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
M95xxx
D
W
Q
S
HOLD
W
HOLD
V
SS
V
Supply Voltage
Ground
CC
AI01789C
V
SS
4/39
M95160, M95080
SIGNAL DESCRIPTION
During all operations, V must be held stable and
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Write
cycle is in progress, the device will be in the Stand-
by Power mode. Driving Chip Select (S) Low se-
lects the device, placing it in the Active Power
mode.
CC
within the specified valid range: V (min) to
CC
V
(max).
CC
All of the input and output signals must be held
High or Low (according to voltages of V , V , V
IH OH IL
or V , as specified in Table 14. to Table 19.).
OL
These signals are described next.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be written.
Values are latched on the rising edge of Serial
Clock (C).
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driven Low.
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of mem-
ory that is protected against Write instructions (as
specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either High or Low, and
must be stable during all write instructions.
5/39
M95160, M95080
CONNECTING TO THE SPI BUS
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register in-
structions) have been clocked into the device.
Figure 4. shows three devices, connected to an
MCU, on an SPI bus. Only one device is selected
at a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output
Figure 4. Bus Master and Memory Devices on the SPI Bus
VCC
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
VCC
VCC
C
Q
D
C
Q
D
C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
R(2)
R(2)
R(2)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
S
S
S
W
HOLD
W
HOLD
HOLD
W
AI03746e
Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
2. These pull-up resistors, R, ensure that the M95080 and M95160 are not selected if the Bus Master leaves the S line in high-imped-
ance state (example: during the Master reset sequence).
6/39
M95160, M95080
SPI Modes
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
–
–
CPOL=0, CPHA=0
CPOL=1, CPHA=1
–
–
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
Figure 5. SPI Modes Supported
CPOL CPHA
C
C
0
1
0
1
D
MSB
Q
MSB
AI01438B
7/39
M95160, M95080
OPERATING FEATURES
Power-up
At Power-down (continuous decay of V ), as
CC
soon as V drops from the normal operating volt-
CC
When the power supply is turned on, V
rises
CC
age, below the Power On Reset threshold voltage,
the device stops responding to any instruction sent
to it.
from V to V
.
SS
CC
During this time, the Chip Select (S) must be al-
lowed to follow the V voltage. It must not be al-
CC
lowed to float, but should be connected to V via
a suitable pull-up resistor.
CC
Power-down
At Power-down, the device must be deselected
and in Standby Power mode (i.e. no internal Write
cycle in progress). Chip Select (S) should be al-
As a built-in safety feature, Chip Select (S) is edge
sensitive as well as level sensitive. After Power-
up, the device does not become selected until a
falling edge has first been detected on Chip Select
(S). This ensures that Chip Select (S) must have
been High, prior to going Low to start the first op-
eration.
lowed to follow the voltage applied on V
.
CC
Active Power and Standby Power Modes
When Chip Select (S) is Low, the device is select-
ed, and in the Active Power mode. The device
Device Internal Reset
consumes I , as specified in Table 14. to Table
CC
19.
In order to prevent inadvertent Write operations
during Power-up, a Power On Reset (POR) circuit
is included. At Power-up (continuous rise up of
When Chip Select (S) is High, the device is dese-
lected. If an Erase/Write cycle is not currently in
progress, the device then goes into the Standby
Power mode, and the device consumption drops
V
), the device will not respond to any instruction
CC
until the V
has reached the Power On Reset
CC
to I
.
threshold voltage (this threshold is lower than the
minimum V operating voltage defined in Tables
CC1
CC
10, 11 and 13). When V
POR threshold, the device is reset and is the fol-
lowing state:
has passed over the
Hold Condition
CC
The Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
–
–
Standby Power mode
deselected (after Power-up, a falling edge is
required on Chip Select (S) before any
instructions can be started).
–
not in the Hold Condition
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
Status register state:
–
–
the Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0
Normally, the device is kept selected, for the whole
duration of the Hold condition. Deselecting the de-
vice while it is in the Hold condition, has the effect
of resetting the state of the device, and this mech-
anism can be used if it is required to reset any pro-
cesses that had been in progress.
The Hold condition starts when the Hold (HOLD)
signal is driven Low at the same time as Serial
Clock (C) already being Low.
The SRWD, BP1 and BP0 bits of the Status Reg-
ister are unchanged from the previous power-
down (they are non-volatile bits).
Prior to selecting and issuing instructions to the
memory, a valid and stable V
applied. This voltage must remain stable and valid
until the end of the transmission of the instruction
and, for a Write instruction, until the completion of
voltage must be
CC
The Hold condition ends when the Hold (HOLD)
signal is driven High at the same time as Serial
Clock (C) already being Low.
the internal write cycle (t ).
W
8/39
M95160, M95080
Status Register
plications that could experience problems if
memory bytes are corrupted. Consequently, the
device features the following data protection
mechanisms:
Figure 6. shows the position of the Status Register
in the control logic of the device. The Status Reg-
ister contains a number of status and control bits
that can be read or set (as appropriate) by specific
instructions.
■
Write and Write Status Register instructions
are checked that they consist of a number of
clock pulses that is a multiple of eight, before
they are accepted for execution.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle.
■
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
–
–
Power-up
Write Disable (WRDI) instruction
completion
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
–
–
Write Status Register (WRSR) instruction
completion
Write (WRITE) instruction completion
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP1, BP0) become
read-only bits.
■
■
The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only.
This is the Software Protected Mode (SPM).
The Write Protect (W) signal allows the Block
Protect (BP1, BP0) bits to be protected. This is
the Hardware Protected Mode (HPM).
For any instruction to be accepted, and executed,
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) for the last bit of the in-
struction, and before the next rising edge of Serial
Clock (C).
Table 3. Status Register Format
b7
b0
SRWD
0
0
0
BP1 BP0 WEL WIP
Two points need to be noted in the previous sen-
tence:
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
–
The ‘last bit of the instruction’ can be the
eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction
(except for Read Status Register (RDSR) and
Read (READ) instructions).
–
The ‘next rising edge of Serial Clock (C)’ might
(or might not) be the next bus transaction for
some other device on the SPI bus.
Data Protection and Protocol Control
Non-volatile memory devices can be used in envi-
ronments that are particularly noisy, and within ap-
Table 4. Write-Protected Block Size
Status Register Bits
Protected Block
Array Addresses Protected
BP1
BP0
M95160
none
M95080
none
0
0
1
1
0
1
0
1
none
Upper quarter
Upper half
0600h - 07FFh
0400h - 07FFh
0000h - 07FFh
0300h - 03FFh
0200h - 03FFh
0000h - 03FFh
Whole memory
9/39
M95160, M95080
MEMORY ORGANIZATION
The memory is organized as shown in Figure 6.
Figure 6. Block Diagram
HOLD
High Voltage
Generator
W
S
Control Logic
C
D
Q
I/O Shift Register
Address Register
and Counter
Data
Register
Status
Register
Size of the
Read only
EEPROM
area
1 Page
X Decoder
AI01272C
10/39
M95160, M95080
INSTRUCTIONS
Each instruction starts with a single-byte code, as
summarized in Table 5.
If an invalid instruction is sent (one not contained
in Table 5.), the device automatically deselects it-
self.
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.
As shown in Figure 7., to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D). The device then enters a wait
state. It waits for the device to be deselected, by
Chip Select (S) being driven High.
Table 5. Instruction Set
Instruc
tion
Instruction
Format
Description
WREN Write Enable
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
WRDI
RDSR
Write Disable
Read Status Register
WRSR Write Status Register
READ Read from Memory Array
WRITE Write to Memory Array
Figure 7. Write Enable (WREN) Sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI02281E
11/39
M95160, M95080
Write Disable (WRDI)
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events:
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in Figure 8., to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).
–
–
–
–
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure 8. Write Disable (WRDI) Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03750D
12/39
M95160, M95080
Read Status Register (RDSR)
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
These bits are written with the Write Status Regis-
ter (WRSR) instruction. When one or both of the
Block Protect (BP1, BP0) bits is set to 1, the rele-
vant memory area (as defined in Table 3.) be-
comes protected against Write (WRITE)
instructions. The Block Protect (BP1, BP0) bits
can be written provided that the Hardware Protect-
ed mode has not been set.
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Write or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is rec-
ommended to check the Write In Progress (WIP)
bit before sending a new instruction to the device.
It is also possible to read the Status Register con-
tinuously, as shown in Figure 9.
The status and control bits of the Status Register
are as follows:
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP1, BP0) be-
come read-only bits and the Write Status Register
(WRSR) instruction is no longer accepted for exe-
cution.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle
is in progress, when reset to 0 no such cycle is in
progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write or Write Status Register in-
struction is accepted.
Figure 9. Read Status Register (RDSR) Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031E
13/39
M95160, M95080
Write Status Register (WRSR)
(WIP) bit. The Write In Progress (WIP) bit is 1 dur-
ing the self-timed Write Status Register cycle, and
is 0 when it is completed. When the cycle is com-
pleted, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that is to be treated as read-only, as defined
in Table 3.
The Write Status Register (WRSR) instruction also
allows the user to set or reset the Status Register
Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected Mode (HPM). The Write Status Register
(WRSR) instruction is not executed once the Hard-
ware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable
(SRWD) and Block Protect (BP1, BP0) bits are fro-
zen at their current values from just before the
start of the execution of Write Status Register
(WRSR) instruction. The new, updated, values
take effect at the moment of completion of the ex-
ecution of Write Status Register (WRSR) instruc-
tion.
The Write Status Register (WRSR) instruction al-
lows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in Figure 10.
The Write Status Register (WRSR) instruction has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) that latches in the eighth
bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status
Register (WRSR) instruction is not executed. As
soon as Chip Select (S) is driven High, the self-
timed Write Status Register cycle (whose duration
is t ) is initiated. While the Write Status Register
W
cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress
Table 6. Protection Modes
Memory Content
W
Signal
SRWD
Bit
Write Protection of the
Status Register
Mode
(1)
(1)
Protected Area
Unprotected Area
1
0
0
0
Status Register is Writable
Software (if the WREN instruction
Protected has set the WEL bit)
Ready to accept Write
instructions
Write Protected
(SPM)
The values in the BP1 and
BP0 bits can be changed
1
1
Status Register is
Hardware Hardware write protected
Protected The values in the BP1 and Write Protected
Ready to accept Write
instructions
0
1
(HPM)
BP0 bits cannot be
changed
Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 6..
The protection features of the device are summa-
rized in Table 4.
need to be considered, depending on the state of
Write Protect (W):
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, regardless of whether Write Protect (W)
is driven High or Low.
–
If Write Protect (W) is driven High, it is
possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit
has previously been set by a Write Enable
(WREN) instruction.
If Write Protect (W) is driven Low, it is not
possible to write to the Status Register even if
the Write Enable Latch (WEL) bit has
–
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the
14/39
M95160, M95080
Status Register are rejected, and are not
accepted for execution). As a consequence,
all the data bytes in the memory area that are
software protected (SPM) by the Block Protect
(BP1, BP0) bits of the Status Register, are
also hardware protected against data
modification.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP1, BP0) bits of
the Status Register, can be used.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered:
–
by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low
or by driving Write Protect (W) Low after
setting the Status Register Write Disable
(SRWD) bit.
Table 7. Address Range Bits
Device
M95160
M95080
–
Address Bits
A10-A0
A9-A0
Note: b15 to b11 are Don’t Care on the M95160.
b15 to b10 are Don’t Care on the M95080.
Figure 10. Write Status Register (WRSR) Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
15/39
M95160, M95080
Read from Memory Array (READ)
When the highest address is reached, the address
counter rolls over to zero, allowing the Read cycle
to be continued indefinitely. The whole memory
can, therefore, be read with a single READ instruc-
tion.
The Read cycle is terminated by driving Chip Se-
lect (S) High. The rising edge of the Chip Select
(S) signal can occur at any time during the cycle.
As shown in Figure 11., to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and address bytes are
then shifted in, on Serial Data Input (D). The ad-
dress is loaded into an internal address register,
and the byte of data at that address is shifted out,
on Serial Data Output (Q).
The first byte addressed can be any byte within
any page.
The instruction is not accepted, and is not execut-
ed, if a Write cycle is currently in progress.
If Chip Select (S) continues to be driven Low, the
internal address register is automatically incre-
mented, and the byte of data at the new address is
shifted out.
Figure 11. Read from Memory Array (READ) Sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
AI01793D
Note: Depending on the memory size, as shown in Table 7., the most significant address bits are Don’t Care.
16/39
M95160, M95080
Write to Memory Array (WRITE)
Each time a new data byte is shifted in, the least
significant bits of the internal address counter are
incremented. If the number of data bytes sent to
the device exceeds the page boundary, the inter-
nal address counter rolls over to the beginning of
the page, and the previous data there are overwrit-
ten with the incoming data. (The page size of
these devices is 32 bytes).
As shown in Figure 12., to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High at a byte boundary of the input data.
In the case of Figure 12., this occurs after the
eighth bit of the data byte has been latched in, in-
dicating that the instruction is being used to write
a single byte. The self-timed Write cycle starts,
The instruction is not accepted, and is not execut-
ed, under the following conditions:
–
if the Write Enable Latch (WEL) bit has not
been set to 1 (by executing a Write Enable
instruction just before)
and continues for a period t
(as specified in Ta-
WC
–
–
if a Write cycle is already in progress
ble 22. to Table 25.), at the end of which the Write
in Progress (WIP) bit is reset to 0.
if the device has not been deselected, by Chip
Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last
data byte that has been latched in)
If, though, Chip Select (S) continues to be driven
Low, as shown in Figure 13., the next byte of input
data is shifted in, so that more than a single byte,
starting from the given address towards the end of
the same page, can be written in a single internal
Write cycle.
–
if the addressed page is in the region
protected by the Block Protect (BP1 and BP0)
bits.
Figure 12. Byte Write (WRITE) Sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
Data Byte
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
Q
High Impedance
AI01795D
Note: Depending on the memory size, as shown in Table 7., the most significant address bits are Don’t Care.
17/39
M95160, M95080
Figure 13. Page Write (WRITE) Sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
D
Instruction
16-Bit Address
Data Byte 1
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
S
C
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
0
7
6
5
4
3
2
0
6
5
4
3
2
0
1
1
1
D
AI01796D
Note: Depending on the memory size, as shown in Table 7., the most significant address bits are Don’t Care.
DELIVERY STATE
Initial Delivery State
The device is delivered with the memory array set
at all 1s (FFh). The Status Register Write Disable
(SRWD) and Block Protect (BP1 and BP0) bits are
initialized to 0.
18/39
M95160, M95080
MAXIMUM RATING
Stressing the device outside the ratings listed in
Table 8. may cause permanent damage to the de-
vice. These are stress ratings only, and operation
of the device at these, or any other conditions out-
side those indicated in the Operating sections of
this specification, is not implied. Exposure to Ab-
solute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to
the STMicroelectronics SURE Program and other
relevant quality documents.
Table 8. Absolute Maximum Ratings
Symbol
Parameter
Ambient Operating Temperature
Min.
–40
–65
Max.
Unit
T
A
130
T
Storage Temperature
150
°C
STG
(1)
TLEAD
VO
Lead Temperature during Soldering
Output Voltage
°C
V
See note
–0.50
–0.50
–0.50
V
CC+0.6
6.5
VI
Input Voltage
V
V
Supply Voltage
6.5
V
CC
(2)
VESD
–4000
4000
V
Electrostatic Discharge Voltage (Human Body model)
®
Note: 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)
19/39
M95160, M95080
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 9. Operating Conditions (M95160 and M95080)
Symbol
Parameter
Min.
4.5
Max.
5.5
Unit
V
V
Supply Voltage
CC
Ambient Operating Temperature (Device Grade 6)
Ambient Operating Temperature (Device Grade 3)
–40
–40
85
°C
°C
TA
125
Table 10. Operating Conditions (M95160-W and M95080-W)
Symbol
Parameter
Min.
2.5
Max.
5.5
Unit
V
V
Supply Voltage
CC
Ambient Operating Temperature (Device Grade 6)
Ambient Operating Temperature (Device Grade 3)
–40
–40
85
°C
°C
TA
125
Table 11. Operating Conditions (M95160-R and M95080-R)
1
1
Symbol
Unit
V
Parameter
Min.
1.8
Max.
5.5
V
Supply Voltage
Ambient Operating Temperature
CC
TA
–40
85
°C
Note: 1. This product is under development. For more information, please contact your nearest ST sales office.
Table 12. Operating Conditions (M95160-S and M95080-S)
1
1
Symbol
Unit
V
Parameter
Min.
1.65
–40
Max.
5.5
V
Supply Voltage
Ambient Operating Temperature
CC
TA
85
°C
Note: 1. This product is under development. For more information, please contact your nearest ST sales office.
Table 13. AC Measurement Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
C
Load Capacitance
30
pF
ns
V
L
Input Rise and Fall Times
50
0.2V to 0.8V
Input Pulse Voltages
CC
CC
0.3V to 0.7V
Input and Output Timing Reference Voltages
V
CC
CC
Note: Output Hi-Z is defined as the point where data out is no longer driven.
20/39
M95160, M95080
Figure 14. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI00825B
Table 14. Capacitance
Symbol
Parameter
Test Condition
= 0V
Min.
Max.
Unit
pF
C
Output Capacitance (Q)
Input Capacitance (D)
Input Capacitance (other pins)
V
8
8
6
OUT
OUT
V
= 0V
= 0V
pF
IN
IN
C
IN
V
pF
Note: Sampled only, not 100% tested, at T =25°C and a frequency of 5MHz.
A
21/39
M95160, M95080
Table 15. DC Characteristics (M95160 and M95080, Device Grade 3)
Symbol
Parameter
Test Condition
Min.
Max.
± 2
Unit
µA
I
LI
V
= V or V
IN SS CC
Input Leakage Current
Output Leakage Current
I
LO
S = V , V
= V or V
CC
± 2
µA
CC OUT
SS
C = 0.1V /0.9V at 2MHz,
CC
CC
4
3
mA
mA
µA
V
= 5V, Q = open, Process “Blank”
CC
I
Supply Current
CC
C = 0.1V /0.9V at 5MHz,
CC
CC
V
= 5V, Q = open, Process /W or /S
CC
S = V , V = 5V,
CC
CC
10
V
= V or V
Process “Blank”
CC,
IN
SS
Supply Current
(Standby)
I
CC1
S = V , V = 5V,
CC
CC
5
µA
V
= V or V , Process /W or /S
SS CC
IN
V
0.3 V
Input Low Voltage
Input High Voltage
Output Low Voltage
–0.45
0.7 V
V
V
V
IL
CC
V
V
+1
CC
IH
CC
(1)
(1)
I
= 2mA, V = 5V
0.4
V
V
OL
CC
OL
I
= –2mA, V = 5V
0.8 V
CC
Output High Voltage
V
OH
CC
OH
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
Table 16. DC Characteristics (M95160 and M95080, Device Grade 6)
Symbol
Parameter
Test Condition
Min.
Max.
± 2
Unit
µA
I
LI
V
= V or V
IN SS CC
Input Leakage Current
Output Leakage Current
I
LO
S = V , V
= V or V
CC
± 2
µA
CC OUT
SS
C = 0.1V /0.9V at 5MHz,
CC
CC
4
5
mA
mA
mA
µA
V
= 5V, Q = open, Process L
CC
C = 0.1V /0.9V at 10MHz,
CC
CC
I
Supply Current
CC
V
= 5V, Q = open, Process W or SA
CC
C = 0.1V /0.9V at 20MHz,
CC
CC
10
10
2
(2)
V
= 5V, Q = open, Process GB or SB
CC
S = V , V = 5V,
CC
CC
V
= V or V , Process L
SS CC
IN
S = V , V = 5V,
CC
CC
Supply Current
(Standby)
µA
I
CC1
V
= V or V , Process W or SA
SS CC
IN
S = V , V = 5V,
CC
CC
2
µA
(2)
V
= V or V , Process GB or SB
SS CC
IN
V
0.3 V
Input Low Voltage
Input High Voltage
Output Low Voltage
–0.45
0.7 V
V
V
V
IL
CC
V
V
+1
CC
IH
CC
(1)
(1)
I
= 2 mA, V = 5V
0.4
V
V
OL
CC
OL
I
= –2 mA, V = 5V
0.8 V
CC
Output High Voltage
V
OH
CC
OH
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Preliminary data
22/39
M95160, M95080
Table 17. DC Characteristics (M95160-W and M95080-W, Device Grade 3)
Symbol
Parameter
Test Condition
Max.
± 2
Unit
µA
Min.
I
LI
V
= V or V
IN SS CC
Input Leakage Current
Output Leakage Current
I
LO
S = V , V
= V or V
CC
± 2
µA
CC OUT
SS
C = 0.1V /0.9V at 2MHz,
CC
CC
5
2
2
mA
mA
µA
V
= 2.5V, Q = open, Process “Blank”
CC
I
Supply Current
CC
C = 0.1V /0.9V at 5MHz,
CC
CC
V
= 2.5V, Q = open, Process /W or /S
CC
S = V , V = 2.5V, V = V or V ,
CC
CC
CC
IN
SS
Process “Blank”
S = V , V = 2.5V, V = V or V ,
CC
Supply Current
(Standby)
I
CC1
CC
CC
IN
SS
2
µA
Process /W or /S
V
0.3 V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.45
0.7 V
V
V
V
V
IL
CC
V
V
V
+1
CC
IH
CC
I
I
= 1.5mA, V = 2.5V
0.4
OL
OL
CC
V
OH
= –0.4mA, V = 2.5V
0.8 V
CC
OH
CC
Table 18. DC Characteristics (M95160-W and M95080-W, Device Grade 6)
Symbol
Parameter
Test Condition
Min.
Max.
± 2
Unit
µA
I
LI
V
= V or V
IN SS CC
Input Leakage Current
Output Leakage Current
I
LO
S = V , V
= V or V
CC
± 2
µA
CC OUT
SS
C = 0.1V /0.9V at 2MHz,
CC
CC
2
2
5
2
1
mA
mA
mA
µA
V
= 2.5V, Q = open, Process L
CC
C = 0.1V /0.9V at 5MHz,
CC
CC
I
Supply Current
CC
V
= 2.5V, Q = open, Process W or SA
CC
C = 0.1V /0.9V at 10MHz,
CC
CC
(1)
V
= 2.5V, Q = open, Process GB or SB
CC
S = V , V = 2.5V
CC
CC
V
= V or V , Process L
SS CC
IN
S = V , V = 2.5V
CC
CC
Supply Current
(Standby)
µA
I
CC1
V
= V or V , Process W or SA
SS CC
IN
S = V , V = 2.5V
CC
CC
1
µA
(1)
V
= V or V , Process GB or SB
SS CC
IN
V
0.3 V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.45
0.7 V
V
V
V
V
IL
CC
V
V
V
+1
CC
IH
CC
I
= 1.5mA, V = 2.5V
0.4
OL
OL
CC
V
OH
I
= –0.4mA, V = 2.5V
0.8 V
CC
OH
CC
Note: 1. Preliminary data
23/39
M95160, M95080
Table 19. DC Characteristics (M95160-R and M95080-R) (1
Symbol
Parameter
Test Condition
Unit
µA
Min.
Max.
± 2
I
LI
V
= V or V
IN SS CC
Input Leakage Current
Output Leakage Current
I
LO
S = V , V
= V or V
CC
± 2
µA
CC OUT
SS
C = 0.1V /0.9V at 5MHz,
CC
CC
I
Supply Current
3
mA
µA
CC
V
= 1.8 V, Q = open
CC
Supply Current
(Standby)
I
S = V , V = V or V , V = 1.8V
CC IN SS CC CC
0.5
CC1
V
0.3 V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.45
0.7 V
V
V
V
V
IL
CC
V
V
+1
CC
IH
CC
V
OL
I
I
= 0.15 mA, V = 1.8 V
0.3
OL
CC
V
OH
= –0.1 mA, V = 1.8 V
0.8 V
CC
OH
CC
Note: 1. Preliminary data
Table 20. DC Characteristics (M95160-S and M95080-S) (1)
Symbol
Parameter
Test Condition
Unit
µA
Min.
Max.
± 2
I
V
= V or V
IN SS CC
Input Leakage Current
Output Leakage Current
LI
I
S = V , V
= V or V
CC
± 2
µA
LO
CC OUT
SS
C = 0.1V /0.9V at 2MHz,
CC
CC
I
Supply Current
2
mA
µA
CC
V
= 1.65 V, Q = open
CC
Supply Current
(Standby)
I
S = V , V = V or V , V = 1.65V
CC IN SS CC CC
0.5
CC1
V
0.3 V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.45
0.7 V
V
V
V
V
IL
CC
V
V
+1
CC
IH
CC
V
OL
I
I
= 0.15 mA, V = 1.65V
0.3
OL
CC
V
OH
= –0.1 mA, V = 1.65V
0.8 V
CC
OH
CC
Note: 1. Preliminary data
24/39
M95160, M95080
Table 21. AC Characteristics (M95160 and M95080, Device Grade 3)
Test conditions specified in Table 13. and Table 9.
Process “Blank”
Process /W or /S
Symbol
Alt.
Parameter
Unit
Min.
D.C.
200
200
200
200
200
Max.
Min.
D.C.
90
Max.
f
f
Clock Frequency
2
5
MHz
ns
C
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
90
ns
SHCH
t
t
100
90
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
CHSH
t
90
ns
CHSL
(1)
t
200
200
90
90
ns
t
CLH
CH
(1)
t
Clock Low Time
Clock Rise Time
ns
µs
t
CLL
CL
(2)
(2)
t
1
1
1
1
t
t
RC
CLCH
t
FC
Clock Fall Time
µs
ns
ns
ns
ns
ns
CHCL
t
t
DSU
Data In Setup Time
40
50
140
90
0
20
30
70
40
0
DVCH
t
t
t
Data In Hold Time
CHDX
HHCH
DH
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock Low Set-up Time before HOLD Active
t
HLCH
t
CLHL
Clock Low Set-up Time before HOLD not
Active
t
0
0
ns
CLHH
(2)
t
Output Disable Time
Clock Low to Output Valid
Output Hold Time
250
150
100
60
ns
ns
ns
ns
t
DIS
SHQZ
t
t
CLQV
V
t
t
0
0
CLQX
HO
RO
(2)
(2)
t
Output Rise Time
100
100
100
250
10
50
50
50
100
5
t
t
QLQH
t
Output Fall Time
ns
ns
FO
QHQL
t
t
HOLD High to Output Valid
HOLD Low to Output High-Z
Write Time
HHQV
LZ
(2)
t
ns
t
HZ
HLQZ
t
t
WC
ms
W
Note: 1. t + t must never be lower than the shortest possible clock period, 1/f (max).
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
25/39
M95160, M95080
Table 22. AC Characteristics (M95160 and M95080, Device Grade 6)
Test conditions specified in Table 13. and Table 9.
(3)
Process L
Process W or SA
Process GB or SB
Symbol Alt.
Parameter
Unit
Min.
Max.
Min.
D.C.
15
Max.
Min.
D.C.
15
Max.
f
f
SCK
Clock Frequency
D.C.
90
5
10
20
MHz
ns
C
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
CSS1
t
90
15
15
ns
SHCH
CSS2
t
t
100
90
40
20
ns
SHSL
CHSH
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
25
15
ns
t
90
15
15
ns
CHSL
(1)
t
90
40
40
20
20
ns
t
CLH
CH
(1)
t
Clock Low Time
Clock Rise Time
90
ns
µs
t
CL
CLL
(2)
(2)
t
1
1
1
1
2
2
t
t
RC
CLCH
t
Clock Fall Time
µs
ns
ns
FC
CHCL
t
t
DSU
Data In Setup Time
Data In Hold Time
20
30
15
15
5
DVCH
t
t
t
10
CHDX
DH
Clock Low Hold Time
after HOLD not Active
70
40
0
15
20
0
15
15
0
ns
ns
ns
HHCH
Clock Low Hold Time
after HOLD Active
t
HLCH
Clock Low Set-up Time
before HOLD Active
t
CLHL
Clock Low Set-up Time
before HOLD not Active
t
0
0
0
ns
ns
ns
CLHH
(2)
t
Output Disable Time
100
60
25
35
20
20
t
DIS
SHQZ
Clock Low to Output
Valid
t
t
V
CLQV
t
t
Output Hold Time
Output Rise Time
Output Fall Time
0
0
0
ns
ns
ns
CLQX
HO
RO
(2)
(2)
t
50
50
20
20
20
20
t
t
QLQH
QHQL
t
t
FO
HOLD High to Output
Valid
t
50
25
20
ns
HHQV
LZ
HOLD Low to Output
High-Z
(2)
t
100
10
35
5
20
5
ns
t
HZ
HLQZ
t
t
WC
Write Time
ms
W
Note: 1. t + t must never be lower than the shortest possible clock period, 1/f (max).
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
3. Preliminary data
26/39
M95160, M95080
Table 23. AC Characteristics (M95160-W and M95080-W, Device Grade 3)
Test conditions specified in Table 13. and Table 10.
Process “Blank”
Process /W or /S
Unit
Symbol Alt.
Parameter
Min.
D.C.
200
200
200
200
200
Max.
Min.
D.C.
90
Max.
f
f
SCK
Clock Frequency
2
5
MHz
ns
C
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
CSS1
CSS2
t
90
ns
SHCH
t
t
100
90
ns
SHSL
CHSH
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
t
90
ns
CHSL
(1)
t
200
200
90
90
ns
t
CLH
CH
(1)
t
Clock Low Time
Clock Rise Time
ns
µs
t
CL
CLL
(2)
(2)
t
1
1
1
1
t
t
RC
CLCH
t
Clock Fall Time
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FC
CHCL
t
t
DSU
Data In Setup Time
40
50
140
90
0
20
30
70
40
0
DVCH
t
t
t
Data In Hold Time
CHDX
HHCH
DH
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock Low Set-up Time before HOLD Active
Clock Low Set-up Time before HOLD not Active
Output Disable Time
t
HLCH
t
CLHL
CLHH
t
0
0
(2)
t
250
150
100
60
t
DIS
SHQZ
t
t
Clock Low to Output Valid
Output Hold Time
CLQV
V
t
t
0
0
CLQX
HO
RO
(2)
(2)
t
Output Rise Time
100
100
100
250
10
50
50
50
100
5
t
t
QLQH
t
Output Fall Time
ns
ns
FO
QHQL
t
t
HOLD High to Output Valid
HOLD Low to Output High-Z
Write Time
HHQV
LZ
(2)
t
HZ
ns
t
HLQZ
t
t
WC
ms
W
Note: 1. t + t must never be lower than the shortest possible clock period, 1/f (max).
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
27/39
M95160, M95080
Table 24. AC Characteristics (M95160-W and M95080-W, Device Grade 6)
Test conditions specified in Table 13. and Table 10.
(3)
Process L
Process W or SA
Process GB or SB
Symbol Alt.
Parameter
Unit
Min.
Max.
Min.
D.C.
90
Max.
Min.
D.C.
30
Max.
f
f
SCK
Clock Frequency
D.C.
200
2
5
10
MHz
ns
C
t
t
t
S Active Setup Time
SLCH
CSS1
CSS2
S Not Active Setup
Time
t
200
90
30
ns
SHCH
t
t
S Deselect Time
200
200
200
200
100
90
40
30
30
40
ns
ns
ns
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
CHSH
t
90
CHSL
(1)
t
90
t
CLH
CH
(1)
t
Clock Low Time
Clock Rise Time
200
90
40
ns
µs
t
CLL
CL
(2)
(2)
t
1
1
1
1
2
2
t
t
RC
CLCH
t
Clock Fall Time
µs
ns
ns
FC
CHCL
t
t
DSU
Data In Setup Time
Data In Hold Time
40
50
20
30
10
10
DVCH
t
t
t
CHDX
DH
Clock Low Hold Time
after HOLD not Active
140
90
0
70
40
0
30
30
0
ns
ns
ns
HHCH
Clock Low Hold Time
after HOLD Active
t
HLCH
Clock Low Set-up Time
before HOLD Active
t
CLHL
Clock Low Set-up Time
before HOLD not Active
t
0
0
0
ns
ns
ns
CLHH
(2)
t
Output Disable Time
250
150
100
60
40
40
t
t
DIS
SHQZ
Clock Low to Output
Valid
t
t
CLQV
V
t
t
Output Hold Time
Output Rise Time
Output Fall Time
0
0
0
ns
ns
ns
CLQX
HO
(2)
(2)
t
100
100
50
50
40
40
RO
QLQH
QHQL
t
t
t
FO
HOLD High to Output
Valid
t
100
50
40
ns
HHQV
LZ
HOLD Low to Output
High-Z
(2)
t
250
10
100
5
40
5
ns
t
HZ
HLQZ
t
t
WC
Write Time
ms
W
Note: 1. t + t must never be lower than the shortest possible clock period, 1/f (max).
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
3. Preliminary data
28/39
M95160, M95080
Table 25. AC Characteristics (M95160-R and M95080-R)
Test conditions specified in Table 13. and Table 11.
(3)
Process GB or SB
Symbol
Alt.
Parameter
Unit
Min.
D.C.
60
Max.
f
C
f
Clock Frequency
5
MHz
ns
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
60
ns
SHCH
t
t
90
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
60
ns
CHSH
t
60
ns
CHSL
(1)
t
80
80
ns
t
CLH
CH
(1)
t
Clock Low Time
Clock Rise Time
ns
µs
t
CLL
CL
(2)
(2)
t
2
2
t
t
RC
CLCH
t
FC
Clock Fall Time
µs
ns
ns
ns
ns
0
CHCL
t
t
DSU
Data In Setup Time
Data In Hold Time
20
20
60
60
0
DVCH
t
t
t
DH
CHDX
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock Low Set-up Time before HOLD Active
Clock Low Set-up Time before HOLD not Active
Output Disable Time
HHCH
t
HLCH
t
CLHL
CLHH
t
0
0
(2)
t
80
80
ns
ns
ns
ns
t
DIS
SHQZ
t
t
V
Clock Low to Output Valid
CLQV
t
t
t
Output Hold Time
0
CLQX
HO
RO
(2)
(2)
Output Rise Time
80
80
80
80
5
t
t
QLQH
t
Output Fall Time
ns
ns
ns
ms
FO
QHQL
t
t
HOLD High to Output Valid
HOLD Low to Output High-Z
Write Time
HHQV
LZ
(2)
t
HZ
t
HLQZ
t
W
t
WC
Note: 1. t + t must never be lower than the shortest possible clock period, 1/f (max).
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
3. Preliminary data
29/39
M95160, M95080
Table 26. AC Characteristics (M95160-S and M95080-S)
Test conditions specified in Table 13. and Table 11.
(3)
Process GB or SB
Symbol
Alt.
Parameter
Unit
Min.
D.C.
150
150
200
150
150
Max.
f
f
Clock Frequency
2
MHz
ns
C
SCK
CSS1
CSS2
t
t
t
S Active Setup Time
S Not Active Setup Time
S Deselect Time
SLCH
t
ns
SHCH
t
t
ns
SHSL
CS
t
t
CSH
S Active Hold Time
S Not Active Hold Time
Clock High Time
ns
CHSH
t
ns
CHSL
(1)
t
200
200
ns
t
CLH
CH
(1)
t
Clock Low Time
Clock Rise Time
ns
µs
t
CL
CLL
(2)
(2)
t
2
2
t
RC
CLCH
t
FC
Clock Fall Time
µs
ns
ns
ns
ns
0
t
CHCL
t
t
DSU
Data In Setup Time
50
50
150
150
0
DVCH
t
t
t
DH
Data In Hold Time
CHDX
Clock Low Hold Time after HOLD not Active
Clock Low Hold Time after HOLD Active
Clock Low Set-up Time before HOLD Active
Clock Low Set-up Time before HOLD not Active
Output Disable Time
HHCH
t
HLCH
t
CLHL
CLHH
t
0
0
(2)
t
200
200
ns
ns
ns
ns
t
DIS
SHQZ
t
t
V
Clock Low to Output Valid
Output Hold Time
CLQV
t
t
t
0
CLQX
HO
RO
(2)
(2)
Output Rise Time
200
200
200
200
10
t
t
QLQH
t
Output Fall Time
ns
ns
FO
QHQL
t
t
HOLD High to Output Valid
HOLD Low to Output High-Z
Write Time
HHQV
LZ
(2)
t
HZ
ns
t
HLQZ
t
W
t
WC
ms
Note: 1. t + t must never be lower than the shortest possible clock period, 1/f (max).
CH
CL
C
2. Value guaranteed by characterization, not 100% tested in production.
3. Preliminary data
30/39
M95160, M95080
Figure 15. Serial Input Timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
High Impedance
AI01447C
Figure 16. Hold Timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHHQV
tHLQZ
Q
D
HOLD
AI01448B
31/39
M95160, M95080
Figure 17. Output Timing
S
tCH
C
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
tCLQX
LSB OUT
Q
D
tQLQH
tQHQL
ADDR.LSB IN
AI01449D
32/39
M95160, M95080
PACKAGE MECHANICAL
Figure 18. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
A2
A
C
B
ddd
e
D
8
1
E
H
A1
α
L
SO-A
Note: Drawing is not to scale.
Table 27. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.75
0.25
1.65
0.51
0.25
5.00
0.10
4.00
–
Typ
Max
0.069
0.010
0.065
0.020
0.010
0.197
0.004
0.157
–
A
A1
A2
B
1.35
0.053
0.004
0.043
0.013
0.007
0.189
0.10
1.10
0.33
C
0.19
D
4.80
ddd
E
3.80
–
0.150
–
e
1.27
0.050
H
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
h
L
α
N
8
8
33/39
M95160, M95080
Figure 19. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Package Outline
e
b
D
L1
L3
E
E2
L
A
D2
ddd
A1
UFDFPN-01
Note: 1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to V . It must not be allowed to be connected to
SS
any other voltage or signal line on the PCB, for example during the soldering process.
Table 28. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Package Mechanical Data
millimeters
Min.
inches
Min.
Symbol
Typ.
Max.
0.60
0.05
0.30
Typ.
Max.
0.024
0.002
0.012
A
A1
b
0.55
0.50
0.022
0.020
0.000
0.008
0.00
0.25
2.00
0.20
0.010
0.079
D
D2
ddd
E
1.55
1.65
0.05
0.061
0.065
0.002
3.00
0.118
E2
e
0.15
–
0.25
–
0.006
–
0.010
–
0.50
0.45
0.020
0.018
L
0.40
0.50
0.15
0.016
0.020
0.006
L1
L3
N
0.30
8
0.012
8
34/39
M95160, M95080
Figure 20. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
Note: Drawing is not to scale.
Table 29. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
millimeters
Min
inches
Symbol
Typ
Max
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
Typ
Min
Max
A
A1
A2
b
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8
8°
0°
8
8°
N
35/39
M95160, M95080
Figure 21. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size,
Package Outline
D
8
1
5
4
c
E1
E
α
A1
L
A
A2
L1
CP
b
e
TSSOP8BM
Note: Drawing is not to scale.
Table 30. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size,
Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.100
0.150
0.950
0.400
0.230
3.100
5.150
3.100
–
Typ
Max
A
A1
A2
b
0.0433
0.0059
0.0374
0.0157
0.0091
0.1220
0.2028
0.1220
–
0.050
0.750
0.250
0.130
2.900
4.650
2.900
–
0.0020
0.0295
0.0098
0.0051
0.1142
0.1831
0.1142
–
0.850
0.0335
c
D
3.000
4.900
3.000
0.650
0.1181
0.1929
0.1181
0.0256
E
E1
e
CP
L
0.100
0.700
0.0039
0.0276
0.550
0.950
0.400
0.0217
0.0374
0.0157
L1
α
0°
8
6°
0°
8
6°
N
36/39
M95160, M95080
PART NUMBERING
Table 31. Ordering Information Scheme
Example:
M95160
–
W MN
6
T
P
/W
Device Type
M95 = SPI serial access EEPROM
Device Function
160 = 16 Kbit (2048 x 8)
080 = 8 Kbit (1024 x 8)
Operating Voltage
blank = V = 4.5 to 5.5V
CC
W = V = 2.5 to 5.5V
CC
R = V = 1.8 to 5.5V
CC
S = V = 1.65 to 5.5V
CC
Package
MN = SO8 (150 mil width)
(2)
DW = TSSOP8
(3)
DS = TSSOP8 (3x3mm body size, MSOP)
MB = MLP8 (UFDFPN8)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
(1)
3 = Device tested with High Reliability Certified Flow
Automotive temperature range (–40 to 125 °C)
.
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
G or P = RoHS compliant
(4)
Process
Blank (L) = F6SP26%
/W or /S = F6SP36%
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-
tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
2. TSSOP8, 169 mil width, package is not available for the M95160 identified by the process identification letter L.
3. TSSOP8, 3x3mm body size, package is available for the M95080 series only.
4. Blank, /W or /S processes apply only to Range 3 devices.
For Range 6 devices, process letters (L, W, SA, SB, GA or GB) do not appear in the Ordering Information but only appear on the
device package (marking) and on the shipment box. Please contact your nearest ST Sales Office.
For more information on how to identify products by the Process Identification Letter, please refer to AN2043: Serial EEPROM De-
vice Marking.
37/39
M95160, M95080
REVISION HISTORY
Table 32. Document Revision History
Date
Rev.
Description of Revision
19-Jul-2001
06-Feb-2002
18-Oct-2002
04-Nov-2002
13-Nov-2002
21-Nov-2003
1.0 Document written from previous M95640/320/160/080 datasheet
1.1 Announcement made of planned upgrade to 10MHz clock for the 5V, –40 to 85°C, range
1.2 TSSOP8 (3x3mm body size, MSOP8) package added
1.3 New products, identified by the process letter W, added
1.4 Correction to footnote in Ordering Information table
Table of contents, and Pb-free options added. V (min) improved to –0.45V
2.0
3.0
IL
MLP8 package added. Absolute Maximum Ratings for V (min) and V (min) improved.
IO
CC
Soldering temperature information clarified for RoHS compliant devices. Device Grade 3
clarified, with reference to HRCF and automotive environments. Process identification letter
“G” information added. SO8 narrow and TSSOP8 Package mechanical specifications
updated.
08-Jun-2004
07-Oct-2004
21-Sept-2005
Product List summary table added. AEC-Q100-002 compliance. tHHQX corrected to tHHQV.
10MHz, 5ms Write is now the present product. tCH+tCL<1/fC constraint clarified
4.0
Added 20MHz and -S product information. Removed DIP package. Info on Pull-up resistors,
VCC lines and Note 2. added to Figure 4., Bus Master and Memory Devices on the SPI Bus.
5.0 Device Internal Reset paragraph clarified. Packages compliant with the JEDEC Std J-STD-
020C. Process info updated in DC AND AC PARAMETERS and Table 31., Ordering
Information Scheme.
38/39
M95160, M95080
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
ECOPACK is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
39/39
相关型号:
M95160-RMB6P/S
2KX8 SPI BUS SERIAL EEPROM, PDSO8, 2 X 3 MM, HALOGEN FREE AND ROHS COMPLIANT, UFDFP-8
STMICROELECTR
M95160-RMB6TP/G
2KX8 SPI BUS SERIAL EEPROM, PDSO8, 2 X 3 MM, HALOGEN FREE AND ROHS COMPLIANT, UFDFP-8
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明