M8813F2Y-15K1 [STMICROELECTRONICS]
SPECIALTY MEMORY CIRCUIT, PQCC52, PLASTIC, LCC-52;型号: | M8813F2Y-15K1 |
厂家: | ST |
描述: | SPECIALTY MEMORY CIRCUIT, PQCC52, PLASTIC, LCC-52 内存集成电路 |
文件: | 总8页 (文件大小:62K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M88 FAMILY
In-System Programmable (ISP)
Multiple-Memory and Logic FLASH+PSD Systems for MCUs
DATA BRIEFING
■ Single Supply Voltage:
– 5 V±10% for M88x3FxY
– 3 V (+20/–10%) for M88x3FxW
■ Fast Access Time:
– 90 ns or 150 ns at 5 V
– 150 ns at 3 V
■ 1 Mbit (128K x 8) Flash memory
– 8 uniform blocks of 16K x 8 each
■ A second non-volatile memory:
PQFP52 (T)
– 256 Kbit (32K x 8) EEPROM (for M8813F1x)
or Flash memory (for M88x3F2x)
– 4 uniform blocks
■ 16 Kbit (2K x 8) SRAM for M8813Fxx (not
available on M8803Fxx)
■ Over 3,000 Gates of PLD
■ Reconfigurable I/O ports
■ JTAG Interface
■ Programmable power management
■ High Endurance:
PLCC52 (K)
– 100,000 Erase/Write Cycles of Flash Memory
– 10,000 Erase/Write Cycles of EEPROM
– 1,000 Erase/Write Cycles of PLD
Figure 1. Logic Diagram
V
CC
Table 1. Signal Names
8
PA0-PA7
PB0-PB7
Port-A Data Lines
Port-B Data Lines
Port-C Data Lines
PC2 = Voltage Stand-by
Port-D Data Lines
Address/Data Lines
Control Lines
PA0-PA7
3
8
8
3
PC0-PC7
CNTL0-
CNTL2
PB0-PB7
PC0-PC7
PD0-PD2
FLASH+PSD
PD0-PD2
16
AD0-AD15
RESET
AD0-AD15
CNTL0-CNTL2
RESET
CNTL1 = CLOCK IN
Reset
V
V
Supply Voltage
Ground
CC
SS
V
AI02856
SS
January 2000
1/8
Complete data available on Data-on-Disc CD-ROM or at www.st.com
M88 FAMILY
Figure 2A. PLCC Connections
Figure 2B. PQFP Connections
8
PD2
PD1
PD0
PC7
PC6
PC5
PC4
VCC
GND
PC3
PC2
PC1
PC0
46
45
44
43
42
41
40
39
38
37
36
AD15
AD14
AD13
AD12
AD11
AD10
AD9
9
PD2
PD1
PD0
PC7
PC6
PC5
PC4
1
2
3
4
5
6
7
8
9
39 AD15
38 AD14
37 AD13
36 AD12
35 AD11
34 AD10
33 AD9
10
11
12
13
14
15
16
17
18
19
20
AD8
V
32 AD8
CC
GND
31
V
CC
VCC
PC3 10
PC2 11
PC1 12
PC0 13
30 AD7
29 AD6
28 AD5
27 AD4
AD7
AD6
AD5
35
34
AD4
AI02857
AI02858
DESCRIPTION
and the internal PSD registers, to simplify
communication between the MCU and other
supporting devices.
The M88x3Fxx FLASH+PSD family of memory
systems for microcontrollers (MCUs) brings In-
System-Programmability (ISP) to Flash memory
and programmable logic. The result is a simple
and flexible solution for embedded designs.
M88x3Fxx FLASH+PSD devices combine many of
the peripheral functions found in MCU based
applications.
M88x3Fxx FLASH+PSD devices feature an
optimized “microcontroller macrocell” logic
architecture called the Macrocell. The Macrocell
was created to address the unique requirements
of embedded system designs. It allows direct
connection between the system address/data bus,
The M88x3Fxx FLASH+PSD family includes a
JTAG serial programming interface, to allow in-
system-programming of the entire device. This
feature reduces development time, simplifies the
manufacturing flow, and dramatically lowers the
cost of field upgrades. Using ST’s special Fast-
JTAG programming, a design can be rapidly
programmed into the M88x3Fxx FLASH+PSD.
The innovative M88x3Fxx FLASH+PSD family
solves key problems faced by designers when
managing discrete Flash memory devices, such
as:
1
Table 2. Product Range
2
Part Number
Flash Program Store I/O Ports 2nd NVM (Boot Area) Voltage Range Access Time
SRAM
M8813F1Y
M8813F2Y
M8813F3Y
M8803F2Y
M8803F3Y
M8813F1W
M8813F2W
M8813F3W
M8803F2W
M8803F3W
16 Kbit
16 Kbit
16 Kbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
27
27
27
27
27
27
27
27
27
27
256 Kbit EEPROM
256 Kbit Flash
90 ns or
150 ns
4.5-5.5 V
2.7-3.6 V
256 Kbit Flash
16 Kbit
16 Kbit
16 Kbit
256 Kbit EEPROM
256 Kbit Flash
150 ns
256 Kbit Flash
Note: 1. All products support: JTAG Serial ISP, MCU Parallel ISP, ISP Flash memory, ISP CPLD, Security features, Power Management
Unit (PMU), Automatic Power Down (APD)
2. All devices with SRAM may be backed up using an external battery.
2/8
M88 FAMILY
Figure 3. M88x3Fxx FLASH+PSD Block Diagram
P O R I / T O
P r o g r a m m a b l e
P O R I / T O
T
P O R I / O
P r o g r a m m a b l e
T
P O R I / O
P r o g r a m m a b
o g P r a r m m a b l e
l e
o r P t s I / O
B U S I N P U P T L D
e c a f e t r n I l o r n o t C
M C U
A d d r e s s / D a t a
M C U
AI02861C
Sometimes computers try to be too clever for their own good. Take this illustration for instance.
Just because so many of the labels are rotated through ninety degrees, FrameMaker seems to
want to insist on telling the postscript file that I would find it more convenient to see this page
displayed in landscape, rotated by ninety degrees. Well I wouldn’t. So I am putting in all this text
just to weight the average in this direction.
3/8
M88 FAMILY
– In-system first-time programming
– Complex address decoding
concurrently while the secondary memory is
executing code.
– Concurrent Flash or EEPROM programming.
■ Optional 16 Kbit (2K x 8) scratch-pad SRAM. Its
contents can be protected from a power failure
by connecting an external battery.
The M88x3Fxx FLASH+PSD’s serial JTAG
interface allows in-system-programming and
eliminates the need for a boot EPROM or Flash
memory, or an external programmer. To simplify
Flash memory updates, some members of the
family perform program execution out of a
secondary EEPROM (for the M8813F1x) or Flash
memory (for the M88x3F2x) while the main Flash
memory is being updated. This solution avoids the
complicated hardware and software overhead
necessary to implement in-system Flash memory
updates.
ST makes available a software development tool,
PSDsoft, that generates ANSI-C compliant code
for use with your target MCU. This code allows you
to manipulate the non-volatile memory (NVM)
within the PSD. Code examples are also provided
for:
■ Optional 64 byte One Time Programmable
(OTP) memory (on the M8813F1x) that can be
used for product configuration and calibration.
■ CPLD with 16 Output Macrocells (OMCs) and
24 Input Macrocells (IMCs). The CPLD may be
used to implement efficiently a variety of logic
functions for internal and external control.
Examples include state machines, loadable
shift registers, and loadable counters.
■ Decode PLD (DPLD) that decodes address for
selection of internal memory blocks. The DPLD
can also be used to generate external chip
selects.
– Flash memory ISP via the UART of the host
MCU
– Memory paging to execute code across several
PSD memory pages
■ 27 individually configurable I/O port pins that
can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os
– 16 of the I/O ports may be configured as
open-drain outputs.
– Loading, reading, and manipulation of PSD
Macrocells by the MCU.
KEY FEATURES
■ A simple interface to 8-bit microcontrollers,
without the need for external glue-logic. The bus
interface logic uses the control signals
generated by the microcontroller when the
address is decoded and a read or write is
performed. The MCU families supported
include:
■ Stand-by current as low as 50 µA for 5 V
devices, 25 µA for 3 V devices.
■ Built-in JTAG compliant serial port allows full-
chip In-System Programmability (ISP). With it,
you can program a blank device or reprogram a
device in the factory or the field.
– Intel 8031, 80196, 80186, 80C251, and
80386EX
■ Internal page register that can be used to
expand the microcontroller address space by a
factor of 256.
– Motorola 68HC11, 68HC16, 68HC12, and
683XX
■ Internal programmable Power Management
Unit (PMU) that supports a low power mode
called Power Down Mode. The PMU can
automatically detect a lack of microcontroller
activity and put theM88x3Fxx FLASH+PSD into
Power Down Mode.
– Philips 8031 and 8051XA
– Zilog Z80 and Z8
– NEURON 3150 CHIP .
■ Internal 1Mbit (128K x 8) Flash memory. This is
the main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with
user-specified addresses.
GENERAL INFORMATION
■ Optional internal secondary 256 Kbit (32K x 8)
EEPROM or Flash boot memory. This is divided
into four equal-sized blocks that can be
The M88x3Fxx FLASH+PSD architecture allows
In-System Programming of all Memory, PLD Logic
and Device Configuration. The embedded Input
and Output
Macrocells enable
efficient
accessed with user-specified addresses. The
main Flash memory can be updated
implementation of user defined logic functions that
require both software and hardware interaction.
4/8
M88 FAMILY
The devices eliminate the need for discrete ‘glue’
logic, and allow the development of entire systems
using only a few highly integrated devices.
times for all memory types includes the address
latching and DPLD decoding time.
Page Register
The eight-bit Page Register expands the address
range of the microcontroller by up to 256 times.
The paged address can be used as part of the
address space to access external memory and
peripherals, or internal memory and I/O. The Page
Register can also be used to change the address
mapping of blocks of Flash memory into different
memory spaces for in-circuit reprogramming.
M88X3FXX FLASH+PSD FAMILY
All M88x3Fxx FLASH+PSD devices provide the
base features: 1 Mbit main Flash Memory, JTAG
port, CPLD, DPLD, power management, and
twenty-seven I/O pins. Some of the members of
the M88x3Fxx FLASH+PSD family add to this set
of basic features:
■ M8813Fxx adds 16 Kbit (2K x 8) SRAM to the
PLDs
base feature set.
The device contains two PLD blocks, each
optimized for a different function, as shown in
Table 3. The functional partitioning of the PLDs
reduces power consumption, optimizes cost/
performance, and eases design entry.
■ M8813F1x adds 256 Kbit (32K x 8) EEPROM to
the base feature set. It also adds 64 bytes of
OTP memory for any use (product serial
number, calibration constants, etc.). Once
written, the OTP memory can never be altered.
The Decode PLD (DPLD) is used to decode
addresses and to generate chip selects for the
M88x3Fxx FLASH+PSD internal memory and
registers. The CPLD can implement user-defined
logic functions. The DPLD has combinatorial
outputs. The CPLD has 16 Output Macrocells and
■ M88x3F2x adds a secondary 256 Kbit (32K x 8)
Flash memory to the base feature set.
These independent memories can operate
concurrently with each other and with the main
Flash memory.
3
combinatorial outputs. The M88x3Fxx
FLASH+PSD also has 24 Input Macrocells that
can be configured as inputs to the PLDs. The
PLDs receive their inputs from the PLD Input Bus
and are differentiated by their output destinations,
number of Product Terms, and Macrocells.
Table 2 summarizes all the devices in the
M88x3Fxx FLASH+PSD family.
M88X3FXX FLASH+PSD ARCHITECTURAL
OVERVIEW
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo Bit in the PMMR0 register and other
bits in the PMMR2 registers. These registers are
set by the microcontroller at run-time. There is a
slight penalty to PLD propagation time when
invoking the power management features.
M88x3Fxx FLASH+PSD devices contain several
major functional blocks. Figure 3 shows the
architecture of the M88x3Fxx FLASH+PSD device
family. The functions of each block are described
briefly in the following sections. Many of the blocks
perform multiple functions and are user
configurable.
I/O Ports
Memory
The M88x3Fxx FLASH+PSD has 27 I/O pins
distributed over the four ports (Port A, B, C, and
D). Each I/O pin can be individually configured for
different functions. Ports A, B, C and D can be
configured as standard MCU I/O ports, PLD I/O, or
latched address outputs for microcontrollers using
multiplexed address/data buses.
The JTAG pins can be enabled on Port C for In-
System Programming (ISP).
Ports A and B can also be configured as a data
port for a non-multiplexed bus or multiplexed
address/data bus for certain types of 8-bit
microcontrollers.
Each of the memories is briefly discussed in the
following paragraphs. A more detailed discussion
can be found in the full data sheet.
The 1 Mbit (128K x 8) Flash memory is the main
memory of the M88x3Fxx FLASH+PSD. It is
divided into eight equally-sized blocks that are
individually selectable.
The optional 256 Kbit (32K x 8) EEPROM or Flash
memory is divided into four equally-sized blocks.
Each block is individually selectable.
The optional 16 Kbit (2K x 8) SRAM is intended for
use as a scratch-pad memory or as an extension
to the microcontroller SRAM. If an external battery
is connected to the M88x3Fxx FLASH+PSD’s
Microcontroller Bus Interface
The M88 Family easily interfaces with most 8-bit
microcontrollers that have either multiplexed or
non-multiplexed address/data buses. The device
is configured to respond to the microcontroller’s
control signals, which are also used as inputs to
V
pin, data will be retained in the event of a
STBY
power failure.
Each block of memory can be located in a different
address space as defined by the user. The access
5/8
M88 FAMILY
Table 3. PLD I/O
Table 4. JTAG SIgnals on Port C
Product
Terms
Port C Pins
PC0
JTAG Signal
TMS
Name
Abbreviation Inputs Outputs
Decode
PLD
DPLD
CPLD
73
73
17
19
42
PC1
TCK
PC3
TSTAT
TERR
TDI
Complex
PLD
140
PC4
PC5
the PLDs. Where there is a requirement to use a
16-bit data bus to interface to 16-bit
PC6
TDO
a
microcontroller, two PSDs must be used. The full
data sheet contains microcontroller interface
examples.
Power Management Unit
The Power Management Unit (PMU) in the
M88x3Fxx FLASH+PSD gives the user control of
the power consumption on selected functional
blocks based on system requirements. The PMU
includes an Automatic Power Down unit (APD)
that will turn off device functions due to
microcontroller inactivity. The APD unit has a
Power Down Mode that helps reduce power
consumption.
The M88x3Fxx FLASH+PSD also has some bits
that are configured at run-time by the MCU to
reduce power consumption of the CPLD. The
turbo bit in the PMMR0 register can be turned off
and the CPLD will latch its outputs and go to sleep
until the next transition on its inputs.
JTAG Port
In-System Programming can be performed
through the JTAG pins on Port C. This serial
interface allows complete programming of the
entire M88x3Fxx FLASH+PSD device. A blank
device can be completely programmed. The JTAG
signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can
be multiplexed with other functions on Port C.
Table
4
indicates the JTAG signals pin
assignments. Four-pin JTAG is also fully
supported.
In-System Programming
Using the JTAG signals on Port C, the entire
M88x3Fxx FLASH+PSD
device can be
programmed or erased without the use of the
microcontroller. The main Flash memory can also
be programmed in-system by the microcontroller
executing the programming algorithms out of the
optional EEPROM, Flash Boot memory, or SRAM.
The optional EEPROM or Flash Boot memory can
be programmed the same way by executing out of
the main Flash memory. The PLD logic or other
M88x3Fxx FLASH+PSD configuration can be
programmed through the JTAG port or a device
Additionally, bits in the PMMR2 register can be set
by the MCU to block signals from entering the
CPLD to reduce power consumption. Please see
the full data sheet for more details.
programmer.
Table
5
indicates
which
programming methods can program different
functional blocks of the M88x3Fxx FLASH+PSD.
Table 5. Methods of Programming Different Functional Blocks of the M88x3Fxx FLASH+PSD
Functional Block
Main Flash Memory
JTAG Programming Device Programmer In-System Parallel Programming
Yes
Yes
Yes
Yes
Yes
Yes
Optional EEPROM/Flash Boot
Memory
PLD Array (DPLD and CPLD)
PSD Configuration
Yes
Yes
No
Yes
Yes
Yes
No
No
Yes
Optional OTP Row
6/8
M88 FAMILY
Table 6. Ordering Information Scheme
Example:
M88 1 3 F 1 W –
15
T
1
T
SRAM Capacity
Option
0
1
0 Kbit
T
1
Tape & Reel Packing
16 Kbit
Flash Memory Capacity
Temperature Range
3
1 Mbit (128K x 8)
0 to 70 °C
2nd Non Volatile Memory
256 Kbit EEPROM
256 Kbit Flash Memory
none
Package
PLCC52
1
2
3
K
T
PQFP52
Operating Voltage
Speed
1
4.5 V to 5.5 V
Y
-90
90 ns
W
2.7 V to 3.6 V
-15 150 ns
Note: 1. Available on the 4.5 to 5.5 V range, only.
ORDERING INFORMATION SCHEME
When delivered from ST, the M88x3Fxx
FLASH+PSD device has all bits in the PLDs and
memories in the “1” or high state. The
configuration bits are in the “0” or low state. The
code, configuration, and PLDs logic are loaded
using the programming procedure. Information for
programming the device is available directly from
ST.
Please
contact
your
local
sales
representative.
The notation used for the device number is as
shown in Table 6. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please see the full data
sheet (please consult our pages on the world wide
web: www.st.com/flashpsd). Alternatively, please
contact your nearest ST Sales Office.
7/8
M88 FAMILY
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express writtenapproval of STMicroelectronics.
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All other names are the property of their respective owners.
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