M74HC648RM13TR [STMICROELECTRONICS]
HC/UH SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24, SOP-24;
| 型号： | M74HC648RM13TR |
| 厂家： | 
ST |
| 描述： | HC/UH SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24, SOP-24 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总15页 (文件大小：547K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M74HC648
OCTAL BUS TRANSCEIVER/REGISTER
WITH 3 STATE OUTPUTS (INVERTING)
■
■
■
■
■
■
■
HIGH SPEED:
= 79 MHz (TYP.) at V = 6V
f
MAX
CC
LOW POWER DISSIPATION:
= 4µA(MAX.) at T =25°C
I
CC
A
HIGH NOISE IMMUNITY:
= V = 28 % V (MIN.)
V
NIH
NIL
CC
DIP
SOP
TSSOP
T & R
SYMMETRICAL OUTPUT IMPEDANCE:
|I | = I = 6mA (MIN)
OH
OL
BALANCED PROPAGATION DELAYS:
t
t
ORDER CODES
PACKAGE
PLH
PHL
WIDE OPERATING VOLTAGE RANGE:
(OPR) = 2V to 6V
TUBE
V
CC
DIP
SOP
M74HC648B1R
M74HC648M1R
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 648
M74HC648RM13TR
M74HC648TTR
TSSOP
DESCRIPTION
The 74HC648 is an advanced high-speed CMOS
OCTAL BUS TRANSCEIVER AND REGISTER
(3-STATE) fabricated with silicon gate C MOS
register or in both. The select controls (Select AB
select BA) can multiplex stored and real time
(transparent mode) data. The direction control
determines which bus will receive data when
enable G is active (low). In the isolation mode
(enable G high), "A" data may be stored in one
register and/or "B" data may be stored in the other
register. When an output function is disabled, the
input function is still enabled and may be used to
store and transmit data. Only one of the two
buses, A or B, may be driven at a time.
2
technology.
This device consists of bus transceiver circuits
with 3 state, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data
directly from the input bus or from the internal
registers. Data on the A or B bus will be clocked
into register on the low to high transition of the
appropriate clock pin (Clock AB or Clock BA).
Enable (G) and direction (DIR) pins are provided
to control the transceiver functions. In the
transceiver mode, data present at the
high-impedance port may be stored in either
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2003
1/15
M74HC648
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
1
CLOCK AB A to B Clock Input (LOW
(CAB)
to HIGH, Edge-Triggered)
2
3
SELECT AB Select A to B Source Input
(SAB)
DIR
Direction Control Input
A Data Inputs/Outputs
4, 5, 6, 7, 8,
9, 10, 11
A1 to A8
20, 19, 18,
17, 16, 15,
14, 13
B1 to B8
G
B Data Inputs/Outputs
21
22
23
Output Enable Input
(Active LOW)
SELECT BA Select B to A Source Input
(SBA)
CLOCK BA B to A Clock Input (LOW
(CBA)
to HIGH, Edge Triggered)
12
24
GND
Ground (0V)
V
Positive Supply Voltage
CC
TRUTH TABLE
G
DIR CAB CBA SAB SBA
A
B
FUNCTION
INPUTS
Z
INPUTS Both the A bus and the B bus are inputs
X
X
X
X
X
X
Z
The Output functions of the A and B bus are disabled
Both the A and B bus are used for inputs to the internal
H
X
INPUTS
INPUTS flip-flops. Data at the bus will be stored on low to high
transition of the clock inputs.
INPUTS OUTPUTS The A bus are inputs and the B bus are outputs
L
H
L
H
L
X
X
X*
X*
X*
X*
L
L
X
X
X
X
The data at the A bus are displayed at the B bus
H
The data at the A bus are displayed at the B bus. The
data of the A bus are stored to internal flip-flop on low
to high transition of the clock pulse
H
L
L
H
The data stored to the internal flip-flop are displayed at
the B bus.
H
H
X
L
Qn
H
The data at the A bus are stored to the internal flip-flop
on low to high transition of the clock pulse. The states
of the internal flip-flops output directly to the B bus.
H
L
OUTPUTS INPUTS The B bus are inputs and the A bus are outputs.
H
L
L
H
L
X*
X
X
X
L
The data at the B bus are displayed at the A bus
H
The data at the B bus are displayed at the A bus. The
data of the B bus are stored to the internal flip-flop on
low to high transition of the clock pulse.
X*
X*
X*
X
X
X
L
H
H
L
H
X
L
L
The data stored to the internal flip-flops are displayed
at the A bus
Qn
H
L
L
The data at the B bus are stored to the internal flip-flop
on low to high transition of the clock pulse. The states
of the internal flip-flops output directly to the A bus.
H
X : Don’t Care
Z : High Impedance
Qn : The data stored to the internal flip-flops by most recent low to high transition of the clock inputs
* : The data at the A and B bus will be stored to the internal flip-flops on every low to high transition of the clock inputs.
2/15
M74HC648
LOGIC DIAGRAM
TIMING CHART
3/15
M74HC648
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7
V
V
CC
V
DC Input Voltage
-0.5 to V + 0.5
I
O
CC
V
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
-0.5 to V + 0.5
V
CC
I
± 20
± 20
mA
mA
mA
mA
mW
°C
IK
I
OK
I
± 35
O
I
or I
DC V
or Ground Current
CC
± 70
CC
GND
P
Power Dissipation
500(*)
-65 to +150
300
D
T
Storage Temperature
Lead Temperature (10 sec)
stg
T
°C
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
Supply Voltage
2 to 6
0 to V
V
V
CC
V
Input Voltage
I
CC
V
Output Voltage
0 to V
CC
V
O
T
Operating Temperature
Input Rise and Fall Time
-55 to 125
0 to 1000
0 to 500
0 to 400
°C
ns
ns
ns
op
V
V
V
= 2.0V
= 4.5V
= 6.0V
CC
CC
CC
t , t
r
f
4/15
M74HC648
DC SPECIFICATIONS
Test Condition
Value
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
T
= 25°C
Symbol
Parameter
A
V
CC
(V)
V
High Level Input
Voltage
2.0
4.5
6.0
2.0
4.5
6.0
2.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
IH
V
V
V
Low Level Input
Voltage
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
IL
V
High Level Output
Voltage
I =-20 µA
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
1.9
4.4
OH
O
I =-20 µA
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
O
I =-20 µA
5.9
5.9
V
V
O
I =-6.0 mA
4.18 4.31
4.13
5.63
4.10
5.6
O
I =-7.8 mA
5.68
5.8
0.0
0.0
0.0
O
V
Low Level Output
Voltage
I =20 µA
0.1
0.1
0.1
0.1
0.1
0.1
0.1
OL
O
I =20 µA
O
I =20 µA
0.1
0.1
O
I =6.0 mA
0.17 0.26
0.18 0.26
0.37
0.37
0.37
0.37
O
I =7.8 mA
O
I
Input Leakage
Current
I
V = V
or GND
CC
6.0
6.0
6.0
± 0.1
± 0.5
4
± 1
± 5
40
± 1
± 10
80
µA
µA
µA
I
I
High Impedance
Output Leakage
Current
OZ
V = V or V
IL
I
IH
V
= V or GND
CC
O
I
Quiescent Supply
Current
CC
V = V
or GND
CC
I
5/15
M74HC648
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6ns)
L
r
f
Test Condition
Value
T
= 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
C
L
CC
(V)
(pF)
Min. Typ. Max. Min. Max. Min. Max.
t
t
Output Transition
Time
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
25
7
60
12
75
15
80
20
TLH THL
50
ns
ns
6
10
13
15
t
t
t
t
t
t
Propagation Delay
Time (BUS - BUS)
74
21
18
91
26
22
98
28
24
116
33
28
81
23
20
98
28
24
84
24
20
102
29
25
60
23
20
19
67
79
30
7
150
30
190
38
195
42
PLH PHL
50
150
50
26
32
35
190
38
240
48
245
52
ns
32
41
48
t
Propagation Delay
Time (CLOCK -
BUS)
210
42
265
53
275
60
PLH PHL
ns
36
45
50
250
50
315
63
325
75
150
50
ns
43
54
60
t
Propagation Delay
Time (SELECT -
BUS)
170
34
215
43
225
56
PLH PHL
ns
29
37
45
210
42
265
53
275
60
150
50
ns
36
45
50
t
High Impedance
Output Enable
Time (G, DIR)
175
35
220
44
225
50
PZL PZH
R = 1 KΩ
ns
L
30
37
45
215
43
270
54
280
60
R = 1 KΩ
150
50
ns
L
37
46
55
t
High Impedance
Output Disable
Time (G, DIR)
175
35
220
44
230
50
PLZ PHZ
R = 1 KΩ
ns
L
30
37
45
f
Maximum Clock
Frequency
6
4.8
24
28
4.0
20
25
MAX
50
30
35
MHz
ns
t
t
Minimum Pulse
Width
75
15
13
50
10
9
95
19
16
65
13
11
5
100
22
18
70
15
13
5
W(H)
50
W(L)
6
t
Minimum Set-Up
Time
16
4
s
50
ns
3
t
Minimum Hold
Time
5
h
50
5
5
5
ns
5
5
5
6/15
M74HC648
CAPACITIVE CHARACTERISTICS
Test Condition
Value
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
T
= 25°C
Symbol
Parameter
A
V
CC
(V)
C
Input Capacitance
5
10
10
10
pF
IN
C
Power Dissipation
Capacitance (note
1)
PD
38
pF
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
= C x V x f + I /8 (per bit)
CC(opr)
PD CC IN CC
TEST CIRCUIT
TEST
SWITCH
t
t
t
, t
Open
PLH PHL
, t
V
CC
PZL PLZ
, t
GND
PZH PHZ
C
R
R
= 50pF/150pF or equivalent (includes jig and probe capacitance)
= 1KΩ or equivalent
L
1
T
= Z
of pulse generator (typically 50Ω)
OUT
7/15
M74HC648
WAVEFORM 1 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
WAVEFORM 2 : PROPAGATION DELAY, MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle)
8/15
M74HC648
WAVEFORM 3 : MINIMUM PULSE WIDTH, SETUP AND HOLD TIME (f=1MHz; 50% duty cycle)
WAVEFORM 4 : OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
9/15
M74HC648
Plastic DIP-24 (0.25) MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
MIN.
MAX.
A
A1
A2
B
4.32
0.170
0.38
0.015
3.3
0.46
1.52
0.25
31.75
0.130
0.018
0.060
0.010
1.250
0.41
1.40
0.20
31.62
7.62
6.35
0.51
1.65
0.30
31.88
8.26
6.86
0.016
0.055
0.008
1.245
0.300
0.250
0.020
0.065
0.012
1.255
0.325
0.270
B1
c
D
E
E1
e
6.60
2.54
7.62
0.260
0.100
0.300
E1
L
3.18
0˚
3.43
15˚
0.125
0˚
0.135
15˚
M
E
E1
Stand-off
B
B1
e
e1
c
D
24
13
12
.015
0,38
Gage Plane
1
M
0034965/D
10/15
M74HC648
SO-24 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
2.65
0.2
MIN.
MAX.
0.104
0.008
0.096
0.019
0.012
A
a1
a2
b
0.1
0.004
2.45
0.49
0.32
0.35
0.23
0.014
0.009
b1
C
0.5
0.020
c1
D
45˚ (typ.)
15.20
10.00
15.60
10.65
0.598
0.393
0.614
0.419
E
e
1.27
0.050
0.550
e3
F
13.97
7.40
0.50
7.60
1.27
0.291
0.020
0.300
0.050
L
S
˚ (max.)
8
L
c1
b
e
s
e3
E
D
24
13
1
1
2
PO13T
11/15
M74HC648
TSSOP24 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.1
MIN.
MAX.
0.043
0.006
A
A1
A2
b
0.05
0.15
0.002
0.9
0.035
0.19
0.09
7.7
0.30
0.20
7.9
0.0075
0.0035
0.303
0.246
0.169
0.0118
0.0079
0.311
0.256
0.177
c
D
E
6.25
4.3
6.5
E1
e
4.5
0.65 BSC
0.0256 BSC
K
0˚
8˚
0˚
8˚
L
0.50
0.70
0.020
0.028
A2
A
K
L
b
e
A1
E
c
D
E1
PIN 1 IDENTIFICATION
1
7047476A
12/15
M74HC648
Tape & Reel SO-24 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
30.4
11.0
15.9
3.1
1.197
0.433
0.626
0.122
0.161
0.476
Ao
Bo
Ko
Po
P
10.8
15.7
2.9
0.425
0.618
0.114
0.153
0.468
3.9
4.1
11.9
12.1
13/15
M74HC648
Tape & Reel TSSOP24 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
22.4
7
0.882
0.276
0.331
0.075
0.161
0.476
Ao
Bo
Ko
Po
P
6.8
8.2
0.268
0.323
0.067
0.153
0.468
8.4
1.9
4.1
12.1
1.7
3.9
11.9
14/15
M74HC648
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2003 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
© http://www.st.com
15/15
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明