M7020R_技术文档

M7020R

32K x 68-bit Entry NETWORK SEARCH ENGINE

PRELIMINARY DATA

FEATURES SUMMARY

■ 32K DATA ENTRIES IN 68-BIT MODE

Figure 1. 272-ball PBGA Package

■ TABLE MAY BE PARTITIONED INTO UP TO

FOUR (4) QUADRANTS

(Data entry width in each octant is configurable

as 34, 68, 136, or 272 bits.)

■ UP TO 83 MILLION SUSTAINED SEARCHES

PER SECOND IN 68-BIT and 136-BIT

CONFIGURATIONS

■ UP TO 41.5 MILLION SEARCHES PER

SECOND IN 34-BIT and 272-BIT

CONFIGURATIONS

■ SEARCHES ANY SUB-FIELD IN A SINGLE

CYCLE

■ OFFERS BIT-BY-BIT and GLOBAL MASKING

■ SYNCHRONOUS, PIPELINED OPERATION

272-ball PBGA

27mm x 27mm

■ UP TO 31 SEARCH ENGINES CASCADABLE

WITHOUT PERFORMANCE DEGRADATION

■ WHEN CASCADED, THE DATABASE

ENTRIES CAN SCALE FROM 248K TO 1984K

DEPENDING ON THE WIDTH OF THE ENTRY

■ GLUELESS INTERFACE TO INDUSTRY-

STANDARD SRAMS

■ SIMPLE HARDWARE INSTRUCTION

INTERFACE

■ IEEE 1149.1 TEST ACCESS PORT

■ OPERATING SUPPLY VOLTAGES INCLUDE:

V

(Operating Supply Voltage) = 1.8V

DD

(Operating Supply Voltage for I/O) = 2.5

DDQ

or 3.3V

■ 272 PBGA, 27mm x 27mm

December 2001

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M7020R

TABLE OF CONTENTS

DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Product Range (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Switch/Router Implementation Using the M7020R (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Signal Names (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Connections (Figure 3.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

M7020R Block Diagram (Figure 4.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Absolute Maximum Ratings (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DC and AC Measurement Conditions (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

M7020R 2.5, or 3.3V AC Testing Load (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

M7020R 2.5, or 3.3V Input Waveform (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

M7020R 2.5, or 3.3V I/O Output Load Equivalent (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Capacitance (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

AC Timing Waveforms with CLK2X (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

AC Timing Parameters with CLK2X (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

CMD Bus and DQ Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Database Entry (Data Array and Mask Array). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Arbitration Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Pipeline and SRAM Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Full Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

CONNECTION DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Clocks and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CMD and DQ Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Cascade Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Clocks (CLK2X and PHS_L) (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Register Overview (Table 8.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Comparand Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Comparand Register Selection During SEARCH and LEARN Instructions (Figure 10.) . . . . . . . . . 22

Addressing the Global Masks Register Array (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SEARCH-Successful Registers (SSR[0:7]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SEARCH-Successful Register (SSR) Description (Table 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

The Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Command Register Field Descriptions (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

The Information Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Information Register Field Descriptions (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

The Read Burst Address Register (RBURREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

The Write Burst Address Register (WBURREG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

The NFA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Read Burst Register Description (Table 12.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Write Burst Register Description (Table 13.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

NFA Register (Table 14.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

SEARCH ENGINE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Data and Mask Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

M7020R Database Width Configuration (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Bit Position Match (Table 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Multi-width Configuration Example (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

M7020R Data and Mask Array Addressing (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

COMMAND CODES AND PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Commands and Command Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Command Codes (Table 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Command Parameters (Table 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

READ COMMAND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Single Location READ Cycle Timing (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Burst READ of the Data and Mask Arrays (BLEN = 4) (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . 31

READ Command Parameters (Table 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Data and Mask Array, SRAM Read Address Format (Table 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . 32

READ Address Format for Internal Registers (Table 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

READ Address Format for Data and Mask Arrays (Table 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

WRITE COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Single Location WRITE Cycle Timing (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Burst WRITE of the Data and Mask Arrays (BLEN = 4) (Figure 18.). . . . . . . . . . . . . . . . . . . . . . . . 35

(Single) WRITE Address Format for Data and Mask Arrays or SRAM (Table 22.) . . . . . . . . . . . . . 35

WRITE Address Format for Internal Registers (Table 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

WRITE Address Format for Data and Mask Array (Burst Write) (Table 24.). . . . . . . . . . . . . . . . . . 36

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SEARCH COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

68-bit Configuration with Single Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Hardware Diagram for a Table with One Device (Figure 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Timing Diagram for a 68-bit Configuration SEARCH for One Device (Figure 20.) . . . . . . . . . . . . . 38

x68 Table with One Device (Figure 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, 1 Device (Table 25.). . . . . . 39

Shift of SSF and SSV from SADR (Table 26.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

68-bit SEARCH on Tables Configured as x68 Using up to Eight M7020R Devices. . . . . . . . . 40

Hit/Miss Assumption (Table 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Hardware Diagram for a Table with Eight Devices (Figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

x68 Table with Eight Devices (Figure 23.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Timing Diagrams for x68 Using up to Eight M7020R Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

68-bit SEARCH For Device 0 (Figure 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

68-bit SEARCH For Device 1 (Figure 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

68-bit SEARCH For Device 7 (Last Device) (Figure 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, Up to 8 Devices (Table 28.) 46

Shift of SSF and SSV from SADR (Table 29.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

68-bit SEARCH on Tables Configured as x68 Using Up To 31 M7020R Devices. . . . . . . . . . . 46

Hit/Miss Assumption (Table 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Hardware Diagram for a Table with 31 Devices (Figure 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Hardware Diagram for a Block of Up To Eight Devices (Figure 28.) . . . . . . . . . . . . . . . . . . . . . . . . 49

x68 Table with 31 Devices (Figure 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Timing Diagrams for x68 Using Up To 31 M7020R Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Each Device in Block Number 0 (Miss on Each Device) (Figure 30.) . . . . . . . . . . . . . . . . . . . . 51

Each Device Above the Winning Device in Block Number 1 (Figure 31.). . . . . . . . . . . . . . . . . 52

Globally Winning Device in Block Number 1 (Figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Devices Below the Winning Device in Block Number 1 (Figure 33.). . . . . . . . . . . . . . . . . . . . . 54

Devices Above the Winning Device in Block Number 2 (Figure 34.) . . . . . . . . . . . . . . . . . . . . 55

Globally Winning Device in Block Number 2 (Figure 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Devices Below the Winning Device in Block Number 2 (Figure 36.). . . . . . . . . . . . . . . . . . . . . 57

Devices Above the Winning Device in Block Number 3 (Figure 37.) . . . . . . . . . . . . . . . . . . . . 58

Globally Winning Device in Block Number 3 (Figure 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Devices Below the Winning Device in Block Number 3 (not Device 30 - Last Device). . . . . . . 60

Device 6 in Block Number 3 (Device 30 in Depth-Cascaded Table) (Figure 40.) . . . . . . . . . . . 61

Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, Up to 31 Devices . . . . . . . . 62

Shift of SSF and SSV from SADR (Table 32.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

136-bit Configuration with Single Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Hardware Diagram for a Table with 1 Device (Figure 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Timing Diagram for a 136-bit SEARCH for One Device (Figure 42.). . . . . . . . . . . . . . . . . . . . . . . . 64

x136 Table with One Device (Figure 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Latency of SEARCH from Instruction to SRAM Access Cycle, 136-bit, 1 Device (Table 33.). . . . . 65

Shift of SSF and SSV from SADR (Table 34.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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136-bit Search on Tables Configured as x136 Using Up to Eight M7020R Devices . . . . . . . . 66

Hit/Miss Assumption (Table 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Hardware Diagram for a Table with Eight Devices (Figure 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

x136 Table with Eight Devices (Figure 45.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Timing Diagrams for x136 Using Up to Eight M7020R Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

136-bit SEARCH for Device Number 0 (Figure 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

136-bit SEARCH for Device Number 1 (Figure 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

136-bit SEARCH for Device Number 7 (Last Device) (Figure 48.) . . . . . . . . . . . . . . . . . . . . . . 71

Latency of SEARCH from Instruction to SRAM Access Cycle, 136-bit, Up to 8 Devices . . . . . . . . 72

Shift of SSF and SSV from SADR (Table 37.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

136-bit Search on Tables Configured as x136 Using Up to 31 M7020R Devices. . . . . . . . . . . 72

Hit/Miss Assumption (Table 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Hardware Diagram for a Table with 31 Devices (Figure 49.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Hardware Diagram for a Block of Up to Eight Devices (Figure 50.) . . . . . . . . . . . . . . . . . . . . . . . . 75

x136 Table with 31 Devices (Figure 51.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Timing Diagrams for x136 Using Up to 31 M7020R Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Each Device in Block Number 0 (Miss on Each Device) (Figure 52.) . . . . . . . . . . . . . . . . . . . . 77

Each Device Above the Winning Device in Block Number 1 (Figure 53.). . . . . . . . . . . . . . . . . 78

Globally Winning Device in Block Number 1 (Figure 54.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Devices Below the Winning Device in Block Number 1 (Figure 55.). . . . . . . . . . . . . . . . . . . . . 80

Devices Above the Winning Device in Block Number 2 (Figure 56.) . . . . . . . . . . . . . . . . . . . . 81

Globally Winning Device in Block Number 2 (Figure 57.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Devices Below the Winning Device in Block Number 2 (Figure 58.). . . . . . . . . . . . . . . . . . . . . 83

Devices Above the Winning Device in Block Number 3 (Figure 59.) . . . . . . . . . . . . . . . . . . . . 84

Globally Winning Device in Block Number 3 (Figure 60.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Devices Below the Winning Device in Block Number 3 (not Device 30 - Last Device). . . . . . . 86

Device 6 in Block Number 3 (Device 30 in Depth-Cascaded Table) (Figure 62.) . . . . . . . . . . . 87

Latency of SEARCH from Instruction to SRAM Access Cycle, 136-bit, Up to 31 Devices . . . . . . . 88

Shift of SSF and SSV from SADR (Table 40.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

272-bit SEARCH on Tables Configured as x272 Using a Single M7020R Device . . . . . . . . . . 88

Hardware Diagram for a Table with One Device (Figure 63.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Timing Diagram for a 272-bit SEARCH for One Device (Figure 64.). . . . . . . . . . . . . . . . . . . . . . . . 90

x272 Table with One Device (Figure 65.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, 1 Device. . . . . . . . . . 91

Shift of SSF and SSV from SADR (Table 42.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

272-bit SEARCH on Tables x272-configured Using Up to Eight M7020R Devices . . . . . . . . . 92

Hit/Miss Assumption (Table 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Hardware Diagram for a Table with Eight Devices (Figure 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

x272 Table with Eight Devices (Figure 67.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Timing Diagrams for x272-configured Using Up to Eight M7020R Devices . . . . . . . . . . . . . . . . . . 96

272-bit SEARCH for Device Number 0 (Figure 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

272-bit SEARCH for Device Number 1 (Figure 69.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

272-bit SEARCH for Device Number 7 (Last Device) (Figure 70.) . . . . . . . . . . . . . . . . . . . . . . 98

Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, Up to 8 Devices . . . . 99

Shift of SSF and SSV from SADR (Table 45.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5/150

M7020R

272-bit Search on Tables Configured as x272 Using Up to 31 M7020R Devices. . . . . . . . . . . 99

Hit/Miss Assumption (Table 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Hardware Diagram for a Table with 31 Devices (Figure 71.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Hardware Diagram for a Block of Up to Eight Devices (Figure 72.) . . . . . . . . . . . . . . . . . . . . . . . 102

x272 Table with 31 Devices (Figure 73.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Timing Diagrams for x272 Using Up to 31 M7020R Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Each Device in Block Number 0 (Miss on Each Device) (Figure 74.) . . . . . . . . . . . . . . . . . . . 104

Each Device Above the Winning Device in Block Number 1 (Figure 75.). . . . . . . . . . . . . . . . 105

Globally Winning Device in Block Number 1 (Figure 76.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Devices Below the Winning Device in Block Number 1 (Figure 77.). . . . . . . . . . . . . . . . . . . . 107

Devices Above the Winning Device in Block Number 2 (Figure 78.) . . . . . . . . . . . . . . . . . . . 108

Globally Winning Device in Block Number 2 (Figure 79.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Devices Below the Winning Device in Block Number 2 (Figure 80.). . . . . . . . . . . . . . . . . . . . 110

Devices Above the Winning Device in Block Number 3 (Figure 81.) . . . . . . . . . . . . . . . . . . . 111

Globally Winning Device in Block Number 3 (Figure 82.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Devices Below the Winning Device in Block Number 3 (not Device 30 - Last Device). . . . . . 113

Last Device in Block Number 3 (Device 30 in the Table) (Figure 84.) . . . . . . . . . . . . . . . . . . 114

Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, Up to 31 Devices . . 115

Shift of SSF and SSV from SADR (Table 48.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

MIXED SEARCHES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Tables Configured with Different Widths Using an M7020R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Timing Diagram for Mixed SEARCH for One Device (Figure 85.). . . . . . . . . . . . . . . . . . . . . . . . . 116

Multi-Width Configurations Example (Figure 86.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

LRAM AND LDEV DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

LEARN COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Timing Diagram of LEARN: TLSZ = 00 (Figure 87.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Timing Diagram of LEARN: TLSZ = 01 (Except on the Last Device) (Figure 88.). . . . . . . . . . . . . 120

Timing Diagram of LEARN on Device 7: TLSZ = 01 (Figure 89.) . . . . . . . . . . . . . . . . . . . . . . . . . 121

Latency of SRAM WRITE Cycle from Second Cycle of LEARN Instruction (Table 49.) . . . . . . . . 121

DEPTH-CASCADING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Depth-Cascading Up to Eight Devices (One Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Depth-Cascading Up to 31 Devices (4 Blocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Depth-Cascading to Generate a “FULL” Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Depth-Cascading to Form a Single Block (Figure 90.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Depth-Cascading Four Blocks (Figure 91.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

“FULL” Generation in a Cascaded Table (Figure 92.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SRAM ADDRESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

SRAM PIO Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

6/150

M7020R

SRAM READ with a Table of One Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Generating an SRAM Bus Address (Table 50.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

SRAM READ Access for One Device (Figure 93.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

SRAM READ with a Table of Up to Eight Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table with Eight Devices (Figure 94.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

SRAM READ Through Device 0 in a Block of Eight Devices (Figure 95.). . . . . . . . . . . . . . . . . . . 130

SRAM READ Timing for Device 7 in a Block of Eight Devices (Figure 96.) . . . . . . . . . . . . . . . . . 131

SRAM READ with a Table of Up to 31 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table of 31 Devices Made of Four Blocks (Figure 97.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

SRAM READ Through Device 0 in a Bank of 31 Devices (Device 0 Timing) (Figure 98.) . . . . . . 134

SRAM READ Through Device 0 in a Bank of 31 Devices (Device 30 Timing) (Figure 99.) . . . . . 135

SRAM WRITE with a Table of One Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

SRAM WRITE Access for One Device (Figure 100.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

SRAM WRITE with a Table of Up to Eight Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table with Eight Devices (Figure 101.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

SRAM WRITE Through Device 0 in a Block of Eight Devices (Figure 102.) . . . . . . . . . . . . . . . . . 140

SRAM WRITE Timing for Device 7 in a Block of Eight Devices (Figure 103.). . . . . . . . . . . . . . . . 141

SRAM WRITE with Table(s) of Up to 31 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table of 31 Devices (Four Blocks) (Figure 104.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 0 Timing) (Figure 105.). . . . . 144

SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 30 Timing) (Figure 106.). . . . 145

JTAG (1149.1) TESTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Supported Operations (Table 51.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

TAP Device ID Register (Table 52.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

7/150

M7020R

DESCRIPTION

Overview

ST Microelectronics, Inc.’s M7020R Search En-

gine incorporates patent-pending Associative Pro-

cessing Technology™ (APT) and is designed to

be a high-performance, pipelined, synchronous,

32K-entry network database search engine. The

M7020R database entry size can be 68 bits, 136

bits, or 272 bits. In the 68-bit entry mode, the size

of the database is 32K entries. In the 136-bit

mode, the size of the database is 16K entries, and

in the 272-bit mode, the size of the database is 8K

entries. The M7020R is configurable to support

multiple databases with different entry sizes. The

34-bit entry table can be implemented using the

Global Mask Registers (GMRs) building-database

size of 64K entries with a single device.

of 34 or 272 bits, the Search Engine will perform at

41.5 million transactions per second. STM’s

M7020R can be used to accelerate network proto-

cols such as Longest-prefix Match (CIDR), ARP,

MPLS, and other Layer 2, 3, and 4 protocols.

Applications

This high-speed, high-capacity Search Engine can

be deployed in a variety of networking and com-

munications applications. The performance and

features of the M7020R make it attractive in appli-

cations such as Enterprise LAN switches and rout-

ers and broadband switching and/or routing

equipment supporting multiple data rates at OC–

48 and beyond. The Search Engine is designed to

be scalable in order to support network database

sizes to 1984K entries specifically for environ-

ments that require large network policy databases.

Figure 4, page 11 shows the block diagram for the

M7020R device.

Performance

The Search Engine can sustain 83 million transac-

tions per second when the database is pro-

grammed or configured as 68 or 136 bits. When

the database is programmed to have an entry size

Table 1. Product Range

Operating

Part Number

Operating I/O

Voltage

Speed

Temperature Range

Supply Voltage

M7020R-083ZA1

M7020R-066ZA1

M7020R-050ZA1

1.8V

2.5 or 3.3V

83MHz

66MHz

50MHz

Commercial

Figure 2. Switch/Router Implementation Using the M7020R

SRAM

Bank

System Bus

m

y

a

r

Prog

Search

Engine

Memor

Host

ASIC

Switch

ic

abr

F

Netw

or

Switch

k Line Interf

aces

Processor

AI04272

8/150

M7020R

Table 2. Signal Names

(1)

Cascade Interface

Symbol

Description

Type

LHI[6:0]

LHO[1:0]

BHI[2:0]

BHO[2:0]

FULI[6:0]

FULO[1:0]

FULL

I

O

I

Local Hit In

Local Hit Out

Block Hit In

Block Hit Out

Full In

Clocks and Reset

CLK2X

I

Master Clock

PHS_L

TEST

Phase

O

I

Test Input

Reset

RST_L

O

Full Out

Command and DQ Bus

Full Flag

CMD[8:0]

CMDV

I

Command Bus

Device Identification

Supplies

Command Valid

Address/Data Bus

READ Acknowledge

ID[4:0]

I

DQ[67:0]

I/O

T

(4)

ACK

V

n/a

Chip Core Supply (1.8V)

DD

(4)

T

End of Transfer

EOT

Chip I/O Supply (2.5 or

3.3V)

V

DDQ

SSF

SSV

SEARCH Successful Flag

Valid

Test Access Port

T

Test Access Port’s Test

Data In

TDI

I

SRAM Interface

SADR[21:0]

CE_L

T

SRAM Address

Test Access Port’s Test

Clock

TCK

TDO

SRAM Chip Enable

SRAM Write Enable

SRAM Output Enable

Address Latch Enable

Test Access Port’s Test

Data Out

WE_L

T

OE_L

Test Access Port’s Test

Mode Select

TMS

I

ALE_L

TRST_L

Test Access Port’s Reset

Note: 1. Signal types are: I = Input only; I/O = Input or Output; O = Output; and T = Tristate

2. “CLK” is an internal clock signal. Any reference to “CLK Cycles” means one cycle of CLK.

3. ACK and EOT Signals require a weak, external pull-down resistor of 47 KΩ or 100 KΩ.

9/150

M7020R

Figure 3. Connections

V

DD

BHO0

FULI5 FULI4 FULI1

BHI0

ID2

NC

EOT NC

LHI6

ID0 TDO

NC

GND

NC

DD

NC

DD

V

FULL

ACK

NC

LHI3

FULI6

NC

LHI2

LHI0

NC

BHI2

TDI

NC

FULO1

FULI2

DDQ LHI5

LHO1 LHI4

LHO0

TMS

TCK

BHO1

BHO2

FULI0

ID3

ID1

DD

V

DDQ

V

NC

DQ65

DQ64

DQ62

DQ60

DD

NC

DDQ

DD

DDQ

T

V

FULI3

NC

GND

BHI1

GND LHI1 ID4

FULO0

NC

RSTL

GND DQ63

DQ61 DQ57

GND

DD

RST_L

TOP

V

DQ67

NC DQ66

DQ59

DQ53

NC

DDQ

NC

V

DQ58

DD

DQ56

DDQ DQ55

DD

DQ49

DQ51

V

DQ50

NC

DQ47

GND

DQ52 DQ54

DDQ

NC

DDQ

DQ46

GND

DQ44

DQ38

DQ30

DQ26

DQ45 DQ43

DQ48

V

GND GND GND GND

V

DQ41

DQ40 DQ42

DQ37

DD

DQ39

DDQ

V

DQ31

NC

DD

DQ35 DQ33

DQ36

DDQ

RIGHT

LEFT

V

DQ34 DQ32

DDQ

NC

DD

DQ29

DDQ

NC

V

DQ28

GND

GND GND

DQ27

DQ21

DQ17

DDQ

DQ23 DQ25

V

GND

DQ24

DQ19

DDQ

GND

DD DQ20

V

DQ22

V

NC

DQ16

DQ15

DQ14

DDQ

V

DQ9

DQ6

DQ11 DQ13

DD DQ18

DD

DDQ

NC

DQ5

NC

DQ1

GND

DQ7

NC

DQ12 DQ8 DQ0

V

BOTTOM

SADR

15

SADR

5

V

DDQ

V

NC

CLK2X DD

GND

DQ10

GND

CMD4 CMD2 GND WE_L

DDQ

SADR SADR

SADR

0

SADR

16

SADR SADR

SADR

6

SADR

12

V

AE_L

CMD3 CMD0

OE_L

NC

DQ3

NC

DQ2 DQ4

CMD6

DD SSF

DD

21

18

9

7

SADR

4

SADR

19

SADR SADR

SADR

3

V

DDQ

NC

PHS_L

DDQ

NC

SSV CMD5 CMD1 CMDV DDQ

10

11

SADR

20

SADR

14

SADR

8

SADR SADR

2

SADR

17

SADR

13

V

DDQ

V

DD

V

NC

CMD7

DD

CMD8

NC CE_L NC

DD

DDQ

1

AI04270

10/150

M7020R

Figure 4. M7020R Block Diagram

PHS_L

CLK2X

RST_L

Comparand Registers[15:0]

Global Mask Registers [7:0]

Information and Command Register

Burst Read Register

Burst Write Register

Next Free Address Register

Search Successful Index Registers [7:0]

(All registers are 68-bit-wide)

TAP

Controller

TAP

DQ [67:0]

Cmd Compare/PIO Data

Configurable as

64K x 34

32K x 68

16K x 136

8K x 272

SADR [21:0]

OE_L

CMD [8:0]

Command

Pipeline

and

SRAM

Control

CMDV

Decode

and PIO Access

Data Array

ACK

WE_L

EOT

Configurable as

64K x 34

CE_L

32K x 68

16K x 136

8K x 272

ALE_L

ID [4:0]

Mask Array

FULL [6:0]

Full Logic

LHI [6:0]

BHI [2:0]

FULL

LHO [1:0]

Arbitration

Logic

BHO [2:0]

SSF

SSV

FULO [1:0]

AI04271

11/150

M7020R

MAXIMUM RATING

Stressing the device above the rating listed in the

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Exposure to Absolute Maximum Rat-

ing conditions for extended periods may affect de-

vice

reliability.

Refer

also

to

the

STMicroelectronics SURE Program and other rel-

evant quality documents.

Table 3. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

T

STG

Storage Temperature (V Off)

DD

–0 to 70

°C

(1)

Lead Solder Temperature for 10 seconds

235

1.9

°C

V

T

SLD

V

Operating Supply Voltage

Voltage for I/O (3.3V)

DD

V

3.465

2.6

V

DDQ

V

Voltage for I/O (2.5V)

V

I

Output Current

200

< 5

mA

W

O

P

Power Dissipation

D

Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

12/150

M7020R

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests performed under the Measure-

ment Conditions listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 4. DC and AC Measurement Conditions

Sym

Parameter

Operating Supply Voltage

Voltage for I/O (3.3V)

Min

1.7

3.135

2.4

0

Max

Units

V

DD

V

1.9

DD

V

3.465

V

DDQ

V

Voltage for I/O (2.5V)

2.6

V

t

Ambient Operating Temperature

70

°C

%

V

A

Supply Voltage Tolerance

–5

+5

Input Pulse Levels (V

= 3.3V)

= 2.5V)

GND to 3.0

DDQ

Input Pulse Levels (V

GND to 2.5

V

Input Rise and Fall Times at 0.3V and 2.7V (V

= 3.3V)

≤ 2ns (see Figure 6, page 14)

ns

V

DDQ

Input Rise and Fall Times at 0.25V and 2.25V (V

= 2.5V)

≤ 2ns (see Figure 6, page 14)

DDQ

Input Timing Reference Levels (V

= 3.3V)

= 2.5V)

= 3.3V)

1.5

DDQ

1.25

V

DDQ

Output Timing Reference Levels (V

Output Load

1.5

V

DDQ

= 2.5V)

1.25

V

DDQ

(see Figure 5 and Figure 7, page 14)

V

Note: 1. Maximum allowable applies to overshoot only (V

2. Minimum allowable applies to undershoot only.

is 3.3V supply).

DDQ

13/150

M7020R

Figure 5. M7020R 2.5, or 3.3V AC Testing Load

Z = 50Ω

0

50Ω

D

OUT

V = 1.25V for V

V = 1.50V for V

L

= 2.5V

= 3.3V

L

DDQ

C

L

AC Load

AI05653

Figure 6. M7020R 2.5, or 3.3V Input Waveform

+2.5V V

+3.0V V

= 2.5V /

= 3.3V

DDQ

90%

10%

GND

AI04299

Figure 7. M7020R 2.5, or 3.3V I/O Output Load Equivalent

V

DDQ

208Ω for V

158Ω for V

= 2.5V

= 3.3V

DDQ

Q

192Ω for V

175Ω for V

= 2.5V

= 3.3V

DDQ

5pF

(1, 2)

For Hi-Z and V /V

OL OH

AI04266

Note: 1. Output loading is specified with CL = 5pF as in Figure 7. Transition is measured at ± 200 mV from steady-state voltage.

2. The load used for V , V testing is shown in Figure 7.

OH OL

14/150

M7020R

Table 5. Capacitance

Symbol

(1,2)

Parameter

Min

Max

6

Unit

pF

Test Condition

C

V

IN

= 0V

Input Capacitance

Output Capacitance

IN

(3)

V

OUT

6

pF

C

IO

Note: 1. Effective capacitance measured with power supply. Sampled only, not 100% tested.

2. At 25°C, f = 1MHz.

3. Outputs deselected.

Table 6. DC Characteristics

(1)

Sym

Parameter

Input Leakage Current

Output Leakage Current

Min

Max

Unit

Test Condition

V

= V

(max), V = 0 to V

(max)

±10

0.8

µA

V

I

LI

DDQ

IN

DDQ

I

V

= V

(max), V = 0 to V

(max)

LO

DDQ

IN

DDQ

V

IL

Input Low Voltage (V

= 3.3V)

= 2.5V)

= 3.3V)

–0.3

2.0

DDQ

V

IH

Input High Voltage (V

V

+ 0.3

DDQ

V

DDQ

V

IL

Input Low Voltage (V

–0.3

1.7

0.7

+ 0.3

DDQ

V

IH

Input High Voltage (V

V

DDQ

V

OL

Output Low Voltage (V

V

DDQ

= V

(min), I = 8mA

OL

0.4

V

DDQ

V

OH

Output High Voltage (V

Output Low Voltage (V

V

= V

(min), I

= 8mA

OH

2.4

2.0

V

DDQ

V

OL

= 2.5V)

V

DDQ

= V

(min), I = 8mA

DDQ OL

0.4

V

DDQ

V

OH

Output High Voltage (V

V

= V

(min), I

= 8mA

OH

V

DDQ

66MHz Search Rate

50MHz Search Rate

2300

1800

200

mA

I

1.8V Supply Current at V (max)

DD

DD1

DD2

66MHz Search Rate, I

50MHz Search Rate, I

66MHz Search Rate, I

50MHz Search Rate, I

= 0mA

OUT

3.3V Supply Current at V (max)

DD

= 0mA

150

160

2.5V Supply Current at V (max)

DD

120

Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 1.5V.

A

DD

15/150

M7020R

Figure 8. AC Timing Waveforms with CLK2X

Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle

0

1

2

3

4

5

6

7

8

9

10

11

12

CLK2X

CLK

tIHCH

tISCH

Signal

Group 0

tISCH

tIHCH

tISCH

Signal

Group 1

tIHCH

tICHCH

Signal

Group 2

tICSCH

tCKHOV

Signal

Group 3

tCKHOV

tCKHSHZ

Signal

Group 4

tCKHSV

tCKHSLZ

tCKHDZ

Signal

Group 5

tCKHDV

Signal Group 0: PHS_L, RST_L

Signal Group 1: DQ, CMD, CMDV

Signal Group 2: LHI, BHI, FULI

Signal Group 3: LHO, BHO, FULO, FULL

Signal Group 4: SADR, CE_L, OE_L, WE_L, ALE_L, SSF, SSV

Signal Group 5: DQ, ACK, EOT

AI04265

16/150

M7020R

Table 7. AC Timing Parameters with CLK2X

M7020R-050 M7020R-066 M7020R-083

(1)

Row Symbol

Unit

Description

Min

Max

Min

Max

Min

Max

f

1

2

3

100

133

166 MHz CLK2X frequency

ns CLK2X period

CLOCK

t

10

4.0

2.5

0.6

7.5

3.0

2.5

0.6

CLK

(2)

t

ns

CKHI

CLK2X high pulse

(2

t

4

5

6

CKLO

CLK2X low pulse

(2)

t

2.5

0.6

ISCH

Input Setup Time to CLK2X rising edge.

(2)

t

IHCH

Input Hold Time to CLK2X rising edge.

Cascaded Input Setup Time to CLK2X rising

t

7

8

9

4.2

0.6

4.2

0.6

4.2

0.6

ns

ICSCH

ICHCH

CKHOV

(2)

edge.

Cascaded Input Hold Time to CLK2X rising

t

(2)

edge.

Rising edge of CLK2X to LHO, FULO, BHO,

t

9.5

8.5

(3)

FULL valid.

(2)

t

10

11

12

10.0

9.5

9.0

9.5

9.0

ns

CKHDV

CKHDZ

CKHSV

Rising edge of CLK2X to DQ valid.

(4)

1.2

9.5

Rising edge of CLK2X to DQ high-Z.

(2)

10.0

Rising edge of CLK2X to SRAM Bus valid.

Rising edge of CLK2X to SRAM Bus high-

t

13

14

7.0

6.5

ns

CKHSHZ

(2,4)

Z.

Rising edge of CLK2X to SRAM Bus low-

t

7.5

7.0

CKHSLZ

(2,4)

Z.

Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 1.8V.

A

DD

2. Values are based on 50% signal levels.

3. Based on an AC load of CL = 30pF (see Figure 5, Figure 6, and Figure 7, page 14).

4. These parameters are sampled and not 100% tested, and are based on an AC load of 5pF.

17/150

M7020R

OPERATION

The following subsections contain command

(CMD and DQ Bus (command and databus), data-

base entry, arbitration logic, pipeline, and SRAM

control, and full logic descriptions.

Arbitration Logic

When multiple Search Engines are cascaded to

create large databases, the data being searched is

presented to all search engines simultaneously in

the cascaded system. If multiple matches occur

within the cascaded devices, arbitration logic on

the search engines will enable the winning device

(with a matching entry that is closest to address “0”

of the cascaded database) to drive the SRAM bus.

CMD Bus and DQ Bus

CMD[8:0] carries the CMD and its associated pa-

rameter. DQ[67:0] is used for data transfer to and

from the database entries, which comprise a data

and a mask field that are organized as data and

mask arrays. The DQ Bus carries the SEARCH

data (of the data and mask arrays and internal reg-

isters) during the SEARCH command as well as

the address and data during READ and/or WRITE

operations. The DQ Bus can also carry the ad-

dress information for the flow-through accesses to

the external SRAMs and/or SSRAMs.

Pipeline and SRAM Control

Pipeline latency is added to give enough time to a

cascaded system’s arbitration logic to determine

the device that will drive the index of the matching

entry on the SRAM bus. Pipeline logic adds laten-

cy to both the SRAM access cycles and the SSF

and SSV signals to align them to the host ASIC re-

ceiving the associated data.

Database Entry (Data Array and Mask Array)

Each database entry comprises a data and a mask

field. The resultant value of the entry is ’1,' ’0,’ or

’X (don’t care),’ depending on the value in the data

and mask bits. The on-chip priority encoder se-

lects the first matching entry in the database that

is nearest to location '0.'

Full Logic

Bit[0] in each of the 68-bit entries has a special

purpose for the LEARN command (0 = empty, 1 =

full). When all the data entries have bit[0] = 1, the

database asserts the FULL Flag, indicating all the

search engines in the depth-cascaded array are

full.

18/150

M7020R

CONNECTION DESCRIPTIONS

Clocks and Reset

SRAM Interface

Master Clock (CLK2X). M7020R samples all the

data and control pins on the positive edge of

CLK2X. All signals are driven out of the device on

the rising edge of CLK2X (when PHS_L is low).

Phase (PHS_L). This signal runs at half the fre-

quency of CLK2X and generates an internal CLK

from CLK2X see Figure 9, page 20.

SRAM Address (SADR[21:0]). This bus con-

tains address lines to access off-chip SRAMs that

contain associative data. See Table 50, page 127

for the details of the generated SRAM address. In

a database of multiple M7020Rs, each corre-

sponding bit of SADR from all cascaded devices

must be connected.

SRAM Chip Enable (CE_L). This is chip enable

control for external SRAMs. In a database of mul-

tiple M7020Rs, CE_L of all cascaded devices

must be connected. This signal is then driven by

only one of the devices.

SRAM Write Enable (WE_L). This is write en-

able control for external SRAMs. In a database of

multiple M7020Rs, WE_L of all cascaded devices

must be connected together. This signal is then

driven by only one of the devices.

Test Input (TEST - for Cypress Semiconductor

Use Only). This signal should be connected to

ground.

Reset (RST_L). Driving RST_L low initializes the

device to a known state.

CMD and DQ Bus

CMD Bus (CMD[8:0]. [1:0] specifies the com-

mand; [8:2] contains the CMD parameters. The

descriptions of individual commands explains the

details of the parameters. The encoding of com-

mands based on the [1:0] field are:

SRAM Output Enable (OE_L). This is output en-

able control for external SRAMs. Only the last de-

vice drives this signal (with the LRAM bit set).

– 00: PIO READ

– 01: PIO WRITE

– 10: SEARCH

– 11: LEARN

Address Latch Enable (ALE_L). When this sig-

nal is low, the addresses are valid on the SRAM

Address Bus. In a database of multiple M7020Rs,

the ALE_L of all cascaded devices must be con-

nected. This signal is then driven by only one of

the devices.

CMD Valid (CMDV). Qualifies the CMD bus:

– 0: No Command

Cascade Interface

– 1: Command

Local Hit In (LHI[6:0]). These pins depth-cas-

cade the device to form a larger table size. One

signal of this bus is connected to the LHO[1] or

LHO[0] of each of the upstream devices in a block.

All unused LHI pins are connected to a logic '0.'

(For more information, see DEPTH-CASCADING,

page 122.)

Address/Data Bus (DQ[67:0]). This signal carries

the READ and WRITE address and data during

register, data, and mask array operations. It car-

ries the compare data during SEARCH opera-

tions. It also carries the SRAM address during

SRAM PIO accesses.

READ Acknowledge (ACK). This signal indi-

cates that valid data is available on the DQ Bus

during register, data, and mask array READ oper-

ations, or the data is available on the SRAM data

bus during SRAM READ operations.

Note: ACK Signals require a weak external pull-

down resistor such as 47 or 100 KΩ.

End of Transfer (EOT). This signal indicates the

end of burst transfer to the data or mask array dur-

ing READ or WRITE burst operations.

Note: EOT Signals require a weak external pull-

down resistor such as 47 KΩ or 100 KΩ.

SEARCH Successful Flag (SSF). When assert-

ed, this signal indicates that the device is the glo-

bal winner in a SEARCH operation.

SEARCH Successful Flag Valid (SSV). When

asserted, this signal qualifies the SSF signal.

Local Hit Out (LHO[1:0]). LHO[1] and LHO[0]

are the same logical signal. LHO[1] or LHO[0] is

connected to one input of the LHI bus of up to four

downstream devices in a block of up to eight de-

vices. (For more information, see DEPTH-CAS-

CADING, page 122.)

Block Hit In (BHI[2:0]). Inputs from the previous

BHO[2:0] are tied to the BHI[2:0] of the current de-

vice. In a four-block system, the last block can

contain only seven devices because the ID code

11111 is used for broadcast access.

Block Hit Out (BHO[2:0]). These outputs from

the last device in a block are connected to the

BHI[2:0] inputs of the devices in the downstream

blocks.

Full In (FULI[6:0]). Each signal in this bus is con-

nected to FULO[0] or FULO[1] of an upstream de-

vice to generate the FULL signal for the depth-

cascaded block.

19/150

M7020R

Full Out (FULO[1:0]). FULO[1] and FULO[0] are

the same logical signal. One of these two signals

must be connected to the FULI of up to four down-

stream devices in a depth-cascaded table. Bit [0]

in the data array indicates if the entry is full (1) or

empty (0).This signal is asserted if all of the bits in

the data array are ’1s.’ Refer to Depth-Cascading

to Generate a “FULL” Signal, page 122.

On a broadcast READ-only, the device with the

LDEV bit set to '1' responds.

Supplies

Chip Core Supply (V ). This is equal to 1.8V.

DD

Chip I/O Supply (V

). This is equal to either

DDQ

2.5 or 3.3V.

Test Access Port

Full Flag (FULL). When asserted, this signal in-

dicates that the table consisting of many depth-

cascaded devices is full.

Test Data In (TDI). This is the Test Access Port’s

Test Data In.

Test Clock (TCK). This is the Test Access Port’s

Test Clock.

Device Identification

Device Identification (ID[4:0]). The binary-en-

coded device ID for a depth-cascaded system

starts at 00000 and goes up to 11110. 11111 is re-

served for a special broadcast address that se-

lects all cascaded search engines in the system.

Test Data Out (TDO). This is the Test Access

Port’s Test Data Out.

Test Mode Select (TMS). This is the Test Ac-

cess Port’s Test Mode Select.

Test Reset (TRST_L). This is the Test Access

Port’s Test Reset.

CLOCKS

The M7020R receives the CLK2X and PHS_L sig-

nals. It uses the PHS_L signal to divide CLK2X

and generate an internal clock (CLK), as shown in

Figure 9. The M7020R uses CLK2X and CLK for

internal operations.

Figure 9. Clocks (CLK2X and PHS_L)

CLK2X

PHS_L

(1)

CLK

AI04750

Note: Any reference to “CLK Cycles” means 1 cycle of the signal, “CLK.”

1. “CLK” is an internal signal.

20/150

M7020R

REGISTERS

All registers in the M7020R are 68 bits wide. The

M7020R contains 8 pairs of comparand storage

registers, 16 pairs of global mask registers

(GMRs), eight search successful index registers

and one each of CMD, information, burst READ,

burst WRITE, and next-free address registers. Ta-

ble 8 provides an overview of all the M7020R reg-

isters. The registers are ordered in ascending

address order. Each register group is then de-

scribed in the following subsections.

Table 8. Register Overview

Address

Abbreviation

Type

Name

16 Comparand Registers. Stores comparands from the DQ Bus for

learning later.

0–31

COMP0–31

R

32–47

48–55

56

MASKS

SSR0–7

COMMAND

INFO

RW

R

8 Global Mask Registers Array.

8 SEARCH Successful Index Registers.

Command Register.

RW

R

57

Information Register.

58

RBURREG

WBURREG

NFA

RW

R

Burst Read Register.

59

Burst Write Register.

60

Next Free Address Register.

Reserved

61–63

–

21/150

M7020R

Comparand Registers

Figure 10. Comparand Register Selection

During SEARCH and LEARN

Instructions

The device contains 32 68-bit comparand regis-

ters (16 pairs) dynamically selected in every

SEARCH operation to store the comparand pre-

sented on the DQ Bus. The LEARN command will

later use these registers when executed. The

M7020R stores the SEARCH command’s Cycle A

comparand in the even-numbered register and the

Cycle B comparand in the odd-numbered register,

as shown in Figure 10.

68

Address

Index

135

0

1

0

1

2

4

3

5

Mask Registers

The device contains 16 68-bit global mask regis-

ters (8 pairs) dynamically selected in every

SEARCH operation to select the search subfield.

The addressing of these registers is explained in

Figure 11. The three-bit GMR Index supplied on

the CMD bus can apply 8 pairs of global masks

during the SEARCH and WRITE operations, as

shown in Figure 11.

6

7

Note: In 68-bit SEARCH and WRITE operations,

the host ASIC must program both the even and

odd mask registers with the same values.

15

30

31

Each mask bit in the GMRs is used during

SEARCH and WRITE operations. In SEARCH op-

erations, setting the mask bit to '1' enables com-

pares; setting the mask bit to '0' disables

compares (forced match) at the corresponding bit

position. In WRITE operations to the data or mask

array, setting the mask bit to '1' enables WRITEs;

setting the mask bit to '0' disables WRITEs at the

corresponding bit position.

AI04275

Figure 11. Addressing the Global Masks

Register Array

68

Address

Index

135

0

2

4

6

8

1

3

5

7

9

1

2

3

4

11

10

5

6

7

13

15

12

14

SEARCH and WRITE Command

Global Mask Selection

AI04276

22/150

M7020R

SEARCH-Successful Registers (SSR[0:7])

The device contains eight search successful reg-

isters (SSRs) to hold the index of the location

where a successful search occurred. The format of

each register is described in Table 9. The

SEARCH command specifies which SSR stores

the index of a specific SEARCH command in Cy-

cle B of the SEARCH Instruction. Subsequently,

the host ASIC can use this register to access that

data array, mask array, or external SRAM using

the index as part of the indirect access address

(see Table 19, page 32 and Table 22, page 35).

The device with a valid bit set performs a READ or

WRITE operation. All other devices suppress the

operation.

Table 9. SEARCH-Successful Register (SSR) Description

Field

Range

Initial Value

Description

Index. This is the address of the 68-bit entry where a successful

search occurs. The device updates this field only when a search is

successful. If a hit occurs in a 136-bit entry-size quadrant, the LSB is

’0.’ If a hit occurs in a 272-bit entry size quadrant, the two LSBs are

’00.’ This index updates if the device is either a local or global winner

in a SEARCH operation.

INDEX

[14:0]

X

–

VALID

–

[30:15]

[31]

0

Reserved.

Valid. During SEARCH operation in a depth-cascaded configuration,

the device that is a global winner in a match sets this bit to '1.' This bit

updates only when the device is a global winner in a SEARCH

operation.

[67:32]

Reserved.

23/150

M7020R

The Command Register

Table 10. Command Register Field Descriptions

Field

Range

Initial Value

Description

Software Reset. If ’1,’ this bit resets the device, with the same effect

as the hardware reset. Internally, it generates a reset pulse lasting for

eight CLK cycles. This bit automatically resets to a ’0’ the reset cycle

has completed.

SRST

[0]

0

Device Enable. If ’0,’ it keeps the SRAM Bus (SADR, WE_L, CE_L,

OE_L, and ALE_L), SSF, and SSV signals in 3-state condition and

forces the cascade interface output signals LHO[1:0] and BHO[2:0] to

’0.’ It also keeps the DQ Bus in input mode. The purpose of this bit is

to make sure that there are no bus contentions when the devices

power up in the system.

DEVE

TLSZ

[1]

0

Table Size. The host ASIC must program this field to configure the

chips into a table of a certain size. This field affects the pipeline

latency of the SEARCH and LEARN operations as well as the READ

and WRITE accesses to the SRAM (SADR[21:0], CE_L, OE_L,

WE_L, ALE_L, SSV, SSF, and ACK). Once programmed, the search

latency stays constant.

[3:2]

01

Latency in #

of CLK Cycles

00: 1 device

4

5

6

TLSZ

[3:2]

01

01: 2-8 devices

10: 9-31 devices

11: Reserved

Latency of Hit Signals. This field adds latency to the SSF and SSV

signals during SEARCH, and ACK signal during SRAM READ access

by the following number of CLK cycles.

000: 0

001: 1

010: 2

011: 3

100: 4

101: 5

110: 6

111: 7

HLAT

[6:4]

000

Last Device in the Cascade. When set, this device is the last device

on the SRAM bus in the depth-cascaded table and is the default driver

for the SSF and SSV signals.

In the event of a SEARCH failure, the device with this bit set drives the

hit signals as follows:

SSF = 0, SSV = 1

LDEV

[7]

0

During non-SEARCH cycles, the device with this bit set drives the

signals as follows:

SSF = 0, SSV = 0

Last device on this SRAM Bus. When set, this device is the last

device on this SRAM bus in the depth-cascaded table and is the

default driver for the SADR, CE_L, WE_L, and ALE_L signals. In

cycles where no M7020R device in a depth-cascaded table drives

these signals, this device drives the signals as follows:

SADR = 3FFFFF,

LRAM

[8]

0

CE_L = 1

WE_L = 1

ALE_L = 1

OE_L is always driven by the device for which this bit is set.

24/150

M7020R

Field

Range

Initial Value

Description

Database Configuration. The device is internally divided into four

quadrants of 8K x 68, each of which can be configured as 8K x 68, 4K

x 136, or 2K x 272 as follows:

00: 8K x 68

01: 4K x 136

10: 2K x 272

0000

11: Reserved

CFG

[16:9]

Bits [10:9] apply to configuring the 1st quadrant in the address space.

Bits [12:11] apply to configuring the 2nd quadrant in the address

space.

Bits [14:13] apply to configuring the 3rd quadrant in the address

space.

Bits [16:15] apply to configuring the 4th quadrant in the address

space.

[67:17]

0

Reserved.

The Information Register

Table 11. Information Register Field Descriptions

Field

Range

Initial Value

Description

Revision Number. This is the current device revision

number. Numbers start from one and increment by one

for each revision of the device.

(1)

Revision

[3:0]

0001

Implementation

Reserved

[6:4]

[7]

001

0

This is the M7020R implementation number.

Reserved.

Device ID

[11:8]

[12]

0001 or 0010

This is the Device Identification Number.

Reserved

Device ID

[15:13]

00000100

This is the Device Identification Number.

Manufacturer ID. This field is the same as the

MFID

[31:16]

1101_1100_0111_1111 manufacturer ID and continuation bits in the TAP

controller.

[67:32]

Reserved.

Note: 1. This field may change in future versions.

25/150

M7020R

The Read Burst Address Register (RBURREG)

These READ burst address register fields must be

programmed before burst READ (see Table 12).

set to ’0’). Every WRITE/LEARN command loads

the address of first 68-bit location that contains a

'0' in the entry’s bit[0]. This is stored in the NFA

register (see Table 14). If all the bits in a device are

set to '1,' the M7020R asserts FULO[1:0] to '1.'

In 136-bit-configured quadrants, the LSB of this

register is always set to '0.' The host ASIC must

set bit '0' and Bit 68in a 136-bit word to either '0' or

'1' to indicate full/empty status.

The Write Burst Address Register (WBURREG)

These WRITE burst address register fields must

be programmed before burst WRITE (see Table

13).

The NFA Register

Bit [0] of each 68-bit data entry is a special bit des-

ignated for use in the operation of the LEARN

command. In 68-bit quadrants, the bit[0] indicates

whether a location is full (bit set to ’1’) or empty (bit

Note: Both bits (0 and 68) must be set to '0' or '1'

(e.g., '10' or '01' settings are invalid).

Table 12. Read Burst Register Description

Field

Range

Initial Value

Description

Address. This is the starting address of the data array or mask array

during a burst READ operation. It automatically increments by 1 for

each successive read of the data array or mask array. Once the

operation is complete, the contents of this field must be reinitialized for

the next operation.

ADR

[14:0]

0

[18:15]

[27:19]

[67:28]

Reserved.

Length of Burst Access. The device is capable of writing from 4 up

to 511 locations in a single burst. The BLEN decrements

automatically. Once the operation is complete, the contents of this

field must be reinitialized for the next operation.

BLEN

0

Reserved.

Table 13. Write Burst Register Description

Field

Range

Initial Value

Description

Address. This is the starting address of the data array or mask array

during a burst WRITE operation. It automatically increments by 1 for

each successive write of the data array or mask array. Once the

operation is complete, the contents of this field must be reinitialized for

the next operation.

ADR

[14:0]

0

[18:15]

[27:19]

[67:28]

Reserved.

Length of Burst Access. The device is capable of writing from 4 up

to 511 locations in a single burst. The BLEN decrements

automatically. Once the operation is complete, the contents of this field

must be reinitialized for the next operation.

BLEN

0

Reserved.

Table 14. NFA Register

Address

67 - 15

14 - 0

Index

60

Reserved

26/150

M7020R

SEARCH ENGINE ARCHITECTURE

The M7020R consists of 32K x 68-bit storage cells

referred to as data bits. There is a mask cell corre-

sponding to each data cell. Figure 12 shows the

three organizations of the device based on the val-

ue of the CFG bits in the command register.

During a SEARCH operation, the search data bit

(S), data array bit (D), mask array bit (M) and the

global mask bit (G) are used in the following man-

ner to generate a match at that bit position (see

Table 15, page 28).

272-bit positions must generate a match for 4 con-

secutive entries aligned to 4 entry-page bound-

aries of 68-bit entries in quadrants configured as

272 bits.

An arbitration mechanism using a cascade bus de-

termines the global winning device among the lo-

cal winning devices in a SEARCH cycle. The

global winning device drives the SRAM Bus, SSV,

and the SSF signals. In case of a SEARCH failure,

the devices with the LDEV and LRAM bits set

drive(s) the SRAM Bus, SSF, and SSV signals.

The M7020R device can be configured to contain

tables of different widths, even within the same

chip. Figure 13, page 28 shows a sample configu-

ration of different widths.

Data and Mask Addressing

Figure 14, page 28 shows the M7020R data array

and mask array addressing procedure.

The entry with all matched bit positions results in a

successful search during a SEARCH operation.

In order for a successful search within a device to

make the device the local winner in the SEARCH

operation, all 68-bit positions must generate a

match for a 68-bit entry in 68-bit-configured quad-

rants, or all 136-bit positions must generate a

match for two consecutive even and odd 68-bit en-

tries in quadrants configured as 136 bits, or all

Figure 12. M7020R Database Width Configuration

68

136

272

Masks

8 K

16 K

32 K

Data

Masks

CFG = 10101010

Data

CFG = 01010101

CFG = 00000000

AI04279

27/150

M7020R

Table 15. Bit Position Match

Figure 13. Multi-width Configuration Example

G

0

1

M

X

0

1

D

X

0

1

0

1

S

X

0

1

Match

1

0

1

68

8 K

68

8 K

136

4 K

2 K

272

CFG = 10010000

AI04280

Figure 14. M7020R Data and Mask Array Addressing

68

67

0

271

0

135

0

1

2

3

0

4

1

5

2

6

3

7

0

2

4

6

1

3

5

7

8K

32764

32765

32766

32767

32 K

16K

CFG = 10101010

(272-bit configuration)

32767

CFG = 00000000

(68-bit Configuration)

32766

32767

CFG = 01010101

(136-bit Configuration)

AI04281

28/150

M7020R

COMMAND CODES AND PARAMETERS

A master device, such as an ASIC controller, is-

sues commands to the M7020R using the Com-

mand Valid CMDV signal and the CMD Bus. The

following subsections describe the functions of the

commands.

cles. These two CLK2X cycles are designated as

“Cycle A” and “Cycle B.” The controller ASIC must

align the instructions with the PHS_L signal. The

CMD[8:2] field passes the parameters of the com-

mand in Cycles A and B.

Command Codes

Commands and Command Parameters

The M7020R implements four basic commands

shown in Table 16. The Command Code must be

presented to CMD[1:0] while keeping the com-

mand valid (CMDV) signal high for two CLK2X cy-

Table 17, page 29 lists the CMD bus fields that

contain the M7020R command parameters as well

as their respective cycles.

Table 16. Command Codes

CMD Code

Command

Description

Reads one of the following: data array, mask array, device registers, or external

SRAM.

00

READ

Writes one of the following: data array, mask array, device registers, or external

SRAM.

01

10

WRITE

Searches the data array for a desired pattern using the specified register from the

global mask register array and local mask associated with each data cell.

SEARCH

The device has internal storage for up to 16 comparands that it can learn. The

device controller can insert these entries at the next free address (as specified by

the NFA register) using the LEARN Instruction.

11

LEARN

Table 17. Command Parameters

Cmd

Cyc

8

7

6

5

4

3

2

1

0

0 = Single

1 = Burst

A

SADR[21]

SADR[20]

X

0

READ

0 = Single

1 = Burst

B

A

B

0

SADR[21]

0

SADR[20]

0

X

0

1

Global Mask

0 = Single

1 = Burst

Register Index [2:0]

WRITE

Global Mask

0 = Single

1 = Burst

Register Index [2:0]

68-bit or 136-bit: 0

272-bit:

1 in 1st Cycle

Global Mask

Register Index [2:0]

A

SADR[21]

SADR[20]

SADR[19]

1

0

SEARCH

0 in 2nd Cycle

B

A

Successful Search Register Index[2:0]

Comparand Register Index

1

0

1

SADR[21]

SADR[20]

X

Comparand Register Index

(1)

Mode

0: 68-bit

1: 136-bit

LEARN

B

0

Comparand Register Index

1

Note: 1. The 272-bit-configured devices or 272-bit-configured quadrants within devices do not support the LEARN Instruction.

29/150

M7020R

READ COMMAND

The READ can be a single read of a data array, a

mask array, an SRAM, or a register location

(CMD[2] = 0). It can be a burst READ (CMD[2] = 1)

or mask array locations using an internal auto-in-

crementing address register (RBURADR). Table

18, page 32 describes each type of READ com-

mand.

and describes the format of the READ address for

a data array, mask array, or SRAM.

In a burst READ operation, the READ lasts 4 + 2n

CLK-cycles (where “n” stands for the number of

accesses in the burst specified by the BLEN field

of the RBURREG). Table 20, page 33 describes

the READ address format for the internal registers.

Figure 16, page 31 illustrates the timing diagram

for the burst READ of the data or mask array. This

operation assumes that the host ASIC has pro-

grammed the RBURREG with the starting address

(ADR) and the length of transfer (BLEN) before ini-

tiating the burst READ command.

A single-location READ operation lasts six cycles,

as shown in Figure 15, page 31. The burst READ

adds two cycles for each successive READ. The

SADR[21:20] bits supplied in the READ Instruction

Cycle A drive SADR[21:20] signals during the

READ of an SRAM location.

The single READ operation takes six CLK cycles,

in the following sequence:

– Cycle 1: The host ASIC applies the READ In-

struction on the CMD[1:0] (CMD[2] = 1), using

CMDV=1 and the address supplied on the DQ

Bus, as shown in Table 21, page 33. The host

ASIC selects the M7020R for which ID[4:0]

matches the DQ[25:21] lines. If the DQ[25:21] =

11111, the host ASIC selects the M7020R with

the LDEV Bit set.

– Cycle 2: The host ASIC floats DQ[67:0] to the 3-

state condition.

– Cycle 3: The host ASIC keeps DQ[67:0] in the

– Cycle 1: The host ASIC applies the READ In-

struction on the CMD[1:0] (CMD[2] = 0), using

CMDV = 1, and the DQ Bus supplies the ad-

dress, as shown in Table 19, page 32 and Table

20, page 33. The host ASIC selects the M7020R

for which ID[4:0] matches the DQ[25:21] lines. If

the DQ[25:21] = 11111, the host ASIC selects

the M7020R with the LDEV Bit set. The host

ASIC also supplies SADR[21:20] on CMD[8:7]

in Cycle A of the READ Instruction if the READ

is directed to the external SRAM.

3-state condition.

– Cycle 4: The selected device starts to drive the

DQ[67:0] Bus and drives ACK and EOT from Z

to low.

– Cycle 2: The host ASIC floats DQ[67:0] to 3-

state condition.

– Cycle 3: The host ASIC keeps DQ[67:0] in 3-

– Cycle 5: The selected device drives the READ

data from the addressed location on the

DQ[67:0] Bus and drives the ACK signal high.

state condition.

– Cycle 4: The selected device starts to drive the

DQ[67:0] Bus and drives the ACK signal from Z

to low.

– Cycle 5: The selected device drives the read

data from the addressed location on the

DQ[67:0] Bus and drives the ACK signal high.

Note: Cycles four and five repeat for each addi-

tional access until all the accesses specified in

the burst length (BLEN) field of RBURREG are

complete. On the last transfer, the M7020R

drives the EOT signal high.

– Cycle 6: The selected device floats DQ[67:0] to

– Cycle (4 + 2n): The selected device drives the

DQ[67:0] to 3-state condition and drives the

ACK and the EOT signals low.

At the termination of Cycle 4 + 2n, the selected de-

vice floats the ACK line to 3-state condition. The

burst READ Instruction is complete, and a new op-

eration can begin (see Table 21, page 33 for burst

READ address formats).

3-state condition and drives the ACK signal low.

At the termination of Cycle 6, the selected device

releases the ACK line to 3-state condition. The

READ Instruction is complete, and a new opera-

tion can begin.

Note: The latency of the SRAM READ will be dif-

ferent than the one described above (see SRAM

PIO Access, page 126). Table 19, page 32 lists

30/150

M7020R

Figure 15. Single Location READ Cycle Timing

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 6

CLK2X

PHS_L

CMDV

Read

CMD[1:0]

CMD[8:2]

A

B

Data

DQ

Address

FF

ACK

AI04672

Figure 16. Burst READ of the Data and Mask Arrays (BLEN = 4)

Cycle 1

Cycle 3

Cycle 5

Cycle 4

Cycle 7

Cycle 6

Cycle 9

Cycle 8 Cycle 10

Cycle 11

Cycle 12

Cycle 2

CLK2X

PHS_L

CMDV

Read

CMD[1:0]

CMD[8:2]

DQ

A

B

Address

Data2

Data3

Data0 FF Data1 FF

FF

ACK

EOT

AI04283

31/150

M7020R

Table 18. READ Command Parameters

CMD Parameter

Read Command

CMD[2]

Description

Reads a single location of the data array, mask array, external SRAM,

or device registers. All access information is applied on the DQ Bus.

0

Single Read

Reads a block of locations from the data array or mask array as a

burst.

The internal register (RBURADR) specifies the starting address and

the length of the data transfer from the data array or mask array, and it

auto-increments the address for each access.

1

Burst Read

All other access information is applied on the DQ Bus.

Note: The device registers and external SRAM can only be read in

single-read mode.

Table 19. Data and Mask Array, SRAM Read Address Format

DQ

[67:30]

[29]

[28:26]

[25:21]

[20:19]

[18:15]

[14:0]

If DQ[29] is ’0,’ this field carries

address of data array location.

If DQ[29] is ’1,’ the successful

search register ID (SSRI)

specified on DQ[28:26] supplies

the address of the data array

location:

SuccessfulSEARCH

Register Index

1: Indirect (Applicable if DQ[29]

is indirect)

0: Direct

00: Data

Array

Reserved

ID

Reserved

{SSR[14:2], SSR[1] | DQ[1],

(1)

SSR[0] | DQ[0]}

If DQ[29] is ’0,’ this field carries

address of mask array location.

If DQ[29] is ’1,’ the successful

search register ID (SSRI)

specified on DQ[28:26] supplies

the address of the mask array

location:

SuccessfulSEARCH

0: Direct

Register Index

1: Indirect (Applicable if DQ[29]

is indirect)

01: Mask

Array

Reserved

{SSR[14:2], SSR[1] | DQ[1],

(1)

SSR[0] | DQ[0]}

If DQ[29] is ’0,’ this field carries

address of SRAM location.

If DQ[29] is ’1,’ the successful

search register ID (SSRI)

specified on DQ[28:26] supplies

the address of the SRAM

location:

SuccessfulSEARCH

10:

External

SRAM

0: Direct

Register Index

1: Indirect (Applicable if DQ[29]

is indirect)

Reserved

{SSR[14:2], SSR[1] | DQ[1],

(1)

SSR[0] | DQ[0]}

Note: 1. “|” stands for Logical OR operation. “{ }” stands for concatenation operator.

32/150

M7020R

Table 20. READ Address Format for Internal Registers

DQ[67:26]

DQ[25:21]

DQ[20:19]

DQ[18:6]

DQ[5:0]

Reserved

ID

11: Register

Reserved

Register Address

Table 21. READ Address Format for Data and Mask Arrays

DQ[67:26]

DQ[25:21]

DQ[20:19]

DQ[18:15]

DQ[14:0]

Do not care. These 15 bits come from the internal

register (RBURADR) which increments for each

access.

Reserved

ID

00: Data Array

Reserved

Do not care. These 16 bits come from the internal

register (RBURADR) which increments for each

access.

01: Mask

Array

Reserved

ID

Reserved

WRITE COMMAND

The WRITE can be a single write of a data array,

mask array, register, or external SRAM location

(CMD[2] = 0). It can be a burst WRITE

(CMD[2] = 1) using an internal auto-incrementing

address register (WBURADR) of the data array or

mask array locations. A single-location WRITE is a

three-cycle operation, shown in Figure 17, page

34. The burst WRITE adds one extra cycle for

each successive WRITE.

– Cycle 3: Idle cycle. At the termination of this cy-

cle, another operation can begin.

Note: The latency of the SRAM WRITE will be

different than the one described above (see

SRAM PIO Access, page 126).

The burst WRITE operation lasts for n + 2 CLK cy-

cles (where n signifies the number of accesses in

the burst as specified in the BLEN field of the

WBURREG register, please see Figure 18, page

35).

The WRITE operation sequence is as follows:

– Cycle 1A: The host ASIC applies the WRITE In-

struction on the CMD[1:0] (CMD[2] = 0), using

CMDV=1 and the address supplied on the DQ

Bus, as shown in Table 22, page 35. The host

ASIC also supplies the index to the global mask

register to mask the write to the data array or

mask array location in CMD[5:3]. For SRAM

WRITEs, the host ASIC must supply the

SADR[21:20] on CMD[8:6]. The host ASIC sets

CMD[9] to '0' for the normal WRITE.

This operation assumes that the host ASIC has

programmed the WBURREG with the starting ad-

dress (ADR) and the length of transfer (BLEN) be-

fore initiating the burst write command (see Table

24, page 36 for format). The sequence is as fol-

lows:

– Cycle 1A: The host ASIC applies the WRITE In-

struction on the CMD[1:0] (CMD[2] = 1), using

CMDV = 1 and the address supplied on the DQ

Bus, as shown in Table 24, page 36. The host

ASIC also supplies the index to the global mask

register to mask the write to the data or mask ar-

ray locations in CMD[5:3].

– Cycle 1B: The host ASIC continues to apply the

WRITE

Instruction

to

the

CMD[1:0]

(CMD[2] = 0), using CMDV = 1 and the address

supplied on the DQ Bus. The host ASIC contin-

ues to supply the global mask register index to

mask the WRITE to the data or mask array loca-

tions in CMD[5:3]. The host ASIC selects the

device where ID[4:0] matches the DQ[25:21]

lines, or it selects all the devices when

DQ[25:21] = 11111.

– Cycle 1B: The host ASIC continues to apply the

WRITE

Instruction

on

the

CMD[1:0]

(CMD[2] = 0), using CMDV = 1 and the address

supplied on the DQ Bus. The host ASIC contin-

ues to supply the global mask register index to

mask the WRITE to the data or mask array loca-

tions in CMD[5:3]. The host ASIC selects the

device where ID[4:0] matches the DQ[25:21]

lines, or it selects all the devices when

DQ[25:21] = 11111.

– Cycle 2: The host ASIC drives the DQ[67:0]

with the data to be written to the data array,

mask array, external SRAM, or register location

of the selected device.

33/150

M7020R

– Cycle 2: The host ASIC drives the DQ[67:0]

with the data to be written to the data array or

mask array location of the selected device. The

M7020R writes the data from the DQ[67:0] Bus

only to the subfield that has the corresponding

mask bit set to '1' in the global mask register

specified by the index CMD[5:3] and supplied in

Cycle 1.

The M7020R writes the data on the DQ[67:0]

Bus only to the subfield that has the correspond-

ing mask bit set to '1' in the global mask register

specified by the index CMD[5:3] and supplied in

Cycle 1. The M7020R drives the EOT signal low

from Cycle 3 to Cycle n; the M7020R drives the

EOT signal high in Cycle n + 1 (n is specified in

the BLEN field of the WBURREG).

– Cycles 3 to n + 1: The host ASIC drives the

DQ[67:0] with the data to be written to the next

data array or mask array location (addressed by

the auto-increment ADR field of the WBURREG

register) of the selected device.

– Cycle n + 2: The M7020R drives the EOT signal

low. At the termination of the Cycle n + 2, the

M7020R floats the EOT signal to a 3-state, and

a new instruction can begin.

Figure 17. Single Location WRITE Cycle Timing

Cycle 0

Cycle 1

Cycle 2

Cycle 3

Cycle 4

CLK2X

PHS_L

CMDV

CMD[1:0]

CMD[8:2]

DQ

Write

A

B

Data

X

Address

AI04284

34/150

M7020R

Figure 18. Burst WRITE of the Data and Mask Arrays (BLEN = 4)

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 6

CLK2X

PHS_L

CMDV

CMD[1:0]

CMD[8:2]

Write

A

B

DQ

Data1

Data3

Address

Data0

Data2

X

EOT

AI04285

Table 22. (Single) WRITE Address Format for Data and Mask Arrays or SRAM

DQ

[67:30]

[29]

[28:26]

[25:21]

[20:19]

[18:15]

[14:0]

If DQ[29] is ’0,’ this field carries the

address of the data array location.

If DQ[29] is ’1,’ the successful

search register specified by

DQ[28:26] supplies the address of

the data array location:

Successful

SEARCH

Register

Index

(Applicable

if DQ[29] is

indirect)

0: Direct

1: Indirect

00: Data

Array

Reserved

ID

Reserved

{SSR[14:2], SSR[1] | DQ[1], SSR[0]

(1)

| DQ[0]}

If DQ[29] is ’0,’ this field carries

address of the mask array location.

If DQ[29] is ’1,’ the successful

search register specified by

DQ[28:26] supplies the address of

the mask array location:

Successful

SEARCH

Register

Index

(Applicable

if DQ[29] is

indirect)

0: Direct

1: Indirect

01: Mask

Array

{SSR[14:2], SSR[1] | DQ[1], SSR[0]

(1)

| DQ[0]}

If DQ[29] is ’0,’ this field carries

address of the data SRAM location.

If DQ[29] is ’1,’ the successful

search register specified by

DQ[28:26] supplies the address of

the SRAM location:

Successful

SEARCH

Register

Index

(Applicable

if DQ[29] is

indirect)

10:

External

SRAM

0: Direct

1: Indirect

{SSR[14:2], SSR[1] | DQ[1], SSR[0]

(1)

| DQ[0]}

Note: 1. “|” stands for Logical OR operation. “{ }” stands for concatenation operator.

35/150

M7020R

Table 23. WRITE Address Format for Internal Registers

DQ[67:26]

DQ[25:21]

DQ[20:19]

DQ[18:6]

DQ[5:0]

Reserved

ID

11: Register

Reserved

Register address

Table 24. WRITE Address Format for Data and Mask Array (Burst Write)

DQ

[67:26]

[25:21]

[20:19]

[18:15]

[14:0]

Don’t care. These 15 bits come from the internal

register (WBURADR), which increments with each

access.

Reserved

ID

00: Data array

Reserved

Don’t care. These 15 bits come from the internal

register (WBURADR), which increments with each

access.

01: Mask

array

Reserved

ID

Reserved

SEARCH COMMAND

The M7020R (Silicon) Search Engine can be con-

figured in ten ways:

tion assumes that the host ASIC has programmed

TLSZ to '00,' HLAT to '000,' LRAM to '1,' and LDEV

to '1' in the command register.

The following is the sequence of operations for a

single 68-bit SEARCH command.

– 68-bit SEARCH on tables configured as x68

using one device

– 68-bit SEARCH on tables configured as x68

using up to 8 devices

– Cycle A: The host ASIC drives CMDV high and

applies the SEARCH command code ('10') on

CMD[1:0] signals. CMD[5:3] must be driven with

the index to the global mask register pair for use

in the SEARCH operation. CMD[8:7] signals

must be driven with the same bits that will be

driven on SADR[21:20] by this device if it has a

hit. DQ[67:0] must be driven with the 68-bit data

to be compared. The CMD[2] signal must be

driven to Logic '0.'

– Cycle B: The host ASIC continues to drive

CMDV high and applies the SEARCH command

('10') on CMD[1:0]. CMD[5:2] must be driven by

the index of the comparand register pair for stor-

ing the 136-bit word presented on the DQ Bus

during Cycles A and B. CMD[8:6] signals must

be driven with the index of the SSR that will be

used for storing the address of the matching en-

try and the Hit Flag (see SEARCH-Successful

Registers (SSR[0:7]), page 23). The DQ[67:0]

continues to carry the 68-bit data to be com-

pared.

– 68-bit SEARCH on tables configured as x68

using up to 31 devices

– 136-bit SEARCH on tables configured as

x136 using one device

– 136-bit SEARCH on tables configured as

x136 using up to 8 devices

– 136-bit SEARCH on tables configured as

x136 using up to 31 devices

– 272-bit SEARCH on tables configured as

x272 using one devices

– 272-bit SEARCH on tables configured as

x272 using up to 8 devices

– 272-bit SEARCH on tables configured as

x272 using up to 31 devices

– Mixed-sizes on tables configured with differ-

ent widths using an M7020R

Note: In the 68-bit configuration, the host ASIC

must supply the same data on DQ[67:0] during

both Cycles A and B. The even and odd pair of

GMRs selected for the comparison must be pro-

grammed with the same value.

68-bit Configuration with Single Device

The hardware diagram of the search subsystem of

a single device is shown in Figure 19. Figure 20,

page 38 shows the timing diagram for a SEARCH

operation in the 68-bit configuration (CFG =

00000000) for one set of parameters. This illustra-

36/150

M7020R

The logical 68-bit SEARCH operation is shown in

Figure 21, page 39. The entire table consisting of

68-bit entries is compared to a 68-bit word K (pre-

sented on the DQ Bus in both Cycles A and B of

the command) using the GMR and the local mask

bits. The effective GMR is the 68-bit word speci-

fied by the identical value in both even and odd

GMR pairs selected by the GMR Index in the com-

mand’s Cycle A. The 68-bit word K (presented on

the DQ Bus in both Cycles A and B of the com-

mand) is also stored in both even and odd com-

parand register pairs selected by the Comparand

Register Index in the command’s Cycle B. In a x68

configuration, only the even comparand register

can be subsequently used by the LEARN com-

mand. The word K (presented on the DQ Bus in

both Cycles A and B of the command) is compared

with each entry in the table starting at location “0.”

The first matching entry’s location address, “L,” is

the winning address that is driven as part of the

SRAM address on the SADR[21:0] lines (see

SRAM ADDRESSING, page 126).

The SEARCH command is a pipelined operation

and executes a SEARCH at half the rate of the fre-

quency of CLK2X for 68-bit searches in x68-con-

figured tables. The latency of SADR, CE_L,

ALE_L, WE_L, SSV, and SSF from the 68-bit

SEARCH command cycle (two CLK2X cycles) is

shown in Table 25, page 39.

The latency of a SEARCH from command to

SRAM access cycle is 4 for a single device in the

table and TLSZ = 00. In addition, SSV and SSF

shift further to the right for different values of

HLAT, as specified in Table 26, page 39.

Figure 19. Hardware Diagram for a Table with One Device

BHI[2:0]

6

5

4

3

LHI

2

1

0

DQ[67:0]

SRAM

M7020R

CMDV, CMD[8:0]

SSF, SSV

LHO[1]

LHO[0]

AI05664

37/150

M7020R

Figure 20. Timing Diagram for a 68-bit Configuration SEARCH for One Device

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search4

Search2

CMD[8:2]

DQ

A

B

A

B

D3

D1

D2

D4

SADR[23:0]

CE_L

A1

A3

0

1

0

1

ALE_L

WE_L

0

1

0

1

0

1

0

1

0

1

0

OE_L

SSV

SSF

0

1

0

1

Search1

Hit

Search3

Hit

Search4

Miss

Search2

Miss

CFG = 00000000, HLAT = 000, TLSZ = 00, LRAM = 1, LDEV = 1

AI04286

38/150

M7020R

Figure 21. x68 Table with One Device

0

67

Comparand Register (even)

GMR

K

0

67

Location

address

0

1

2

3

0

67

Comparand Register (even)

K

Comparand Register (odd)

K

L

(First matching entry)

32767

CFG = 00000000

(68-bit Configuration)

AI05665

Table 25. Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, 1 Device

# of devices

1 (TLSZ = 00)

Max Table Size

32K x 68-bit

Latency in CLK Cycles

4

5

6

2–8 (TLSZ = 01)

9–31 (TLSZ = 10)

256K x 68-bit

992K x 68-bit

Table 26. Shift of SSF and SSV from SADR

HLAT

Number of CLK Cycles

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

39/150

M7020R

68-bit SEARCH on Tables Configured as x68 Using up to Eight M7020R Devices

The hardware diagram of the search subsystem of

eight devices is shown in Figure 22, page 41. The

following are the parameters programmed into the

eight devices:

Registers (SSR[0:7]), page 23). The DQ[67:0]

continues to carry the 68-bit data to be com-

pared.

Note: For 68-bit searches, the host ASIC must

supply the same data on DQ[67:0] during both

Cycles A and B. The even and odd pair of

GMRs selected for the comparison must be pro-

grammed with the same value.

– First seven devices (device 0–6):

CFG = 00000000, TLSZ = 01, HLAT = 010,

LRAM = 0, and LDEV = 0.

– Eighth device (device 7):

The logical 68-bit SEARCH operation is shown in

Figure 23, page 42. The entire table with eight de-

vices of 68-bit entries is compared to a 68-bit word

K (presented on the DQ Bus in both Cycles A and

B of the command) using the GMR and the local

mask bits. The effective GMR is the 68-bit word

specified by the identical value in both even and

odd GMR pairs in each of the eight devices and

selected by the GMR Index in the command’s Cy-

cle A. The 68-bit word K (presented on the DQ Bus

in both Cycles A and B of the command) is also

stored in both even and odd comparand register

pairs (selected by the Comparand Register Index

in command Cycle B) in each of the eight devices.

In the x68 configuration, only the even comparand

register can subsequently be used by the LEARN

command in one of the devices (only the first non-

full device). The word K (presented on the DQ Bus

in both Cycles A and B of the command) is com-

pared with each entry in the table starting at loca-

tion “0.” The first matching entry’s location

address, “L,” is the winning address that is driven

as part of the SRAM address on the SADR[21:0]

lines (see SRAM ADDRESSING, page 126). The

global winning device will drive the bus in a specif-

ic cycle. On a global miss cycle the device with

LRAM = 1 (default driving device for the SRAM

Bus) and LDEV = 1 (default driving device for SSF

and SSV signals) will be the default driver for such

missed cycles.

The SEARCH command is a pipelined operation

and executes a search at half the rate of the fre-

quency of CLK2X for 72-bit searches in x68-con-

figured tables. The latency of SADR, CE_L,

ALE_L, WE_L, SSV, and SSF from the 68-bit

SEARCH command cycle (two CLK2X cycles) is

shown in Table 28, page 46

The latency of the search from command to SRAM

access cycle is 5 for up to eight devices in the table

(TLSZ = 01). SSV and SSF also shift further to the

right for different values of HLAT, as specified in

Table 29, page 46.

CFG = 00000000, TLSZ = 01, HLAT = 010,

LRAM = 1, and LDEV = 1.

Note: All eight devices must be programmed with

the same values for TLSZ and HLAT. Only the last

device in the table (Device 7 in this case) must be

programmed with LRAM = 1 and LDEV = 1. All

other upstream devices (Devices 0 through 6 in

this case) must be programmed with LRAM = 0

and LDEV = 0.

Figure 24, page 43 shows the timing diagram for a

SEARCH command in the 68-bit-configured table

of eight devices for Device 0. Figure 25, page 44

shows the timing diagram for a SEARCH com-

mand in the 68-bit-configured table of eight devic-

es for Device 1. Figure 26, page 45 shows the

timing diagram for a SEARCH command in the

68-bit-configured table of eight devices for Device

7 (the last device in this specific table). For these

timing diagrams four 68-bit searches are per-

formed sequentially. HIT/MISS assumptions were

made as shown below in Table 27.

The sequence of operation for a 68-bit SEARCH

command is as follows:]

– Cycle A: The host ASIC drives CMDV high and

applies the SEARCH command code ('10') on

CMD[1:0] signals. CMD[5:3] must be driven with

the index to the global mask register pair for use

in the SEARCH operation. CMD[8:7] signals

must be driven with the same bits that will be

driven on SADR[23:21] by this device if it has a

hit. DQ[67:0] must be driven with the 68-bit data

to be compared. The CMD[2] signal must be

driven to Logic '0.'

– Cycle B: The host ASIC continues to drive

CMDV high and applies the SEARCH command

('10') on CMD[1:0]. CMD[5:2] must be driven by

the index of the comparand register pair for stor-

ing the 136-bit word presented on the DQ Bus

during Cycles A and B. CMD[8:6] signals must

be driven with the index of the SSR that will be

used for storing the address of the matching en-

try and the Hit Flag (see SEARCH-Successful

40/150

M7020R

Table 27. Hit/Miss Assumption

Search Number

Device 0

1

2

3

Hit

4

Hit

Miss

Hit

Miss

Hit

Device 1

Miss

Hit

Device 2-6

Device 7

Miss

Hit

Figure 22. Hardware Diagram for a Table with Eight Devices

SRAM

BHI[2:0]

6

5

4

3

2

1

0

LHI

M7020R #0

M7020R #1

LHO[1]

LHO[0]

SSF, SSV

DQ[67:0]

6

5

4

3

LHI

2

1

0

LHO[1]

LHO[0]

CMDV

CMD[8:0]

6

5

4

3

LHI

2

1

M7020R #2

M7020R #3

M7020R #4

M7020R #5

M7020R #6

M7020R #7

LHO[1]

LHO[0]

3

2

1

LHI

LHO[1]

LHO[0]

3

LHI

2

1

0

LHO[0]

3

2

1

0

6

5

LHI

LHO[0]

4

LHI

3

2

LHI

6

5

LHI

LHO[0]

3

2

LHI

1

0

6

5

LHI

4

BHO[0]

BHO[1]

BHO[2]

BHI[2:0]

BHO[0]

BHO[1]

BHO[2]

LHO[1]

LHO[0]

AI05666

41/150

M7020R

Figure 23. x68 Table with Eight Devices

0

67

Must be the same in each

of the eight devices

GMR

K

Location

address

0

1

2

3

0

67

Comparand Register (even)

K

Comparand Register (odd)

K

L

(First matching entry)

262148

Will be the same in each

of the eight devices

CFG = 00000000

(68-bit Configuration)

AI05667

42/150

M7020R

Timing Diagrams for x68 Using up to Eight M7020R Devices

Figure 24. 68-bit SEARCH For Device 0

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 7 Cycle 9

Cycle 10

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search4

Search2

CMD[8:2]

DQ

A

B

A

B

D3

D1

D2

D4

0

(1)

(LHI[6:0])

(2)

LHO[1:0]

z

A3

SADR[21:0]

CE_L

A1

z

0

ALE_L

WE_L

OE_L

z

1

z

SSV

SSF

1

Search1

(This device

is the global

winner.)

CFG = 00000000,

HLAT = 010, TLSZ = 01,

LRAM = 0, LDEV = 0

Search2

(Miss on this

device.)

Search3

(This device

is the global

winner.)

Search4

(Miss on this

device.)

AI05668

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

43/150

M7020R

Figure 25. 68-bit SEARCH For Device 1

Cycle 2

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 7 Cycle 9

Cycle 10

Cycle 1

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search4

Search2

CMD[8:2]

DQ

A

B

A

B

D3

D1

D2

D4

(1)

(LHI[6:0])

(2)

LHO[1:0]

z

SADR[21:0]

CE_L

A2

z

0

ALE_L

z

WE_L

OE_L

1

z

1

SSV

SSF

Search1

(Miss on

this device.)

CFG = 00000000,

HLAT = 010, TLSZ = 01,

LRAM = 0, LDEV = 0

Search2

(This device

is global

winner.)

Search3

(Local winner

but not global

winner.)

Search4

(Miss on this

device.)

AI05669

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

44/150

M7020R

Figure 26. 68-bit SEARCH For Device 7 (Last Device)

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search4

Search2

CMD[8:2]

DQ

A

B

A

B

D3

D1

D2

D4

(1)

(LHI[6:0])

(2)

LHO[1:0]

z

SADR[21:0]

A2

0

CE_L

0

ALE_L

z

WE_L

OE_L

1

0

1

0

z

SSV

SSF

1

Search1

(Miss on

this device.)

CFG = 00000000,

HLAT = 010, TLSZ = 01,

LRAM = 1, LDEV = 1

Search2

(Miss on

this device.)

Search3

(Local winner

but not global

winner.)

Search4

(Global

winner.)

AI05670

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

45/150

M7020R

Table 28. Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, Up to 8 Devices

# of devices

1 (TLSZ = 00)

Max Table Size

32K x 68-bit

Latency in CLK Cycles

4

5

6

2–8 (TLSZ = 01)

9–31 (TLSZ = 10)

256K x 68-bit

992K x 68-bit

Table 29. Shift of SSF and SSV from SADR

HLAT

Number of CLK Cycles

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

68-bit SEARCH on Tables Configured as x68 Using Up To 31 M7020R Devices

The hardware diagram of the search subsystem of

31 devices is shown in Figure 27, page 48. Each

of the four blocks in the diagram represents eight

M7020R devices (except the last, which has seven

devices). The diagram for a block of eight devices

is shown in Figure 28, page 49. The following are

the parameters programmed into the 31 devices:

one device with a matching entry in each of the

blocks. Figure 30, page 51 shows the timing dia-

gram for a SEARCH command in the 68-bit-con-

figured table of 31 devices for each of the eight

devices in Block Number 0. Figure 31, page 52

shows a timing diagram for a SEARCH command

in the 68-bit-configured table of 31 devices for the

all the devices in Block Number 1 (above the win-

ning device in that block). Figure 32, page 53

shows the timing diagram for the globally winning

device (defined as the final winner within its own

and all blocks) in Block Number 1. Figure 33, page

54 shows the timing diagram for all the devices be-

low the globally winning device in Block Number 1.

Figure 34, page 55, Figure 35, page 56, and Fig-

ure 36, page 57 show the timing diagrams of the

devices above the globally winning device, the glo-

bally winning device, and the devices below the

globally winning device, respectively, for Block

Number 2. Figure 37, page 58, Figure 38, page 59,

Figure 39, page 60, and Figure 40, page 61 show

the timing diagrams of the devices above globally

winning device, the globally winning device, and

the devices below the globally winning device ex-

cept the last device (Device 30), respectively, for

Block Number 3.

– First thirty devices (devices 0–29):

CFG = 00000000, TLSZ = 10, HLAT = 001,

LRAM = 0, and LDEV = 0.

– Thirty-first device (device 30):

CFG = 00000000, TLSZ = 10, HLAT = 001,

LRAM = 1, and LDEV = 1.

Note: All 31 devices must be programmed with the

same values for TLSZ and HLAT. Only the last de-

vice in the table must be programmed with

LRAM = 1 and LDEV = 1 (Device 30 in this case).

All other upstream devices must be programmed

with LRAM = 0 and LDEV = 0 (Devices 0 through

29 in this case).

The timing diagrams referred to in this paragraph

reference the HIT/MISS assumptions defined in

Table 30, page 47. For the purpose of illustrating

the timings, it is further assumed that there is only

46/150

M7020R

The following is the sequence of operation for a

single 68-bit SEARCH command (also refer to

Command Codes, page 29).

cle B. In the x68 configuration, the even com-

parand register can be subsequently used by the

LEARN command only in the first non-full device.

The word K (presented on the DQ Bus in both Cy-

cles A and B of the command) is compared with

each entry in the table starting at location “0.” The

first matching entry’s location address, “L,” is the

winning address that is driven as part of the SRAM

address on the SADR[21:0] lines (see SRAM AD-

DRESSING, page 126). The global winning device

will drive the bus in a specific cycle. On global miss

cycles the device with LRAM = 1 and LDEV = 1 will

be the default driver for such missed cycles.

– Cycle A: The host ASIC drives the CMDV high

and applies SEARCH command code ('10') on

CMD[1:0] signals. CMD[5:3] signals must be

driven with the index to the GMR pair for use in

this SEARCH operation. CMD[8:7] signals must

be driven with the same bits that will be driven

on SADR[21:20] by this device if it has a hit.

DQ[67:0] must be driven with the 68-bit data to

be compared. The CMD[2] signal must be driv-

en to a logic '0.'

The SEARCH command is a pipelined operation

and executes a search at half the rate of the fre-

quency of CLK2X for 68-bit searches in x68-con-

figured tables. The latency of SADR, CE_L,

ALE_L, WE_L, SSV, and SSF from the 68-bit

SEARCH command cycle (two CLK2X cycles) is

shown in Table 31, page 62.

For up to 31 devices in the table (TLSZ = 10),

search latency from command to SRAM access

cycle is 6. In addition, SSV and SSF shift further to

the right for different values of HLAT, as specified

in Table 32, page 62.

– Cycle B: The host ASIC continues to drive the

CMDV high and applies SEARCH command

('10') on CMD[1:0]. CMD[5:2] must be driven by

the index of the comparand register pair for stor-

ing the 136-bit word presented on the DQ Bus

during Cycles A and B. CMD[8:6] signals must

be driven with the index of the SSR that will be

used for storing the address of the matching en-

try and the Hit Flag (see SEARCH-Successful

Registers (SSR[0:7]), page 23). The DQ[67:0]

continues to carry the 68-bit data to be com-

pared.

Note: For 68-bit searches, the host ASIC must

supply the same 68-bit data on DQ[67:0] during

both Cycles A and B. The even and odd pair of

GMRs selected for the comparison must be pro-

grammed with the same value.

The 68-bit SEARCH operation is pipelined and ex-

ecutes as follows:

– Four cycles from the SEARCH command, each

of the devices knows the outcome internal to it

for that operation;

The logical 68-bit SEARCH operation is shown in

Figure 29, page 50. The entire table (31 devices of

68-bit entries) is compared to a 68-bit word K (pre-

sented on the DQ Bus in both Cycles A and B of

the command) using the GMR and the local mask

bits. The effective GMR is the 68-bit word speci-

fied by the identical value in both even and odd

GMR pairs in each of the eight devices and select-

ed by the GMR Index in the command’s Cycle A.

The 68-bit word K (presented on the DQ Bus in

both Cycles A and B of the command) is also

stored in both even and odd comparand register

pairs in each of the eight devices and selected by

the Comparand Register Index in command’s Cy-

– In the fifth cycle after the SEARCH command,

the devices in a block arbitrate for a winner

amongst them (a “block” being defined as less

than or equal to eight devices resolving the win-

ner within them using the LHI[6:0] and LHO[1:0]

signalling mechanism);

– In the sixth cycle after the SEARCH command,

the blocks (of devices) resolve the winning block

through the BHI[2:0] and BHO[2:0] signalling

mechanism. The winning device within the win-

ning block is the global winning device for a

SEARCH operation.

Table 30. Hit/Miss Assumption

Search Number

Block 0

1

2

3

4

Miss

Hit

Miss

Hit

Miss

Hit

Miss

Block 1

Block 2

Hit

Block 3

Hit

Miss

47/150

M7020R

Figure 27. Hardware Diagram for a Table with 31 Devices

BHI[2]

BHI[1]

BHI[0]

GND

SRAM

SSF, SSV

Block of 8 M7020Rs, Block 0 (Devices 0-7)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

Block of 8 M7020Rs, Block 1 (Devices 8-15)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

Block of 8 M7020Rs, Block 2 (Devices 16-23)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

DQ[67:0]

Block of 7 M7020Rs, Block 3 (Devices 24-30)

BHO[2]

CMD[8:0], CMDV

BHO[1]

BHO[0]

AI05671

48/150

M7020R

Figure 28. Hardware Diagram for a Block of Up To Eight Devices

SRAM

BHI[2:0]

6

5

4

3

2

1

0

LHI

M7020R #0

M7020R #1

LHO[1]

LHO[0]

6

5

4

3

LHI

2

1

0

LHO[1]

LHO[0]

DQ[67:0]

CMDV

CMD[8:0]

6

5

4

3

LHI

2

1

M7020R #2

M7020R #3

M7020R #4

M7020R #5

SSV, SSF

LHO[1]

LHO[0]

3

2

LHI

LHO[0]

LHO[1]

BHI[2:0]

5

4

3

LHI

2

1

0

LHO[0]

3

2

1

0

6

5

4

LHI

LHO[0]

LHI

2

LHI

6

5

LHI

M7020R #6_LHO[0]

3

2

LHI

1

0

6

5

LHI

4

BHO[0]

BHO[1]

BHO[2]

BHI[2:0]

M7020R #7

BHO[0]

BHO[1]

BHO[2]

LHO[1] LHO[0]

AI05672

49/150

M7020R

Figure 29. x68 Table with 31 Devices

0

67

Must be the same for

each of the 31 devices

GMR

K

Location

address

0

1

2

3

0

67

Comparand Register (even)

K

Comparand Register (odd)

K

L

(First matching entry)

1015807

Will be the same in each

of the 31 devices

CFG = 00000000

(68-bit Configuration)

AI05673

50/150

M7020R

Timing Diagrams for x68 Using Up To 31 M7020R Devices

Figure 30. Each Device in Block Number 0 (Miss on Each Device)

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search4

Search2

CMD[8:2]

DQ

A

B

A

B

D3

D1

D2

D4

0

(1)

(LHI[6:0])

0

(2)

LHO[1:0]

(3)

(BHI[2:0])

(4)

BHO[2:0]

z

SADR[21:0]

CE_L

z

ALE_L

WE_L

OE_L

SSV

z

SSF

Search1

(Miss on this

device.)

CFG = 00000000,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on this

device.)

Search3

(Miss on this

device.)

Search4

(Miss on this

device.)

AI05674

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

51/150

M7020R

Figure 31. Each Device Above the Winning Device in Block Number 1

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search4

Search2

CMD[8:2]

DQ

A

B

A

B

D3

D1

D2

D4

0

(1)

(LHI[6:0])

0

(2)

LHO[1:0]

(3)

(BHI[2:0])

(4)

BHO[2:0]

z

SADR[21:0]

CE_L

z

ALE_L

WE_L

OE_L

SSV

z

SSF

Search1

(Miss on this

device.)

CFG = 00000000,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on this

device.)

Search3

(Miss on this

device.)

Search4

(Miss on this

device.)

AI05674

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

52/150

M7020R

Figure 32. Globally Winning Device in Block Number 1

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

CMD[1:0]

CMD[8:2]

Search1

01

Search3

01

Search2

Search4

A

B A

B

A

B

A

B

D3

D1

D2

D4

DQ

(1)

0

(LHI[6:0])

(2)

(3)

LHO[1:0]

(BHI[2:0])

0

(4)

BHO[2:0]

0

z

SADR[21:0]

CE_L

A3

z

ALE_L

z

WE_L

OE_L

z

SSV

SSF

Search1

(Miss on

this device.)

CFG = 00000000,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on

this device.)

Search3

(This device

global winner.)

Search4

(Miss on this

device.)

AI05675

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

53/150

M7020R

Figure 33. Devices Below the Winning Device in Block Number 1

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B A

B

A

B

A

B

D3

D1

D2

D4

(1)

(LHI[6:0])

0

(2)

LHO[1:0]

(3)

(BHI[2:0])

(4)

0

z

BHO[2:0]

SADR[21:0]

CE_L

z

ALE_L

WE_L

OE_L

z

SSV

SSF

Search1

(Miss on

this device.)

CFG = 00000000,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on

this device.)

Search3

(Miss on

Search4

this device.)

(Miss on this

device.)

AI05676

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

54/150

M7020R

Figure 34. Devices Above the Winning Device in Block Number 2

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B A

B

A

B

A

B

D3

D1

D2

D4

(1)

0

(LHI[6:0])

(2)

LHO[1:0]

(3)

0

(BHI[2:0])

(4)

0

z

BHO[2:0]

SADR[21:0]

CE_L

z

ALE_L

WE_L

OE_L

z

SSV

SSF

Search1

(Miss on

this device.)

CFG = 00000000,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on

this device.)

Search3

(Miss on

Search4

this device.)

(Miss on this

device.)

AI05677

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

55/150

M7020R

Figure 35. Globally Winning Device in Block Number 2

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7 Cycle 9

CLK2X

PHS_L

CMDV

CMD[1:0]

CMD[8:2]

Search1

01

Search3

01

Search2

Search4

A

B A

B

A

B

A

B

D3

D1

D2

D4

DQ

(1)

0

(LHI[6:0])

(2)

LHO[1:0]

(3)

(BHI[2:0])

BHO[2:0]

(4)

0

z

SADR[21:0]

CE_L

A2

z

0

ALE_L

WE_L

OE_L

z

1

SSV

SSF

z

1

Search1

(Miss on

this device.)

CFG = 00000000,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Global

winner.)

Search3

(Hit but not

a winner.)

Search4

(Miss on this

device.)

AI05678

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

56/150

M7020R

Figure 36. Devices Below the Winning Device in Block Number 2

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B A

B

A

B

A

B

D3

D1

D2

D4

(1)

(LHI[6:0])

0

(2)

LHO[1:0]

(3)

(BHI[2:0])

0

(4)

BHO[2:0]

0

z

SADR[21:0]

CE_L

ALE_L

WE_L

OE_L

SSV

z

SSF

Search1

(Miss on

this device.)

CFG = 00000000,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on

this device.)

Search3

(Miss on

Search4

this device.)

(Miss on this

device.)

AI05679

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

57/150

M7020R

Figure 37. Devices Above the Winning Device in Block Number 3

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B A

B

A

B

A

B

D3

D1

D2

D4

(1)

0

(LHI[6:0])

(2)

LHO[1:0]

(3)

0

(BHI[2:0])

(4)

0

z

BHO[2:0]

SADR[21:0]

CE_L

z

ALE_L

WE_L

OE_L

z

SSV

SSF

Search1

(Miss on

this device.)

CFG = 00000000,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on

this device.)

Search3

(Miss on

Search4

this device.)

(Miss on this

device.)

AI05680

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

58/150

M7020R

Figure 38. Globally Winning Device in Block Number 3

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7 Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B A

B

A

B

A

B

D3

D1

D2

D4

(1)

0

(LHI[6:0])

(2)

LHO[1:0]

(3)

(BHI[2:0])

(4)

BHO[2:0]

0

z

SADR[21:0]

CE_L

A1

z

0

ALE_L

WE_L

OE_L

z

1

SSV

SSF

z

1

Search1

(Global

winner.)

CFG = 00000000,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Hit but

not a global

winner.)

Search3

(Miss on this

device.)

Search4

(Miss on this

device.)

AI05681

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

59/150

M7020R

Figure 39. Devices Below the Winning Device in Block Number 3 (not Device 30 - Last Device)

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B A

B

A

B

A

B

D3

D1

D2

D4

(1)

(LHI[6:0])

0

(2)

LHO[1:0]

(3)

(BHI[2:0])

0

(4)

BHO[2:0]

0

z

SADR[21:0]

CE_L

ALE_L

WE_L

OE_L

SSV

z

SSF

Search1

(Miss on

this device.)

CFG = 00000000,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on

this device.)

Search3

(Miss on

Search4

this device.)

(Miss on this

device.)

AI05682

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

60/150

M7020R

Figure 40. Device 6 in Block Number 3 (Device 30 in Depth-Cascaded Table)

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B A

B

A

B

A

B

D3

D1

D2

D4

(1)

(LHI[6:0])

0

(2)

LHO[1:0]

(3)

0

(BHI[2:0])

(4)

BHO[2:0]

z

SADR[21:0]

CE_L

z

0

ALE_L

WE_L

z

1

0

OE_L

SSV

0

z

1

0

SSF

Search1

(Hit on

CFG = 00000000,

Search2

(Hit on

some device

above.)

some device

above.)

HLAT = 001, TLSZ = 10,

LRAM = 1, LDEV = 1

Search3

(Hit on

Search4

(Global miss;

this device

some device

above.)

default driver.)

AI05683

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

61/150

M7020R

Table 31. Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, Up to 31 Devices

# of devices

1 (TLSZ = 00)

Max Table Size

32K x 68-bit

Latency in CLK Cycles

4

5

6

2–8 (TLSZ = 01)

9–31 (TLSZ = 10)

256K x 68-bit

992K x 68-bit

Table 32. Shift of SSF and SSV from SADR

HLAT

Number of CLK Cycles

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

136-bit Configuration with Single Device

The hardware diagram for this search subsystem

is shown in Figure 41.

tions. The CMD[2] signal must be driven to logic

'0.'

Figure 42, page 64 shows the timing diagram for a

SEARCH command in the 136-bit-configured ta-

ble (CFG = 01010101) consisting of a single de-

vice for one set of parameters. This illustration

assumes that the host ASIC has programmed

TLSZ to ’00,’ HLAT to ’001,’ LRAM to ’1,’ and LDEV

to ’1.’

The following is the operation sequence for a sin-

gle 136-bit SEARCH command (refer to COM-

MAND CODES AND PARAMETERS, page 29).

– Cycle B: The host ASIC continues to drive the

CMDV high and applies the command code of

SEARCH command ('10') on CMD[1:0].

CMD[5:2] must be driven by the index of the

comparand register pair for storing the 136-bit

word presented on the DQ Bus during Cycles A

and B. CMD[8:6] signals must be driven with the

index of the SSR that will be used for storing the

address of the matching entry and Hit Flag (see

SEARCH-Successful Registers (SSR[0:7]),

page 23). The DQ[67:0] is driven with 68-bit

data ([67:0]), compared to all odd locations.

– Cycle A: The host ASIC drives the CMDV high

and applies SEARCH command code ('10') to

CMD[1:0] signals. CMD[5:3] signals must be

driven with the index to the GMR pair for use in

this SEARCH operation. CMD[8:7] signals must

be driven with the same bits that will be driven

on SADR[21:20] by this device if it has a hit.

DQ[67:0] must be driven with the 68-bit data

([135:68]) to be compared against all even loca-

Note: For 136-bit searches, the host ASIC must

supply two distinct 68-bit data words on

DQ[67:0] during Cycles A and B. The even-

numbered GMR of the pair specified by the

GMR Index is used for masking the word in Cy-

cle A. The odd-numbered GMR of the pair spec-

ified by the GMR Index is used for masking the

word in Cycle B.

62/150

M7020R

The logical 136-bit search operation is shown in

Figure 43, page 65. The entire table of 136-bit en-

tries is compared to a 136-bit word K (presented

on the DQ Bus in Cycles A and B of the command)

using the GMR and the local mask bits. The GMR

is the 136-bit word specified by the even and odd

global mask pair selected by the GMR Index in the

command’s Cycle A. The 136-bit word K (present-

ed on the DQ Bus in Cycles A and B of the com-

mand) is also stored in both even and odd

comparand register pairs selected by the Com-

parand Register Index in the command’s Cycle B.

The two comparand registers can subsequently

be used by the LEARN command with the even

comparand register stored in an even location,

and the odd comparand register stored in an adja-

cent odd location. The word K (presented on the

DQ Bus in Cycles A and B of the command) is

compared with each entry in the table starting at

location “0.” The first matching entry’s location ad-

dress, “L,” is the winning address that is driven as

part of the SRAM address on the SADR[21:0] lines

(see SRAM ADDRESSING, page 126).

Note: The matching address is always going to an

even address for a 136-bit SEARCH.

The SEARCH command is a pipelined operation

that executes searches at half the rate of the fre-

quency of CLK2X for 136-bit searches in x136-

configured tables. The latency of SADR, CE_L,

ALE_L, WE_L, SSV, and SSF from the 136-bit

SEARCH command cycle (two CLK2X cycles) is

shown in Table 33, page 65.

For a single device in the table with TLSZ = 00, the

latency of the SEARCH from command to SRAM

access cycle is 4. In addition, SSV and SSF shift

further to the right for different values of HLAT, as

specified in Table 34, page 65.

Figure 41. Hardware Diagram for a Table with 1 Device

BHI[2:0]

6

5

4

3

LHI

2

1

0

DQ[67:0]

SRAM

M7020R

CMDV, CMD[8:0]

SSF, SSV

BHO[2:0]

LHO[1]

LHO[0]

AI06329

63/150

M7020R

Figure 42. Timing Diagram for a 136-bit SEARCH for One Device

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search4

Search2

CMD[8:2]

DQ

A

B

A

B

A

B

A

D2

D3

D1

D4

SADR[21:0]

CE_L

A1

A3

0

1

0

1

ALE_L

WE_L

0

1

0

1

0

1

0

1

0

1

0

OE_L

SSV

SSF

0

1

0

1

Search1

Hit

Search3

Hit

Search4

Miss

Search2

Miss

CFG = 01010101, HLAT = 001, TLSZ = 00, LRAM = 1, LDEV = 1

AI06330

64/150

M7020R

Figure 43. x136 Table with One Device

0

135

GMR

K

Even

A

Odd

B

Location

address

0

2

4

6

0

67

Comparand Register (even)

A

Comparand Register (odd)

B

L

(First matching entry)

32766

CFG = 01010101

(136-bit Configuration)

AI06331

Table 33. Latency of SEARCH from Instruction to SRAM Access Cycle, 136-bit, 1 Device

# of devices

1 (TLSZ = 00)

Max Table Size

16K x 136-bit

128K x 136-bit

496K x 136-bit

Latency in CLK Cycles

4

5

6

2–8 (TLSZ = 01)

9–31 (TLSZ = 10)

Table 34. Shift of SSF and SSV from SADR

HLAT

000

Number of CLK Cycles

0

1

2

3

4

5

6

7

001

010

011

100

101

110

111

65/150

M7020R

136-bit Search on Tables Configured as x136 Using Up to Eight M7020R Devices

The hardware diagram of the search subsystem of

eight devices is shown in Figure 44, page 67. The

following are parameters programmed into the

eight devices:

and B. CMD[8:6] signals must be driven with the

SSR Index that will be used for storing the

address of the matching entry and the Hit

Flag (see

SEARCH-Successful

Registers

(SSR[0:7]), page 23). The DQ[67:0] is driven

with 68-bit data ([67:0]) compared against all

odd locations.

– First seven devices (devices 0–6):

CFG = 01010101, TLSZ = 01, HLAT = 010,

LRAM = 0, and LDEV = 0.

The logical 136-bit search operation is shown in

Figure 45, page 68. The entire table (eight devices

of 136-bit entries) is compared to a 136-bit word K

(presented on the DQ Bus in Cycles A and B of the

command) using the GMR and local mask bits.

The GMR is the 136-bit word specified by the even

and odd global mask pair selected by the GMR In-

dex in the command’s Cycle A.

– Eighth device (device 7):

CFG = 01010101, TLSZ = 01, HLAT = 010,

LRAM = 1, and LDEV = 1.

Note: All eight devices must be programmed with

the same value of TLSZ and HLAT. Only the last

device in the table must be programmed with

LRAM = 1 and LDEV = 1 (Device 7 in this case).

All other upstream devices must be programmed

with LRAM = 0 and LDEV = 0 (Devices 0 through

6 in this case).

The 136-bit word K (presented on the DQ Bus in

Cycles A and B of the command) is also stored in

the even and odd comparand registers specified

by the Comparand Register Index in the com-

mand’s Cycle B. In x136 configurations, the even

and odd comparand registers can subsequently

be used by the LEARN command in only one of

the devices (the first non-full device). The word K

(presented on the DQ Bus in Cycles A and B of the

command) is compared to each entry in the table

starting at location “0.” The first matching entry’s

location, “L,” is the winning address that is driven

as part of the SRAM address on the SADR[21:0]

lines (see SRAM ADDRESSING, page 126). The

global winning device will drive the bus in a specif-

ic cycle. On global miss cycles the device with

LRAM = 1 (the default driving device for the SRAM

Bus) and LDEV = 1 (the default driving device for

SSF and SSV signals) will be the default driver for

such missed cycles.

Figure 46, page 69 shows the timing diagram for a

SEARCH command in the 136-bit-configured ta-

ble of eight devices for Device 0. Figure 47, page

70 shows the timing diagram for a SEARCH com-

mand in the 136-bit-configured table consisting of

eight devices for Device 1. Figure 48, page 71

shows the timing diagram for a SEARCH com-

mand in the 136-bit configured table consisting of

eight devices for Device 7 (the last device in this

specific table). For these timing diagrams, four

136-bit searches are performed sequentially, and

the following HIT/MISS assumptions were made

(see Table 35)

The following is the sequence of operation for a

single 136-bit SEARCH command (see COM-

MAND CODES AND PARAMETERS, page 29).

– Cycle A: The host ASIC drives CMDV high and

applies SEARCH command code ('10') on

CMD[1:0] signals. CMD[5:3] signals must be

driven with the index to the GMR pair for use in

this SEARCH operation. CMD[8:7] signals must

be driven with the same bits that will be driven

by this device on SADR[21:20] if it has a hit.

DQ[67:0] must be driven with the 68-bit data

([135:68]) in order to be compared against all

even locations. The CMD[2] signal must be driv-

en to a logic '0.'

– Cycle B: The host ASIC continues to drive

CMDV high and to apply the command code for

SEARCH command ('10') on CMD[1:0].

CMD[5:2] must be driven by the index of the

comparand register pair for storing the 136-bit

word presented on the DQ Bus during Cycles A

Note: During 136-bit searches of 136-bit-config-

ured tables, the search hit will always be at an

even address.

The SEARCH command is a pipelined operation

and executes a search at half the rate of the fre-

quency of CLK2X for 136-bit searches in x136-

configured tables. The latency of SADR, CE_L,

ALE_L, WE_L, SSV, and SSF from the 136-bit

SEARCH command cycle (two CLK2X cycles) is

shown in Table 36, page 72.

For one to eight devices in the table and

TLSZ = 01, the latency of a SEARCH from com-

mand to SRAM access cycle is 5. In addition, SSV

and SSF shift further to the right for different val-

ues of HLAT as specified in Table 37, page 72.

66/150

M7020R

Table 35. Hit/Miss Assumption

Search Number

Device 0

1

2

3

Hit

4

Hit

Miss

Hit

Miss

Hit

Device 1

Miss

Hit

Device 2-6

Device 7

Miss

Hit

Figure 44. Hardware Diagram for a Table with Eight Devices

SRAM

BHI[2:0]

6

5

4

3

2

1

0

LHI

M7020R #0

M7020R #1

LHO[1]

LHO[0]

SSF, SSV

DQ[67:0]

6

5

4

3

LHI

2

1

0

LHO[1]

LHO[0]

CMDV

CMD[8:0]

6

5

4

3

LHI

2

1

M7020R #2

M7020R #3

M7020R #4

M7020R #5

M7020R #6

M7020R #7

LHO[1]

LHO[0]

3

2

1

LHI

LHO[1]

LHO[0]

3

LHI

2

1

0

LHO[0]

3

2

1

0

6

5

LHI

LHO[0]

4

LHI

3

2

LHI

6

5

LHI

LHO[0]

3

2

LHI

1

0

6

5

LHI

4

BHO[0]

BHO[1]

BHO[2]

BHI[2:0]

BHO[0]

BHO[1]

BHO[2]

LHO[1]

LHO[0]

AI05666

67/150

M7020R

Figure 45. x136 Table with Eight Devices

0

135

Must be the same in each

of the eight devices

GMR

K

Even

A

Odd

B

Location

address

0

2

4

6

0

67

Comparand Register (even)

A

Comparand Register (odd)

B

L

(First matching entry)

262142

CFG = 01010101

(136-bit Configuration)

Will be the same in each

of the eight devices

AI06332

68/150

M7020R

Timing Diagrams for x136 Using Up to Eight M7020R Devices

Figure 46. 136-bit SEARCH for Device Number 0

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 7 Cycle 9

Cycle 10

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search4

Search2

CMD[8:2]

DQ

A

B

A

B

A

B

A

D4

D1

D2

D3

0

(1)

(LHI[6:0])

(2)

LHO[1:0]

z

SADR[21:0]

CE_L

A1

A3

z

0

ALE_L

WE_L

OE_L

z

1

z

SSV

SSF

1

Search1

(This device

is the global

winner.)

CFG = 01010101,

HLAT = 010, TLSZ = 01,

LRAM = 0, LDEV = 0

Search2

(Miss on this

device.)

Search3

(This device

is the global

winner.)

Search4

(Miss on this

device.)

AI06333

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

69/150

M7020R

Figure 47. 136-bit SEARCH for Device Number 1

Cycle 2

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 7 Cycle 9

Cycle 10

Cycle 1

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search4

Search2

CMD[8:2]

DQ

A

B

A

B

A

B

A

D3

D1

D2

D4

(1)

(LHI[6:0])

(2)

LHO[1:0]

z

SADR[21:0]

CE_L

A2

z

0

ALE_L

z

WE_L

OE_L

1

z

1

SSV

SSF

Search1

(Miss on

this device.)

CFG = 01010101,

HLAT = 010, TLSZ = 01,

LRAM = 0, LDEV = 0

Search2

(This device

is global

winner.)

Search3

(Local winner

but not global

winner.)

Search4

(Miss on this

device.)

AI06334

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

70/150

M7020R

Figure 48. 136-bit SEARCH for Device Number 7 (Last Device)

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search4

Search2

CMD[8:2]

DQ

A

B

A

B

A

B

A

D1

D2

D3

D4

(1)

(LHI[6:0])

(2)

LHO[1:0]

z

SADR[21:0]

A4

0

CE_L

0

ALE_L

z

WE_L

OE_L

1

0

1

0

z

SSV

SSF

1

Search1

(Miss on

this device.)

CFG = 01010101,

HLAT = 010, TLSZ = 01,

LRAM = 1, LDEV = 1

Search2

(Miss on

this device.)

Search3

(Local winner

but not global

winner.)

Search4

(Global

winner.)

AI06335

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

71/150

M7020R

Table 36. Latency of SEARCH from Instruction to SRAM Access Cycle, 136-bit, Up to 8 Devices

# of devices

1 (TLSZ = 00)

Max Table Size

16K x 136-bit

128K x 136-bit

496K x 136-bit

Latency in CLK Cycles

4

5

6

2–8 (TLSZ = 01)

9–31 (TLSZ = 10)

Table 37. Shift of SSF and SSV from SADR

HLAT

Number of CLK Cycles

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

136-bit Search on Tables Configured as x136 Using Up to 31 M7020R Devices

The hardware diagram of the search subsystem of

31 devices is shown in Figure 49, page 74. Each

of the four blocks in the diagram represents a

block of eight M7020R devices (except the last,

which has seven devices).The diagram for a block

of eight devices is shown in Figure 50, page 75.

Following are the parameters programmed into

the 31 devices.

First thirty devices (devices 0–29):

CFG = 01010101, TLSZ = 10, HLAT = 001,

LRAM = 0, and LDEV = 0.

Thirty-first device (device 30):

CFG = 01010101, TLSZ = 10, HLAT = 001,

one device with a matching entry in each of the

blocks. Figure 52, page 77 shows the timing dia-

gram for a SEARCH command in the 136-bit-con-

figured table (31 devices) for each of the eight

devices in Block 0. Figure 53, page 78 shows the

timing diagram for SEARCH command in the

68-bit-configured table (31 devices) for all the de-

vices in Block 1 above the winning device in that

block. Figure 54, page 79 shows the timing dia-

gram for the globally winning device (the final win-

ner within its own block and all blocks) in Block 1.

Figure 55, page 80 shows the timing diagram for

all the devices below the globally winning device in

Block 1. Figure 56, page 81, Figure 57, page 82,

and Figure 58, page 83 respectively show the tim-

ing diagrams of the devices above globally win-

ning device, the globally winning device and

devices below the globally winning device for

Block 2. Figure 59, page 84, Figure 60, page 85,

Figure 61, page 86, and Figure 62, page 87 re-

spectively show the timing diagrams of the devices

above the globally winning device, the globally

winning device, and devices below the globally

winning device except the last device (Device 30),

and the last device (Device 30) for Block 3.

LRAM = 1, and LDEV = 1.

Note: All 31 devices must be programmed with the

same value of TLSZ and HLAT. Only the last de-

vice in the table must be programmed with

LRAM = 1 and LDEV = 1 (Device 30 in this case).

All other upstream devices must be programmed

with LRAM = 0 and LDEV = 0 (Devices 0 through

29 in this case).

The timing diagrams referred to in this paragraph

reference the HIT/MISS assumptions defined in

Table 38, page 73. For the purpose of illustrating

timings, it is further assumed that the there is only

72/150

M7020R

The following is the sequence of operation for a

single 136-bit SEARCH command (see COM-

MAND CODES AND PARAMETERS, page 29).

The word K that is presented on the DQ Bus in Cy-

cles A and B of the command is compared with

each entry in the table starting at location “0.” The

first matching entry’s location address, “L,” is the

winning address that is driven as part of the SRAM

address on the SADR[21:0] lines (see SRAM AD-

DRESSING, page 126). The global winning device

will drive the bus in a specific cycle. On global miss

cycles the device with LRAM = 1 (the default driv-

ing device for the SRAM bus) and LDEV = 1 (the

default driving device for SSF and SSV signals)

will be the default driver for such missed cycles.

Note: During 136-bit searches of 136-bit-config-

ured tables, the search hit will always be at an

even address.

The SEARCH command is a pipelined operation.

It executes a search at half the rate of the frequen-

cy of CLK2X for 136-bit searches in x136-config-

ured tables. The latency of SADR, CE_L, ALE_L,

WE_L, SSV, and SSF from the 136-bit SEARCH

command cycle (two CLK2X cycles) is shown in

Table 39, page 88.

The latency of a search from command to the

SRAM access cycle is 6 for 1–31 devices in the ta-

ble and where TLSZ = 10. In addition, SSV and

SSF shift further to the right for different values of

HLAT, as specified in Table 40, page 88.

The 136-bit SEARCH operation is pipelined and

executes as follows:

– Four cycles from the SEARCH command, each

of the devices knows the outcome internal to it

for that operation.

– In the fifth cycle after the SEARCH command,

the devices in a block (being less than or equal

to eight devices resolving the winner within

them using the LHI[6:0] and LHO[1:0] signalling

mechanism) arbitrate for a winner amongst

them.

– Cycle A: The host ASIC drives the CMDV high

and applies SEARCH command code ('10') on

CMD[1:0] signals. CMD[5:3] signals must be

driven with the index to the GMR pair for use in

this SEARCH operation. CMD[8:7] signals must

be driven with the bits that will be driven on

SADR[21:20] by this device if it has a hit.

DQ[67:0] must be driven with the 68-bit data

([135:68]) in order to be compared against all

even locations. The CMD[2] signal must be driv-

en to logic '0.'

– Cycle B: The host ASIC continues to drive the

CMDV high and to apply SEARCH command

code ('10') on CMD[1:0]. CMD[5:2] must be driv-

en by the index of the comparand register pair

for storing the 136-bit word presented on the DQ

Bus during Cycles A and B. CMD[8:6] signals

must be driven with the index of the SSR that

will be used for storing the address of the

matching entry and the Hit Flag (see SEARCH-

Successful Registers (SSR[0:7]), page 23). The

DQ[67:0] is driven with 68-bit data ([67:0]) to be

compared against all odd locations.

The logical 136-bit SEARCH operation is as

shown in Figure 51, page 76. The entire table of 31

devices (consisting of 136-bit entries) is compared

against a 136-bit word K that is presented on the

DQ Bus in Cycles A and B of the command using

the GMR and local mask bits. The GMR is the 136-

bit word specified by the even and odd global

mask pair selected by the GMR Index in the com-

mand’s Cycle A.

The 136-bit word K that is presented on the DQ

Bus in Cycles A and B of the command is also

stored in the even and odd comparand registers

specified by the Comparand Register Index in the

command’s Cycle B. In x136 configurations, the

even and odd comparand registers can subse-

quently be used by the LEARN command in only

the first non-full device.

– In the sixth cycle after the SEARCH command,

the blocks (of devices) resolve the winning block

through the BHI[2:0] and BHO[2:0] signalling

mechanism. The winning device in the winning

block is the global winning device for a

SEARCH operation.

Note: The LEARN command is supported for only

one of the blocks consisting of up to eight devices

in a depth-cascaded table of more than one block.

Table 38. Hit/Miss Assumption

Search Number

Block 0

1

2

3

4

Miss

Hit

Miss

Hit

Miss

Hit

Miss

Block 1

Block 2

Hit

Block 3

Hit

Miss

73/150

M7020R

Figure 49. Hardware Diagram for a Table with 31 Devices

BHI[2]

BHI[1]

BHI[0]

GND

SRAM

SSF, SSV

Block of 8 M7020Rs, Block 0 (Devices 0-7)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

Block of 8 M7020Rs, Block 1 (Devices 8-15)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

Block of 8 M7020Rs, Block 2 (Devices 16-23)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

DQ[67:0]

Block of 7 M7020Rs, Block 3 (Devices 24-30)

BHO[2]

CMD[8:0], CMDV

BHO[1]

BHO[0]

AI05671

74/150

M7020R

Figure 50. Hardware Diagram for a Block of Up to Eight Devices

SRAM

BHI[2:0]

6

5

4

3

2

1

0

LHI

M7020R #0

M7020R #1

LHO[1]

LHO[0]

6

5

4

3

LHI

2

1

0

LHO[1]

LHO[0]

DQ[67:0]

CMDV

CMD[8:0]

6

5

4

3

LHI

2

1

M7020R #2

M7020R #3

M7020R #4

M7020R #5

SSV, SSF

LHO[1]

LHO[0]

3

2

LHI

LHO[0]

LHO[1]

BHI[2:0]

5

4

3

LHI

2

1

0

LHO[0]

3

2

1

0

6

5

4

LHI

LHO[0]

LHI

2

LHI

6

5

LHI

M7020R #6_LHO[0]

3

2

LHI

1

0

6

5

LHI

4

BHO[0]

BHO[1]

BHO[2]

BHI[2:0]

M7020R #7

BHO[0]

BHO[1]

BHO[2]

LHO[1] LHO[0]

AI05672

75/150

M7020R

Figure 51. x136 Table with 31 Devices

0

135

Must be the same in each

of the 31 devices

GMR

K

Even

A

Odd

B

Location

address

0

2

4

6

0

67

Comparand Register (even)

A

Comparand Register (odd)

B

L

(First matching entry)

1015806

CFG = 01010101

(136-bit Configuration)

Will be the same in each

of the 31 devices

AI05684

76/150

M7020R

Timing Diagrams for x136 Using Up to 31 M7020R Devices

Figure 52. Each Device in Block Number 0 (Miss on Each Device)

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search4

Search2

CMD[8:2]

DQ

A

B

A

B

A

B

A

D2

D3

D4

D1

0

(1)

(LHI[6:0])

0

(2)

LHO[1:0]

(3)

(BHI[2:0])

(4)

BHO[2:0]

z

SADR[21:0]

CE_L

z

ALE_L

WE_L

OE_L

SSV

z

SSF

Search1

(Miss on this

device.)

CFG = 01010101,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on this

device.)

Search3

(Miss on this

device.)

Search4

(Miss on this

device.)

AI05685

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

77/150

M7020R

Figure 53. Each Device Above the Winning Device in Block Number 1

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search4

Search2

CMD[8:2]

DQ

A

B

A

B

A

B

A

D2

D3

D4

D1

0

(1)

(LHI[6:0])

0

(2)

LHO[1:0]

(3)

(BHI[2:0])

(4)

BHO[2:0]

z

SADR[21:0]

CE_L

z

ALE_L

WE_L

OE_L

SSV

z

SSF

Search1

(Miss on this

device.)

CFG = 01010101,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on this

device.)

Search3

(Miss on this

device.)

Search4

(Miss on this

device.)

AI05685

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

78/150

M7020R

Figure 54. Globally Winning Device in Block Number 1

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B

A

B

A

B

A

B

A

B

A

D3

D1

D2

D4

(1)

0

(LHI[6:0])

(2)

LHO[1:0]

0

(3)

(BHI[2:0])

(4)

BHO[2:0]

0

z

SADR[21:0]

CE_L

A3

z

0

ALE_L

z

WE_L

OE_L

1

z

1

SSV

SSF

Search1

(Miss on

this device.)

CFG = 01010101,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on

this device.)

Search3

(This device

global winner.)

Search4

(Miss on this

device.)

AI05686

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

79/150

M7020R

Figure 55. Devices Below the Winning Device in Block Number 1

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B

A

B

A

B

A

B

A

B

A

B

A

D1

D2

D3

D4

(1)

(LHI[6:0])

0

(2)

LHO[1:0]

(3)

(BHI[2:0])

(4)

0

z

BHO[2:0]

SADR[21:0]

CE_L

z

ALE_L

WE_L

OE_L

z

SSV

SSF

Search1

(Miss on

this device.)

CFG = 01010101,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on

this device.)

Search3

(Miss on

Search4

this device.)

(Miss on this

device.)

AI05687

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

80/150

M7020R

Figure 56. Devices Above the Winning Device in Block Number 2

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B

A

B

A

B

A

B

A

B

A

D3

D1

D2

D4

(1)

0

(LHI[6:0])

(2)

LHO[1:0]

(3)

0

(BHI[2:0])

(4)

0

z

BHO[2:0]

SADR[21:0]

CE_L

z

ALE_L

WE_L

OE_L

z

SSV

SSF

Search1

(Miss on

this device.)

CFG = 01010101,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on

this device.)

Search3

(Miss on

Search4

this device.)

(Miss on this

device.)

AI05688

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

81/150

M7020R

Figure 57. Globally Winning Device in Block Number 2

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7 Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B

A

B

A

B

A

B

A

B

A

D1

D4

D2

D3

(1)

0

(LHI[6:0])

(2)

LHO[1:0]

(3)

(BHI[2:0])

(4)

BHO[2:0]

0

z

SADR[21:0]

CE_L

A2

z

0

ALE_L

WE_L

OE_L

z

1

SSV

SSF

z

1

Search1

(Miss on

this device.)

CFG = 01010101,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Global

winner.)

Search3

(Hit but not

a winner.)

Search4

(Miss on this

device.)

AI05689

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

82/150

M7020R

Figure 58. Devices Below the Winning Device in Block Number 2

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B

A

B

A

B

A

B

A

B

A

D3

D1

D2

D4

(1)

(LHI[6:0])

0

(2)

LHO[1:0]

(3)

(BHI[2:0])

0

(4)

BHO[2:0]

0

z

SADR[21:0]

CE_L

ALE_L

WE_L

OE_L

SSV

z

SSF

Search1

(Miss on

this device.)

CFG = 01010101,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on

this device.)

Search3

(Miss on

Search4

this device.)

(Miss on this

device.)

AI05690

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

83/150

M7020R

Figure 59. Devices Above the Winning Device in Block Number 3

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B

A

B

A

B

A

B

A

B

A

D1

D3

D2

D4

(1)

0

(LHI[6:0])

(2)

LHO[1:0]

(3)

0

(BHI[2:0])

(4)

0

z

BHO[2:0]

SADR[21:0]

CE_L

z

ALE_L

WE_L

OE_L

z

SSV

SSF

Search1

(Miss on

this device.)

CFG = 01010101,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on

this device.)

Search3

(Miss on

Search4

this device.)

(Miss on this

device.)

AI05691

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

84/150

M7020R

Figure 60. Globally Winning Device in Block Number 3

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7 Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B

A

B

A

B

A

B

A

B

A

D3

D1

D2

D4

(1)

0

(LHI[6:0])

(2)

LHO[1:0]

(3)

(BHI[2:0])

(4)

BHO[2:0]

0

z

SADR[21:0]

CE_L

A1

z

0

ALE_L

WE_L

OE_L

z

1

SSV

SSF

z

1

Search1

(Global

winner.)

CFG = 01010101,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Hit but

not a global

winner.)

Search3

(Miss on this

device.)

Search4

(Miss on this

device.)

AI05692

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

85/150

M7020R

Figure 61. Devices Below the Winning Device in Block Number 3 (not Device 30 - Last Device)

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B

A

B

A

B

A

B

A

B

A

D1

D2

D3

D4

(1)

(LHI[6:0])

0

(2)

LHO[1:0]

(3)

(BHI[2:0])

0

(4)

BHO[2:0]

0

z

SADR[21:0]

CE_L

ALE_L

WE_L

OE_L

SSV

z

SSF

Search1

(Miss on

this device.)

CFG = 01010101,

HLAT = 001, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on

this device.)

Search3

(Miss on

Search4

this device.)

(Miss on this

device.)

AI05693

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

86/150

M7020R

Figure 62. Device 6 in Block Number 3 (Device 30 in Depth-Cascaded Table)

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1 Cycle 3

Cycle 5

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

Search4

CMD[8:2]

DQ

A

B

A

B

A

B

A

B

A

B

A

D3

D1

D2

D4

(1)

(LHI[6:0])

0

(2)

LHO[1:0]

(3)

(BHI[2:0])

0

(4)

BHO[2:0]

z

SADR[21:0]

CE_L

z

0

1

ALE_L

WE_L

z

1

0

OE_L

z

1

0

SSV

SSF

Search1

(Hit on

CFG = 01010101,

Search2

(Hit on

some device

above.)

some device

above.)

HLAT = 001, TLSZ = 10,

LRAM = 1, LDEV = 1

Search3

(Hit on

Search4

(Global miss;

this device

some device

above.)

default driver.)

AI05694

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

87/150

M7020R

Table 39. Latency of SEARCH from Instruction to SRAM Access Cycle, 136-bit, Up to 31 Devices

# of devices

1 (TLSZ = 00)

Max Table Size

16K x 136-bit

128K x 136-bit

496K x 136-bit

Latency in CLK Cycles

4

5

6

2–8 (TLSZ = 01)

9–31 (TLSZ = 10)

Table 40. Shift of SSF and SSV from SADR

HLAT

Number of CLK Cycles

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

272-bit SEARCH on Tables Configured as x272 Using a Single M7020R Device

The hardware diagram for this search subsystem

is shown in Figure 63, page 89. Figure 64, page 90

shows the timing diagram for a SEARCH com-

mand in the 272-bit-configured table (CFG =

10101010) consisting of a single device for one set

of parameters: TLSZ = ’00,’ HLAT = ’001,’ LRAM =

’1,’ and LDEV = ’1.’

The following is the sequence of operation for a

single 136-bit SEARCH command (also refer to

COMMAND CODES AND PARAMETERS, page

29).

– Cycle C: The host ASIC drives the CMDV high

and applies SEARCH command code ('10') on

CMD[1:0] signals. CMD[5:3] signals must be

driven with the index to the GMR pair used for

bits [135:0] of the data being searched.

CMD[8:7] signals must be driven with the bits

that will be driven on SADR[21:20] by this de-

vice if it has a hit. DQ[67:0] must be driven with

the 68-bit data ([135:68]) to be compared to all

locations “2” in the four 68-bits-word page. The

CMD[2] signal must be driven to logic '0.'

– Cycle D: The host ASIC continues to drive the

CMDV high and applies SEARCH command

code ('10') on CMD[1:0]. CMD[8:6] signals must

be driven with the index of the SSR that will be

used for storing the address of the matching en-

try and the Hit Flag (see SEARCH-Successful

Registers (SSR[0:7]), page 23). The DQ[67:0] is

driven with the 68-bit data ([67:0]) to be com-

pared to all locations “3” in the four 68-bits-word

page. CMD[5:2] is ignored because the LEARN

Instruction is not supported for x272 tables.

– Cycle A: The host ASIC drives the CMDV high

and applies SEARCH command code ('10') on

CMD[1:0] signals. CMD[5:3] signals must be

driven with the index to the GMR pair used for

bits [271:136] of the data being searched.

DQ[67:0] must be driven with the 68-bit data

([271:204]) to be compared to all locations “0” in

the four 68-bits-word page. The CMD[2] signal

must be driven to logic ’1.’

Note: CMD[2] = 1 signals that the search is a

x272-bit search. CMD[8:3] in this cycle is ig-

nored.

Note: For 272-bit searches, the host ASIC must

supply four distinct 68-bit data words on

DQ[67:0] during Cycles A, B, C, and D. The

GMR Index in Cycle A selects a pair of GMRs

that apply to DQ data in Cycles A and B. The

GMR Index in Cycle C selects a pair of GMRs

that apply to DQ data in Cycles C and D.

– Cycle B: The host ASIC continues to drive the

CMDV high and continues to apply the com-

mand code of SEARCH command ('10') on

CMD[1:0]. The DQ[67:0] is driven with the 68-bit

data ([204:136]) to be compared to all locations

“1” in the four 68-bits-word page.

88/150

M7020R

The logical 272-bit SEARCH operation is shown in

Figure 65, page 91. The entire table of 272-bit en-

tries is compared to a 272-bit word K that is pre-

sented on the DQ Bus in Cycles A, B, C, and D of

the command using the GMR and local mask bits.

The GMR is the 272-bit word specified by the two

pairs of GMRs selected by the GMR Indexes in the

command’s Cycles A and C. The 272-bit word K

that is presented on the DQ Bus in Cycles A, B, C,

and D of the command is compared with each en-

try in the table starting at location “0.” The first

matching entry’s location address, “L,” is the win-

ning address that is driven as part of the SRAM

address on SADR[21:0] lines (see SRAM AD-

DRESSING, page 126).

SEARCH (two LSBs of the matching index will be

'00').

The SEARCH command is a pipelined operation

and executes at one-fourth the rate of the frequen-

cy of CLK2X for 272-bit searches in x272-config-

ured tables. The latency of SADR, CE_L, ALE_L,

WE_L, SSV, and SSF from the 272-bit SEARCH

command (measured in CLK cycles) from the

CLK2X cycle that contains the C and D Cycles is

shown in Table 41, page 91.

The latency of a SEARCH from command to

SRAM access cycle is 4 for only a single device in

the table and TLSZ = 00. In addition, SSV and SSF

shift further to the right for different values of

HLAT, as specified in Table 42, page 91.

Note: The matching address is always going to be

location “0” in a four-entry page for a 272-bit

Figure 63. Hardware Diagram for a Table with One Device

BHI[2:0]

6

5

4

3

LHI

2

1

0

DQ[67:0]

SRAM

M7020R

CMDV, CMD[8:0]

SSF, SSV

BHO[2:0]

LHO[1]

LHO[0]

AI05695

89/150

M7020R

Figure 64. Timing Diagram for a 272-bit SEARCH for One Device

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search2

01

CMD[1:0]

CMD[2]

CMD[8:2]

A

C

B

D

A

C

B

D

DQ

D2

D1

SADR[21:0]

CE_L

A1

0

1

ALE_L

WE_L

0

1

0

1

0

1

0

OE_L

SSV

SSF

0

1

0

Search1

Hit

Search2

Miss

CFG = 10101010, HLAT = 001, TLSZ = 00, LRAM = 1, LDEV = 1

AI05696

90/150

M7020R

Figure 65. x272 Table with One Device

0

271

GMR

K

0

1

2

3

A

B

C

D

271

Location

address

0

4

8

12

L

(First matching entry)

32764

CFG = 10101010

(272-bit Configuration)

AI05697

Table 41. Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, 1 Device

# of devices

1 (TLSZ = 00)

Max Table Size

8K x 272-bit

Latency in CLK Cycles

4

5

6

2–8 (TLSZ = 01)

9–31 (TLSZ = 10)

64K x 272-bit

248K x 272-bit

Table 42. Shift of SSF and SSV from SADR

HLAT

Number of CLK Cycles

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

91/150

M7020R

272-bit SEARCH on Tables x272-configured Using Up to Eight M7020R Devices

The hardware diagram of the search subsystem of

eight devices is shown in Figure 66, page 94. The

following are the parameters programmed in the

eight devices.

– Cycle C: The host ASIC drives the CMDV high

and applies SEARCH command code ('10') on

CMD[1:0] signals. CMD[5:3] signals must be

driven with the index to the GMR pair used for

bits [135:0] of the data being searched.

CMD[8:7] signals must be driven with the bits

that will be driven on SADR[21:20] by this de-

vice if it has a hit. DQ[67:0] must be driven with

the 68-bit data ([135:68]) to be compared

against all locations “2” in the four 68-bits-word

page. The CMD[2] signal must be driven to logic

'0.'

– First seven devices (devices 0–6):

CFG = 10101010, TLSZ = 01, HLAT = 000,

LRAM = 0, and LDEV = 0.

– Eighth device (device 7):

CFG = 10101010, TLSZ = 01, HLAT = 000,

LRAM = 1, and LDEV = 1.

Note: All eight devices must be programmed with

the same value of TLSZ and HLAT. Only the last

device in the table must be programmed with

LRAM = 1 and LDEV = 1 (Device 7 in this case).

All other upstream devices must be programmed

with LRAM = 0 and LDEV = 0 (Devices 0 through

6 in this case).

– Cycle D: The host ASIC continues to drive the

CMDV high and applies SEARCH command

code ('10') on CMD[1:0]. CMD[8:6] signals must

be driven with the index of the SSR that will be

used for storing the address of the matching en-

try and the Hit Flag (see SEARCH-Successful

Registers (SSR[0:7]), page 23). The DQ[67:0] is

driven with the 68-bit data ([67:0]) to be com-

pared to all locations “3” in the four 68-bits-word

page. CMD[5:2] is ignored because the LEARN

Instruction is not supported for x272 tables.

Figure 68, page 96 shows the timing diagram for a

SEARCH command in the 272-bit-configured ta-

ble of eight devices for Device 0. Figure 69, page

97 shows the timing diagram for a SEARCH com-

mand in the 272-bit-configured table of eight de-

vices for Device 1. Figure 70, page 98 shows the

timing diagram for a SEARCH command in the

272-bit-configured table of eight devices for De-

vice 7 (the last device in this specific table). For

these timing diagrams three 272-bit searches are

performed sequentially. The following HIT/MISS

assumptions were made as shown in Table 43,

page 93.

Note: For 272-bit searches, the host ASIC must

supply four distinct 68-bit data words on

DQ[67:0] during Cycles A, B, C, and D. The

GMR Index in Cycle A selects a pair of GMRs in

each of the eight devices that apply to DQ data

in Cycles A and B. The GMR Index in Cycle C

selects a pair of GMRs in each of the eight de-

vices that apply to DQ data in Cycles C and D.

The logical 272-bit SEARCH operation is shown in

Figure 67, page 95. The entire table of 272-bit en-

tries is compared to a 272-bit word K that is pre-

sented on the DQ Bus in Cycles A, B, C, and D of

the command using the GMR and the local mask

bits. The GMR is the 272-bit word specified by the

two pairs of GMRs selected by the GMR Indexes

in the command’s Cycles A and C in each of the

eight devices. The 272-bit word K that is presented

on the DQ Bus in Cycles A, B, C, and D of the com-

mand is compared to each entry in the table start-

ing at location “0.” The first matching entry’s

location address, “L,” is the winning address that is

driven as part of the SRAM address on the

SADR[23:0] lines (see SRAM ADDRESSING,

page 126).

The following is the sequence of operation for a

single 272-bit SEARCH command (also COM-

MAND CODES AND PARAMETERS, page 29).

– Cycle A: The host ASIC drives the CMDV high

and applies SEARCH command code ('10') on

CMD[1:0] signals. CMD[5:3] signals must be

driven with the index to the GMR pair used for

bits [271:136] of the data being searched in this

operation. DQ[67:0] must be driven with the 68-

bit data ([271:204]) to be compared against all

locations “0” in the four-word, 68-bit page. The

CMD[2] signal must be driven to logic '1.'

Note: CMD[2] = 1 signals that the search is a

272-bit search. CMD[8:3] in this cycle is ig-

nored.

Note: The matching address is always going to be

a location “0” in a four-entry page for 272-bit

SEARCH (two LSBs of the matching index will be

'00').

– Cycle B: The host ASIC continues to drive the

CMDV high and applies SEARCH command

code ('10') on CMD[1:0]. The DQ[67:0] is driven

with the 68-bit data ([203:136]) to be compared

against all locations “1” in the four 68-bits-word

page.

92/150

M7020R

The SEARCH command is a pipelined operation

and executes search at one-fourth the rate of the

frequency of CLK2X for 272-bit searches in x272-

configured tables. The latency of SADR, CE_L,

ALE_L, WE_L, SSV, and SSF from the 272-bit

SEARCH command (measured in CLK cycles)

from the CLK2X cycle that contains the C and D

Cycles is shown in Table 44, page 99.

The latency of search from command to SRAM ac-

cess cycle is 5 for only a single device in the table

and TLSZ = 01. In addition, SSV and SSF shift fur-

ther to the right for different values of HLAT, as

specified in Table 45, page 99.

Table 43. Hit/Miss Assumption

Search Number

Device 0

1

2

3

Hit

Miss

Hit

Miss

Device 1

Miss

Device 2-6

Device 7

Miss

93/150

M7020R

Figure 66. Hardware Diagram for a Table with Eight Devices

SRAM

BHI[2:0]

6

5

4

3

2

1

0

LHI

M7020R #0

M7020R #1

LHO[1]

LHO[0]

SSF, SSV

DQ[67:0]

6

5

4

3

LHI

2

1

0

LHO[1]

LHO[0]

CMDV

CMD[8:0]

6

5

4

3

LHI

2

1

M7020R #2

M7020R #3

M7020R #4

M7020R #5

M7020R #6

M7020R #7

LHO[1]

LHO[0]

3

2

1

LHI

LHO[1]

LHO[0]

3

LHI

2

1

0

LHO[0]

3

2

1

0

6

5

LHI

LHO[0]

4

LHI

3

2

LHI

6

5

LHI

LHO[0]

3

2

LHI

1

0

6

5

LHI

4

BHO[0]

BHO[1]

BHO[2]

BHI[2:0]

BHO[0]

BHO[1]

BHO[2]

LHO[1]

LHO[0]

AI05666

94/150

M7020R

Figure 67. x272 Table with Eight Devices

0

271

Must be the same

in each of eight

devices

GMR

K

0

1

2

3

A

B

C

D

271

Location

address

0

4

8

12

L

(First matching entry)

262140

CFG = 10101010

(272-bit Configuration)

AI05698

95/150

M7020R

Timing Diagrams for x272-configured Using Up to Eight M7020R Devices

Figure 68. 272-bit SEARCH for Device Number 0

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search2

01

Search3

01

CMD[1:0]

CMD[2]

CMD[8:2]

DQ

A

C

A

C

B

D

A

B

A

C

B

D

D1

D2

D3

0

(1)

(LHI[6:0])

(2)

LHO[1:0]

z

SADR[21:0]

CE_L

A1

z

0

ALE_L

WE_L

OE_L

z

1

z

SSV

SSF

1

Search1

(This device

is the global

winner.)

CFG = 10101010,

HLAT = 000, TLSZ = 01,

LRAM = 0, LDEV = 0

Search2

(Miss on this

device.)

Search3

(Miss on this

device.)

AI05699

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

96/150

M7020R

Figure 69. 272-bit SEARCH for Device Number 1

Cycle 2

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 7 Cycle 9

Cycle 10

Cycle 1

CLK2X

PHS_L

CMDV

Search1

01

Search2

01

Search3

01

CMD[1:0]

CMD[2]

CMD[8:2]

A

C

B

D

A

B

A

C

B

D

DQ

C

D

D1

D2

D3

(1)

(LHI[6:0])

(2)

LHO[1:0]

z

SADR[21:0]

CE_L

A2

0

z

ALE_L

WE_L

z

1

OE_L

z

SSV

SSF

1

Search1

(Miss on this

device.)

CFG = 10101010,

HLAT = 000, TLSZ = 01,

LRAM = 0, LDEV = 0

Search2

(This device

is global

winner.)

Search3

(Miss on this

device.)

AI06300

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

97/150

M7020R

Figure 70. 272-bit SEARCH for Device Number 7 (Last Device)

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search2

01

Search3

01

CMD[1:0]

CMD[2]

CMD[8:2]

A

C

A

C

B

D

A

B

A

C

B

D

DQ

D

D1

D2

D3

(1)

(LHI[6:0])

(2)

LHO[1:0]

SADR[21:0]

A2

z

0

CE_L

0

1

ALE_L

z

WE_L

OE_L

1

0

z

1

0

SSV

SSF

z

Search1

(Miss on this

device.)

CFG = 10101010,

HLAT = 000, TLSZ = 01,

LRAM = 1, LDEV = 1

Search2

(Miss on this

device.)

Search3

(Global

miss.)

AI06301

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

98/150

M7020R

Table 44. Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, Up to 8 Devices

# of devices

1 (TLSZ = 00)

Max Table Size

8K x 272-bit

Latency in CLK Cycles

4

5

6

2–8 (TLSZ = 01)

9–31 (TLSZ = 10)

64K x 272-bit

248K x 272-bit

Table 45. Shift of SSF and SSV from SADR

HLAT

Number of CLK Cycles

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

272-bit Search on Tables Configured as x272 Using Up to 31 M7020R Devices

The hardware diagram of the search subsystem of

31 devices is shown in Figure 71, page 101. Each

of the four blocks in the diagram represents a

block of eight M7020R devices, except the last

which has seven devices.The diagram for a block

of eight devices is shown in Figure 72, page 102.

The following are the parameters programmed

into the 31 devices.

the timings, it is further assumed that there is only

one device with the matching entry in each block.

Figure 74, page 104 shows the timing diagram for

a SEARCH command in the 272-bit-configured ta-

ble consisting of 31 devices for each of the eight

devices in Block 0. Figure 75, page 105 shows the

timing diagram for a SEARCH command in the

272-bit-configured table of 31 devices for all devic-

es above the winning device in Block 1. Figure 76,

page 106 shows the timing diagram for the global-

ly winning device (the final winner within its own

and all blocks) in Block 1. Figure 77, page 107

shows the timing diagram for all the devices below

the globally winning device in Block 1. Figure 78,

page 108, Figure 79, page 109, and Figure 80,

page 110, respectively, show the timing diagrams

of the devices above the globally winning device,

the globally winning device, and the devices below

the globally winning device for Block 2. Figure 81,

page 111, Figure 82, page 112, Figure 83, page

113, and Figure 84, page 114, respectively, show

the timing diagrams of the device above the glo-

bally winning device, the globally winning device,

the devices below the globally winning device (ex-

cept Device 30), and last device (Device 30) for

Block 3.

– First thirty devices (devices 0–29):

CFG = 10101010, TLSZ = 10, HLAT = 000,

LRAM = 0, and LDEV = 0.

– Thirty-first device (device 30):

CFG = 10101010, TLSZ = 10, HLAT = 000,

LRAM = 1, and LDEV = 1.

Note: All 31 devices must be programmed with the

same value of TLSZ and HLAT. Only the last de-

vice in the table must be programmed with

LRAM = 1 and LDEV = 1 (Device 30 in this case).

All other upstream devices must be programmed

with LRAM = 0 and LDEV = 0 (Devices 0 through

29 in this case).

The timing diagrams referred to in this paragraph

reference the HIT/MISS assumptions defined in

Table 46, page 101. For the purpose of illustrating

99/150

M7020R

The following is the sequence of operation for a

single 272-bit SEARCH command (see COM-

MAND CODES AND PARAMETERS, page 29).

lects a pair of GMRs in each of the 31 devices

that apply to DQ data in Cycles C and D.

The logical 272-bit SEARCH operation is as

shown in Figure 73, page 103. The entire table of

272-bit entries is compared to a 272-bit word K

that is presented on the DQ Bus in Cycles A, B, C,

and D of the command using the GMR and local

mask bits. The GMR is the 272-bit word specified

by the two pairs of GMRs selected by the GMR In-

dexes in the command’s Cycles A and C in each

of the 31 devices. The 272-bit word K that is pre-

sented on the DQ Bus in Cycles A, B, C, and D of

the command is compared to each entry in the ta-

ble starting at location “0.” The first matching en-

try’s location address, “L,” is the winning address

that is driven as part of the SRAM address on the

SADR[21:0] lines (see SRAM ADDRESSING,

page 126).

– Cycle A: The host ASIC drives the CMDV high

and applies SEARCH command code ('10') on

CMD[1:0] signals. CMD[5:3] signals must be

driven with the index to the GMR pair used for

bits [271:136] of the data being searched.

DQ[67:0] must be driven with the 68-bit data

([271:204])to be compared to all locations “0” in

the four 68-bit-word page. The CMD[2] signal

must be driven to logic '1.'

Note: CMD[2] = 1 signals that the search is a

x272-bit search. CMD[8:7] is ignored in this cy-

cle.

– Cycle B: The host ASIC continues to drive the

CMDV high and applies SEARCH command

('10') on CMD[1:0]. The DQ[67:0] is driven with

the 68-bit data ([203:136]) to be compared to all

locations '1' in the four 68-bits-word page.

Note: The matching address is always going to be

location “0” in a four-entry page for 272-bit search

(two LSBs of the matching index will be '00').

– Cycle C: The host ASIC drives the CMDV high

and applies SEARCH command code ('10') on

CMD[1:0] signals. CMD[5:3] signals must be

driven with the index to the GMR pair used for

the bits [135:0] of the data being searched.

CMD[8:7] signals must be driven with the bits

that will be driven by this device on

SADR[21:20] if it has a hit. DQ[67:0] must be

driven with the 68-bit data ([135:68]) to be com-

pared to all locations “2” in the four 68-bit-word

page. The CMD[2] signal must be driven to logic

'0.'

– Cycle D: The host ASIC continues to drive the

CMDV high and continues to apply SEARCH

command code ('10') on CMD[1:0]. CMD[8:6]

signals must be driven with the index of the SSR

that will be used for storing the address of the

matching entry and the Hit Flag (see SEARCH-

Successful Registers (SSR[0:7]), page 23). The

DQ[67:0] is driven with the 68-bit data ([67:0]) to

be compared to all locations “3” in the four 68-

bit-word page. CMD[5:2] is ignored because the

LEARN Instruction is not supported for x272 ta-

bles.

The SEARCH command is a pipelined operation

and executes a search at one-fourth the rate of the

frequency of CLK2X for 272-bit searches in x272-

configured tables. The latency of SADR, CE_L,

ALE_L, WE_L, SSV, and SSF from the 272-bit

SEARCH command (measured in CLK cycles)

from the CLK2X cycle that contains Cycles C and

D shown in Table 47, page 115.

The latency of a SEARCH from command to

SRAM access cycle is 6 for only a single device in

the table and TLSZ = 10. In addition, SSV and SSF

shift further to the right for different values of

HLAT, as specified in Table 48, page 115

The 272-bit SEARCH operation is pipelined and

executes as follows:

– Four cycles from the last cycle of the SEARCH

command each of the devices knows the out-

come internal to it for that operation.

– In the fifth cycle from the SEARCH command,

the devices in a block (which is less than or

equal to eight devices resolving the winner with-

in them using an LHI[6:0] and LHO[1:0] signal-

ling mechanism) arbitrate for a winner.

Note: For 272-bit searches, the host ASIC must

supply four distinct 68-bit data words on

DQ[67:0] during Cycles A, B, C, and D. The

GMR Index in Cycle A selects a pair of GMRs in

each of the 31 devices that apply to DQ data in

Cycles A and B. The GMR Index in Cycle C se-

– In the sixth cycle after the SEARCH command,

the blocks of devices resolve the winning block

through a BHI[2:0] and BHO[2:0] signalling

mechanism. The winning device within the win-

ning block is the global winning device for the

SEARCH operation.

100/150

M7020R

Table 46. Hit/Miss Assumption

Search Number

1

2

3

Block 0

Block 1

Block 2

Block 3

Miss

Hit

Miss

Hit

Miss

Hit

Miss

Figure 71. Hardware Diagram for a Table with 31 Devices

BHI[2]

BHI[1]

BHI[0]

GND

SRAM

SSF, SSV

Block of 8 M7020Rs, Block 0 (Devices 0-7)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

GND

Block of 8 M7020Rs, Block 1 (Devices 8-15)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

GND

Block of 8 M7020Rs, Block 2 (Devices 16-23)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

DQ[67:0]

Block of 7 M7020Rs, Block 3 (Devices 24-30)

BHO[2]

CMD[8:0], CMDV

BHO[1]

BHO[0]

AI05671

101/150

M7020R

Figure 72. Hardware Diagram for a Block of Up to Eight Devices

SRAM

BHI[2:0]

6

5

4

3

2

1

0

LHI

M7020R #0

M7020R #1

LHO[1]

LHO[0]

6

5

4

3

LHI

2

1

0

LHO[1]

LHO[0]

DQ[67:0]

CMDV

CMD[8:0]

6

5

4

3

LHI

2

1

M7020R #2

M7020R #3

M7020R #4

M7020R #5

SSV, SSF

LHO[1]

LHO[0]

3

2

LHI

LHO[0]

LHO[1]

BHI[2:0]

5

4

3

LHI

2

1

0

LHO[0]

3

2

1

0

6

5

4

LHI

LHO[0]

LHI

2

LHI

6

5

LHI

M7020R #6_LHO[0]

3

2

LHI

1

0

6

5

LHI

4

BHO[0]

BHO[1]

BHO[2]

BHI[2:0]

M7020R #7

BHO[0]

BHO[1]

BHO[2]

LHO[1] LHO[0]

AI05672

102/150

M7020R

Figure 73. x272 Table with 31 Devices

0

271

Must be the same

in each of 31

devices

GMR

K

0

1

2

3

A

B

C

D

271

Location

address

0

4

8

12

L

(First matching entry)

262140

CFG = 10101010

(272-bit Configuration)

AI06302

103/150

M7020R

Timing Diagrams for x272 Using Up to 31 M7020R Devices

Figure 74. Each Device in Block Number 0 (Miss on Each Device)

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search2

01

Search3

01

CMD[1:0]

CMD[2]

CMD[8:2]

DQ

A

C

A

C

B

D

A

B

A

C

B

D

D1

D2

D3

(1)

0

(LHI[6:0])

(2)

0

z

LHO[1:0]

(3)

(BHI[2:0])

(4)

BHO[2:0]

SADR[21:0]

CE_L

z

ALE_L

WE_L

OE_L

SSV

SSF

Search1

(Miss on this

device.)

CFG = 10101010,

HLAT = 000, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on this

device.)

Search3

(Miss on this

device.)

AI06303

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

104/150

M7020R

Figure 75. Each Device Above the Winning Device in Block Number 1

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search2

01

Search3

01

CMD[1:0]

CMD[2]

CMD[8:2]

DQ

A

C

A

C

B

D

A

B

A

C

B

D

D1

D2

D3

(1)

0

(LHI[6:0])

(2)

0

z

LHO[1:0]

(3)

(BHI[2:0])

(4)

BHO[2:0]

SADR[21:0]

CE_L

z

ALE_L

WE_L

OE_L

SSV

SSF

Search1

(Miss on this

device.)

CFG = 10101010,

HLAT = 000, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on this

device.)

Search3

(Miss on this

device.)

AI06303

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

105/150

M7020R

Figure 76. Globally Winning Device in Block Number 1

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search2

01

Search3

01

CMD[1:0]

CMD[2]

CMD[8:2]

A

C

A

C

B

D

A

B

A

C

B

D

DQ

D

D1

D2

D3

(1)

0

(LHI[6:0])

(2)

LHO[1:0]

0

(3)

(BHI[2:0])

(4)

0

z

BHO[2:0]

SADR[21:0]

CE_L

A3

0

ALE_L

z

WE_L

OE_L

1

z

1

SSV

SSF

Search1

(Miss on this

device.)

CFG = 10101010,

HLAT = 000, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on this

device.)

Search3

(This device

global winner.)

AI06304

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

106/150

M7020R

Figure 77. Devices Below the Winning Device in Block Number 1

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search2

01

Search3

01

CMD[1:0]

CMD[2]

CMD[8:2]

A

C

A

C

B

D

A

B

A

C

B

D

DQ

D

D1

D2

D3

(1)

(LHI[6:0])

0

(2)

LHO[1:0]

(3)

(BHI[2:0])

(4)

BHO[2:0]

0

z

SADR[21:0]

CE_L

ALE_L

WE_L

OE_L

SSV

SSF

Search1

(Miss on this

device.)

CFG = 10101010,

HLAT = 000, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on this

device.)

Search3

(Miss on this

device.)

AI06305

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

107/150

M7020R

Figure 78. Devices Above the Winning Device in Block Number 2

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search2

01

Search3

01

CMD[1:0]

CMD[2]

CMD[8:2]

A

C

A

C

B

D

A

B

A

C

B

D

DQ

D

D1

D2

D3

(1)

0

(LHI[6:0])

(2)

LHO[1:0]

(3)

(BHI[2:0])

0

z

(4)

BHO[2:0]

SADR[21:0]

CE_L

ALE_L

WE_L

OE_L

SSV

SSF

Search1

(Miss on this

device.)

CFG = 10101010,

HLAT = 000, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on this

device.)

Search3

(Miss on this

device; hit

in Block 0 or 1.)

AI06306

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

108/150

M7020R

Figure 79. Globally Winning Device in Block Number 2

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search2

01

Search3

01

CMD[1:0]

CMD[2]

CMD[8:2]

A

C

A

C

B

D

A

B

A

C

B

D

DQ

D

D1

D2

D3

(1)

0

(LHI[6:0])

(2)

LHO[1:0]

(3)

(BHI[2:0])

(4)

BHO[2:0]

0

z

SADR[21:0]

A2

z

CE_L

0

ALE_L

z

WE_L

OE_L

1

z

1

SSV

SSF

Search1

(Miss on this

device.)

CFG = 10101010,

HLAT = 000, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Global

winner.)

Search3

(Hit but not

a winner.)

AI06307

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

109/150

M7020R

Figure 80. Devices Below the Winning Device in Block Number 2

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search2

01

Search3

01

CMD[1:0]

CMD[2]

CMD[8:2]

A

C

A

C

B

D

A

B

A

C

B

D

DQ

D

D1

D2

D3

(1)

0

(LHI[6:0])

(2)

LHO[1:0]

(3)

0

(BHI[2:0])

(4)

0

BHO[2:0]

SADR[21:0]

z

CE_L

ALE_L

WE_L

OE_L

SSV

z

SSF

Search1

(Miss on this

device.)

CFG = 10101010,

HLAT = 000, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on this

device.)

Search3

(Miss on this

device.)

AI06308

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

110/150

M7020R

Figure 81. Devices Above the Winning Device in Block Number 3

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search2

01

Search3

01

CMD[1:0]

CMD[2]

CMD[8:2]

A

C

A

C

B

D

A

B

A

C

B

D

DQ

D

D1

D2

D3

(1)

0

(LHI[6:0])

(2)

LHO[1:0]

(3)

(BHI[2:0])

0

(4)

0

z

BHO[2:0]

SADR[21:0]

CE_L

ALE_L

WE_L

OE_L

SSV

SSF

Search1

(Miss on this

device.)

CFG = 10101010,

HLAT = 000, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on this

device.)

Search3

(Miss on this

device.)

AI06309

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

111/150

M7020R

Figure 82. Globally Winning Device in Block Number 3

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search2

01

Search3

01

CMD[1:0]

CMD[2]

CMD[8:2]

A

C

A

C

B

D

A

B

A

C

B

D

DQ

D

D1

D2

D3

(1)

0

(LHI[6:0])

(2)

LHO[1:0]

(3)

(BHI[2:0])

(4)

BHO[2:0]

0

z

SADR[21:0]

A1

CE_L

0

ALE_L

z

WE_L

OE_L

1

z

1

SSV

SSF

Search1

(Global

winner.)

CFG = 10101010,

HLAT = 000, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Hit but not

a global

Search3

(Miss on this

device.)

winner.)

AI06310

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

112/150

M7020R

Figure 83. Devices Below the Winning Device in Block Number 3 (not Device 30 - Last Device)

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search2

01

Search3

01

CMD[1:0]

CMD[2]

CMD[8:2]

A

C

A

C

B

D

A

B

A

C

B

D

DQ

D

D1

D2

D3

(1)

(LHI[6:0])

0

(2)

LHO[1:0]

(3)

0

(BHI[2:0])

(4)

BHO[2:0]

0

SADR[21:0]

z

CE_L

ALE_L

WE_L

OE_L

SSV

z

SSF

Search1

(Miss on this

device.)

CFG = 10101010,

HLAT = 000, TLSZ = 10,

LRAM = 0, LDEV = 0

Search2

(Miss on this

device.)

Search3

(Miss on this

device.)

AI06311

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

113/150

M7020R

Figure 84. Last Device in Block Number 3 (Device 30 in the Table)

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search2

01

Search3

01

CMD[1:0]

CMD[2]

CMD[8:2]

A

C

A

C

B

D

A

B

A

C

B

D

DQ

D

D1

D2

D3

(1)

(LHI[6:0])

0

(2)

LHO[1:0]

(3)

(BHI[2:0])

0

(4)

BHO[2:0]

z

SADR[21:0]

z

CE_L

0

ALE_L

z

WE_L

OE_L

z

1

z

0

SSV

SSF

Search1

(Hit on some

device above.)

CFG = 10101010,

HLAT = 000, TLSZ = 10,

LRAM = 1, LDEV = 1

Search2

(Hit on some

device above.)

Search3

(Hit on some

device above.)

AI06312

Note: 1. (LHI[6:0]) stands for the boolean ’OR’ of the entire bus LHI[6:0].

2. Each bit in LHO[1:0] is the same logical signal.

3. (BHI[2:0]) stands for the boolean ’OR’ of the entire bus BHI[2:0].

4. Each bit in BHO[2:0] is the same logical signal.

114/150

M7020R

Table 47. Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, Up to 31

Devices

# of devices

Max Table Size

8K x 272-bit

Latency in CLK Cycles

1 (TLSZ = 00)

2–8 (TLSZ = 01)

9–31 (TLSZ = 10)

4

5

6

64K x 272-bit

248K x 272-bit

Table 48. Shift of SSF and SSV from SADR

HLAT

Number of CLK Cycles

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

MIXED SEARCHES

Tables Configured with Different Widths Using

an M7020R

Note: The DQ[67:66] will be '00' in both of the Cy-

cles A and B of the x68-bit search (Search1).

DQ[67:66] is '01' in both of the Cycles A and B of

the x136-bit search (Search2). DQ[67:66] is '10' in

all of the Cycles A, B, C, and D of the x272-bit

search (Search 3). By having table designation

bits, the M7020R enables the creation of many ta-

bles in a bank of search engines of different

widths.

The sample operation shown is for a single device

with CFG = 1001000. It contains three tables of

x68, x136, and x272 widths. The operation may be

generalized to a block of 8–31 devices using four

blocks; the timing and the pipeline operation is the

same as described previously for fixed searches

on a table of one-width-size.

Figure 86, page 117 shows the sample table. Two

bits in each 68-bit entry will need to designated as

the Table Number Bits. One example choice can

be the '00' values for the table configured as x68,

'01' values for tables configured as x136, and '10'

values for tables configured as x272. For the

above explanation, it is further assumed that bits

[67:66] for each entry will be designed as these

Table Designation Bits.

Figure 85, page 116 shows three sequential

searches:

– a 68-bit search on the table configured as x68;

– a 136-bit search on a table configured as x136;

and

– a 272-bit search on the table configured as x272

bits that each results in a hit.

115/150

M7020R

Figure 85. Timing Diagram for Mixed SEARCH for One Device

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

Search1

01

Search3

01

CMD[1:0]

01

Search2

CMD[2]

CMD[8:2]

DQ

A

B

A

C

B

D

D1

D2

D3

A1

A2

0

A3

1

SADR[21:0]

CE_L

1

0

1

ALE_L

0

1

WE_L

OE_L

1

0

1

0

1

0

SSV

SSF

1

0

Search1

(x68 Hit)

CFG = 10010000,

Search2

(x136 Hit)

HLAT = 010, TLSZ = 00,

LRAM = 1, LDEV = 1

Search3

(x272 Hit)

AI06313

116/150

M7020R

Figure 86. Multi-Width Configurations Example

68

16 K

136

4 K

2 K

272

CFG = 10 01 00 00

AI06314

LRAM AND LDEV DESCRIPTION

When search engines are cascaded using multiple

M7020Rs, the SADR, CE_L, and WE_L (3-state

signals) are all tied together. In order to eliminate

external pull-up and pull-downs, one device in a

bank is designated as the default driver. For non-

SEARCH or non-LEARN cycles (see LEARN

COMMAND in the section below) or search cycles

with a global miss, the SADR, CE_L, and WE_L

signals are driven by the device with the LRAM Bit

set.

Note: It is important that only one device in a bank

of search engines that are cascaded have this bit

set. Failure to do so will cause contention on

SADR, CE_L, WE_L, and can potentially cause

damage to the device(s).

Similarly, when search engines using multiple

M7020Rs are cascaded, SSF and SSV (also 3-

state signals) are tied together. In order to elimi-

nate external pull-up and pull-downs, one device

in a bank is designated as the default driver. For

non-SEARCH cycles or SEARCH cycles with a

global miss the SSF and SSV signals are driven by

the device with the LDEV Bit set.

Note: It is important that only one device in a bank

of search engines that are cascaded together

have this bit set. Failure to do so will cause conten-

tion on SSV and SSF and can potentially cause

damage to the device(s).

117/150

M7020R

LEARN COMMAND

Bit [0] of each 68-bit data location specifies wheth-

er an entry in the database is occupied. If all the

entries in a device are occupied, the device as-

serts FULO signal to inform the downstream de-

vices that it is full.

The result of this communication between depth-

cascaded devices determines the global FULL

signal for the entire table. The FULL signal in the

last device determines the fullness of the depth-

cascaded table.

In a depth-cascaded table, only a single device will

learn the entry through the application of a LEARN

Instruction. The determination of which device is

going to learn is based on the FULI and FULO sig-

nalling between the devices. The first non-full de-

vice learns the entry by storing the contents of the

specified comparand registers to the location(s)

pointed to by NFA.

In a x68-configured table the LEARN command

writes a single 68-bit location. In a x136-config-

ured table the LEARN command writes the next

even and odd 68-bit locations. In 136-bit mode,

Bit[0] of the even and odd 68-bit locations is ’0,’

which indicates they are cascaded empty, or ’1,’

which indicates they are occupied.

The global FULL signal indicates to the Table Con-

troller (the host ASIC) that all entries within a block

are occupied and that no more entries can be

learned. The M7020R updates the signal after

each WRITE or LEARN command to a data array.

The LEARN command generates a WRITE cycle

to the external SRAM, also using the NFA register

as part of the SRAM address (see SRAM AD-

DRESSING, page 126).

The LEARN command is supported on a single

block containing up to eight devices if the table is

configured either as a x68 or a x136. The LEARN

command is not supported for x272-configured ta-

bles.

LEARN is a pipelined operation and lasts for two

CLK cycles, as shown in Figure 87, page 119

where TLSZ = 00, and Figure 88, page 120 and

Figure 89, page 121 where TLSZ = 01 (which as-

sume the device performing the LEARN operation

is not the last device in the table and has its LRAM

Bit set to ’0.’

Note: The OE_L for the device with the LRAM Bit

set goes high for two cycles for each LEARN (one

during the SRAM WRITE cycle, and one the cycle

before). The latency of the SRAM WRITE cycle

from the second cycle of the Instruction is shown

in Table 49, page 121.

The sequence of operation is as follows:

– Cycle 1A: The host ASIC applies the LEARN In-

struction on the CMD[1:0], using CMDV = 1.

The CMD[5:2] field specifies the index of the

comparand register pair that will be written in

the data array in the 136-bit-configured table.

For a LEARN in a 68-bit-configured table, the

even-numbered comparands specified by this

index will be written. CMD[8:7] carries the bits

that will be driven on SADR[21:20] in the SRAM

WRITE cycle.

– Cycle 1B: The host ASIC continues to drive

CMDV to '1,' CMD[1:0] to '11,' and CMD[5:2]

with the comparand pair index. CMD[6] must be

set to '0' if the LEARN is being performed on a

68-bit-configured table, and to '1' if the LEARN

is being performed on a 136-bit-configured ta-

ble.

– Cycle 2: The host ASIC drives the CMDV to '0.'

At the end of Cycle 2, a new instruction can be-

gin. The latency of the SRAM WRITE is the

same as the search to the SRAM READ Cycle.

It is measured from the second cycle of the

LEARN Instruction.

118/150

M7020R

Figure 87. Timing Diagram of LEARN: TLSZ = 00

Cycle 2

Cycle 4

Cycle 6

Cycle 8

Cycle 10

Cycle 1

Cycle 3

Cycle 5

Cycle 7 Cycle 9

CLK2X

PHS_L

CMDV

CMD[1:0]

CMD[8:2]

Learn2

Comp2

X

Learn1

Comp1

X

1A 1B

X

DQ

z

A2

SADR[21:0]

A1

0

CE_L

WE_L

1

0

1

OE_L

0

SSV

SSF

TLSZ = 00, LRAM = 1, LDEV = 1

AI06315

119/150

M7020R

Figure 88. Timing Diagram of LEARN: TLSZ = 01 (Except on the Last Device)

Cycle 2

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 7 Cycle 9

Cycle 10

Cycle 1

CLK2X

PHS_L

CMDV

CMD[1:0]

Learn2

X

Learn1

Comp1

X

Comp2

CMD[8:2]

DQ

X

1A 1B

X

z

X

z

A2

SADR[21:0]

CE_L

A1

0

WE_L

0

z

OE_L

SSV

SSF

TLSZ = 01, LRAM = 0, LDEV = 0

AI06316

120/150

M7020R

Figure 89. Timing Diagram of LEARN on Device 7: TLSZ = 01

Cycle 2

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 1

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

CMD[1:0]

CMD[8:2]

Learn2

X

Learn1

Comp1

X

Comp2

X

1A 1B

X

z

X

DQ

z

SADR[21:0]

z

CE_L

WE_L

1

OE_L

0

SSV

SSF

TLSZ = 01, LRAM = 1, LDEV = 1

AI06317

Table 49. Latency of SRAM WRITE Cycle from Second Cycle of LEARN Instruction

# of devices

1 (TLSZ = 00)

Latency in CLK Cycles

4

5

6

2–8 (TLSZ = 01)

9–31 (TLSZ = 10)

121/150

M7020R

DEPTH-CASCADING

The search engine application can depth-cascade

the device to various table sizes of different widths

(e.g., 68-bit, 136-bit, and 272-bit configurations).

The devices perform all the necessary arbitration

to decide which device drives the SRAM Bus. The

latency of the searches increases as the table size

increases while the search rate remains constant.

devices within that block, these signals stay open

and floating. The host ASIC must program the ta-

ble size (TLSZ) field to ’10’ in each of the devices

for cascading up to 31 devices (in up to four

blocks).

Depth-Cascading to Generate a “FULL” Signal

Bit[0] of each of the 68-bit entries is designated as

a special bit (1 = occupied; 0 = empty). For each

LEARN or PIO WRITE to the data array, each de-

vice asserts FULO[1] and FULO[0] if it does not

have any empty locations (see Figure 92, page

125).

Depth-Cascading Up to Eight Devices (One

Block)

Figure 90, page 123 shows how up to eight devic-

es can cascade to form a 256K x68, 128K x136, or

64K x272 bit table. It also shows the interconnec-

tion between the devices for depth-cascading.

Each Search Engine asserts the LHO[1] and

LHO[0] signals to inform downstream devices of

its result. The LHI[6:0] signals for a device are con-

nected to LHO signals of the upstream devices.

The host ASIC must program the TLSZ to ’01’ for

each of up to eight devices in a block. Only a single

device drives the SRAM Bus in any single cycle.

Each device combines the FULO signals from the

devices above it with its own “full” status to gener-

ate a FULL signal that gives the “full” status of the

table up to the device asserting the FULL signal.

Figure 92, page 125 shows the hardware connec-

tion diagram for generating the FULL signal that

goes back to the ASIC. In a depth-cascaded block

of up to eight devices, the FULL signal from the

last device should be fed back to the ASIC control-

ler to indicate the fullness of the table. The FULL

signal of the other devices should be left open.

Note: The LEARN instruction is supported for only

up to eight devices, whereas FULL cascading is

allowed only for one block in tables containing

more than eight devices. In tables for which a

LEARN Instruction is not going to be used, the

Bit[0] of each 68-bit entry should always be set to

'1.'

Depth-Cascading Up to 31 Devices (4 Blocks)

Figure 91, page 124 shows how to cascade up to

four blocks. Each block contains up to eight

M7020Rs (except the last block) and the intercon-

nection within each is shown in Figure 90, page

123.

Note: The interconnection between blocks for

depth-cascading is important. For each SEARCH,

a block asserts BHO[2], BHO[1], and BHO[0]. The

BHO[2:0] signals for a block are the signals taken

only from the last device in the block. For all other

122/150

M7020R

Figure 90. Depth-Cascading to Form a Single Block

SRAM

BHI[2:0]

6

5

4

3

LHI

2

1

0

M7020R #0

LHO[1]

LHO[0]

SSF, SSV

DQ[67:0]

BHI[2:0]

6

5

4

3

2

1

0

LHI

M7020R #1

M7020R #2

M7020R #3

M7020R #4

M7020R #5

M7020R #6

M7020R #7

LHO[1]

LHO[0]

CMDV

CMD[8:0]

6

5

4

3

LHI

2

1

LHO[1]

LHO[0]

3

2

1

LHI

LHO[1]

LHO[0]

3

LHI

2

1

0

LHO[0]

3

2

1

0

6

5

LHI

4

LHI

LHO[0]

3

2

LHI

6

5

LHI

LHO[0]

3

2

LHI

1

0

6

5

LHI

4

BHO[0]

BHO[1]

BHO[2]

BHI[2:0]

BHO[0]

BHO[1]

BHO[2]

LHO[1]

LHO[0]

AI05666

123/150

M7020R

Figure 91. Depth-Cascading Four Blocks

BHI[2]

BHI[1]

BHI[0]

GND

SRAM

SSF, SSV

Block of 8 M7020Rs, Block 0 (Devices 0-7)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

Block of 8 M7020Rs, Block 1 (Devices 8-15)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

Block of 8 M7020Rs, Block 2 (Devices 16-23)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

DQ[67:0]

Block of 7 M7020Rs, Block 3 (Devices 24-30)

BHO[2]

CMD[8:0], CMDV

BHO[1]

BHO[0]

AI05671

124/150

M7020R

Figure 92. “FULL” Generation in a Cascaded Table

V

DDQ

DQ[71:0]

6

5

4

FULI

3

2

1

0

M7020R

FULO[1]

FULO[0]

FULL

DDQ

6

5

4

3

2

1

0

FULI

M7020R

FULO[1]

FULO[0]

V

FULL

DDQ

6

5

4

FULI

3

2

1

M7020R

FULO[1]

FULO[0]

4

3

2

FULI

M7020R

FULO[1]

FULO[0]

DDQ

4

3

2

1

0

FULI

FULO[0]

M7020R

V

DDQ

FULL

3

2

1

0

6

5

4

FULI

M7020R

FULI

FULO[0]

V

2

FULI

6

5

4

FULI

FULO[0]

FULL

3

2

FULI

1

0

6

5

4

FULI

FULO[1] FULO[0]

AI06318

125/150

M7020R

SRAM ADDRESSING

Table 50, page 127 describes the commands used

to generate addresses on the SRAM Address Bus.

The index [14:0] field contains the address of a 68-

bit entry that results in a hit in 68-bit-configured

quadrant. It is the address of the 68-bit entry that

lies at the 136-bit page, and the 272-bit page

boundaries in 136-bit- and 272-bit-configured

quadrants, respectively.

the address appearing on the SRAM Bus is the

same as the latency of the SEARCH Instruction

and will depend on the TLSZ value parameter pro-

grammed in the device configuration register. The

latency of the ACK from the READ Instruction is

the same as the latency of the SEARCH Instruc-

tion to the SRAM address plus the HLAT pro-

grammed in the configuration register.

REGISTERS, page 21 of this specification, de-

scribes the NFA and SSR Registers. ADR[14:0]

contains the address supplied on the DQ Bus dur-

ing PIO access to the M7020R. Command Bits 8

and 7 {CMD[8:7]} are passed from the command

to the SRAM Address Bus (see COMMAND

CODES AND PARAMETERS, page 29 for more

information). ID[4:0] is the ID of the device driving

the SRAM Bus (see Figure 3, page 10 and Table

2, page 9 for more information).

The following explains the SRAM READ operation

in a table with only one device that has the follow-

ing parameters: TLSZ = 00, HLAT = 000, LRAM =

1, and LDEV = 1. Figure 93, page 127 shows the

associated timing diagram.

For the following description, the selected device

refers to the only device in the table because it is

the only device to be accessed.

The sequence of the operation is as follows:

– Cycle 1A: The host ASIC applies the READ In-

struction on the CMD[1:0], using CMDV = 1.

The DQ Bus supplies the address with

DQ[20:19] set to '10' to select the SRAM ad-

dress. The host ASIC selects the device for

which the ID[4:0] matches the DQ[25:21] lines.

During this cycle, the host ASIC also supplies

SADR[21:20] on CMD[8:7] in this cycle.

– Cycle 1B: The host ASIC continues to apply the

READ Instruction on the CMD[1:0] using

CMDV = 1. The DQ Bus supplies the address

with DQ[20:19] set to '10' to select the SRAM

address.

SRAM PIO Access

SRAM READ enables READ access to off-chip

SRAM that contains associative data. The latency

from the issuance of the READ Instruction to the

address appearing on the SRAM Bus is the same

as the latency of the SEARCH Instruction and will

depend on the TLSZ value parameter pro-

grammed in the device Configuration Register.

The latency of the ACK from the READ Instruction

is the same as the latency of the SEARCH Instruc-

tion to the SRAM address plus the HLAT pro-

grammed in the Configuration Register.

Note: SRAM READ is a blocking operation – no

new instruction can begin until the ACK is returned

by the selected device performing the access.

– Cycle 2: The host ASIC floats DQ[67:0] to a 3-

state condition.

– Cycle 3: The host ASIC keeps DQ[67:0] in a 3-

SRAM WRITE enables WRITE access to the off-

chip SRAM containing associative data. The laten-

cy from the second cycle of the WRITE Instruction

to the address appearing on the SRAM Bus is the

same as the latency of the SEARCH Instruction

and will depend on the TLSZ value parameter pro-

grammed in the device Configuration Register.

Note: SRAM WRITE is a pipelined operation –

new instruction can begin right after the previous

command has ended.

state condition.

– Cycle 4: The selected device starts to drive

DQ[67:0] and drives ACK from High-Z to low.

– Cycle 5: The selected device drives the READ

address on SADR[21:0]; it also drives ACK high,

CE_L low, and ALE_L low.

– Cycle 6: The selected device drives CE_L high,

ALE_L high, the SADR Bus, and the DQ Bus in

a 3-state condition; it drives ACK low.

At the end of Cycle 6, the selected device floats

ACK in a 3-state condition, and a new command

can begin.

SRAM READ with a Table of One Device

SRAM READ enables READ access to the off-

chip SRAM containing associative data. The laten-

cy from the issuance of the READ Instruction to

126/150

M7020R

Table 50. Generating an SRAM Bus Address

Command

SEARCH

SRAM Operation

READ

21

C8

20

C7

[19:15]

ID[4:0]

[14:0]

Index[14:0]

NFA[14:0]

ADR[14:0]

SSR[14:0]

LEARN

WRITE

PIO READ

PIO WRITE

Indirect Access

READ

WRITE

WRITE/READ

Figure 93. SRAM READ Access for One Device

Cycle 1 Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 6

CLK2X

PHS_L

CMDV

READ

CMD[1:0]

A

B

CMD[8:2]

DQ

z

Address

(DQ driven by M7040)

0

1

OE_L

WE_L

CE_L

0

1

ALE_L

SADR

ACK

Address

z

1

0

SSV

SSF

HLAT = 000, TLSZ = 00, LRAM = 1, LDEV = 1

AI06319

127/150

M7020R

SRAM READ with a Table of Up to Eight Devices

The following explains the SRAM READ operation

completed through a table of up to eight devices

using the following parameters: TLSZ = 01. Figure

94, page 129 diagrams a block of eight devices.

with DQ[20:19] set to '10' to select the SRAM

address.

– Cycle 2: The host ASIC floats DQ[67:0] to a 3-

state condition.

The following assumes that SRAM access is suc-

cessfully achieved through M7020R Device 0. Fig-

ure 95, page 130 and Figure 96, page 131 show

timing diagrams for Device 0 and Device 7, re-

spectively.

– Cycle 1A: The host ASIC applies the READ In-

struction on the CMD[1:0] using CMDV = 1. The

DQ Bus supplies the address, with DQ[20:19]

set to '10' to select the SRAM address. The host

ASIC selects the device for which ID[4:0] match-

es the DQ[25:21] lines. During this cycle the

host ASIC also supplies SADR[21:20] on

CMD[8:7].

– Cycle 3: The host ASIC keeps DQ[67:0] in a 3-

state condition.

– Cycle 4: The selected device starts to drive

DQ[67:0].

– Cycle 5: The selected device continues to drive

DQ[67:0] and drives ACK from high-Z to low

– Cycle 6: The selected device drives the READ

address on SADR[21:0]. It also drives ACK

high, CE_L low, WE_L high, and ALE_L low.

– Cycle 7: The selected device drives CE_L,

ALE_L, WE_L, and the DQ Bus in a 3-state con-

dition. It continues to drive ACK low.

– Cycle 1B: The host ASIC continues to apply the

READ Instruction on the CMD[1:0] using

CMDV = 1. The DQ Bus supplies the address

At the end of Cycle 7, the selected device floats

ACK in 3-state condition and a new command can

begin.

128/150

M7020R

Figure 94. Table with Eight Devices

SRAM

BHI[2:0]

6

5

4

3

2

1

0

LHI

M7020R #0

M7020R #1

LHO[1]

LHO[0]

SSF, SSV

BHI[2:0]

6

5

4

3

LHI

2

1

0

LHO[1]

LHO[0]

DQ[67:0]

CMDV

BHI[2:0]

6

5

4

3

LHI

2

1

CMD[8:0]

M7020R #2

M7020R #3

M7020R #4

M7020R #5

M7020R #6

M7020R #7

LHO[1]

LHO[0]

BHI[2:0]

3

2

1

LHI

LHO[1]

LHO[0]

3

LHI

2

1

0

LHO[0]

3

2

1

0

6

5

LHI

LHO[0]

4

LHI

2

LHI

6

5

LHI

LHO[0]

3

2

LHI

1

0

6

5

LHI

4

BHO[0]

BHO[1]

BHO[2]

BHI[2:0]

BHO[0]

BHO[1]

BHO[2]

LHO[1]

LHO[0]

AI05666

129/150

M7020R

Figure 95. SRAM READ Through Device 0 in a Block of Eight Devices

Cycle 1 Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 6 Cycle 7

CLK2X

PHS_L

CMDV

READ

CMD[1:0]

A

B

CMD[8:2]

DQ

z

Address

(DQ driven by the selected M7040)

z

OE_L

WE_L

CE_L

z

1

0

z

0

ALE_L

SADR

z

Address

z

1

ACK

0

z

SSV

SSF

HLAT = 000, TLSZ = 01, LRAM = 0, LDEV = 0

AI06320

130/150

M7020R

Figure 96. SRAM READ Timing for Device 7 in a Block of Eight Devices

Cycle 1 Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 6

CLK2X

PHS_L

CMDV

READ

CMD[1:0]

A

B

CMD[8:2]

DQ

z

Address

0

OE_L

WE_L

CE_L

z

1

ALE_L

SADR

z

ACK

SSV

SSF

HLAT = 000, TLSZ = 01, LRAM = 0, LDEV = 0

AI06321

131/150

M7020R

SRAM READ with a Table of Up to 31 Devices

The following explains the SRAM READ operation

accomplished through a table of up to 31 devices,

using the following parameters: TLSZ = 10. The di-

agram of such a table is shown in Figure 97, page

133.

The following assumes that SRAM access is being

accomplished through M7020R Device 0 and that

Device 0 is the selected device. Figure 98, page

134 and Figure 99, page 135 show the timing dia-

grams for Device 0 and Device 30, respectively.

– Cycle 1A: The host ASIC applies the READ In-

struction to CMD[1:0] using CMDV = 1. The DQ

Bus supplies the address, with DQ[20:19] set to

'10,' to select the SRAM address. The host

ASIC selects the device for which the ID[4:0]

matches the DQ[25:21] lines. During this cycle,

the host ASIC also supplies SADR[21:20] on

CMD[8:7].

DQ[20:19] set to '10,' to select the SRAM ad-

dress.

– Cycle 2: The host ASIC floats DQ[67:0] to a 3-

state condition.

– Cycle 3: The host ASIC keeps DQ[67:0] in a 3-

state condition.

– Cycle 4: The selected device starts to drive

DQ[67:0].

– Cycles 5 to 6: The selected device continues to

drive DQ[67:0].

– Cycle 7: The selected device continues to drive

DQ[67:0] and drives an SRAM READ cycle.

– Cycle 8: The selected device drives ACL from Z

to low.

– Cycle 9: The selected device drives ACK to

high.

– Cycle 10: The selected device drives ACK from

– Cycle 1B: The host ASIC continues to apply the

READ Instruction to CMD[1:0] using CMDV = 1.

The DQ Bus supplies the address, with

high to low.

At the end of Cycle 10, the selected device floats

ACL in a 3-state condition.

132/150

M7020R

Figure 97. Table of 31 Devices Made of Four Blocks

BHI[2]

BHI[1]

BHI[0]

GND

SRAM

SSF, SSV

Block of 8 M7020Rs, Block 0 (Devices 0-7)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

Block of 8 M7020Rs, Block 1 (Devices 8-15)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

Block of 8 M7020Rs, Block 2 (Devices 16-23)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

DQ[67:0]

Block of 7 M7020Rs, Block 3 (Devices 24-30)

BHO[2]

CMD[8:0], CMDV

BHO[1]

BHO[0]

AI05671

133/150

M7020R

Figure 98. SRAM READ Through Device 0 in a Bank of 31 Devices (Device 0 Timing)

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

CMD[1:0]

CMD[8:2]

READ

00

A

B

Address

DQ driven by the selected M7040

DQ

OE_L

WE_L

CE_L

ALE_L

z

1

z

0

z

0

z

Address

z

SADR[21:0]

z

1

ACK

0

z

SSV

SSF

HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0

AI06322

134/150

M7020R

Figure 99. SRAM READ Through Device 0 in a Bank of 31 Devices (Device 30 Timing)

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

CMD[1:0]

CMD[8:2]

READ

00

A

B

Address

DQ

OE_L

WE_L

CE_L

ALE_L

0

z

1

z

SADR[21:0]

z

ACK

SSV

SSF

0

HLAT = 010, TLSZ = 01, LRAM = 1, LDEV = 1

AI06323

135/150

M7020R

SRAM WRITE with a Table of One Device

SRAM WRITE enables WRITE access to the off-

chip SRAM that contains associative data. The la-

tency from the second cycle of the WRITE Instruc-

tion to the address appearing on the SRAM Bus is

the same as the latency of the SEARCH Instruc-

tion, and will depend on the TLSZ value parameter

programmed in the device configuration register.

The following explains the SRAM WRITE opera-

tion accomplished with a table of only one device

of the following parameters: TLSZ = 00, HLAT =

000, LRAM = 1, and LDEV = 1. Figure 100, page

137 shows the timing diagram.

Note: CMD[2] must be set to '0' for SRAM

WRITE because Burst WRITEs into the SRAM

are not supported.

– Cycle 1B: The host ASIC continues to apply the

WRITE Instruction on CMD[1:0], using

CMDV = 1. The DQ Bus supplies the address

with DQ[20:19] set to '10' to select the SRAM

address.

Note: CMD[2] must be set to '0' for SRAM

WRITE because Burst WRITEs into the SRAM

are not supported.

– Cycle 2: The host ASIC continues to drive

DQ[67:0]. The data in this cycle is not used by

the M7020R device.

– Cycle 3: The host ASIC continues to drive

DQ[67:0]. The data in this cycle is not used by

the M7020R device.

At the end of Cycle 3, a new command can begin.

The WRITE is a pipelined operation. The WRITE

Cycle appears at the SRAM Bus, however, with

the same latency as that of a SEARCH Instruction,

as measured from the second cycle of the WRITE

command.

For the following description the selected device

refers to the only device in the table as it is the only

device that will be accessed.

– Cycle 1A: The host ASIC applies the WRITE In-

struction on CMD[1:0] using CMDV = 1. The DQ

Bus supplies the address with DQ[20:19] set to

'10' to select the SRAM address. The host ASIC

selects the device for which the ID[4:0] matches

the DQ[25:21] lines. The host ASIC also sup-

plies SADR[21:20] on CMD[8:7] in this cycle.

136/150

M7020R

Figure 100. SRAM WRITE Access for One Device

Cycle 1 Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 6

CLK2X

PHS_L

CMDV

WRITE

CMD[1:0]

A

B

CMD[8:2]

DQ

Address

X

1

0

1

OE_L

0

WE_L

CE_L

1

ALE_L

SADR

Address

z

ACK

SSV

0

SSF

HLAT = 000, TLSZ = 00, LRAM = 1, LDEV = 1

AI06324

137/150

M7020R

SRAM WRITE with a Table of Up to Eight Devices

The following explains the SRAM WRITE opera-

tion done through a table(s) of up to eight devices

with the following parameters (TLSZ = 01). The di-

agram of such a table is shown in Figure 101,

page 139.

– Cycle 1B: The host ASIC continues to apply the

WRITE Instruction on CMD[1:0] using CMDV =

1. The DQ Bus supplies the address with

DQ[20:19] set to '10' to select the SRAM ad-

dress.

The following assumes that SRAM access is done

through M7020R Device 0. Figure 102, page 140

and Figure 103, page 141 show the timing dia-

gram for Device 0 and Device 7, respectively.

– Cycle 1A: The host ASIC applies the WRITE In-

struction on CMD[1:0] using CMDV = 1. The DQ

Bus supplies the address with DQ[20:19] set to

'10' to select the SRAM address. The host ASIC

selects the device for which the ID[4:0] matches

the DQ[25:21] lines. The host ASIC also sup-

plies SADR[23:21] on CMD[8:6] in this cycle.

Note: CMD[2] must be set to '0' for SRAM

WRITE because Burst WRITEs into the SRAM

are not supported.

– Cycle 2: The host ASIC continues to drive

DQ[67:0]. The data in this cycle is not used by

the M7020R device.

– Cycle 3: The host ASIC continues to drive

DQ[67:0]. The data in this cycle is not used by

the M7020R device.

At the end of cycle 3, a new command can begin.

The WRITE is a pipelined operation. The WRITE

Cycle appears at the SRAM Bus, however, with

the same latency as that of a SEARCH Instruction,

as measured from the second cycle of the WRITE

command.

Note: CMD[2] must be set to '0' for SRAM

WRITE because Burst WRITEs into the SRAM

are not supported.

138/150

M7020R

Figure 101. Table with Eight Devices

SRAM

BHI[2:0]

6

5

4

3

2

1

0

LHI

M7020R #0

M7020R #1

LHO[1]

LHO[0]

SSF, SSV

BHI[2:0]

6

5

4

3

LHI

2

1

0

LHO[1]

LHO[0]

DQ[67:0]

CMDV

BHI[2:0]

6

5

4

3

LHI

2

1

CMD[8:0]

M7020R #2

M7020R #3

M7020R #4

M7020R #5

M7020R #6

M7020R #7

LHO[1]

LHO[0]

BHI[2:0]

3

2

1

LHI

LHO[1]

LHO[0]

3

LHI

2

1

0

LHO[0]

3

2

1

0

6

5

LHI

LHO[0]

4

LHI

3

2

LHI

6

5

LHI

LHO[0]

3

2

LHI

1

0

6

5

LHI

4

BHO[0]

BHO[1]

BHO[2]

BHI[2:0]

BHO[0]

BHO[1]

BHO[2]

LHO[1]

LHO[0]

AI05666

139/150

M7020R

Figure 102. SRAM WRITE Through Device 0 in a Block of Eight Devices

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

CMD[1:0]

CMD[8:2]

WRITE

01

A

B

Address

X

DQ

OE_L

WE_L

CE_L

ALE_L

z

0

z

0

z

Address

z

SADR[21:0]

z

ACK

SSV

SSF

z

HLAT = XXX, TLSZ = 01, LRAM = 0, LDEV = 0

AI06325

140/150

M7020R

Figure 103. SRAM WRITE Timing for Device 7 in a Block of Eight Devices

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

CMD[1:0]

CMD[8:2]

WRITE

01

A

B

Address

DQ

X

0

OE_L

WE_L

CE_L

1

z

1

ALE_L

z

SADR[21:0]

z

ACK

SSV

SSF

0

HLAT = XXX, TLSZ = 01, LRAM = 1, LDEV = 1

AI06326

141/150

M7020R

SRAM WRITE with Table(s) of Up to 31 Devices

The following explains the SRAM WRITE opera-

tion done through a table(s) of up to 31 devices

with the following parameters (TLSZ = 10). The di-

agram of such table(s) is shown in Figure 104,

page 143. The following assumes that SRAM ac-

cess is done through M7020R Device 0 – Device

0 is the selected device. Figure 105, page 144 and

Figure 106, page 145 show the timing diagram for

Device 0 and Device 30, respectively.

– Cycle 1A: The host ASIC applies the WRITE In-

struction on CMD[1:0] using CMDV = 1. The DQ

Bus supplies the address with DQ[20:19] set to

'10' to select the SRAM address. The host ASIC

selects the device for which the ID[4:0] matches

the DQ[25:21] lines. The host ASIC also sup-

plies SADR[21:20] on CMD[8:7] in this cycle.

– Cycle 1B: The host ASIC continues to apply the

WRITE Instruction on CMD[1:0] using CMDV =

1. The DQ Bus supplies the address with

DQ[20:19] set to '10' to select the SRAM ad-

dress.

Note: CMD[2] must be set to '0' for SRAM

WRITE because Burst WRITEs into the SRAM

are not supported.

– Cycle 2: The host ASIC continues to drive

DQ[67:0]. The data in this cycle is not used by

the M7020R device.

– Cycle 3: The host ASIC continues to drive

DQ[67:0]. The data in this cycle is not used by

the M7020R device.

At the end of Cycle 3, a new command can begin.

The WRITE is a pipelined operation. The WRITE

Cycle appears at the SRAM Bus, however, with

the same latency as that of a SEARCH Instruction,

as measured from the second cycle of the WRITE

command

Note: CMD[2] must be set to '0' for SRAM

WRITE because Burst WRITEs into the SRAM

are not supported.

142/150

M7020R

Figure 104. Table of 31 Devices (Four Blocks)

BHI[2]

BHI[1]

BHI[0]

GND

SRAM

SSF, SSV

Block of 8 M7020Rs, Block 0 (Devices 0-7)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

Block of 8 M7020Rs, Block 1 (Devices 8-15)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

Block of 8 M7020Rs, Block 2 (Devices 16-23)

BHO[2]

BHO[1]

BHO[0]

BHI[2]

BHI[1]

BHI[0]

DQ[67:0]

Block of 7 M7020Rs, Block 3 (Devices 24-30)

BHO[2]

CMD[8:0], CMDV

BHO[1]

BHO[0]

AI05671

143/150

M7020R

Figure 105. SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 0 Timing)

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

CMD[1:0]

CMD[8:2]

WRITE

01

A

B

Address

DQ

OE_L

WE_L

CE_L

ALE_L

X

z

0

z

0

Address

z

SADR[21:0]

ACK

SSV

SSF

z

HLAT = XXX, TLSZ = 10, LRAM = 0, LDEV = 0

AI06327

144/150

M7020R

Figure 106. SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 30 Timing)

Cycle 2

Cycle 1

Cycle 4

Cycle 3

Cycle 6

Cycle 5

Cycle 8

Cycle 10

Cycle 7

Cycle 9

CLK2X

PHS_L

CMDV

CMD[1:0]

CMD[8:2]

WRITE

01

A

B

Address

DQ

X

0

OE_L

WE_L

CE_L

1

z

1

ALE_L

z

SADR[21:0]

z

ACK

SSV

SSF

0

HLAT = XXX, TLSZ = 10, LRAM = 1, LDEV = 1

AI06328

145/150

M7020R

JTAG (1149.1) TESTING

The M7020R supports the Test Access Port and

Boundary Scan Architecture as specified in the

IEEE JTAG standard 1149.1. The pin interface to

the chip consists of five signals with the standard

definitions: TCK, TMS, TDI, TDO, and TRST_L.

Table 51 describes the operations that the test ac-

cess port controller supports and Table 52 de-

scribes the TAP Device ID Register.

Note: To disable JTAG functionality, connect the

TCK, TMS, and TDI pins to Ground, and TRST_L

to V

.

DD

Table 51. Supported Operations

Instruction

Type

Description

Sample/Preload. Loads the values of signals going to and from IO

pins into the boundary scan shift register to provide a snapshot of

the normal functional operation.

SAMPLE/PRELOAD

Mandatory

External Test. Uses boundary scan values shifted in from TAP to

test connectivity external to the device.

EXTEST

INTEST

Mandatory

Optional

Internal Test. Allows slow-speed, functional testing of the device

using the boundary scan register to provide the I/O values.

Table 52. TAP Device ID Register

Field

Range

Initial Value

Description

Revision Number. This is the current device revision number.

Numbers start from one and increment by one for each revision of

the device.

Revision

[31:28]

0001

Part #

MFID

LSB

[27:12]

[11:1]

[0]

0000 0000 0000 0001 This is the part number for this device.

Manufacturer ID. This field is the same as the manufacturer ID

000_1101_1100

1

used in the TAP controller.

Least Significant Bit

146/150

M7020R

PART NUMBERING

Table 53. Ordering Information Scheme

Example:

M70

20

R

–083

ZA

1

T

Device Type

M70 Search Engine

Density

20 = 2Mb (32K x 68-bit Table Entries)

Operating Supply Voltage

R = V = 1.8V

DD

Speed

–083 = 83 Million Searches per Second

–066 = 66 Million Searches per Second

–050 = 50 Million Searches per Second

Package

(1)

PBGA = 272-ball count, 27mm x 27mm , 1.27mm ball pitch

Temperature Range

1 = 0 to 70°C

Shipping Option

Tape & Reel Packing = T

Note: 1. Where “Z” is the symbol for BGA packages and “A” denotes 1.27mm ball pitch

For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

147/150

M7020R

PACKAGE MECHANICAL INFORMATION

Figure 107. PBGA-Z00 – 272-ball Plastic Ball Grid Array Package Outline

0.56 REF.

A1

1.17 REF.

D2

19 17 15 13 11

20 18 16 14 12 10

9

7

5

3

1

8

6

4

2

A

B

C

D

E

F

30˚ TYP.

e

PIN #1

G

H

J

K

E2

E

L

M

N

P

R

T

U

V

W

Y

E1

A2

b

D1

e

B

4.00*45˚ (4x)

A

C

ddd C

D

0.220 (3x)

S

0.300 C A

B

0.100 C b (272x)

PBGA-Z00

Note: Drawing is not to scale.

Table 54. PBGA-Z00 – 272-ball Plastic Ball Grid Array Package Mechanical Data

mm

Min

inches

Min

Symb

Typ

27.00

0.60

Max

Typ

Max

(4)

(1)

26.80

1.102

0.024

1.094

A

27.20

0.70

1.110

0.029

0.078

1.110

0.037

1.110

(2,3)

0.50

1.63

0.020

0.067

1.094

0.024

1.094

A1

A2

1.90

(4)

27.00

0.75

26.80

0.60

27.20

0.90

1.102

0.031

1.102

0.985

0.980

0.052

1.102

0.985

0.980

B

b

D

27.00

24.13

24.00

1.27

26.80

27.20

D1

D2

e

E

27.00

24.13

24.00

26.80

272

27.20

1.094

272

1.110

E1

E2

n

ddd

eee

0.20

0.30

0.008

0.012

Note: 1. Maximum mounted height is 2.45mm based on a 0.65mm ball pad diameter. Solder paste is 0.15mm thickness and 0.65mm in di-

ameter.

2. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink, or metallized markings, or other feature

of package body or integral heatslug.

3. A distinguished feature is allowable on the bottom surface of the package to identify the terminal A1 corner.

4. Exact shape of each corner is optional.

148/150

M7020R

REVISION HISTORY

Table 55. Document Revision History

Date

Revision Details

February 2001 First Issue

03/23/01

04/02/01

07/23/01

Document re-organization, change in Power Distribution text

Updated mechanical drawing and table (Figure 107, Table 54)

Routine maintenance (based on recent data sheet review findings)

Change references to “Lara” and “ST” to Cypress in “Description” section; added 83MHz speed

grade to document; values, references, and footnotes changed (Table 3, 4, 5, 6, 7, 54); labels

changed (Figures 5, 8); basic formatting changes based on recent reviews

10/02/01

11/14/01

Rework document (add graphics, change text) after Cypress purchase

149/150

M7020R

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -

Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

www.st.com

150/150


型号：	M7020R
厂家：	ST
描述：	32K x 68-bit Entry NETWORK SEARCH ENGINE 32K X 68位输入网络搜索引擎
文件：	总150页 (文件大小：991K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M7020R [STMICROELECTRONICS]

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