M68AF031AL70N1F [STMICROELECTRONICS]
256 Kbit (32K x 8) 5.0V Asynchronous SRAM; 256千位（ 32K ×8 ） 5.0V异步SRAM
| 型号： | M68AF031AL70N1F |
| 厂家： | 
ST |
| 描述： | 256 Kbit (32K x 8) 5.0V Asynchronous SRAM |
| 文件： | 总22页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M68AF031A
256 Kbit (32K x 8) 5.0V Asynchronous SRAM
FEATURES SUMMARY
■
■
■
■
■
■
■
■
SUPPLY VOLTAGE: 4.5 to 5.5V
Figure 1. Packages
32K x 8 bits SRAM with OUTPUT ENABLE
EQUAL CYCLE and ACCESS TIME: 55, 70ns
LOW STANDBY CURRENT
LOW VCC DATA RETENTION: 2V
TRI-STATE COMMON I/O
AUTOMATIC POWER DOWN
PACKAGES
SO28 (MS)
–
SO28, PDIP28, TSOP28 Standard and
Reverse Pinout.
–
TSOP28 Standard Available in Lead-Free
Version
28
1
PDIP28 (B)
TSOP28 (N)
8 x 13.4mm
TSOP28 (NS)
8 x 13.4 mm (Reverse)
November 2004
1/22
M68AF031A
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. TSOP Connections (Normal). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. TSOP Connections (Reverse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. DC Characteristics (M68AF031A-55 and M68AF031A-70). . . . . . . . . . . . . . . . . . . . . . . . 9
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10.Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11.Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . 11
Figure 12.Chip Enable Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 14.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 15.Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16.SO28 - 28 lead Plastic Small Outline, 300 mils body width, Package Outline . . . . . . . . 16
Table 10. SO28 - 28 lead Plastic Small Outline, 300 mils body width, Package Mechanical Data . 16
Figure 17.PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline . . . . . . . . . . . . . . . . . . . . 17
Table 11. PDIP28 - 28 pin Plastic DIP, n600 mils width, Package Mechanical Data . . . . . . . . . . . 17
Figure 18.TSOP28 - 28 lead Normal Pinout Plastic Small Outline, Package Outline . . . . . . . . . . . 18
Table 12. TSOP28 - 28 lead Normal Pinout Plastic Small Outline, Package Mechanical Data . . . 18
2/22
M68AF031A
Figure 19.TSOP28 - 28 lead Reverse Pinout Plastic Small Outline, Package Outline . . . . . . . . . . 19
Table 13. TSOP28 - 28 lead Reverse Pinout Plastic Small Outline, Package Mechanical Data. . . 19
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
M68AF031A
SUMMARY DESCRIPTION
The M68AF031A is a 256 Kbit (262,144 bit) CMOS
SRAM, organized as 32,768 bytes. The device
features fully static operation requiring no external
clocks or timing strobes, with equal address ac-
cess and cycle times. It requires a single 4.5 to
5.5V supply. This device has an automatic power-
down feature, reducing the power consumption by
over 99% when deselected.
Line) and TSOP28 (28-lead Thin Small Outline,
Standard and Reverse Pinout) packages.
In addition to the standard version, the TSOP28
Standard package is also available in Lead-free
version (standard and Tape & Reel packing), in
compliance with JEDEC Std J-STD-020B, the ST
ECOPACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive. It
is also compliant with Lead-free soldering pro-
cesses.
The M68AF031A is available in SO28 (28-lead
Small Outline), PDIP28 (28-pin Plastic Dual-In-
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A14
Address Inputs
Data Input/Output
Chip Enable
DQ0-DQ7
V
CC
E
G
W
Output Enable
Write Enable
16
8
A0-A14
DQ0-DQ7
V
Supply Voltage
Ground
CC
W
E
M68AF031A
V
SS
NC
Not Connected Internally
G
V
SS
AI05920C
4/22
M68AF031A
Figure 3. SO Connections
Figure 5. TSOP Connections (Normal)
A5
A6
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
G
A1
A2
A3
A4
W
22
21
A0
2
E
A7
3
A4
DQ7
DQ6
DQ5
DQ4
DQ3
A8
4
A3
A9
5
A2
A10
A11
A12
A13
A14
DQ0
DQ1
DQ2
6
A1
M68AF031A
(Normal)
7
G
V
28
1
15
14
CC
A5
M68AF031A
8
A0
V
SS
9
E
A6
A7
A8
A9
DQ2
DQ1
DQ0
A14
A13
A12
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
A10
A11
V
SS
7
8
AI07200C
AI05921C
Figure 4. DIP Connections
Figure 6. TSOP Connections (Reverse)
A5
A6
1
2
3
4
5
6
7
8
9
28
27
V
CC
W
A11
A10
A9
7
8
A12
A13
A14
DQ0
DQ1
DQ2
A7
26 A4
25 A3
24 A2
23 A1
A8
A8
A9
A7
A10
A11
A12
A13
A6
M68AF031A
(Reverse)
22
21 A0
20
G
A5
1
14
15
V
SS
M68AF031A
V
28
DQ3
DQ4
DQ5
DQ6
DQ7
E
CC
W
E
A14 10
DQ0 11
DQ1 12
DQ2 13
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
A4
A3
A2
A1
G
V
14
SS
22
21
A0
AI05922C
AI07201C
5/22
M68AF031A
Figure 7. Block Diagram
A14
ROW
DECODER
MEMORY
ARRAY
A7
DQ7
I/O CIRCUITS
COLUMN
DECODER
DQ0
A0
A6
E
W
G
AI05919
6/22
M68AF031A
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for periods greater than 1 sec periods may
affect device reliability. Refer also to the STMicro-
electronics SURE Program and other relevant
quality documents.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
mA
W
(1)
Output Current
20
I
O
P
Power Dissipation
1
–55 to 125
(1)
D
T
A
Ambient Operating Temperature
Lead Temperature during Soldering
Storage Temperature
°C
°C
°C
V
T
LEAD
T
–65 to 150
–0.5 to 6.5
STG
V
Supply Voltage
CC
(2)
–0.5 to V +0.5
Input or Output Voltage
V
V
IO
CC
Note: 1. One output at a time, not to exceed 1 second duration.
2. Up to a maximum operating V of 6.0V only.
CC
®
3. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
7/22
M68AF031A
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter
M68AF031A
V
Supply Voltage
4.5 to 5.5V
CC
Range 1
Range 6
0 to 70°C
–40 to 85°C
100pF
Ambient Operating Temperature
Load Capacitance (C )
L
Output Circuit Protection Resistance (R )
3.0kΩ
1
Load Resistance (R )
3.1kΩ
2
V
/2
Input and Output Timing Ref. Voltages
Input Rise and Fall Times
CC
1ns/V
0 to V
Input Pulse Voltages
CC
V
= 0.3V ; V = 0.7V
CC RH CC
Output Transition Timing Ref. Voltages
RL
Figure 8. AC Measurement I/O Waveform
Figure 9. AC Measurement Load Circuit
V
CC
I/O Timing Reference Voltage
R
1
V
CC
V
/2
CC
DEVICE
UNDER
TEST
OUT
0V
C
L
Output Timing Reference Voltage
R
2
V
CC
0.7V
0.3V
CC
CC
0V
AI05831
C
includes probe capacitance
L
AI05932
8/22
M68AF031A
Table 4. Capacitance
Symbol
Test
Condition
(1,2)
Min
Max
Unit
Parameter
C
V
= 0V
= 0V
Input Capacitance on all pins (except DQ)
Output Capacitance
6
8
pF
pF
IN
IN
C
V
OUT
OUT
Note: 1. Sampled only, not 100% tested.
2. At T = 25°C, f = 1 MHz, V = 5.0V.
A
CC
Table 5. DC Characteristics (M68AF031A-55 and M68AF031A-70)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
V
= 5.5V, f = 1/t
,
AVAV
CC
(1,2)
Operating Supply Current
50
mA
I
CC1
I
= 0mA
OUT
V
= 5.5V, f = 1MHz,
CC
(3)
Operating Supply Current
5
mA
I
CC2
I
= 0mA
OUT
Range 1
Range 6
0.1
0.1
5
10
1
µA
µA
µA
V
= 5.5V, f = 0,
CC
I
Standby Supply Current CMOS
SB
E ≥ V –0.2V
CC
I
0V ≤ V ≤ V
IN CC
Input Leakage Current
Output Leakage Current
–1
–1
LI
(4)
0V ≤ V
≤ V
CC
1
µA
I
OUT
LO
V
V
CC
+ 0.3
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
2.2
–0.3
2.4
V
V
V
V
IH
V
0.8
0.4
IL
V
I
= –1.0mA
= 2.1mA
OH
OH
V
OL
I
OL
Note: 1. Average AC current, cycling at t
minimum.
AVAV
2. E = V , V = V OR V .
IL
IN
IL
IH
3. E ≤ 0.2V, V ≤ 0.2V OR V ≥ V –0.2V.
IN
IN
CC
4. Output disabled.
9/22
M68AF031A
OPERATION
The M68AF031A has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E = High).
An Output Enable (G) signal provides a high
speed tri-state control, allowing fast read/write cy-
cles to be achieved with the common I/O data bus.
Operational modes are determined by device con-
trol inputs W and E, as summarized in the Operat-
ing Modes table (see Table 6., Operating Modes).
Table 6. Operating Modes
Operation
E
W
G
DQ0-DQ7
Hi-Z
Power
Standby (I
Active (I
V
)
Deselected
Read
X
X
IH
SB
V
IL
V
IL
V
IL
V
IH
V
)
Data Output
Data Input
Hi-Z
IL
CC
V
V
Active (I
Active (I
)
Write
X
IL
CC
V
)
Output Disabled
IH
IH
CC
Note: 1. X = V or V .
IH
IL
Read Mode
The M68AF031A is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and Chip Enable (E) is asserted. This pro-
vides access to data of the 262,144 locations in
the static memory array, specified by the 15 ad-
dress inputs. Valid data will be available at the
eight output pins within tAVQV after the last stable
address, providing G is Low and E is Low. If Chip
Enable or Output Enable access times are not
met, data access will be measured from the limit-
ing parameter (tELQV or tGLQV) rather than the ad-
dress. Data out may be indeterminate at tELQX and
tGLQX but data lines will always be valid at tAVQV
.
Figure 10. Address Controlled, Read Mode AC Waveforms
tAVAV
A0-A14
VALID
tAVQV
tAXQX
DQ0-DQ7
DATA VALID
AI05939
Note: E = Low, G = Low, W = High.
10/22
M68AF031A
Figure 11. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.
tAVAV
A0-A14
VALID
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI05940
Note: Write Enable (W) = High.
Figure 12. Chip Enable Controlled, Standby Mode AC Waveforms
E
tPU
tPD
I
CC
50%
I
SB
AI05956
11/22
M68AF031A
Table 7. Read and Standby Mode AC Characteristics
M68AF031A
Symbol
Parameter
55
70
Unit
Min.
Max.
Min.
Max.
t
Read Cycle Time
55
70
ns
ns
ns
AVAV
t
Address Valid to Output Valid
Data hold from address change
55
70
AVQV
(1)
5
5
5
t
AXQX
(2,3)
Chip Enable High to Output Hi-Z
Chip Enable Low to Output Valid
Chip Enable Low to Output Lo-Z
20
55
25
70
ns
ns
ns
t
t
EHQZ
t
ELQV
(1)
5
t
ELQX
(2,3)
Output Enable High to Output Hi-Z
Output Enable Low to Output Valid
Output Enable Low to Output Transition
20
25
25
35
ns
ns
ns
GHQZ
t
GLQV
(1)
5
0
5
0
t
GLQX
(4)
Chip Enable High to Power Down
Chip Enable Low to Power Up
55
70
ns
ns
t
t
PD
(4)
PU
Note: 1. Test conditions assume transition timing reference level = 0.3V or 0.7V
.
CC
CC
2. At any given temperature and voltage condition, t
is less than t
and t
is less than t
for any given device.
GHQZ
GLQX
EHQZ
ELQX
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
4. Tested initially and after any design or process changes that may affect these parameters.
12/22
M68AF031A
Write Mode
The M68AF031A is in the Write mode whenever
the W and E are Low. Either the Chip Enable input
(E) or the Write Enable input (W) must be de-
asserted during Address transitions for
subsequent write cycles. When E (W) is Low, write
cycle begins on the W (E)'s falling edge.
Therefore, address setup time is referenced to
Write Enable or Chip Enable as tAVWL and tAVEL
respectively, and is determined by the latter
occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E or W.
If the Output is enabled (E = Low, G = Low), then
W will return the outputs to high impedance within
tWLQZ of its falling edge. Care must be taken to
avoid bus contention in this type of operation. Data
input must be valid for tDVWH before the rising
edge of Write Enable, or for tDVEH before the rising
edge of E, whichever occurs first, and remain valid
for tWHDX and tEHDX respectively.
Figure 13. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A14
VALID
tAVWH
tELWH
tWHAX
E
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA (1)
DATA INPUT
DATA (1)
tDVWH
AI05941
Note: 1. During this period DQ0-DQ7 are in output state and input signals should not be applied.
Figure 14. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A14
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tWLEH
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI05942
13/22
M68AF031A
Table 8. Write Mode AC Characteristics
M68AF031A
Symbol
Parameter
55
70
Unit
Min.
55
45
0
Max.
Min.
70
60
0
Max.
t
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Chip Enable High
Address valid to Chip Enable Low
Address Valid to Write Enable High
Address Valid to Write Enable Low
Input Valid to Chip Enable High
AVEH
t
AVEL
t
45
0
60
0
AVWH
t
AVWL
t
25
25
0
30
30
0
DVEH
t
Input Valid to Write Enable High
DVWH
t
Chip Enable High to Address Transition
Chip enable High to Input Transition
Chip Enable Low to Chip Enable High
Chip Enable Low to Write Enable High
Write Enable High to Address Transition
Write Enable High to Input Transition
Write Enable High to Output Transition
EHAX
t
0
0
EHDX
t
45
45
0
60
60
0
ELEH
t
ELWH
t
WHAX
t
0
0
WHDX
(1)
5
5
t
WHQX
t
Write Enable Low to Chip Enable High
Write Enable Low to Output Hi-Z
45
60
ns
ns
ns
WLEH
(1,2)
20
25
t
WLQZ
t
Write Enable Low to Write Enable High
45
50
WLWH
Note: 1. At any given temperature and voltage condition, t
is less than t
for any given device.
WHQX
WLQZ
2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
Figure 15. Low VCC Data Retention AC Waveforms
DATA RETENTION MODE
5.5V
V
4.5V
CC
V
> 2.0V
DR
tCDR
tR
E ≥ V
– 0.2V
DR
E
AI05925
14/22
M68AF031A
Table 9. Low VCC Data Retention Characteristics
Symbol
Parameter
Test Condition
= 2.0V,
Min
Typ
Max
Unit
V
CC
(1)
Supply Current (Data Retention)
6
µA
I
CCDR
(3)
E ≥ V –0.2V, f = 0
CC
Chip Deselected to Data Retention
Time
(1,2)
0
ns
t
CDR
(2)
t
Operation Recovery Time
ns
V
t
AVAV
R
(1)
E ≥ V –0.2V, f = 0
Supply Voltage (Data Retention)
2.0
V
CC
DR
Note: 1. All other Inputs at V ≥ V –0.2V or V ≤ 0.2V.
IH
CC
IL
2. Tested initially and after any design or process changes that may affect these parameters. t
is Read cycle time.
AVAV
3. No input may exceed V +0.2V.
CC
15/22
M68AF031A
PACKAGE MECHANICAL
Figure 16. SO28 - 28 lead Plastic Small Outline, 300 mils body width, Package Outline
D
14
1
h x 45˚
C
E
H
15
28
A
ddd
A1
B
e
A1
α
L
SO-E
Note: Drawing is not to scale.
Table 10. SO28 - 28 lead Plastic Small Outline, 300 mils body width, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
2.79
0.35
2.43
0.50
0.30
18.41
0.10
7.62
–
Typ
Max
0.110
0.014
0.096
0.020
0.012
0.725
0.004
0.300
–
A
A1
A2
B
2.38
0.094
0.002
0.090
0.014
0.008
0.710
0.05
2.28
0.35
C
0.20
D
18.03
ddd
E
7.39
–
0.291
–
e
1.27
0.050
H
11.68
0.79
0°
12.19
1.27
8°
0.460
0.031
0°
0.480
0.050
8°
L
α
N
28
28
16/22
M68AF031A
Figure 17. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
Note: Drawing is not to scale.
Table 11. PDIP28 - 28 pin Plastic DIP, n600 mils width, Package Mechanical Data
millimeters
inches
Min
–
Symbol
Typ
Min
–
Max
5.08
–
Typ
Max
0.200
–
A
A1
A2
B
0.38
3.56
0.38
–
0.015
0.140
0.015
–
4.06
0.51
–
0.160
0.020
–
B1
C
1.52
0.060
0.20
36.83
–
0.30
37.34
–
0.008
1.450
–
0.012
1.470
–
D
D2
E
33.02
15.24
1.300
0.600
–
–
–
–
E1
e1
eA
eB
L
13.59
–
13.84
–
0.535
–
0.545
–
2.54
0.100
0.590
14.99
–
–
–
–
15.24
3.18
1.78
0°
17.78
3.43
2.08
10°
0.600
0.125
0.070
0°
0.700
0.135
0.082
10°
S
α
N
28
28
17/22
M68AF031A
Figure 18. TSOP28 - 28 lead Normal Pinout Plastic Small Outline, Package Outline
A2
22
21
e
28
1
E
B
7
8
D1
D
A
CP
DIE
C
TSOP-C
Note: Drawing is not to scale.
A1
α
L
Table 12. TSOP28 - 28 lead Normal Pinout Plastic Small Outline, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
Typ
Max
A
A1
A2
B
0.0472
0.0059
0.0413
0.050
0.910
0.0020
0.0358
0.220
0.0087
C
0.100
0.210
0.0039
0.0083
CP
D
0.100
0.0039
13.400
11.800
8.000
–
–
0.5276
0.4646
0.3150
0.0217
–
–
D1
E
–
–
–
–
–
–
–
–
–
–
e
0.550
–
0.0118
0
–
0.0276
5
L
0.300
0
0.700
5
α
N
28
28
18/22
M68AF031A
Figure 19. TSOP28 - 28 lead Reverse Pinout Plastic Small Outline, Package Outline
A2
7
8
e
1
28
E
B
22
21
D1
D
A
CP
DIE
C
TSOP-H
Note: Drawing is not to scale.
A1
α
L
Table 13. TSOP28 - 28 lead Reverse Pinout Plastic Small Outline, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
Typ
Max
A
A1
A2
B
0.0472
0.0059
0.0413
0.050
0.910
0.0020
0.0358
0.220
0.0087
C
0.100
0.210
0.0039
0.0083
CP
D
0.100
0.0039
13.400
11.800
8.000
–
–
0.5276
0.4646
0.3150
0.0217
–
–
D1
E
–
–
–
–
–
–
–
–
–
–
e
0.550
–
0.0118
0
–
0.0276
5
L
0.300
0
0.700
5
α
N
28
28
19/22
M68AF031A
PART NUMBERING
Table 14. Ordering Information Scheme
Example:
M68AF031
A
L
70 MS
6
T
Device Type
M68
Mode
A = Asynchronous
Operating Voltage
F = 4.5 to 5.5V
Array Organization
031 = 256 Kbit (32K x8)
Option 1
A = 1 Chip Enable
Option 2
L = L-Die
M = M-Die
Speed Class
55 = 55ns
70 = 70ns
Package
MS = SO28
B = PDIP28
N = TSOP28 8x13.4mm (Standard Pinout)
NS = TSOP28 8x13.4mm (Reverse Pinout)
Operative Temperature
1 = 0 to 70°C
6 = –40 to 85 °C
Shipping
T = Tape & Reel Packing
E = Lead-free and RoHS Package, Standard Packing
F = Lead-free and RoHS Package, Tape & Reel Packing
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
20/22
M68AF031A
REVISION HISTORY
Table 15. Document Revision History
Date
Version
-01
Revision Details
January 2002
07-Feb-2002
First Issue
clarified
I
-02
SB
TSOP28 Package removed
08-Feb-2002
-03
AC Measurement Load Circuit changed (Figure 9)
Operating and AC Measurement Conditions clarified (Table 3)
06-Mar-2002
19-Apr-2002
-04
-05
Document status changed to Data Sheet
Absolute Maximum current value added (Table 2)
Operating and AC Measurement Conditions clarified (Table 3)
Absolute Maximum Ratings Table clarified (Table 2)
Operating and AC Measurement Conditions Table clarified (Table 3)
DC Characteristics Table clarified (Table 5)
26-Apr-2002
-06
Write Mode AC Characteristics Table clarified (Table 8)
Low V Data Retention AC Waveforms clarified (Figure 15)
CC
Low V Data Retention Characteristics Table clarified ( Table 9)
CC
DC Characteristics Table clarified (Table 5)
20-May-2002
29-May-2002
-07
-08
Low V Data Retention Characteristics Table clarified (Table 9)
CC
TSOP28 8x13.4mm Standard and Reverse pinout added (Figure 1, 5, 6, Table 12)
Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot
(revision version 08 equals 8.0).
02-Oct-2002
8.1
New part number added.
09-Oct-2002
23-Apr-2003
27-May-2004
8.2
8.3
9.0
Datasheet number simplified.
55ns speed-class added
Package outline and package mechanical data added for TSOP28 Reverse package.
TSOP28 Standard Lead-free version added in FEATURES SUMMARY, SUMMARY
DESCRIPTION. T
parameter added in Table 2., Absolute Maximum Ratings.
05-Nov-2004
15-Nov-2004
10.0
11.0
LEAD
Standard Lead-free option added in Table 14., Ordering Information Scheme.
TSOP28 Lead-free Tape & Reel version added in FEATURES SUMMARY,
SUMMARY DESCRIPTION.
Lead-Free Tape & Reel option added in Table 14., Ordering Information Scheme.
21/22
M68AF031A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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22/22
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