M58LW128A_技术文档

M58LW128A

M58LW128B

128 Mbit (8Mb x16 or 4Mb x32, Uniform Block, Burst)

3V Supply Flash Memories

PRELIMINARY DATA

FEATURES SUMMARY

■ WIDE DATA BUS for HIGH BANDWIDTH

– M58LW128A: x16

Figure 1. Packages

– M58LW128B: x16/x32

■ SUPPLY VOLTAGE

– V = 2.7 to 3.6V core supply voltage for Pro-

DD

gram, Erase and Read operations

TSOP56 (N)

14 x 20mm

– V

= 1.8 to V for I/O Buffers

DD

DDQ

■ SYNCHRONOUS/ASYNCHRONOUS READ

– Synchronous Burst read

– Pipelined Synchronous Burst Read

– Asynchronous Random Read

TBGA

– Asynchronous Address Latch Controlled

Read

TBGA64 (ZA)

10 x 13mm

– Page Read

■ ACCESS TIME

– Synchronous Burst Read up to 66MHz

– Asynchronous Page Mode Read 150/25ns

– Random Read 150ns

TBGA

■ PROGRAMMING TIME

TBGA80 (ZA)

10 x 13mm

– 16 Word or 8 Double-Word Write Buffer

– 12µs Word effective programming time

■ 128 UNIFORM 64 KWord MEMORY BLOCKS

■ BLOCK PROTECTION/ UNPROTECTION

■ PROGRAM and ERASE SUSPEND

■ OTP SECURITY AREA

■ COMMON FLASH INTERFACE

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h

– Device Code M58LW128A: 8818h

– Device Code M58LW128B: 8819h

February 2003

1/65

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M58LW128A, M58LW128B

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. TSOP56 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. TBGA64 Connections for M58LW128A (Top view through package) . . . . . . . . . . . . . . . 9

Figure 5. TBGA80 Connections for M58LW128B (Top view through package) . . . . . . . . . . . . . . 10

Figure 6. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address Inputs (A1-A23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Inputs/Outputs (DQ0-DQ31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Burst Address Advance (B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Word Organization (WORD).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Ready/Busy (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Program/Erase Enable (V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PP

V

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DD

Input/Output Supply Voltage (V

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DDQ

Ground (V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

SS

Ground (V

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

SSQ

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Asynchronous Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2. Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Synchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Synchronous Pipelined Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 3. Synchronous Burst Read Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2/65

M58LW128A, M58LW128B

Table 4. Address Latch Cycle for Optimum Pipelined Synchronous Burst Read . . . . . . . . . . . . . 17

Figure 7. Synchronous Burst Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. Example Synchronous Pipelined Burst Read Operation . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. Example Burst Address Advance and Burst Abort operations . . . . . . . . . . . . . . . . . . . . 19

Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

X-Latency Bits (M14-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Y-Latency Bit (M9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Valid Data Ready Bit (M8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Burst Type Bit (M7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Valid Clock Edge Bit (M6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Latch Enable Bit (M3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Burst Length Bit (M2-M0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 6. Burst Type Definition (x16 Bus Width). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7. Burst Type Definition (x32 Bus Width). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 8. Burst Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Write to Buffer and Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Block Protect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Blocks Unprotect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 10. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 11. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . 28

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

VPP Status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 12. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3/65

M58LW128A, M58LW128B

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 13. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 14. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 10. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 11. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 15. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 16. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 12. Asynchronous Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 17. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 13. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 36

Table 18. Asynchronous Latch Controlled Bus Read AC Characteristics . . . . . . . . . . . . . . . . . . . 36

Figure 14. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 19. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 15. Asynchronous Write AC Waveform, Write Enable Controlled . . . . . . . . . . . . . . . . . . . 38

Figure 16. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled. . . . . . 38

Table 20. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable

Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 17. Asynchronous Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . 40

Figure 18. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled . . . . . 40

Table 21. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable

Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 19. Synchronous Burst Read AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 20. Synchronous Burst Read - Continuous - Valid Data Ready Output . . . . . . . . . . . . . . . 43

Table 22. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 21. Reset, Power-Down and Power-Up AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 23. Reset, Power-Down and Power-Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 45

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline . . . . . . . 46

Table 24. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data 46

Figure 23. TBGA64 - 10x13mm - 8 x 8 ball array, 1mm pitch, Package Outline. . . . . . . . . . . . . . 47

Table 25. TBGA64 - 10x13mm - 8 x 8 ball array, 1 mm pitch, Package Mechanical Data . . . . . . 47

Figure 24. TBGA80 - 10x13mm - 8 x 10 ball array, 1mm pitch, Package Outline. . . . . . . . . . . . . 48

Table 26. TBGA80 - 10x13mm - 8 x 10 ball array, 1mm pitch, Package Mechanical Data. . . . . . 48

PART NUMBERING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 28. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

APPENDIX B. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 29. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4/65

M58LW128A, M58LW128B

Table 30. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 31. CFI - Device Voltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 32. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 33. Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 34. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

APPENDIX C. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 25. Write to Buffer and Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 57

Figure 26. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 58

Figure 27. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 28. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 60

Figure 29. Command Interface and Program Erase Controller Flowchart (a) . . . . . . . . . . . . . . . . 61

Figure 30. Command Interface and Program Erase Controller Flowchart (b) . . . . . . . . . . . . . . . . 62

Figure 31. Command Interface and Program Erase Controller Flowchart (c) . . . . . . . . . . . . . . . . 63

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 35. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5/65

M58LW128A, M58LW128B

SUMMARY DESCRIPTION

M58LW128 is a 128 Mbit (8Mb x16 or 4Mb x32)

non-volatile memory that can be read, erased and

reprogrammed. These operations can be per-

formed using a single low voltage (2.7V to 3.6V)

core supply. On power-up the memory defaults to

Read mode with an asynchronous bus where it

can be read in the same way as a non-burst Flash

memory.

The memory is divided into 128 blocks of 1Mbit

that can be erased independently so it is possible

to preserve valid data while old data is erased.

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller simplifies the process of

programming or erasing the memory by taking

care of all of the special operations that are re-

quired to update the memory contents. The end of

a Program or Erase operation can be detected and

any error conditions identified in the Status Regis-

ter. The command set required to control the

memory is consistent with JEDEC standards.

The Write Buffer allows the microprocessor to pro-

gram up to 16 Words (or 8 Double Words) in par-

allel, both speeding up the programming and

freeing up the microprocessor to perform other

work. The minimum buffer size for a program op-

eration is an 8 Word (or 4 Double Word) page. A

page can only be programmed once between

Erase operations.

Erase can be suspended in order to perform either

read or program in any other block and then re-

sumed. Program can be suspended to read data in

any other block and then resumed. Each block can

be programmed and erased over 100,000 cycles.

tion status of each block is restored to the state

when power was last removed. Software com-

mands are provided to allow protection of some or

all of the blocks and to cancel all block protection

bits simultaneously. All program or erase opera-

tions are blocked when the Program Erase Enable

input Vpp is low.

The Reset/Power-Down pin is used to apply a

Hardware Reset to the memory and to set the de-

vice in Power-Down mode. It can also be used to

temporarily disable the protection mechanism.

In asynchronous mode Chip Enable, Output En-

able and Write Enable signals control the bus op-

eration of the memory. An Address Latch input can

be used to latch addresses in Latch Controlled

mode. Together they allow simple, yet powerful,

connection to most microprocessors, often without

additional logic.

In synchronous mode all Bus Read operations are

synchronous with the Clock. Chip Enable and Out-

put Enable select the Bus Read operation; the ad-

dress is Latched using the Latch Enable inputs

and the address is advanced using Burst Address

Advance. The signals are compatible with most

microprocessor burst interfaces.

A One Time Programmable (OTP) area is included

for security purposes. Either 512 Words (x16 Bus

Width) or 512 Double-Words (x32 Bus Width) is

available in the OTP area. The process of reading

from and writing to the OTP area is not published

for security purposes; contact STMicroelectronics

for details on how to use the OTP area.

The memory is offered in various packages. The

M58LW128A is available in TSOP56 (14 x 20 mm)

and TBGA64 (1mm pitch). The M58LW128B is

available in TBGA80 (1mm pitch).

Individual block protection against program or

erase is provided for data security. All blocks are

protected during power-up. The protection of the

blocks is non-volatile; after power-up the protec-

6/65

M58LW128A, M58LW128B

Figure 2. Logic Diagram

Table 1. Signal Names

A1

Address Input (x16 Bus Width only)

Address inputs

A2-A23

DQ0-DQ15

V

DD DDQ

Data Inputs/Outputs

23

16

Data Inputs/Outputs (x32 Bus Width of

M58LW128B only)

DQ16-DQ31

A1-A23

DQ0-DQ15

B

Burst Address Advance

Chip Enable

V

PP

E

DQ16-DQ31⁽¹⁾

W

E

G

Output Enable

RB

R

K

Clock

M58LW128A

M58LW128B

L

Latch Enable

G

R

Valid Data Ready

Ready/Busy

RP

RB

RP

L

Reset/Power-Down

Program/Erase Enable

Write Enable

B

K

V

PP

W

WORD⁽¹⁾

WORD

Word Organization (M58LW128B only)

Supply Voltage

V

DD

V

Input/Output Supply Voltage

Ground

DDQ

V

SS SSQ

AI04314

V

SS

Note: 1. M58LW128B only.

V

Input/Output Ground

Not Connected Internally

SSQ

NC

7/65

M58LW128A, M58LW128B

Figure 3. TSOP56 Connections

A22

R

1

56

NC

W

A21

A20

A19

A18

A17

A16

G

RB

DQ15

DQ7

DQ14

DQ6

V

DD

A15

A14

A13

A12

E

SSQ

DQ13

DQ5

DQ12

DQ4

14

15

43

42

V

DDQ

SS

M58LW128A

V

PP

RP

DQ11

DQ3

A11

A10

A9

DQ10

DQ2

A8

V

DD

V

DQ9

DQ1

DQ8

DQ0

B

SS

A7

A6

A5

A4

A3

A2

A1

K

A23

L

28

29

AI04315

8/65

M58LW128A, M58LW128B

Figure 4. TBGA64 Connections for M58LW128A (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

A1

A2

A3

A4

DQ8

K

A6

A8

A9

V

A13

A14

V

A18

A19

A22

R

PP

E

DD

V

NC

SS

A7

A10

A11

DQ9

DQ10

DQ2

A12

RP

A15

A20

A21

A17

RB

G

A5

DQ1

DQ0

B

NC

A16

DQ3

DQ11

DQ4

DQ12

DQ5

DQ13

NC

DQ15

NC

G

H

A23

L

V

DQ6

DQ14

DQ7

W

DDQ

NC

V

SSQ

NC

DD

SS

AI04316

9/65

M58LW128A, M58LW128B

Figure 5. TBGA80 Connections for M58LW128B (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

A1

A2

A8

A7

V

E

A13

A14

V

A18

A19

A22

R

SS

DD

A9

A12

A16

A17

A3

A6

A10

V

A15

A20

A21

NC

PP

A4

A5

A11

RP

A23

NC

DQ16

DQ24

DQ25

DQ18

DQ19

DQ27

WORD

DQ10

DQ6

DQ13

DQ28

DQ20

W

DQ22

DQ29

DQ21

RB

DQ31

DQ23

G

H

J

DQ17

K

DQ26

B

L

DQ3

DQ5

DQ12

DQ4

DQ30

G

DQ2

DQ11

DQ15

DQ0

DQ1

DQ9

V

DQ7

DQ14

DD

SS

SSQ

K

V

DQ8

DD

SS

DDQ

AI04318

10/65

M58LW128A, M58LW128B

Figure 6. Block Addresses

M58LW128B

Double-Word (x32) Bus Width

M58LW128A, M58LW128B

Word (x16) Bus Width

Address lines A1-A23

Address lines A2-A23

(A1 is Don't Care)

7FFFFFh

3FFFFFh

1 Mbit or

64 KWords

32 KDouble-Words

7F0000h

7EFFFFh

3F8000h

3F7FFFh

1 Mbit or

64 KWords

32 KDouble-Words

7E0000h

3F0000h

Total of 128

1 Mbit Blocks

01FFFFh

00FFFFh

1 Mbit or

64 KWords

32 KDouble-Words

010000h

00FFFFh

008000h

007FFFh

1 Mbit or

64 KWords

32 KDouble-Words

000000h

AI06130

Note: Also see Appendix A, Table 28 for a full listing of the Block Addresses

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

to input the data during a Program operation. Dur-

ing Bus Write operations they represent the com-

mands sent to the Command Interface of the

internal state machine. When used to input data or

write commands they are latched on the rising

edge of Write Enable or Chip Enable, whichever

occurs first.

Address Inputs (A1-A23). The Address Inputs

are used to select the cells to access in the mem-

ory array during Bus Read operations either to

read or to program data to. During Bus Write oper-

ations they control the commands sent to the

Command Interface of the internal state machine.

Chip Enable must be low when selecting the ad-

dresses.

The address inputs are latched on the rising edge

of Chip Enable, Write Enable or Latch Enable,

whichever occurs first in a write operation. The ad-

dress latch is transparent when Latch Enable is

When Chip Enable and Output Enable are both

low, V , the data bus outputs data from the mem-

IL

ory array, the Electronic Signature, the Block Pro-

tection status, the CFI Information or the contents

of the Status Register. The data bus is high imped-

ance when the chip is deselected, Output Enable

is High, V

or the Reset/Power-Down signal is

IH,

Low, V . When the Program/Erase Controller is

IL

active the Ready/Busy status is given on DQ7

while DQ0-DQ6 and DQ8-DQ31 are high imped-

ance.

low, V . The address is internally latched in a pro-

IL

gram or erase operation.

With a x32 Bus Width, WORD = V , Address Input

IH

With a x16 Bus Width, WORD = V , DQ16-DQ31

IL

A1 is ignored; the Least Significant Word is output

on DQ0-DQ15 and the Most Significant Word is

output on DQ16-DQ31. With a x16 Bus Width,

are not used and are high impedance.

Chip Enable (E). The Chip Enable, E, input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. Chip Enable, E, at

WORD = V , the Least Significant Word is output

IL

on DQ0-DQ15 when A1 is low, V and the Most

IL,

Significant Word is output on DQ0-DQ15 when A1

V

deselects the memory and reduces the power

IH

is high, V .

consumption to the Standby level, I

.

DD1

IH

Data Inputs/Outputs (DQ0-DQ31). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation, or are used

Output Enable (G). The Output Enable, G, gates

the outputs through the data output buffers during

a read operation. When Output Enable, G, is at V

IH

11/65

M58LW128A, M58LW128B

the outputs are high impedance. Output Enable,

G, can be used to inhibit the data output during a

burst read operation.

Write Enable (W). The Write Enable input, W,

controls writing to the Command Interface, Input

Address and Data latches. Both addresses and

data can be latched on the rising edge of Write En-

able (also see Latch Enable, L).

nous Bus Read operations. The Clock can be con-

figured to have an active rising or falling edge. Bus

signals are latched on the active edge of the Clock

during synchronous bus operations. In Synchro-

nous Burst Read mode the address is latched on

the first active clock edge when Latch Enable is

low, V , or on the rising edge of Latch Enable,

IL

whichever occurs first.

During Asynchronous Bus operations the Clock is

not used.

Burst Address Advance (B). The Burst Address

Advance, B, controls the advancing of the address

by the internal address counter during synchro-

nous bus operations.

Reset/Power-Down (RP). The

Reset/Power-

Down pin can be used to apply a Hardware Reset

to the memory or to temporarily unprotect all

blocks that have been protected.

A Hardware Reset is achieved by holding Reset/

Power-Down Low, V , for at least t

. When

IL

PLPH

Reset/Power-Down is Low, V , the Status Regis-

ter information is cleared and the current is re-

Burst Address Advance, B, is only sampled on the

active clock edge of the Clock when the X- or Y-

latency time has expired. If Burst Address Ad-

IL

duced to

I

(refer to Table 16, DC

DD2

Characteristics). The device is deselected and

outputs are high impedance. If Reset/Power-

vance is Low, V , the internal address counter ad-

IL

vances. If Burst Address Advance is High, V , the

IH

Down goes low, V ,during a Block Erase, a Write

internal address counter does not change; the

same data remains on the Data Inputs/Outputs

and Burst Address Advance is not sampled until

the Y-latency expires.

IL

to Buffer and Program or a Block Protect/Unpro-

tect the operation is aborted and the data may be

corrupted. In this case the Ready/Busy pin stays

low, V , for a maximum timing of t

+ t

.

IL

PLPH

PHRH

The Burst Address Advance, B, may be tied to V .

IL

After Reset/Power-Down goes High, V , the

memory will be ready for Bus Read and Bus Write

IH

Valid Data Ready (R). The Valid Data Ready

output, R, is an open drain output that can be used

to identify if the memory is ready to output data or

not. The Valid Data Ready output is only active

during Synchronous Burst Read operations when

the Burst Length is set to Continuous. The Valid

Data Ready output can be configured to be active

on the clock edge of the invalid data read cycle or

operations after t

. Note that Ready/Busy does

RHEL

not fall during a reset, see Ready/Busy Output

section.

During power-up Reset/Power-Down must be held

Low, V Furthermore it must stay low for t

IL.

VDHPH

after the Supply Voltage inputs become stable.

The device will then be configured in Asynchro-

nous Random Read mode.

See Table 23 and Figure 21, Reset, Power-Down

and Power-up Characteristics, for more details.

one cycle before. Valid Data Ready Low, V , in-

OL

dicates that the data is not, or will not be valid. Val-

id Data Ready in a high-impedance state indicates

that valid data is or will be available.

Unless the Burst Length is set to Continuous and

Synchronous Burst Read has been selected, Valid

Data Ready is high-impedance. It may be tied to

other components with the same Valid Data

Ready signal to create a unique System Ready

signal.

When the system clock frequency is between

33MHz and 50MHz and the Y latency is set to 2,

values of B sampled on odd clock cycles, starting

from the first read are not considered.

Designers should use an external pull-up resistor

of the correct value to meet the external timing re-

quirements for Valid Data Ready rising. Refer to

Figure 20.

Word Organization (WORD). The Word Organi-

zation input, WORD, selects the x16 or x32 Bus

Width on the M58LW128B. The Word Organiza-

tion input is not available on the M58LW128A.

Holding RP at V

protected blocks in the memory. Program and

Erase operations on all blocks will be possible.

will temporarily unprotect the

HH

In an application, it is recommended to associate

Reset/Power-Down pin, RP, with the reset signal

of the microprocessor. Otherwise, if a reset opera-

tion occurs while the memory is performing a pro-

gram or erase operation, the memory may output

the Status Register information instead of being

initialized to the default Asynchronous Random

Read.

Latch Enable (L). The Bus Interface can be con-

figured to latch the Address Inputs on the rising

edge of Latch Enable, L. In synchronous bus oper-

ations the address is latched on the active edge of

the Clock when Latch Enable is Low, V . Once

latched, the addresses may change without affect-

ing the address used by the memory. When Latch

IL

Enable is Low, V , the latch is transparent.

IL

When WORD is Low, V , Word-wide x16 Bus

IL

Clock (K). The Clock, K, is used to synchronize

the memory with the external bus during Synchro-

Width is selected; data is read and written to DQ0-

DQ15; DQ16-DQ31 are at high impedance and A1

12/65

M58LW128A, M58LW128B

is the LSB of the address bus. When WORD is

tect operations, otherwise the operation is not

guaranteed to succeed and data may become cor-

rupt.

High, V , the Double-Word wide x32 Bus Width is

IH

selected and the data is read and written to on

DQ0-DQ31; A2 is the LSB of the address bus and

A1 is don’t care.

V

Supply Voltage. The Supply Voltage, V

,

DD

is the core power supply. All internal circuits draw

Ready/Busy (RB). The Ready/Busy output, RB,

is an open-drain output that can be used to identify

if the Program/Erase Controller is currently active.

When Ready/Busy is high impedance, the memo-

ry is ready for any read, program or erase opera-

their current from the V

gram/Erase Controller.

pin, including the Pro-

DD

A 0.1µF capacitor should be connected between

the Supply Voltage, V , and the Ground, V , to

DD

SS

decouple the current surges from the power sup-

ply. The PCB track widths must be sufficient to

carry the currents required during all operations of

the parts, see Table 16, DC Characteristics, for

maximum current supply requirements.

Input/Output Supply Voltage (V

put/Output Supply Voltage, V

put buffer power supply. All input and output pins

and voltage references are powered and mea-

sured relative to the Input/Output Supply Voltage

tion. Ready/Busy is Low, V , during program and

OL

erase operations. When the device is busy it will

not accept any additional Program or Erase com-

mands except Program/Erase Suspend. When the

Program/Erase Controller is idle, or suspended,

Ready Busy can float High through a pull-up resis-

tor.

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

). The In-

DDQ

, is the input/out-

DDQ

pin, V

.

DDQ

The Input/Output Supply Voltage, V

ways be equal or less than the V

age, including during Power-Up.

A 0.1µF capacitor should be connected between

the Input/Output Supply Voltage, V , and the

, must al-

DDQ

Ready/Busy is not Low during a reset unless the

reset was applied when the Program/Erase Con-

troller was active; Ready/Busy can rise before Re-

set/Power-Down rises.

Supply Volt-

DD

DDQ

Program/Erase Enable (V ). The

Program/

PP

Ground, V

, to decouple the current surges

SSQ

Erase Enable input, V

is used to protect all

PP,

from the power supply. If V

nected together then only one decoupling capaci-

tor is required.

and V are con-

DDQ

DD

blocks, preventing Program and Erase operations

from affecting their data.

When Program/Erase Enable is Low, V , any pro-

gram or erase operation sent to the Command In-

IL

Ground (V ). Ground, V

all core power supply voltages.

is the reference for

SS

SS,

terface will cause the V

Status bit (bit3) in the

PP

Ground (V ). Ground, V

is the reference

SSQ,

SSQ

Status Register to be set. When Program/Erase

for input/output voltage measurements. It is es-

Enable is High, V , program and erase operations

IH

sential to connect V

and V

to the same

SS

SSQ

can be performed on unprotected blocks. Pro-

gram/Erase Enable must be kept High during all

Program, Erase, Block Protect and Block Unpro-

ground

.

13/65

M58LW128A, M58LW128B

BUS OPERATIONS

The bus operations that control the memory are

described in this section, see Tables 2 and 3, Bus

Operations, for a summary. The bus operation is

selected through the Burst Configuration Register;

the bits in this register are described at the end of

this section.

Note that, since the Latch Enable input is transpar-

ent when set Low, V , Asynchronous Bus Read

IL

operations can be performed when the memory is

configured for Asynchronous Latch Enable bus

operations by holding Latch Enable Low, V

throughout the bus operation.

IL

On Power-up or after a Hardware Reset the mem-

ory defaults to Asynchronous Bus Read and Asyn-

chronous Bus Write, no other bus operation can

be performed until the Burst Control Register has

been configured.

Synchronous Read operations and Latch Con-

trolled Bus Read operations can only be used to

read the memory array. The Electronic Signature,

CFI or Status Register will be read in asynchro-

nous mode regardless of the Burst Control Regis-

ter settings.

Asynchronous Page Read. Asynchronous Page

Read operations are used to read from several ad-

dresses within the same memory page. Each

memory page is 8 Words or 4 Double-Words and

has the same A4-A23, only A1, A2 and A3 may

change.

Valid bus operations are the same as Asynchro-

nous Bus Read operations but with different tim-

ings. The first read operation within the page has

identical timings, subsequent reads within the

same page have much shorter access times. If the

page changes then the normal, longer timings ap-

ply again. See Figure 14, Asynchronous Page

Read AC Waveforms and Table 19, Asynchro-

nous Page Read AC Characteristics for details on

when the outputs become valid.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

Asynchronous Bus Operations

For asynchronous bus operations refer to Table 3

together with the text below.

Asynchronous Bus Write. Asynchronous Bus

Write operations write to the Command Interface

in order to send commands to the memory or to

latch addresses and input data to program. Bus

Write operations are asynchronous, the clock, K,

is don’t care during Bus Write operations.

Asynchronous Bus Read. Asynchronous Bus

Read operations read from the memory cells, or

specific registers (Electronic Signature, Status

Register, CFI and Block Protection Status) in the

Command Interface. A valid bus operation in-

volves setting the desired address on the Address

A valid Asynchronous Bus Write operation begins

by setting the desired address on the Address In-

Inputs, applying a Low signal, V , to Chip Enable

IL

puts and setting Latch Enable Low, V . The Ad-

IL

and Output Enable and keeping Write Enable

dress Inputs are latched by the Command

Interface on the rising edge of Chip Enable or

Write Enable, whichever occurs first. The Data In-

puts/Outputs are latched by the Command Inter-

face on the rising edge of Chip Enable or Write

Enable, whichever occurs first. Output Enable

High, V . The Data Inputs/Outputs will output the

IH

value, see Figure 12, Asynchronous Bus Read AC

Waveforms, and Table 17, Asynchronous Bus

Read AC Characteristics, for details of when the

output becomes valid.

Asynchronous Latch Controlled Bus Read.

must remain High, V , during the whole Asyn-

IH

chronous Bus Write operation. See Figures 15,

and 17, Asynchronous Write AC Waveforms, and

Tables 20 and 21, Asynchronous Write and Latch

Controlled Write AC Characteristics, for details of

the timing requirements.

Asynchronous Latch Controlled Bus Read opera-

tions read from the memory cells. The address is

latched in the memory before the value is output

on the data bus, allowing the address to change

during the cycle without affecting the address that

the memory uses.

Asynchronous Latch Controlled Bus Write.

A valid bus operation involves setting the desired

address on the Address Inputs, setting Chip En-

Asynchronous Latch Controlled Bus Write opera-

tions write to the Command Interface in order to

send commands to the memory or to latch ad-

dresses and input data to program. Bus Write op-

erations are asynchronous, the clock, K, is don’t

care during Bus Write operations.

A valid Asynchronous Latch Controlled Bus Write

operation begins by setting the desired address on

the Address Inputs and pulsing Latch Enable Low,

able and Address Latch Low, V and keeping

IL

Write Enable High, V ; the address is latched on

IH

the rising edge of Address Latch. Once latched,

the Address Inputs can change. Set Output En-

able Low, V , to read the data on the Data Inputs/

IL

Outputs; see Figure 13, Asynchronous Latch Con-

trolled Bus Read AC Waveforms and Table 18,

Asynchronous Latch Controlled Bus Read AC

Characteristics for details on when the output be-

comes valid.

V . The Address Inputs are latched by the Com-

IL

mand Interface on the rising edge of Latch Enable,

Chip Enable or Write Enable, whichever occurs

14/65

M58LW128A, M58LW128B

first. The Data Inputs/Outputs are latched by the

Command Interface on the rising edge of Chip En-

able or Write Enable, whichever occurs first. Out-

puts/Outputs pins are placed in the high imped-

ance state regardless of Output Enable or Write

Enable. The Supply Current is reduced to the

put Enable must remain High, V , during the

Standby Supply Current, I

.

IH

DD1

whole Asynchronous Bus Write operation. See

Figures 16 and 18 Asynchronous Latch Controlled

Write AC Waveforms, and Tables 20 and 21,

Asynchronous Write and Latch Controlled Write

AC Characteristics, for details of the timing re-

quirements.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when the Output Enable

is High.

During Program or Erase operations the memory

will continue to use the Program/Erase Supply

Current, I

, for Program or Erase operations un-

DD3

til the operation completes.

Power-Down. The memory is in Power-Down

mode when Reset/Power-Down, RP, is Low. The

current is reduced to I

, and the outputs are

DD2

high impedance, independent of Chip Enable,

Output Enable or Write Enable.

Standby. When Chip Enable is High, V , the

IH

memory enters Standby mode and the Data In-

Table 2. Asynchronous Bus Operations

(2)

Bus Operation

Step

E

G

W

RP

L

A1-A23

Address

X

DQ0-DQ31

Data Output

High Z

M3

0

V

Asynchronous Bus Read

High

X

IL

IH

V

IL

Address Latch

Read

1

Asynchronous Latch

Controlled Bus Read

V

1

Data Output

Data Input

IH

Asynchronous Page Read

Asynchronous Bus Write

0

X

Address

V

X

IH

IL

Asynchronous Latch

Controlled Bus Write

V

Address Latch

High

X

Address

Data Input

IL

V

Output Disable

Standby

High

X

High Z

IH

X

IH

V

IL

Power-Down

X

Note: 1. X = Don’t Care V or V . High = V or V .

HH

IL

IH

2. M15 = 1, Bits M15 and M3 are in the Burst Configuration Register.

15/65

M58LW128A, M58LW128B

Synchronous Bus Operations

For synchronous bus operations refer to Table 3

together with the text below.

Synchronous Burst Read. Synchronous Burst

Read operations are used to read from the memo-

ry at specific times synchronized to an external ref-

erence clock. The burst type, length and latency

can be configured. The different configurations for

Synchronous Burst Read operations are de-

scribed in the Burst Configuration Register sec-

tion.

The Synchronous Burst Read timing diagrams

and AC Characteristics are described in the AC

and DC Parameters section. See Figures 19, 20

and Table 22.

Synchronous Pipelined Burst Read. Synchro-

nous Burst Read operations can be overlapped to

avoid or reduce the X-latency. Pipelined opera-

tions should only be used with Burst Configuration

Register bit M9 = 0 (Y-latency setting).

A valid Synchronous Pipelined Burst Read opera-

tion occurs during a Synchronous Burst Read op-

eration when the new address is set on the

Address Inputs and a Low pulse is applied to Latch

Enable. The data for the new address becomes

valid after the X-latency specified in the Burst Con-

figuration Register has expired.

A valid Synchronous Burst Read operation begins

when the address is set on the Address Inputs,

Write Enable is High, V , and Chip Enable and

IH

Latch Enable are Low, V , during the active edge

IL

of the Clock. The address is latched on the first ac-

tive clock edge when Latch Enable is low, or on

the rising edge of Latch Enable, whichever occurs

first. The data becomes available for output after

the X-latency specified in the Burst Control Regis-

ter has expired. The output buffers are activated

by setting Output Enable Low, V . See Figure 7

for an example of a Synchronous Burst Read op-

eration.

For optimum operation the address should be

latched on the correct clock cycle. Table 4 gives

the clock cycle for each valid X- and Y-latency set-

ting. Only these settings are valid, other settings

must not be used. There is always one Y-Latency

period where the data is not valid. If the address is

latched later than the clock cycle specified in Ta-

bles 4 then additional cycles where the data is not

valid are inserted. See Figure 8 for an example of

a Synchronous Pipelined Burst Read operation.

Here the X-latency is 8, the Y-latency is 1 and the

burst length is 4; the first address is latched on cy-

cle 1 while the next address is latched on cycle 6,

as shown in Table 4.

Synchronous Pipelined Burst Read operations

should only be performed on Burst Lengths of 4 or

8 with a x16 Bus Width or a Burst Length of 4 with

a x32 Bus Width.

Suspending a Pipelined Synchronous Burst Read

operation is not recommended.

IL

The Burst Address Advance input and the Y-laten-

cy specified in the Burst Control Register deter-

mine whether the internal address counter is

advanced on the active edge of the Clock. When

the internal address counter is advanced the Data

Inputs/Outputs change to output the value for the

next address.

In Continuous Burst mode (Burst Length Bit M2-

M0 is set to ‘111’), one Burst Read operation can

access the entire memory sequentially and wrap

at the last address. The Burst Address Advance,

B, must be kept low, V , for the appropriate num-

IL

ber of clock cycles. If Burst Address Advance, B,

Synchronous Burst Read Suspend. During

a

is pulled High, V , the Burst Read will be sus-

IH

Synchronous Burst Read operation it is possible to

suspend the operation, freeing the data bus for

other higher priority devices.

A valid Synchronous Burst Read operation is sus-

pended when both Output Enable and Burst Ad-

pended.

In Continuous Burst Mode, if the starting address

is not associated with a page (4 Word or 2 Double

Word) boundary the Valid Data Ready, R, output

goes Low, V , to indicate that the data will not be

IL

dress Advance are High, V . The Burst Address

IH

ready in time and additional wait-states are re-

quired. The Valid Data Ready output timing (bit

M8) can be changed in the Burst Configuration

Register.

When using the x32 Bus Width certain X-latencies

are not valid and must not be used; see Table 5,

Burst Configuration Register.

Advance going High, V , stops the burst counter

IH

and the Output Enable going High, V , inhibits the

IH

data outputs. The Synchronous Burst Read oper-

ation can be resumed by setting Output Enable

Low. See Figure 7 for an example of a Synchro-

nous Burst Read Suspend operation.

16/65

M58LW128A, M58LW128B

Table 3. Synchronous Burst Read Bus Operations

A1-A23

(3)

Bus Operation

Step

Address Latch

E

G

RP

L

B

K

DQ0-DQ31

Address Input

Data Output

High Z

V

IH

V

IL

X

T

X

IL

V

IL

V

IH

V

IH

Read (no address advance)

Read (with address advance)

Read Suspend

T

X

V

IH

V

IL

Synchronous Burst Read

V

IH

Pipelined Synchronous

Burst Read

Read Resume (no address

advance)

V

IL

V

IH

V

T

X

Data Output

IL

Read Resume (with address

advance)

V

IL

V

IH

V

IL

T

X

Data Output

High Z

V

IH

X

Read Abort

X

IH

Note: 1. X = Don’t Care, V or V

.

IH

IL

2. M15 = 0, Bit M15 is in the Burst Configuration Register.

3. T = transition, see M6 in the Burst Configuration Register for details on the active edge of K.

Table 4. Address Latch Cycle for Optimum Pipelined Synchronous Burst Read

Address Latch Clock Cycle

X-Latency

Y-Latency

Burst Length = 4

Burst Length = 8

8

1

2

6

10

11

14

15

19

9

7

12

13

15

10

11

17/65

M58LW128A, M58LW128B

Figure 7. Synchronous Burst Read Operation

1

0

X-1

X

X+1

K

Address

Inputs

Q1

L

tBHKH

tBLKH

Q1

tBHKH

B

tBHKH

Data Inputs/

Outputs

Q2

Q3 Q4 Q5 Q5 Q5 Q6 Q7 Q7 Q8 Q8

AI03454b

Note: In this example the Burst Configuration Register is set with M2-M0 = 001 (Burst Length = 4 Words or Double Words), M6 = 1 (Valid

Clock Edge = Rising Clock Edge), M7 = 0 or 1 (Burst Type = Interleaved or Sequential), M9 = 0 (Y-Latency = 1), M14-M11 = 0011 (X-

Latency = 8) and M15 = 0 (Read Select = Synchronous Burst Read), other bits are don’t care.

Figure 8. Example Synchronous Pipelined Burst Read Operation

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

K

Address

Inputs

Q1

R1

S1

L

E

G

B

Data

Q1 Q2 Q3 Q4 NV R1 R2 R3 R4 NV S1 S2 S3

Inputs/ Outputs

NV= Not Valid

AI03455

Note: In this example the Burst Configuration Register is set with M2-M0 = 001 (Burst Length = 4 Words or Double Words), M6 = 1 (Valid

Clock Edge = Rising Clock Edge), M7 = 0 or 1 (Burst Type = Interleaved or Sequential), M9 = 0 (Y-Latency = 1), M14-M11 = 0011 (X-

Latency = 8) and M15 = 0 (Read Select = Synchronous Burst Read), other bits are don’t care.

18/65

M58LW128A, M58LW128B

Figure 9. Example Burst Address Advance and Burst Abort operations

1

0

X-2

X

X+2

X+4

X+6

X+8

X+10

X+12

K

Address

Inputs

Q1

L

tBHKH

tBLKH

tBHKH

B

tBHKH

Q2

Data Inputs/

Outputs

Q1

Q3

Q4

AI03457b

Note: 1. In this example the Burst Configuration Register is set with M2-M0 = 010 (Burst Length = 8 Words), M6 = 1 (Valid Clock Edge =

Rising Clock Edge), M7 = 0 or 1 (Burst Type = Interleaved or Sequential), M9 = 1 (Y-Latency = 2), M14-M11 = 0011 (X-Latency =

8) and M15 = 0 (Read Select = Synchronous Burst Read), other bits are don’t care.

2. When the system clock frequency is between 33MHz and 50MHz and the Y latency is set to 2, values of B sampled on odd clock

cycles, starting from the first read are not considered.

19/65

M58LW128A, M58LW128B

Burst Configuration Register

The Burst Configuration Register is used to config-

ure the type of bus access that the memory will

perform.

The Burst Configuration Register is set through

the Command Interface and will retain its informa-

tion until it is re-configured, the device is reset, or

the device goes into Reset/Power-Down mode.

The Burst Configuration Register bits are de-

scribed in Table 5. They specify the selection of

the burst length, burst type, burst X and Y laten-

cies and the Read operation.

Read Select Bit (M15). The Read Select bit,

M15, is used to switch between asynchronous and

synchronous Bus Read operations. When the

Read Select bit is set to ’1’, Bus Read operations

are asynchronous; when the Read Select but is

set to ’0’, Bus Read operations are synchronous.

Ready output pin, R. When the Valid Data Ready

bit is ’0’ the Valid Data Ready output pin is driven

Low for the active clock edge when invalid data is

output on the bus. When the Valid Data Ready bit

is ’1’ the Valid Data Ready output pin is driven Low

one clock cycle prior to invalid data being output

on the bus.

Burst Type Bit (M7). The Burst Type bit is used

to configure the sequence of addresses read as

sequential or interleaved. When the Burst Type bit

is ’0’ the memory outputs from interleaved ad-

dresses; when the Burst Type bit is ’1’ the memory

outputs from sequential addresses. See Tables 6

and 7, Burst Type Definition, for the sequence of

addresses output from a given starting address in

each mode.

Valid Clock Edge Bit (M6). The Valid Clock Edge

bit, M6, is used to configure the active edge of the

Clock, K, during Synchronous Burst Read opera-

tions. When the Valid Clock Edge bit is ’0’ the fall-

ing edge of the Clock is the active edge; when the

Valid Clock Edge bit is ’1’ the rising edge of the

Clock is active.

Latch Enable Bit (M3). The Latch Enable bit is

used to select between Asynchronous Random

Read and Asynchronous Latch Enable Controlled

Read. When the Latch Enable bit is set to ‘0’ Ran-

dom read is selected; when it is set to ‘1’ Latch En-

able Controlled Read is selected. To enable these

Asynchronous Read configurations M15 must be

set to ‘1’.

On reset or power-up the Read Select bit is set

to’1’ for asynchronous accesses.

X-Latency Bits (M14-M11). The X-Latency bits

are used during Synchronous Bus Read opera-

tions to set the number of clock cycles between

the address being latched and the first data be-

coming available. For correct operation the X-La-

tency bits can only assume the values in Table 5,

Burst Configuration Register. The X-Latency bits

should also be selected in conjunction with Table

8, Burst Performance to ensure valid settings.

Y-Latency Bit (M9). The Y-Latency bit is used

during Synchronous Bus Read operations to set

the number of clock cycles between consecutive

reads. The Y-Latency value depends on both the

X-Latency value and the setting in M9.

Burst Length Bit (M2-M0). The Burst Length bits

set the maximum number of Words or Double-

Words that can be output during a Synchronous

Burst Read operation before the address wraps.

When the Y-Latency is 1 the data changes each

clock cycle; when the Y-Latency is 2 the data

changes every second clock cycle. See Table 5,

Burst Configuration Register and Table 8, Burst

Performance, for valid combinations of the Y-La-

tency, the X-Latency and the Clock frequency.

Table 5, Burst Configuration Register gives the

valid combinations of the Burst Length bits that the

memory accepts; Tables 6 and 7, Burst Type Def-

inition, give the sequence of addresses output

from a given starting address for each length.

M10, M5 and M4 are reserved for future use.

Valid Data Ready Bit (M8). The

Valid

Data

Ready bit controls the timing of the Valid Data

20/65

M58LW128A, M58LW128B

Table 5. Burst Configuration Register

Address

Bit

Reset

Value

Valid Bus

Width

Mnemonic Bit Name

Value

Description

0

1

Synchronous Burst Read

Asynchronous Bus Read

x16 or x32

Read

M15

17

1

Select

X-Latency = 7, use only with Continuous Burst

Length

0010

x16 or x32

0011 X-Latency = 8

0100 X-Latency = 9

x16 or x32

X-Latency = 10, use only with Continuous Burst

Length

0101

0110

x16 only

16

to

X-Latency = 11, use only with Continuous Burst

Length

M14-M11 X-Latency XXXX

13

1001 X-Latency = 12

1010 X-Latency = 13

x16 only

X-Latency = 13, use only with Continuous Burst

Length

1011

x16 or x32

1101 X-Latency = 15

Others Reserved, Do Not Use.

When X-Latency < 13, Y-Latency = 1

When M14-M11 = 1011 or 1101, Y-Latency = 2

0

1

x16 or x32

11

M9

X

Y-Latency

When X-Latency ≤15 but M14-M11≠1011 or

1101, Y-Latency = 2,

When M14-M11=1011 or 1101 DO NOT USE.

0

1

R valid Low during valid Clock edge

R valid Low one cycle before valid Clock edge

Interleaved

x16 or x32

x16 only

Valid Data

Ready

10

9

M8

M7

M6

M3

X

0

Burst Type

1

Sequential

0

Falling Clock edge

Valid Clock

Edge

8

1

Rising Clock edge

0

Random Read

Latch

Enable

5

1

Latch Enable Controlled Read

1 Word or Double-Word

2 Words or Double-Words

4 Words or Double-Words

8 Words

100

101

001

010

111

4

to

2

Burst

M2-M0

XXX

Length

Continuous

x16 or x32

Others Reserved, Do Not Use.

21/65

M58LW128A, M58LW128B

Table 6. Burst Type Definition (x16 Bus Width)

Starting Address

Sequential

(decimal)

Interleaved

(decimal)

(binary)

Burst Length

A3 A2 A1

XX0

0, 1

2

XX1

1, 0

X00

0, 1, 2, 3

X01

1, 2, 3, 0

1, 0, 3, 2

4

X10

2, 3, 0, 1

X11

000

001

010

3, 0, 1, 2

3, 2, 1, 0

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 4, 5, 6, 7, 0

2, 3, 4, 5, 6, 7, 0, 1

3, 4, 5, 6, 7, 0, 1, 2

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 0, 1, 2, 3, 4

6, 7, 0, 1, 2, 3, 4, 5

7, 0, 1, 2, 3, 4, 5, 6

A, A+1, A+2...

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

Not Valid

011

8

100

101

110

111

Continuous

A

Note: X = 0 or 1.

Table 7. Burst Type Definition (x32 Bus Width)

Starting Address

Sequential

(decimal)

Interleaved

(decimal)

(binary)

Burst Length

A3 A2

X0

0, 1

1, 0

0, 1

2

X1

1, 0

00

0, 1, 2, 3

1, 2, 3, 0

2, 3, 0, 1

3, 0, 1, 2

Not Valid

A, A+1, A+2...

0, 1, 2, 3

1, 0, 3, 2

2, 3, 0, 1

3, 2, 1, 0

01

4

10

11

8

Continuous

A

Not Valid

Note: X = 0 or 1.

22/65

M58LW128A, M58LW128B

Table 8. Burst Performance

X-Latency

Y-Latency

Bus Width

Clock Frequency

Mode

7

continuous only

8

1

2

continuous, length

continuous only

9

x16, x32

≤ 33 MHz

7

8

continuous, length

9

10

11

12

13

10

11

12

13

15

continuous only

continuous, length

continuous only

1

x16 only

≤ 50 MHz

2

continuous, length

continuous only

2(M9=0)

x16, x32

≤ 66 MHz

continuous, length

23/65

M58LW128A, M58LW128B

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. The Commands are summarized in Table

9, Commands. Refer to Table 9 in conjunction with

the text descriptions below.

Register. One Bus Write cycle is required to issue

the Read Status Register command. Once the

command is issued subsequent Bus Read opera-

tions read the Status Register until another com-

mand is issued.

The Status Register information is present on the

output data bus (DQ1-DQ7) when both Chip En-

After Power-Up or a Reset operation the memory

enters Read mode.

able and Output Enable are low, V .

IL

Synchronous Read operations and Latch Con-

trolled Bus Read operations can only be used to

read the memory array. The Electronic Signature,

CFI or Status Register will be read in Asynchro-

nous mode regardless of the Burst Control Regis-

ter settings. Once the memory returns to Read

Memory Array mode the bus will resume the set-

ting in the Burst Configuration Register automati-

cally.

Read Memory Array Command. The Read Mem-

ory Array command returns the memory to Read

mode. One Bus Write cycle is required to issue the

Read Memory Array command and return the

memory to Read mode. Once the command is is-

sued the memory remains in Read mode until an-

other command is issued. From Read mode Bus

Read operations will access the memory array.

While the Program/Erase Controller is executing a

Program, Erase, Block Protect or Blocks Unpro-

tect operation the memory will not accept the Read

Memory Array command until the operation com-

pletes.

Read Electronic Signature Command. The Read

Electronic Signature command is used to read the

Manufacturer Code, the Device Code and the

Block Protection Status. One Bus Write cycle is re-

quired to issue the Read Electronic Signature

command. Once the command is issued subse-

quent Bus Read operations read the Manufacturer

Code, the Device Code or the Block Protection

Status until another command is issued; see Table

10, Read Electronic Signature.

See the section on the Status Register and Table

12 for details on the definitions of the Status Reg-

ister bits

Clear Status Register Command. The Clear Sta-

tus Register command can be used to reset bits 1,

3, 4 and 5 in the Status Register to ‘0’. One Bus

Write is required to issue the Clear Status Register

command.

The bits in the Status Register are sticky and do

not automatically return to ‘0’ when a new Write to

Buffer and Program, Erase, Block Protect or Block

Unprotect command is issued. If any error occurs

then it is essential to clear any error bits in the Sta-

tus Register by issuing the Clear Status Register

command before attempting a new Program,

Erase or Resume command.

Block Erase Command. The Block Erase com-

mand can be used to erase a block. It sets all of

the bits in the block to ‘1’. All previous data in the

block is lost. If the block is protected then the

Erase operation will abort, the data in the block will

not be changed and the Status Register will output

the error.

Two Bus Write operations are required to issue the

command; the second Bus Write cycle latches the

block address in the internal state machine and

starts the Program/Erase Controller. Once the

command is issued subsequent Bus Read opera-

tions read the Status Register. See the section on

the Status Register for details on the definitions of

the Status Register bits.

During the Erase operation the memory will only

accept the Read Status Register command and

the Program/Erase Suspend command. All other

commands will be ignored. Typical Erase times

are given in Table 11.

See Appendix C, Figure 27, Block Erase Flow-

chart and Pseudo Code, for a suggested flowchart

on using the Block Erase command.

Write to Buffer and Program Command. The

Write to Buffer and Program command is used to

program the memory array.

Read Query Command. The Read Query Com-

mand is used to read data from the Common Flash

Interface (CFI) Memory Area. One Bus Write cycle

is required to issue the Read Query Command.

Once the command is issued subsequent Bus

Read operations read from the Common Flash In-

terface Memory Area. See Appendix B, Tables 29,

30, 31, 32, 33 and 34 for details on the information

contained in the Common Flash Interface (CFI)

memory area.

Note that the addresses for the Common Flash In-

terface Memory Area are A1-A23 for the

M58LW128A and A2-A23 for the M58LW128B, re-

gardless of the Bus Width selected.

Up to 2 pages of 8 Words (or 4 Double Words) can

be loaded into the Write Buffer and programmed

into the memory. The 2 pages are selected by ad-

dress A4. Each Write Buffer has the same A5 -A23

addresses.

Read Status Register Command. The Read Sta-

tus Register command is used to read the Status

24/65

M58LW128A, M58LW128B

Four successive steps are required to issue the

command.

command if the Program/Erase Controller is run-

ning.

1. One Bus Write operation is required to set up

the Write to Buffer and Program Command. Is-

sue the set up command with the selected

memory Block Address where the program op-

eration should occur (any address in the block

where the values will be programmed can be

used). Any Bus Read operations will start to out-

put the Status Register after the 1st cycle.

2. Use one Bus Write operation to write the same

block address along with the value N on the

Data Inputs/Output, where N+1 is the number of

Words (x16 Bus Width) or Double Words (x32

Bus Width) to be programmed.

3. Use N+1 Bus Write operations to load the ad-

dress and data for each Word or Double Word

into the Write Buffer. See the constraints on the

address combinations listed below. The ad-

dresses must have the same A5-A23.

4. Finally, use one Bus Write operation to issue the

final cycle to confirm the command and start the

Program operation.

Invalid address combinations or failing to follow

the correct sequence of Bus Write cycles will set

an error in the Status Register and abort the oper-

ation without affecting the data in the memory ar-

ray. The Status Register should be cleared before

re-issuing the command.

The minimum buffer size for a program operation

is an 8 Word (or 4 Double Word) page. Inside the

page the 8 Words are selected by addresses A3,

A2 and A1.

For any page, only one Write to Buffer and Pro-

gram Command can be issued inside a previously

erased block. Any further Program operations on

that page must be preceded by an Erase operation

on the respective block.

One Bus Write cycle is required to issue the Pro-

gram/Erase Suspend command and pause the

Program/Erase Controller. Once the command is

issued it is necessary to poll the Program/Erase

Controller Status bit (bit 7) to find out when the

Program/Erase Controller has paused; no other

commands will be accepted until the Program/

Erase Controller has paused. After the Program/

Erase Controller has paused, the memory will con-

tinue to output the Status Register until another

command is issued.

During the polling period between issuing the Pro-

gram/Erase Suspend command and the Program/

Erase Controller pausing it is possible for the op-

eration to complete. Once the Program/Erase

Controller Status bit (bit 7) indicates that the Pro-

gram/Erase Controller is no longer active, the Pro-

gram Suspend Status bit (bit 2) or the Erase

Suspend Status bit (bit 6) can be used to deter-

mine if the operation has completed or is suspend-

ed. For timing on the delay between issuing the

Program/Erase Suspend command and the Pro-

gram/Erase Controller pausing see Table 11.

During Program/Erase Suspend the Read Memo-

ry Array, Read Status Register, Read Electronic

Signature, Read Query and Program/Erase Re-

sume commands will be accepted by the Com-

mand Interface. Additionally, if the suspended

operation was Erase then the Write to Buffer and

Program, and the Program Suspend commands

will also be accepted. When a program operation

is completed inside a Block Erase Suspend the

Read Memory Array command must be issued to

reset the device in Read mode, then the Erase Re-

sume command can be issued to complete the

whole sequence. Only the blocks not being erased

may be read or programmed correctly.

See Appendix C, Figure 26, Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

28, Erase Suspend & Resume Flowchart and

Pseudo Code, for suggested flowcharts on using

the Program/Erase Suspend command.

If the block being programmed is protected an er-

ror will be set in the Status Register and the oper-

ation will abort without affecting the data in the

memory array. The block must be unprotected us-

ing the Blocks Unprotect command or by using the

Blocks Temporary Unprotect feature of the Reset/

Power-Down pin, RP.

See Appendix C, Figure 25, Write to Buffer and

Program Flowchart and Pseudo Code, for a sug-

gested flowchart on using the Write to Buffer and

Program command.

Program/Erase Resume Command. The

gram/Erase Resume command can be used to re-

start the Program/Erase Controller after

Pro-

a

Program/Erase Suspend operation has paused it.

One Bus Write cycle is required to issue the Pro-

gram/Erase Resume command. Once the com-

mand is issued subsequent Bus Read operations

read the Status Register.

Program/Erase Suspend Command. The

Pro-

gram/Erase Suspend command is used to pause a

Write to Buffer and Program or Erase operation.

The command will only be accepted during a Pro-

gram or an Erase operation. It can be issued at

any time during an Erase operation but will only be

accepted during a Write to Buffer and Program

Set Burst Configuration Register Command.

The Set Burst Configuration Register command is

used to write a new value to the Burst Configura-

tion Control Register which defines the burst

length, type, X and Y latencies, Synchronous/

25/65

M58LW128A, M58LW128B

Asynchronous Read mode and the valid Clock

edge configuration.

Two Bus Write cycles are required to issue the Set

Burst Configuration Register command. Once the

command is issued the memory returns to Read

mode as if a Read Memory Array command had

been issued.

The value for the Burst Configuration Register is

always presented on A2-A17, regardless of the

bus width that is selected. M0 is on A2, M1 on A3,

etc.; the other address bits are ignored.

During the Block Protect operation the memory will

only accept the Read Status Register command.

All other commands will be ignored. Typical Block

Protection times are given in Table 11.

The Block Protection bits are non-volatile, once

set they remain set through Reset and Power-

Down/Power-Up. They are cleared by a Blocks

Unprotect command or temporary disabled by

raising the Reset/Power-Down pin to V

and

HH

holding it at that level throughout a Block Erase or

Write to Buffer and Program command.

Blocks Unprotect Command. The Blocks Un-

protect command is used to unprotect all of the

blocks. Two Bus Write cycles are required to issue

the Blocks Unprotect command; the second Bus

Write cycle starts the Program/Erase Controller.

Once the command is issued subsequent Bus

Read operations read the Status Register. See the

section on the Status Register for details on the

definitions of the Status Register bits.

During the Block Unprotect operation the memory

will only accept the Read Status Register com-

mand. All other commands will be ignored. Typical

Block Protection times are given in Table 11.

Block Protect Command. The Block Protect

command is used to protect a block and prevent

Program or Erase operations from changing the

data in it. Two Bus Write cycles are required to is-

sue the Block Protect command; the second Bus

Write cycle latches the block address in the inter-

nal state machine and starts the Program/Erase

Controller. Once the command is issued subse-

quent Bus Read operations read the Status Reg-

ister. See the section on the Status Register for

details on the definitions of the Status Register

bits.

26/65

M58LW128A, M58LW128B

Table 9. Commands

Command

Bus Write Operations

2nd Subsequent

1st

Final

Addr

X

Data

FFh

90h

98h

70h

50h

20h

E8h

B0h

D0h

60h

Addr

Data

Addr

Data

Read Memory Array

Read Electronic Signature

Read Query

1

X

1

X

Read Status Register

Clear Status Register

Block Erase

1

X

1

X

2

X

BA

D0h

N

Write to Buffer and Program

Program/Erase Suspend

Program/Erase Resume

Set Burst Configuration Register

Block Protect

4 + N

BA

X

PA

PD

X

D0h

1

2

X

BCR

BA

X

BCR

BA

X

03h

01h

D0h

Blocks Unprotect

Note: X Don’t Care; PA Program Address; PD Program Data; BA Any address in the Block; N+1 Number of Addresses to Program;

BCR Burst Configuration Register value.

Table 10. Read Electronic Signature

(3)

(4)

(2)

Code

Bus Width

x16

Address

Data (DQ31-DQ0)

0020h

Manufacturer Code

000000h

000001h

x32

00000020h

8818h (M58LW128A)

8819h (M58LW128B)

x16

x32

x16

Device Code

00008819h (M58LW128B)

0000h (Block Unprotected)

0001h (Block Protected)

(1)

Block Protection Status

SBA +02h

00000000h (Block Unprotected)

00000001h (Block Protected)

x32

Note: 1. SBA is the Start Base Address of each block.

2. DQ31-DQ16 are available in the M58LW128B only.

3. x32 Bus Width is available in the M58LW128B only.

4. The address is presented on A22-A2 in x32 mode, and on A22-A1 in x16 mode.

27/65

M58LW128A, M58LW128B

Table 11. Program, Erase Times and Program Erase Endurance Cycles

M58LW128A/B

Parameters

Typical after

Unit

Min

Typ

Max

100k W/E Cycles

Block (1Mb) Erase

0.75

0.8

192

3

0.75

0.8

5

s

Block Program

Program Write Buffer

Program Suspend Latency Time

Erase Suspend Latency Time

Block Protect Time

192

µs

10

30

µs

10

µs

192

0.75

µs

Blocks Unprotect Time

Program/Erase Cycles (per Block)

Data Retention

s

100,000

20

cycles

years

Note: (T = 0 to 70°C; V = 2.7V to 3.6V; V =1.8V)

DDQ

A

DD

28/65

M58LW128A, M58LW128B

STATUS REGISTER

The Status Register provides information on the

current or previous Program, Erase, Block Protect

or Blocks Unprotect operation. The various bits in

the Status Register convey information and errors

on the operation. They are output on DQ7-DQ0.

To read the Status Register the Read Status Reg-

ister command can be issued. The Status Register

is automatically read after Program, Erase, Block

Protect, Blocks Unprotect and Program/Erase Re-

sume commands. The Status Register can be

read from any address.

Erase Suspend Status (Bit 6). The Erase Sus-

pend Status bit indicates that an Erase operation

has been suspended and is waiting to be re-

sumed. The Erase Suspend Status should only be

considered valid when the Program/Erase Con-

troller Status bit is High (Program/Erase Controller

inactive); after a Program/Erase Suspend com-

mand is issued the memory may still complete the

operation rather than entering the Suspend mode.

When the Erase Suspend Status bit is Low, V

,

OL

the Program/Erase Controller is active or has com-

pleted its operation; when the bit is High, V , a

OH

The Status Register can only be read using Asyn-

chronous Bus Read operations. Once the memory

returns to Read Memory Array mode the bus will

resume the setting in the Burst Configuration Reg-

ister automatically.

The contents of the Status Register can be updat-

ed during an Erase or Program operation by tog-

gling the Output Enable pin or by dis-activating

Program/Erase Suspend command has been is-

sued and the memory is waiting for a Program/

Erase Resume command.

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has failed to verify

that the block has erased correctly or that all

blocks have been unprotected successfully. The

Erase Status bit should be read once the Program/

Erase Controller Status bit is High (Program/Erase

Controller inactive).

(Chip Enable, V ) and then reactivating (Chip En-

IH

able and Output Enable, V ) the device.

IL

During a Program, Block Erase, Block Protect or

Block Unprotect operation only bit 7 is valid, all

other bits are high impedance. Once the operation

is complete bit 7 is High and all other Status regis-

ter bits are valid.

Status Register bits 5, 4, 3 and 1 are associated

with various error conditions and can only be reset

with the Clear Status Register command. The Sta-

tus Register bits are summarized in Table 12, Sta-

tus Register Bits. Refer to Table 12 in conjunction

with the following text descriptions.

When the Erase Status bit is Low, V , the mem-

OL

ory has successfully verified that the block has

erased correctly or all blocks have been unprotect-

ed successfully. When the Erase Status bit is

High, V , the erase operation has failed. De-

OH

pending on the cause of the failure other Status

Register bits may also be set to High, V

.

OH

■ If only the Erase Status bit (bit 5) is set High,

, then the Program/Erase Controller has

V

OH

Program/Erase Controller Status (Bit 7). The Pro-

gram/Erase Controller Status bit indicates whether

the Program/Erase Controller is active or inactive.

When the Program/Erase Controller Status bit is

applied the maximum number of pulses to the

block and still failed to verify that the block has

erased correctly or that all the blocks have been

unprotected successfully.

Low, V , the Program/Erase Controller is active

OL

and all other Status Register bits are High Imped-

■ If the failure is due to an erase or blocks

ance; when the bit is High, V , the Program/

unprotect with V low, V , then V Status bit

OH

PP OL PP

Erase Controller is inactive.

(bit 3) is also set High, V

.

OH

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is High.

■ If the failure is due to an erase on a protected

block then Block Protection Status bit (bit 1) is

also set High, V

.

OH

■ If the failure is due to a program or erase

incorrect command sequence then Program

During Program, Erase, Block Protect and Blocks

Unprotect operations the Program/Erase Control-

ler Status bit can be polled to find the end of the

operation. The other bits in the Status Register

should not be tested until the Program/Erase Con-

troller completes the operation and the bit is High.

Status bit (bit 4) is also set High, V

.

OH

Once set High, the Erase Status bit can only be re-

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

After the Program/Erase Controller completes its

operation the Erase Status, Program Status and

Block Protection Status bits should be tested for

errors.

Program Status (Bit 4). The Program Status bit

is used to identify a Program or Block Protect fail-

ure. The Program Status bit should be read once

29/65

M58LW128A, M58LW128B

the Program/Erase Controller Status bit is High

(Program/Erase Controller inactive).

Once set High, the V Status bit can only be reset

PP

by a Clear Status Register command or a hard-

ware reset. If set High it should be reset before a

new Program, Erase, Block Protection or Block

Unprotection command is issued, otherwise the

new command will appear to fail.

When the Program Status bit is Low, V , the

OL

memory has successfully verified that the Write

Buffer has programmed correctly or the block is

protected. When the Program Status bit is High,

V

, the program or block protect operation has

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper-

ation has been suspended and is waiting to be re-

sumed. The Program Suspend Status should only

be considered valid when the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive); after a Program/Erase Suspend

command is issued the memory may still complete

the operation rather than entering the Suspend

mode.

OH

failed. Depending on the cause of the failure other

Status Register bits may also be set to High, V

■ If only the Program Status bit (bit 4) is set High,

, then the Program/Erase Controller has

.

OH

V

OH

applied the maximum number of pulses to the

byte and still failed to verify that the Write Buffer

has programmed correctly or that the Block is

protected.

■ If the failure is due to a program or block protect

When the Program Suspend Status bit is Low,

with V low, V , then V Status bit (bit 3) is

PP

OL

PP

V

, the Program/Erase Controller is active or has

OL

also set High, V

.

OH

completed its operation; when the bit is High, V

,

OH

■ If the failure is due to a program on a protected

a Program/Erase Suspend command has been is-

sued and the memory is waiting for a Program/

Erase Resume command.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns Low.

block then Block Protection Status bit (bit 1) is

also set High, V

.

OH

■ If the failure is due to a program or erase

incorrect command sequence then Erase

Status bit (bit 5) is also set High, V

.

OH

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identify if a Pro-

gram or Erase operation has tried to modify the

contents of a protected block.

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

When the Block Protection Status bit is Low, V

,

OL

no Program or Erase operations have been at-

tempted to protected blocks since the last Clear

Status Register command or hardware reset;

V

Status (Bit 3). The V

Status bit can be

PP

used to identify if a Program, Erase, Block Protec-

tion or Block Unprotection operation has been at-

tempted when V is Low, V . The V pin is only

sampled at the beginning of a Program or Erase

operation.

When the V Status bit is Low, V , no Program,

Erase, Block Protection or Block Unprotection op-

erations have been attempted with V Low, V ,

since the last Clear Status Register command, or

hardware reset. When the V Status bit is High,

when the Block Protection Status bit is High, V

,

OH

PP

IL

PP

a Program (Program Status bit 4 set High) or

Erase (Erase Status bit 5 set High) operation has

been attempted on a protected block.

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-

mand or a hardware reset. If set High it should be

reset before a new Program or Erase command is

issued, otherwise the new command will appear to

fail.

PP

OL

PP

IL

PP

V

, a Program, Erase, Block Protection or Block

OH

Unprotection operation has been attempted with

Low, V .

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value should be masked.

V

PP

IL

30/65

M58LW128A, M58LW128B

Table 12. Status Register Bits

Operation

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RB

V

Program/Erase Controller Active

Write Buffer not ready

Write Buffer ready

‘0’

‘1’

Hi-Z

OL

V

(1)

‘0’

‘1’

‘0’

Hi-Z

X

Program suspended

‘1’

Program/Block Protect completed successfully

Program/Block Protect failure due to incorrect command

sequence

(1)

’1’

‘1’

‘0’

Hi-Z

X

(1)

Program/Block Protect failure due to V Error

’1’

‘1’

‘0’

‘1’

‘0’

‘1’

Hi-Z

PP

X

Program failure due to Block Protection

Program/Block Protect failure due cell failure or unerased cell

Erase suspended

‘1’

‘0’

‘1’

‘0’

Hi-Z

‘1’

Erase/Blocks Unprotect completed successfully

‘0’

X

Erase/Blocks Unprotect failure due to incorrect command

sequence

‘1’

‘0’

Hi-Z

Erase/Block Unprotect failure due to V Error

’1’

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

Hi-Z

PP

Erase failure due to Block Protection

Erase/Blocks Unprotect failure due to failed cell(s) in block

Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.

31/65

M58LW128A, M58LW128B

MAXIMUM RATING

Stressing the device above the ratings listed in Ta-

ble 13, Absolute Maximum Ratings, may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Exposure to Absolute Maximum Rat-

ing conditions for extended periods may affect de-

vice

reliability.

Refer

also

to

the

STMicroelectronics SURE Program and other rel-

evant quality documents.

Table 13. Absolute Maximum Ratings

Value

Symbol

Parameter

Temperature Under Bias

Unit

Min

–40

–55

Max

125

T

BIAS

°C

V

T

Storage Temperature

150

STG

T

Maximum TLEAD Temperature during soldering

Input or Output Voltage

t.b.a.

LEAD

V

+0.6

DDQ

–0.6

IO

V

, V

DD DDQ

Supply Voltage

5.0

V

(1)

V

HH

RP Hardware Block Unprotect Voltage

V

10

Note: 1. Cumulative time at a high voltage level of 10V should not exceed 80 hours on RP pin.

32/65

M58LW128A, M58LW128B

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC characteristics Tables that follow, are de-

rived from tests performed under the Measure-

ment Conditions summarized in Table 14,

Operating and AC Measurement Conditions. De-

signers should check that the operating conditions

in their circuit match the measurement conditions

when relying on the quoted parameters.

Table 14. Operating and AC Measurement Conditions

Parameter

M58LW128

Units

Min

2.7

1.8

0

Max

Supply Voltage (V ) M58LW128

3.6

V

DD

Input/Output Supply Voltage (V

)

V

DD

DDQ

Grade 1

70

°C

pF

ns

V

Ambient Temperature (T )

A

Grade 6

–40

85

Load Capacitance (C )

30

L

Clock Rise and Fall Times

Input Rise and Fall Times

Input Pulses Voltages

3

4

0 to V

DDQ

0.5 V

Input and Output Timing Ref. Voltages

V

DDQ

Figure 10. AC Measurement Input Output

Waveform

Figure 11. AC Measurement Load Circuit

1.3V

1N914

V

DDQ

V

DD

3.3kΩ

V

DDQ

0.5 V

DDQ

DEVICE

UNDER

TEST

DQ

S

0V

C

L

AI00610

0.1µF

C

includes JIG capacitance

L

AI03459

Table 15. Capacitance

Symbol

Parameter

Test Condition

Typ

6

Max

8

Unit

pF

C

V

IN

= 0V

Input Capacitance

Output Capacitance

IN

C

OUT

V

OUT

8

12

Note: 1. T = 25°C, f = 1 MHz

A

2. Sampled only, not 100% tested.

33/65

M58LW128A, M58LW128B

Table 16. DC Characteristics

Symbol

Parameter

Test Condition

Min

Max

±1

Unit

µA

I

0V≤ V ≤ V

Input Leakage Current

LI

IN

DDQ

I

0V≤ V

≤V

Output Leakage Current

±5

µA

LO

OUT DDQ

I

E = V , G = V , f

= 6MHz

Supply Current (Random Read)

Supply Current (Burst Read)

Supply Current (Standby)

Supply Current (Reset/Power-Down)

30

mA

µA

DD

IL

IH add

I

E = V , G = V , f = 50MHz

IH clock

50

DDB

IL

I

E = V , RP = V

120

DD1

IH

I

RP = V

µA

DD2

IL

Supply Current (Program or Erase,

Set Protect Bit, Erase Protect Bit)

Program or Erase operation in

progress

I

50

mA

DD3

Supply Current

(Erase/Program Suspend)

I

E = V

50

DD4

IH

V

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

–0.5

0.8

V

IL

V

IH

V

–0.8

V

+ 0.5

DDQ

V

OL

I

= 100µA

OL

0.1

V

OH

I

= –100µA

OH

–0.1

DDQ

RP Hardware Block Unprotect

Voltage

Block Erase in progress,

Write to Buffer and Program

(1)

8.5

9.5

1

V

µA

V

HH

RP Hardware Block Unprotect

Current

I

RP = V

HH

V

DD

Supply Voltage (Erase and

V

2.2

LKO

Program lockout)

Note: 1. Biasing RP pin to V is allowed for a maximum cumulative period of 80 hours.

HH

34/65

M58LW128A, M58LW128B

Figure 12. Asynchronous Bus Read AC Waveforms

tAVAV

A1-A23

VALID

tELQV

tELQX

tAXQX

E

tGLQV

tGLQX

tEHQZ

tEHQX

G

tAVQV

tGHQZ

tGHQX

DQ0-DQx

OUTPUT

AI06131

Note: Asynchronous Read (M15 = 1), Random Read (M3 = 0)

Table 17. Asynchronous Bus Read AC Characteristics.

M58LW128

Symbol

Parameter

Test Condition

Unit

150

0

t

E = V , G = V

IL

Address Valid to Address Valid

Min

Max

Min

Max

Min

Max

Min

Max

ns

AVAV

IL

t

E = V , G = V

Address Valid to Output Valid

AVQV

IL

t

G = V

Chip Enable Low to Output Transition

Chip Enable Low to Output Valid

Output Enable Low to Output Transition

Output Enable Low to Output Valid

Chip Enable High to Output Transition

Output Enable High to Output Transition

Address Transition to Output Transition

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

ELQX

IL

t

G = V

150

0

ELQV

IL

t

E = V

GLQX

IL

t

E = V

30

0

GLQV

IL

t

G = V

EHQX

IL

t

E = V

0

GHQX

IL

t

E = V , G = V

0

AXQX

IL

t

G = V

10

EHQZ

IL

t

E = V

GHQZ

IL

35/65

M58LW128A, M58LW128B

Figure 13. Asynchronous Latch Controlled Bus Read AC Waveforms

A1-A23

VALID

tAVLH

tLHAX

tAVLL

L

tLHLL

tLLLH

tEHLX

tELLH

tELLL

E

tGLQV

tGLQX

tEHQZ

tEHQX

G

tLLQX

tLLQV

tGHQZ

tGHQX

DQ0-DQx

OUTPUT

AI06132b

Note: Asynchronous Read (M15 = 1), Latch Enable Controlled (M3 = 1)

Table 18. Asynchronous Latch Controlled Bus Read AC Characteristics

M58LW128

Symbol

Parameter

Test Condition

Unit

150

0

t

E = V

Address Valid to Latch Enable Low

Address Valid to Latch Enable High

Latch Enable High to Latch Enable Low

Latch Enable Low to Latch Enable High

Chip Enable Low to Latch Enable Low

Chip Enable Low to Latch Enable High

Latch Enable Low to Output Transition

Latch Enable Low to Output Valid

Min

Max

Min

ns

AVLL

IL

t

E = V

10

0

AVLH

IL

t

LHLL

t

E = V

LLLH

IL

t

ELLL

t

10

0

ELLH

t

E = V , G = V

IL

LLQX

IL

t

E = V , G = V

150

10

0

LLQV

IL

t

E = V

Latch Enable High to Address Transition

Output Enable Low to Output Transition

Output Enable Low to Output Valid

Chip Enable High to Latch Enable Transition

LHAX

IL

t

E = V

GLQX

IL

t

E = V

20

0

GLQV

IL

t

EHLX

Note: For other timings see Table 17, Asynchronous Bus Read Characteristics.

36/65

M58LW128A, M58LW128B

Figure 14. Asynchronous Page Read AC Waveforms

A1-A2

VALID

A3-A23

VALID

tAVQV

tELQV

tELQX

tAXQX

E

tAVQV1

tAXQX1

tEHQZ

tEHQX

tGLQV

tGLQX

G

tGHQZ

tGHQX

DQ0-DQx

OUTPUT

AI06133

Note: Asynchronous Read (M15 = 1), Random (M3 = 0)

Table 19. Asynchronous Page Read AC Characteristics

M58LW128

Symbol

Parameter

Test Condition

Unit

150

6

t

E = V , G = V

IL

Address Transition to Output Transition

Address Valid to Output Valid

Min

ns

AXQX1

IL

t

E = V , G = V

IL

Max

25

AVQV1

IL

Note: For other timings see Table 17, Asynchronous Bus Read Characteristics.

37/65

M58LW128A, M58LW128B

Figure 15. Asynchronous Write AC Waveform, Write Enable Controlled

A1-A23

VALID

tAVWH

tWHAX

E

L

tELWL

tGHWL

tWHEH

G

tWHGL

tWLWH

tWHWL

W

tDVWH

INPUT

DQ0-DQ15

tWHDX

RB

tVPHWH

tWHBL

V

PP

AI06134

Figure 16. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled

A1-A23

VALID

tAVWH

tAVLH

tLHAX

tWHAX

L

tELLL

tLLLH

tWLLH

tLHWH

tLHGL

E

tELWL

tGHWL

tWHEH

G

tWHGL

tWLWH

tWHWL

W

tDVWH

INPUT

DQ0-DQ15

tWHDX

tWHBL

RB

tVPHWH

V

PP

AI06135

38/65

M58LW128A, M58LW128B

Table 20. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable

Controlled.

M58LW128

Symbol

Parameter

Test Condition

Min

Unit

150

10

50

0

t

Address Valid to Latch Enable High

ns

AVLH

t

E = V

Address Valid to Write Enable High

Min

Max

Min

AVWH

IL

t

E = V

Data Input Valid to Write Enable High

Chip Enable Low to Write Enable Low

Chip Enable Low to Latch Enable Low

Latch Enable High to Address Transition

Latch Enable High to Output Enable Low

Latch Enable High to Write Enable High

Latch Enable low to Latch Enable High

Latch Enable Low to Write Enable High

Program/Erase Enable High to Write Enable High

Write Enable High to Address Transition

Write Enable High to Ready/Busy low

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Output Enable High to Write Enable Low

Write Enable High to Output Enable Low

Write Enable High to Write Enable Low

Write Enable Low to Write Enable High

Write Enable Low to Latch Enable High

DVWH

t

ELWL

t

0

ELLL

t

3

LHAX

t

35

0

LHGL

t

LHWH

t

10

50

0

LLLH

t

LLWH

t

VPHWH

t

E = V

10

90

0

WHAX

IL

t

WHBL

t

WHDX

IL

t

0

WHEH

t

20

35

30

70

10

GHWL

t

WHGL

t

WHWL

t

E = V

WLWH

IL

t

WLLH

IL

39/65

M58LW128A, M58LW128B

Figure 17. Asynchronous Write AC Waveforms, Chip Enable Controlled

A1-A23

VALID

tAVEH

tEHAX

W

G

tWLEL

tEHWH

tGHEL

tELEH

tEHEL

tEHGL

E

L

tDVEH

INPUT

DQ0-DQ15

RB

tEHDX

tEHBL

tVPHEH

V

PP

AI06136

Figure 18. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled

A1-A23

VALID

tAVLH

tAVEH

tLHAX

tEHAX

L

tLLLH

tELLH

tWLLL

tLHEH

tLHGL

W

G

tWLEL

tGHEL

tEHWH

tELEH

tEHEL

tEHGL

E

tDVEH

INPUT

DQ0-DQ15

tEHDX

RB

tVPHEH

tEHBL

V

PP

AI06137

40/65

M58LW128A, M58LW128B

Table 21. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable

Controlled

M58LW128

Symbol

Parameter

Test Condition

Min

Unit

150

10

50

0

t

Address Valid to Latch Enable High

Address Valid to Chip Enable High

ns

AVLH

t

W = V

Min

Max

Min

AVEH

IL

t

W = V

Data Input Valid to Chip Enable High

Write Enable Low to Chip Enable Low

Write Enable Low to Latch Enable Low

Latch Enable High to Address Transition

Latch Enable High to Output Enable Low

Latch Enable High to Chip Enable High

Latch Enable low to Latch Enable High

Latch Enable Low to Chip Enable High

Program/Erase Enable High to Chip Enable High

Chip Enable High to Address Transition

Chip Enable High to Ready/Busy low

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Output Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

Chip Enable High to Chip Enable Low

Chip Enable Low to Chip Enable High

Chip Enable Low to Latch Enable High

DVEH

t

WLEL

t

0

WLLL

t

3

LHAX

t

35

0

LHGL

t

LHEH

t

10

50

0

LLLH

t

LLEH

t

VPHEH

t

W = V

10

90

10

0

EHAX

IL

t

EHBL

t

EHDX

IL

t

EHWH

t

20

35

30

70

10

GHEL

t

EHGL

t

EHEL

t

W = V

ELEH

IL

t

ELLH

IL

41/65

M58LW128A, M58LW128B

Figure 19. Synchronous Burst Read AC Waveform

Note: Valid Clock Edge = Rising (M6 = 1)

42/65

M58LW128A, M58LW128B

Figure 20. Synchronous Burst Read - Continuous - Valid Data Ready Output

K

(2)

Output

V

NV

V

tRLKH

R

(3)

AI06139

Note: 1. Valid Data Ready = Valid Low during valid clock edge (M8 = 0)

2. V= Valid output, NV= Not Valid output.

3. R is an open drain output. Depending on the Valid Data Ready pin capacitance load an external pull up resistor must be chosen

according to the system clock period.

4. When the system clock frequency is between 33MHz and 50MHz and the Y latency is set to 2, values of B sampled on odd clock

cycles, starting from the first read are not considered.

43/65

M58LW128A, M58LW128B

Table 22. Synchronous Burst Read AC Characteristics

M58LW128

Unit

Symb

Parameter

ol

Test Condition

150

10

20

10

0

t

E = V

Address Valid to Active Clock Edge

Min

Max

Min

ns

AVKH

IL

t

E = V

Address Valid to Latch Enable High

AVLH

IL

t

E = V , G = V , L = V

Burst Address Advance High to Active Clock Edge

Burst Address Advance Low to Active Clock Edge

Chip Enable Low to Active Clock Edge

Chip Enable Low to Latch Enable High

Output Enable Low to Valid Clock Edge

Valid Clock Edge to Address Transition

Valid Clock Edge to Latch Enable Low

Valid Clock Edge to Latch Enable High

Valid Clock Edge to Output Transition

Latch Enable Low to Valid Clock Edge

Latch Enable Low to Latch Enable High

Valid Clock Edge to Output Valid

BHKH

IL

IH

t

E = V , G = V , L = V

BLKH

ELKH

IL

t

E = V

t

ELLH

t

E = V , L = V

GLKH

KHAX

IL

IH

E = V

IL

t

E = V

KHLL

KHLH

IL

t

E = V

0

IL

E = V , G = V , L = V

3

KHQX

IL

IH

t

E = V

10

20

5

LLKH

t

LLLH

KHQV

QVKH

t

E = V , G = V , L = V

IL IL

IH

E = V , G = V , L = V

Output Valid to Active Clock Edge

IL

t

E = V , G = V , L = V

IL IL

Valid Data Ready Low to Valid Clock Edge

Active Clock Edge to Burst Address Advance Low

Active Clock Edge to Burst Address Advance High

5

RLKH

t

E = V , G = V , L = V

IL IL

0

KHBL

t

E = V , G = V , L = V

IL IL

0

KHBH

Note: For other timings see Table 17, Asynchronous Bus Read Characteristics.

44/65

M58LW128A, M58LW128B

Figure 21. Reset, Power-Down and Power-Up AC Waveform

W

E, G

DQ0-DQ15

tRHWL

tRHEL

tRHGL

tPHQV

RB

RP

tPLRH

tVDHPH

tPLPH

VDD, VDDQ

Power-Up

and Reset

Reset during

Program or Erase

AI06140

Note: Write Enable (W) and Output Enable (G) cannot be low together.

Table 23. Reset, Power-Down and Power-Up AC Characteristics

M58LW128

Symbol

Parameter

Reset/Power-Down High to Data Valid

Unit

150

t

Min

150

ns

PHQV

t

Ready/Busy High to Write Enable Low, Chip Enable Low, Output

Enable Low

RHWL

t

10

µs

RHEL

(Program/Erase Controller Active)

t

RHGL

t

Reset/Power-Down Low to Reset/Power-Down High

Reset/Power-Down Low to Ready High

Min

Max

Min

100

30

0

ns

µs

PLPH

PLRH

t

Supply Voltages High to Reset/Power-Down High

VDHPH

45/65

M58LW128A, M58LW128B

PACKAGE MECHANICAL

Figure 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

A1

α

L

Note: Drawing is not to scale.

Table 24. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data

mm

Min

inches

Min

Symbol

Typ

Max

1.20

0.15

1.05

0.27

0.21

20.20

18.50

14.10

–

Typ

Max

0.0472

0.0059

0.0413

0.0106

0.0083

0.7953

0.7283

0.5551

–

A

A1

A2

B

0.05

0.95

0.17

0.10

19.80

18.30

13.90

–

0.0020

0.0374

0.0067

0.0039

0.7795

0.7205

0.5472

–

C

D

D1

E

e

0.50

0.0197

L

0.50

0°

0.70

5°

0.0197

0°

0.0276

5°

α

N

56

CP

0.10

0.0039

46/65

M58LW128A, M58LW128B

Figure 23. TBGA64 - 10x13mm - 8 x 8 ball array, 1mm pitch, Package Outline

D

D1

FD

FE

SD

SE

E

E1

ddd

BALL "A1"

A

e

b

A2

A1

BGA-Z23

Note: Drawing is not to scale.

Table 25. TBGA64 - 10x13mm - 8 x 8 ball array, 1 mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.350

0.850

0.500

10.100

–

Typ

Max

A

A1

A2

b

0.0472

0.300

0.200

0.0118

0.0079

0.0138

0.0335

0.400

9.900

–

0.0157

0.3898

–

0.0197

D

10.000

7.000

0.3937

0.3976

D1

ddd

e

0.2756

–

0.100

–

0.0039

1.000

13.000

7.000

1.500

3.000

0.500

–

0.0394

0.5118

0.2756

0.0591

0.1181

0.0197

–

E

12.900

13.100

–

0.5079

0.5157

E1

FD

FE

SD

SE

–

47/65

M58LW128A, M58LW128B

Figure 24. TBGA80 - 10x13mm - 8 x 10 ball array, 1mm pitch, Package Outline

D

D1

FD

FE

SD

SE

E

E1

BALL "A1"

ddd

e

b

A

A2

A1

BGA-Z27

Note: Drawing is not to scale.

Table 26. TBGA80 - 10x13mm - 8 x 10 ball array, 1mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.350

0.850

0.500

10.100

–

Typ

Max

A

A1

A2

b

0.0472

0.300

0.200

0.0118

0.0079

0.0138

0.0335

0.400

9.900

–

0.0157

0.3898

–

0.0197

D

10.000

7.000

0.3937

0.3976

D1

ddd

E

0.2756

–

0.100

13.100

–

0.0039

13.000

9.000

1.000

1.500

2.000

0.500

12.900

0.5118

0.3543

0.0394

0.0591

0.0787

0.0197

0.5079

0.5157

E1

e

–

FD

FE

SD

SE

–

48/65

M58LW128A, M58LW128B

PART NUMBERING

Table 27. Ordering Information Scheme

Example:

M58LW128A

150 N

1

T

Device Type

M58

Architecture

L = Multi-Bit Cell, Burst Mode, Page Mode

Operating Voltage

W = V = 2.7V to 3.6V; V

= 1.8 to V

DD

DDQ

Device Function

128A = 128 Mbit (x16), Uniform Block

128B = 128 Mbit (x16/x32), Uniform Block

Speed

150 = 150 ns

Package

N = TSOP56: 14 x 20 mm (M58LW128A)

ZA = TBGA64: 10x13mm, 1mm pitch (M58LW128A)

ZA = TBGA80: 10x13mm, 1mm pitch (M58LW128B)

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

E = Lead-free Package, Standard Packing

F = Lead-free Package, Tape & Reel Packing

Note: Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the ST Sales Office nearest to you.

49/65

M58LW128A, M58LW128B

APPENDIX A. BLOCK ADDRESS TABLE

Table 28. Block Addresses

Block

Number

Address Range

(x16 Bus Width)

Address Range

(x32 Bus Width)

Block

Address Range

(x16 Bus Width)

Address Range

(x32 Bus Width)

Number

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

5E0000h-5EFFFFh

5D0000h-5DFFFFh

5C0000h-5CFFFFh

5B0000h-5BFFFFh

5A0000h-5AFFFFh

590000h-59FFFFh

580000h-58FFFFh

570000h-57FFFFh

560000h-56FFFFh

550000h-55FFFFh

540000h-54FFFFh

530000h-53FFFFh

520000h-52FFFFh

510000h-51FFFFh

500000h-50FFFFh

4F0000h-4FFFFFh

4E0000h-4EFFFFh

4D0000h-4DFFFFh

4C0000h-4CFFFFh

4B0000h-4BFFFFh

4A0000h-4AFFFFh

490000h-49FFFFh

480000h-48FFFFh

470000h-47FFFFh

460000h-46FFFFh

450000h-45FFFFh

440000h-44FFFFh

430000h-43FFFFh

420000h-42FFFFh

410000h-41FFFFh

400000h-40FFFFh

3F0000h-3FFFFFh

3E0000h-3EFFFFh

3D0000h-3DFFFFh

2F0000h-2F7FFFh

2E8000h-2EFFFFh

2E0000h-2E7FFFh

2D8000h-2DFFFFh

2D0000h-2D7FFFh

2C8000h-2CFFFFh

2C0000h-2C7FFFh

2B8000h-2BFFFFh

2B0000h-2B7FFFh

2A8000h-2AFFFFh

2A0000h-2A7FFFh

298000h-29FFFFh

290000h-297FFFh

288000h-28FFFFh

280000h-287FFFh

278000h-27FFFFh

270000h-277FFFh

268000h-26FFFFh

260000h-267FFFh

258000h-25FFFFh

250000h-257FFFh

248000h-24FFFFh

240000h-247FFFh

238000h-23FFFFh

230000h-237FFFh

228000h-22FFFFh

220000h-227FFFh

218000h-21FFFFh

210000h-217FFFh

208000h-20FFFFh

200000h-207FFFh

1F8000h-1FFFFFh

1F0000h-1F7FFFh

1E8000h-1EFFFFh

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

7F0000h-7FFFFFh

7E0000h-7EFFFFh

7D0000h-7DFFFFh

7C0000h-7CFFFFh

7B0000h-7BFFFFh

7A0000h-7AFFFFh

790000h-79FFFFh

780000h-78FFFFh

770000h-77FFFFh

760000h-76FFFFh

750000h-75FFFFh

740000h-74FFFFh

730000h-73FFFFh

720000h-72FFFFh

710000h-71FFFFh

700000h-70FFFFh

6F0000h-6FFFFFh

6E0000h-6EFFFFh

6D0000h-6DFFFFh

6C0000h-6CFFFFh

6B0000h-6BFFFFh

6A0000h-6AFFFFh

690000h-69FFFFh

680000h-68FFFFh

670000h-67FFFFh

660000h-66FFFFh

650000h-65FFFFh

640000h-64FFFFh

630000h-63FFFFh

620000h-62FFFFh

610000h-61FFFFh

600000h-60FFFFh

5F0000h-5FFFFFh

3F8000h-3FFFFFh

3F0000h-3F7FFFh

3E8000h-3EFFFFh

3E0000h-3E7FFFh

3D8000h-3DFFFFh

3D0000h-3D7FFFh

3C8000h-3CFFFFh

3C0000h-3C7FFFh

3B8000h-3BFFFFh

3B0000h-3B7FFFh

3A8000h-3AFFFFh

3A0000h-3A7FFFh

398000h-39FFFFh

390000h-397FFFh

388000h-38FFFFh

380000h-387FFFh

378000h-37FFFFh

370000h-377FFFh

368000h-36FFFFh

360000h-367FFFh

358000h-35FFFFh

350000h-357FFFh

348000h-34FFFFh

340000h-347FFFh

338000h-33FFFFh

330000h-337FFFh

328000h-32FFFFh

320000h-327FFFh

318000h-31FFFFh

310000h-317FFFh

308000h-30FFFFh

300000h-307FFFh

2F8000h-2FFFFFh

98

97

96

50/65

M58LW128A, M58LW128B

Block

Number

Address Range

(x16 Bus Width)

Address Range

(x32 Bus Width)

Block

Number

Address Range

(x32 Bus Width)

(x16 Bus Width)

190000h-19FFFFh

180000h-18FFFFh

170000h-17FFFFh

160000h-16FFFFh

150000h-15FFFFh

140000h-14FFFFh

130000h-13FFFFh

120000h-12FFFFh

110000h-11FFFFh

100000h-10FFFFh

0F0000h-0FFFFFh

0E0000h-0EFFFFh

0D0000h-0DFFFFh

0C0000h-0CFFFFh

0B0000h-0BFFFFh

0A0000h-0AFFFFh

090000h-09FFFFh

080000h-08FFFFh

070000h-07FFFFh

060000h-06FFFFh

050000h-05FFFFh

040000h-04FFFFh

030000h-03FFFFh

020000h-02FFFFh

010000h-01FFFFh

000000h-00FFFFh

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

3C0000h-3CFFFFh

3B0000h-3BFFFFh

3A0000h-3AFFFFh

390000h-39FFFFh

380000h-38FFFFh

370000h-37FFFFh

360000h-36FFFFh

350000h-35FFFFh

340000h-34FFFFh

330000h-33FFFFh

320000h-32FFFFh

310000h-31FFFFh

300000h-30FFFFh

2F0000h-2FFFFFh

2E0000h-2EFFFFh

2D0000h-2DFFFFh

2C0000h-2CFFFFh

2B0000h-2BFFFFh

2A0000h-2AFFFFh

290000h-29FFFFh

280000h-28FFFFh

270000h-27FFFFh

260000h-26FFFFh

250000h-25FFFFh

240000h-24FFFFh

230000h-23FFFFh

220000h-22FFFFh

210000h-21FFFFh

200000h-20FFFFh

1F0000h-1FFFFFh

1E0000h-1EFFFFh

1D0000h-1DFFFFh

1C0000h-1CFFFFh

1B0000h-1BFFFFh

1A0000h-1AFFFFh

1E0000h-1E7FFFh

1D8000h-1DFFFFh

1D0000h-1D7FFFh

1C8000h-1CFFFFh

1C0000h-1C7FFFh

1B8000h-1BFFFFh

1B0000h-1B7FFFh

1A8000h-1AFFFFh

1A0000h-1A7FFFh

198000h-19FFFFh

190000h-197FFFh

188000h-18FFFFh

180000h-187FFFh

178000h-17FFFFh

170000h-177FFFh

168000h-16FFFFh

160000h-167FFFh

158000h-15FFFFh

150000h-157FFFh

148000h-14FFFFh

140000h-147FFFh

138000h-13FFFFh

130000h-137FFFh

128000h-12FFFFh

120000h-127FFFh

118000h-11FFFFh

110000h-117FFFh

108000h-10FFFFh

100000h-107FFFh

0F8000h-0FFFFFh

0F0000h-0F7FFFh

0E8000h-0EFFFFh

0E0000h-0E7FFFh

0D8000h-0DFFFFh

0D0000h-0D7FFFh

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

0C8000h-0CFFFFh

0C0000h-0C7FFFh

0B8000h-0BFFFFh

0B0000h-0B7FFFh

0A8000h-0AFFFFh

0A0000h-0A7FFFh

098000h-09FFFFh

090000h-097FFFh

088000h-08FFFFh

080000h-087FFFh

078000h-07FFFFh

070000h-077FFFh

068000h-06FFFFh

060000h-067FFFh

058000h-05FFFFh

050000h-057FFFh

048000h-04FFFFh

040000h-047FFFh

038000h-03FFFFh

030000h-037FFFh

028000h-02FFFFh

020000h-027FFFh

018000h-01FFFFh

010000h-017FFFh

008000h-00FFFFh

000000h-007FFFh

8

7

6

5

4

3

2

1

51/65

M58LW128A, M58LW128B

APPENDIX B. COMMON FLASH INTERFACE - CFI

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

31, 32, 33 and 34 show the addresses used to re-

trieve the data.

When the M58LW128B is used in x16 mode, A1

is the Least Significant Address. Toggling A1 will

not change the CFI information available on the

DQ15-DQ0 outputs.

To read the CFI, in the M58LW128A and

M58LW128B devices, in x16 mode, addresses

A23-A1 are used; for the x32 mode of the

M58LW128B device only addresses A23-A2 are

used. To read the CFI, in the M58LW128B device,

in x16 mode, the address offsets shown must be

multiplied by two in hexadecimal.

When the CFI Query Command (RCFI) is issued

the device enters CFI Query mode and the data

structure is read from the memory. Tables 29, 30,

Table 29. Query Structure Overview

Offset

00h

Sub-section Name

Description

Manufacturer Code

01h

Device Code

10h

CFI Query Identification String

Command set ID and algorithm data offset

Device timing and voltage information

Flash memory layout

1Bh

27h

System Interface Information

Device Geometry Definition

Additional information specific to the Primary

Algorithm (optional)

(1)

Primary Algorithm-specific Extended Query Table

P(h)

Additional information specific to the Alternate

Algorithm (optional)

(2)

Alternate Algorithm-specific Extended Query Table

A(h)

(SBA+02)h Block Status Register

Block-related Information

Note: 1. Offset 0015h (x16) or 00000015h (x32) defines P which points to the Primary Algorithm Extended Query Address Table.

2. Offset 0019h (x16) or 00000019h (x32) defines A which points to the Alternate Algorithm Extended Query Address Table.

3. SBA is the Start Base Address for each block.

52/65

M58LW128A, M58LW128B

Table 30. CFI - Query Address and Data Output

(4)

Data

Address

Instruction

A23-A1 (M58LW128A)

A23-A2 (M58LW128B)

(6)

DQ15-DQ0

DQ31-DQ16

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

0000

0051h

0052h

0059h

0001h

0000h

0031h

0000h

0051h; "Q"

0052h; "R"

0059h; "Y"

Query ASCII String

Primary Vendor:

Command Set and Control Interface ID Code

Primary algorithm extended Query Address Table:

P(h)

Alternate Vendor:

Command Set and Control Interface ID Code

Alternate Algorithm Extended Query address Table

(5)

1Ah

Note: 1. The x8 or Byte Address mode is not available.

2. With the x16 Bus Width, the value of the address location of the CFI Query is independent of A1 pad (M58LW128B).

3. Query Data are always presented on DQ7-DQ0. DQ31-DQ8 are set to ’0’.

4. For M58LW128B, A1 = Don’t Care.

5. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.

6. DQ31-DQ16 are available in the M58LW128B only. They are in the high-impedance state when the device operates In x16 mode.

53/65

M58LW128A, M58LW128B

Table 31. CFI - Device Voltage and Timing Specification

(4)

Address

(5)

DQ15-DQ0

Description

A23-A1 (M58LW128A) DQ31-DQ16

A23-A2 (M58LW128B)

(1)

V

Min, 2.7V

1Bh

1Ch

1Dh

1Eh

0000

DD

PP

0027h

(1)

max, 3.6V

0036h

(2)

min – Not Available

max – Not Available

0000h

(2)

0000h

n

2 µs typical time-out for Word Program – Not Available,

DWord Program – Not Available

(3)

1Fh

0000

0000h

n

20h

21h

22h

0000

0008h

000Ah

2 µs typical time-out for max Buffer Write

n

2 ms, typical time-out for Erase Block

(3)

n

0000h

2 ms, typical time-out for Chip Erase – Not Available

n

2 x typical for Word Program time-out max – (Word and

(3)

23h

0000

0000h

Dword Not Available)

n

24h

25h

26h

0000

0004h

2 x typical for Buffer Write time-out max

n

2 x typical for individual Block Erase time-out maximum

(3)

n

0000h

2 x typical for Chip Erase max time-out – Not Available

Note: 1. Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV.

2. Bit7 to bit4 are coded in Hexadecimal and scaled in Volts while bit3 to bit0 are in Binary Code Decimal and scaled in 100mV.

3. Not supported.

4. For M58LW128B, A1 = Don’t Care.

5. DQ31-DQ16 are available in the M58LW128B only. They are in the high-impedance state when the device operates In x16 mode.

54/65

M58LW128A, M58LW128B

Table 32. Device Geometry Definition

(1)

Address

(2)

DQ15-DQ0

Description

A23-A1 (M58LW128A) DQ31-DQ16

A23-A2 (M58LW128B)

n

27h

28h

0000

N/A

0018h

0001h

0004h

0000h

0005h

0000h

0001h

007Fh

0000h

0002h

2 number of bytes memory Size

Device Interface M58LW128A

0000

Device Interface M58LW128B

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

n

Maximum number of bytes in Write Buffer, 2

Bit7-0 = number of Erase Block Regions in device

Number (n-1) of Erase Blocks of identical size; n=128

Erase Block Region Information

x 256 bytes per Erase block (128K bytes)

Note: 1. For M58LW128B, A1 = Don’t Care. N/A = Not Applicable.

2. DQ31-DQ16 are available in the M58LW128B only. They are in the high-impedance state when the device operates In x16 mode.

Table 33. Block Status Register

Address

A23-A1 (M58LW128A)

A23-A2 (M58LW128B)

Data

Selected Block Information

Block Unprotected

0

1

0

bit0

(1)

Block Protected

(BA+2)h

bit7-1

Reserved for future features

Note: 1. BA specifies the block address location, A23-A17.

55/65

M58LW128A, M58LW128B

Table 34. Extended Query information

Address

offset

(1)

A23-A1 (M58LW128A)

A23-A2 (M58LW128B)

DQ15-DQ0

Description

DQ31-DQ16

(P)h

31h

32h

33h

34h

35h

0000h

0050h

0052h

0049h

0031h

0050h; “P”

0052h; “R”

0049h; “I”

(P+1)h

(P+2)h

(P+3)h

(P+4)h

(P+5)h

Query ASCII string - Extended Table

Major version number

Minor version number

Optional Feature: (1=yes, 0=no)

bit0, Chip Erase Supported (0=no)

bit1, Suspend Erase Supported (1=yes)

36h

0000h

008Eh

(P+6)h

(P+7)h

37h

38h

0000h

0001h

0000h

bit2, Suspend Program Supported (1=yes)

bit3, Protect/Unprotect Supported (1=yes)

bit4, Queue Erase Supported (0=no)

bit5, Instant individual block locking Supported

(0=no)

bit6, Protection Bits Supported (0=no)

bit7, Page Read Supported (1=yes)

bit8, Synchronous Read Supported (1=yes)

Bit 31-9 reserved for future use

(P+8)h

39h

0000h

Supported functions after Suspend:

Program allowed after Erase Suspend (1=yes)

(refer to Commands for other allowed functions)

Bit 7-1 reserved for future use

(P+9)h

3Ah

0000h

0001h

(P+A)h

(P+B)h

3Bh

3Ch

0000h

0001h

0000h

Block Status Register

bit 0 Block Protect Bit Status active (1=yes)

bits 1-15 are reserved

V

OPTIMUM Program/Erase voltage conditions

(P+C)h

(P+D)h

(P+E)h

(P+F)h

(P+10)h

3Dh

3Eh

3Fh

40h

41h

0000h

0033h

0002h

0004h

DD

PP

V

OTP protection: 00 NA, 01 128-bit, 02 OTP area

n

Page Read: 2 Bytes (n = bits 0-7)

Synchronous mode configuration fields

n+1

n where 2

is the number of Words/Double-Words

(P+11)h

(P+12)h

42h

43h

0000h

0001h

for the burst Length (= 2)

n+1

n where 2

is the number of Words/Double-Words

for the burst Length (= 4)

n+1

n where 2

is the number of Words/Double-Words

(P+13)h

(P+14)h

44h

45h

0000h

0002h

0007h

for the burst Length (= 8) (x16 mode only)

burst continuous

Note: 1. DQ31-DQ16 are available in the M58LW128B only. They are in the high-impedance state when the device operates In x16 mode.

56/65

M58LW128A, M58LW128B

APPENDIX C. FLOW CHARTS

Figure 25. Write to Buffer and Program Flowchart and Pseudo Code

Start

Write to Buffer E8h

Command, Block Address

(1)

Note 1: N+1 is number of Words or Double

Words to be programmed

Write N

,

Block Address

Write Buffer Data,

Start Address

X = 0

YES

X = N

NO

Write Next Buffer Data,

Next Program Address

Note 2: Next Program Address must

have same A5-A22.

(2)

X = X + 1

Program Buffer to Flash

Confirm D0h

Read Status

Register

NO

b7 = 1

YES

Note 3: A full Status Register Check must be

done to check the program operation's

success.

Full Status

Register Check

(3)

End

AI03635

57/65

M58LW128A, M58LW128B

Figure 26. Program Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend Command:

– write B0h

– write 70h

Write 70h

do:

Read Status

Register

– read status register

NO

b7 = 1

YES

while b7 = 1

If b2 = 0, Program completed

b2 = 1

YES

Program Complete

Read Memory Array instruction:

– write FFh

Write FFh

– one or more data reads

from other blocks

Read data from

another block

Program Erase Resume Command:

– write D0h

to resume erasure

– if the program operation completed

then this is not necessary. The device

returns to Read Array as normal

(as if the Program/Erase Suspend

command was not issued).

Write D0h

Write FFh

Read Data

Program Continues

AI00612

58/65

M58LW128A, M58LW128B

Figure 27. Erase Flowchart and Pseudo Code

Start

Erase command:

– write 20h

Write 20h

– write D0h to Block Address

(A12-A17)

(memory enters read Status

Register after the Erase command)

Write D0h to

Block Address

NO

do:

Read Status

– read status register

– if Program/Erase Suspend command

given execute suspend erase loop

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

while b7 = 1

YES

NO

YES

NO

V

Invalid

If b3 = 1, V

invalid error:

PP

Error (1)

PP

– error handler

b3 = 0

YES

Command

Sequence Error

If b4, b5 = 1,1 Command Sequence error:

– error handler

b4, b5 = 1,1

NO

If b1 = 1, Erase to Protected Block Error:

– error handler

Erase to Protected

Block Error

b1 = 0

YES

Erase

Error (1)

If b5 = 1, Erase error:

– error handler

b5 = 0

YES

End

AI00613C

Note: 1. If an error is found, the Status Register must be cleared (Clear Status Register Command) before further Program or Erase oper-

ations.

59/65

M58LW128A, M58LW128B

Figure 28. Erase Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend Command:

– write B0h

– write 70h

Write 70h

do:

Read Status

Register

– read status register

NO

b7 = 1

YES

while b7 = 1

If b6 = 0, Erase completed

b6 = 1

YES

Erase Complete

Read Memory Array command:

– write FFh

Write FFh

– one o more data reads

from other blocks

Read data from

another block

or Program

Program/Erase Resume command:

– write D0h to resume the Erase

operation

– if the Program operation completed

then this is not necessary. The device

returns to Read mode as normal

(as if the Program/Erase suspend

was not issued).

Write D0h

Write FFh

Read Data

Erase Continues

AI00615

60/65

M58LW128A, M58LW128B

Figure 29. Command Interface and Program Erase Controller Flowchart (a)

WAIT FOR

COMMAND

WRITE

NO

90h

YES

READ

SIGNATURE

NO

98h

YES

CFI

QUERY

NO

70h

YES

READ

ARRAY

READ

STATUS

NO

50h

YES

CLEAR

STATUS

NO

E8h

YES

PROGRAM

BUFFER

LOAD

NO

(1)

20h

YES

ERASE

NO

FFh

YES

SET-UP

NO

D0h

NO

YES

C

PROGRAM

COMMAND

ERROR

D0h

YES

ERASE

COMMAND

ERROR

A

B

AI03618

Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend.

61/65

M58LW128A, M58LW128B

Figure 30. Command Interface and Program Erase Controller Flowchart (b)

A

B

ERASE

(READ STATUS)

Program/Erase Controller

Status bit in the Status

Register

YES

READ

STATUS

READY

?

NO

READ

NO

ARRAY

B0h

YES

READ

STATUS

NO

FFh

ERASE

SUSPEND

NO

YES

ERASE

SUSPENDED

READY

?

NO

READ

STATUS

YES

WAIT FOR

COMMAND

WRITE

YES

READ

STATUS

70h

NO

READ

SIGNATURE

90h

NO

CFI

QUERY

98h

NO

PROGRAM

BUFFER

LOAD

E8h

NO

PROGRAM

COMMAND

ERROR

YES

READ

STATUS

D0h

NO

(ERASE RESUME)

YES

READ

ARRAY

c

AI03619

62/65

M58LW128A, M58LW128B

Figure 31. Command Interface and Program Erase Controller Flowchart (c)

B

C

PROGRAM

(READ STATUS)

YES

Program/Erase Controller

Status bit in the Status

Register

READ

STATUS

READY

?

NO

READ

ARRAY

NO

B0h

YES

NO

READ

STATUS

FFh

PROGRAM

SUSPEND

NO

YES

PROGRAM

SUSPENDED

READY

?

NO

YES

WAIT FOR

COMMAND

WRITE

READ

STATUS

YES

NO

READ

STATUS

70h

NO

READ

SIGNATURE

90h

NO

CFI

QUERY

98h

NO

YES

READ

ARRAY

READ

STATUS

D0h

(PROGRAM RESUME)

AI00618

63/65

M58LW128A, M58LW128B

REVISION HISTORY

Table 35. Document Revision History

Date

Version

Revision Details

07-Dec-2001

-01

First Issue.

Version number format modified (major.minor),

Revision History moved to end of document.

M58LW128A and M58LW128B device codes changed; Manufacturer code clarified.

Table 10, Read Electronic Signature, clarified.

Data Retention information added to Table 11, Program, Erase Times and Program

Erase Endurance Cycles. CFI information (Table 30, Table 31, Table 32 and Table

34) clarified. Document Status changed to Preliminary Data.

16-Dec-2002

25-Feb-2003

1.1

1.2

OTP size corrected. Word program not supported clarified in Table 31, CFI - Device

Voltage and Timing Specification and DQ15-DQ0 values changed to 0000h for

addresses 1Fh and 23h. Number (n-1) of Erase Blocks of identical size corrected in

Table 32, Device Geometry Definition. ASCII for 0049h corrected in Table 34,

Extended Query information.

E and F lead-free packing options added to Table 27, Ordering Information Scheme.

64/65

M58LW128A, M58LW128B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners

STMicroelectronics group of companies

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65/65


型号：	M58LW128A
厂家：	ST
描述：	128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories 128兆位8Mb的X16或X32 4Mb的，统一座，突发3V供应闪存产品闪存
文件：	总65页 (文件大小：878K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M58LW128A [STMICROELECTRONICS]

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