M50LPW116N_技术文档

M50LPW116

16 Mbit (2Mb x8, Boot Block)

3V Supply Low Pin Count Flash Memory

PRELIMINARY DATA

■ SUPPLY VOLTAGE

– V = 3V to 3.6V for Program, Erase and

CC

Read Operations

– V = 12V for Fast Program and Fast Erase

PP

■ TWO INTERFACES

– Low Pin Count (LPC) Standard Interface for

embedded operation with PC Chipsets.

– Address/Address Multiplexed (A/A Mux) In-

terface for programming equipment compati-

bility.

TSOP40 (N)

10 x 20mm

■ LOW PIN COUNT (LPC) HARDWARE

INTERFACE MODE

– 5 Signal Communication Interface supporting

Read and Write Operations

– Hardware Write Protect Pins for Block Pro-

tection

Figure 1. Logic Diagram (LPC Interface)

– Register Based Read and Write Protection

– 5 Additional General Purpose Inputs for plat-

form design flexibility

V

CC PP

– Synchronized with 33 MHz PCI clock

■ BYTE PROGRAMMING TIME

– Single Byte Mode: 10µs (typical)

– Quadruple Byte Mode: 2.5µs (typical)

■ 50 MEMORY BLOCKS

4

5

4

LAD0-

LAD3

ID0-ID3

GPI0-

GPI4

WP

– 1 Boot Block

– 18 Parameter and 31 Main Blocks

■ PROGRAM/ERASE CONTROLLER

LFRAME

CLK

IC

TBL

M50LPW116

– Embedded Byte Program and Block/Chip

Erase algorithms

– Status Register Bits

RP

■ PROGRAM and ERASE SUSPEND

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code: 30h

INIT

V

SS

AI05466

February 2003

1/36

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M50LPW116

Figure 2. Logic Diagram (A/A Mux Interface)

DESCRIPTION

The M50LPW116 is a 16 Mbit (2Mb x8) non-

volatile memory that can be read, erased and

reprogrammed. These operations can be

performed using a single low voltage (3.0 to 3.6V)

supply. For fast programming, and fast erasing, an

optional 12V power supply can be used to reduce

the programming and the erasing times.

V

CC PP

11

8

The memory is divided into blocks that can be

erased independently so it is possible to preserve

valid data while old data is erased. Blocks can be

protected individually (except Blocks 15 to 0,

which have global protection) to prevent

accidental Program or Erase commands from

modifying the memory. Program and Erase

commands are written to the Command Interface

of the memory. An on-chip Program/Erase

Controller simplifies the process of programming

or erasing the memory by taking care of all of the

special operations that are required to update the

memory contents. The end of a program or erase

operation can be detected and any error

conditions identified. The command set required

to control the memory is consistent with JEDEC

standards.

DQ0-DQ7

A0-A10

RC

IC

M50LPW116

RB

G

W

RP

V

SS

AI05468

The M50LPW116 features an asymmetrical block

architecture. It has an array of 50 blocks: 1 Boot

Block of 16KBytes, 2 Parameter Blocks of

Figure 3. TSOP Connections

NC

1

40

V

SS

CC

SS

CC

IC (V

)

IC (V )

IL

IH

NC

A10

NC

RC

NC

LFRAME W

NC

INIT

RFU

G

NC

RB

NC

DQ7

DQ6

DQ5

DQ4

GPI4

NC

CLK

V

10

31

30

V

CC

SS

CC

SS

M50LPW116

V

11

PP

RP

PP

RP

NC

A9

A8

A7

A6

A5

A4

LAD3

LAD2

LAD1

LAD0

ID0

DQ3

DQ2

DQ1

DQ0

A0

NC

GPI3

GPI2

GPI1

GPI0

WP

ID1

A1

ID2

A2

TBL

20

21

ID3

A3

AI05467

2/36

M50LPW116

8KBytes, 1 Main Block of 32KBytes, 30 Main

Blocks of 64KBytes and 16 Parameter Blocks of

4KBytes.

Two different bus interfaces are supported by the

memory. The primary interface is the Low Pin

Count (or LPC) Standard Interface. This has been

designed to remove the need for the ISA bus in

current PC Chipsets; the M50LPW116 acts as the

PC BIOS on the Low Pin Count bus for these PC

Chipsets.

The secondary interface, the Address/Address

Multiplexed (or A/A Mux) Interface, is designed to

be compatible with current Flash Programmers for

production line programming prior to fitting to a PC

Motherboard.

Table 1. Signal Names (LPC Interface)

LAD0-LAD3

LFRAME

ID0-ID3

GPI0-GPI4

IC

Input/Output Communications

Input Communication Frame

Identification Inputs

General Purpose Inputs

Interface Configuration

Interface Reset

RP

INIT

CPU Reset

CLK

Clock

TBL

Top Block Lock

The memory is offered in TSOP40 (10 x 20mm)

package and it is supplied with all the bits erased

(set to ’1’).

WP

Write Protect

Reserved for Future Use. Leave

disconnected.

RFU

SIGNAL DESCRIPTIONS

There are two different bus interfaces available on

this part. The active interface is selected before

power-up or during Reset using the Interface Con-

figuration Pin, IC.

The signals for each interface are discussed in the

Low Pin Count (LPC) Signal Descriptions section

and the Address/Address Multiplexed (A/A Mux)

Signal Descriptions section below. The supply sig-

nals are discussed in the Supply Signal Descrip-

tions section below.

V

CC

Supply Voltage

Optional Supply Voltage for Fast

Program and Fast Erase Operations

V

PP

V

SS

Ground

NC

Not Connected Internally

Low Pin Count (LPC) Signal Descriptions

Identification Inputs (ID0-ID3). The Identification

Inputs (ID0-ID3) allow to address up to 16

memories on a bus. The value on addresses

A21,A23-A25 is compared to the hardware

strapping on the ID0-ID3 pins to select which

memory is being addressed. For an address bit to

be ‘1’ the correspondent ID pin can be left floating

For the Low Pin Count (LPC) Interface see Figure

1, Logic Diagram (LPC Interface), and Table 1,

Signal Names (LPC Interface).

The LPC address sequence is 32 bits long. The

M50LPW116 responds to addresses mapped to

the top of the 4 GByte memory space, from

FFFF FFFFh. Address bits A31-A26 must be set

to 1. For A25-A23 and A21, refer to Table 2. A22

is set to 1 for array access, and to 0 for register ac-

cess. A20-A0 are for array addresses.

Input/Output Communications (LAD0-LAD3). All

Input and Output Communication with the memory

take place on these pins. Addresses and Data for

Bus Read and Bus Write operations are encoded

on these pins.

Input Communication Frame (LFRAME). The

Input Communication Frame (LFRAME) signals

the start of a bus operation. When Input Commu-

or driven Low, V ; an internal pull-down resistor is

IL

included with a value of R . For an address bit to

IL

be ‘0’ the correspondent ID pin must be driven

High, V ; there will be a leakage current of I

IH

LI2

through each pin when pulled to V ; see Table 20.

IH

By convention the boot memory must have ID0-

ID3 pins left floating or driven Low, V and a ‘1’

IL

value on A21,A23-A25 and all additional

memories take sequential ID0-ID3 configuration,

as shown in Table 2.

General Purpose Inputs (GPI0-GPI4). The Gener-

al Purpose Inputs can be used as digital inputs for

the CPU to read. The General Purpose Input Reg-

ister holds the values on these pins. The pins must

have stable data from before the start of the cycle

that reads the General Purpose Input Register un-

til after the cycle is complete. These pins must not

nication Frame is Low, V , on the rising edge of

IL

the Clock a new bus operation is initiated. If Input

Communication Frame is Low, V , during a bus

IL

operation then the operation is aborted. When In-

put Communication Frame is High, V , the cur-

IH

be left to float, they should be driven Low, V or

rent bus operation is proceeding or the bus is idle.

IL,

High, V .

IH

3/36

M50LPW116

Table 2. Memory Identification Input Configuration

Memory

ID3

ID2

ID1

ID0

A25

A24

A23

A21

Number

V

or floating

V

or floating

V

or floating

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

or floating

1 (Boot)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

IL

V

IH

2

3

IL

V

or floating

IH

V

IH

4

IH

V

IH

V

or floating

5

IL

V

IH

V

IH

6

IL

V

IH

V

or floating

7

IH

V

IH

V

IH

8

IH

V

IH

V

or floating

V

or floating

9

IL

V

IH

V

IH

10

11

12

13

14

15

16

IL

V

IH

V

or floating

IH

V

IH

V

IH

V

IH

V

IH

V

or floating

IL

V

IH

V

IH

V

IH

IL

V

IH

V

IH

V

or floating

IH

V

IH

V

IH

V

IH

Interface Configuration (IC). The Interface Con-

figuration input selects whether the Low Pin Count

(LPC) or the Address/Address Multiplexed (A/A

Mux) Interface is used. The chosen interface must

be selected before power-up or during a Reset

and, thereafter, cannot be changed. The state of

the Interface Configuration, IC, should not be

changed during operation.

CPU Reset (INIT). The CPU Reset, INIT, pin is

used to Reset the memory when the CPU is reset.

It behaves identically to Interface Reset, RP, and

the internal Reset line is the logical OR (electrical

AND) of RP and INIT.

Clock (CLK). The Clock, CLK, input is used to

clock the signals in and out of the Input/Output

Communication Pins, LAD0-LAD3. The Clock

conforms to the PCI specification.

Top Block Lock (TBL). The Top Block Lock

input is used to prevent the Top Block (Block 49)

from being changed. When Top Block Lock, TBL,

To select the Low Pin Count (LPC) Interface the

Interface Configuration pin should be left to float or

driven Low, V ; to select the Address/Address

IL

Multiplexed (A/A Mux) Interface the pin should be

driven High, V . An internal pull-down resistor is

IH

is set Low, V , Program and Block Erase

IL

included with a value of R ; there will be a leakage

IL

operations in the Top Block have no effect,

regardless of the state of the Lock Register. When

current of I through each pin when pulled to V ;

LI2

IH

see Table 20.

Top Block Lock, TBL, is set High, V , the

IH

Interface Reset (RP). The Interface Reset (RP)

input is used to reset the memory. When Interface

protection of the Block is determined by the Lock

Register. The state of Top Block Lock, TBL, does

not affect the protection of the other Blocks

(Blocks 0 to 48).

Reset (RP) is set Low, V , the memory is in Reset

IL

mode: the outputs are put to high impedance and

the current consumption is minimized. When RP is

Top Block Lock, TBL, must be set prior to a Pro-

gram or Block Erase operation is initiated and

must not be changed until the operation completes

or unpredictable results may occur. Care should

be taken to avoid unpredictable behavior by

changing TBL during Program or Erase Suspend.

set High, V , the memory is in normal operation.

IH

After exiting Reset mode, the memory enters

Read mode.

4/36

M50LPW116

Table 3. Signal Names (A/A Mux Interface)

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs hold the data that is written to or read

from the memory. They output the data stored at

the selected address during a Bus Read opera-

tion. During Bus Write operations they represent

the commands sent to the Command Interface of

the internal state machine. The Data Inputs/Out-

puts, DQ0-DQ7, are latched during a Bus Write

operation.

IC

Interface Configuration

Address Inputs

A0-A10

DQ0-DQ7

Data Inputs/Outputs

Output Enable

G

W

Write Enable

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

RC

RB

RP

Row/Column Address Select

Ready/Busy Output

Interface Reset

Row/Column Address Select (RC). The Row/

Column Address Select input selects whether the

Address Inputs should be latched into the Row

Address bits (A0-A10) or the Column Address bits

(A11-A20). The Row Address bits are latched on

the falling edge of RC whereas the Column

Address bits are latched on the rising edge.

V

Supply Voltage

CC

Optional Supply Voltage for Fast

Program and Fast Erase Operations

V

PP

Ground

SS

NC

Not Connected Internally

Ready/Busy Output (RB). The Ready/Busy pin

gives the status of the memory’s Program/Erase

Controller. When Ready/Busy is Low, V , the

OL

Write Protect (WP). The Write Protect input is

used to prevent the Blocks 0 to 48 from being

memory is busy with a Program or Erase operation

and it will not accept any additional Program or

Erase command except the Program/Erase

Suspend command. When Ready/Busy is High,

changed. When Write Protect, WP, is set Low, V ,

IL

Program and Block Erase operations in the Blocks

0 to 48 have no effect, regardless of the state of

the Lock Register. When Write Protect, WP, is set

V

, the memory is ready for any Read, Program

OH

or Erase operation.

Supply Signal Descriptions

The Supply Signals are the same for both interfac-

es.

High, V , the protection of the Block is determined

IH

by the Lock Register. The state of Write Protect,

WP, does not affect the protection of the Top Block

(Block 49).

V

Supply Voltage. The V

Supply Voltage

CC

Write Protect, WP, must be set prior to a Program

or Block Erase operation is initiated and must not

be changed until the operation completes or un-

predictable results may occur. Care should be tak-

en to avoid unpredictable behavior by changing

WP during Program or Erase Suspend.

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is disabled when the V

CC

Supply Voltage is less than the Lockout Voltage,

. This prevents Bus Write operations from

V

LKO

accidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the

memory contents being altered will be invalid.

Reserved for Future Use (RFU). These pins do

not have assigned functions in this revision of the

part. They must be left disconnected.

Address/Address Multiplexed (A/A Mux)

Signal Descriptions

After V

becomes valid the Command Interface

CC

For the Address/Address Multiplexed (A/A Mux)

Interface see Figure 2, Logic Diagram (A/A Mux

Interface), and Table 3, Signal Names (A/A Mux

Interface).

is reset to Read mode.

A 0.1µF capacitor should be connected between

the V Supply Voltage pins and the V Ground

CC

SS

pin to decouple the current surges from the power

Address Inputs (A0-A10). The Address Inputs

are used to set the Row Address bits (A0-A10) and

the Column Address bits (A11-A20). They are

latched during any bus operation by the Row/Col-

umn Address Select input, RC.

supply. Both V Supply Voltage pins must be

CC

connected to the power supply. The PCB track

widths must be sufficient to carry the currents

required during program and erase operations.

5/36

M50LPW116

(1)

Table 4. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

Ambient Operating Temperature (Temperature Range Option 1)

Ambient Operating Temperature (Temperature Range Option 5)

Temperature Under Bias

0 to 70

T

A

–20 to 85

–50 to 125

–65 to 150

°C

T

°C

BIAS

T

Storage Temperature

°C

STG

(2)

–0.6 to V + 0.6

Input or Output Voltage

Supply Voltage

V

CC

IO

V

–0.6 to 4

CC

PP

V

Program Voltage

–0.6 to 13

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Minimum Voltage may undershoot to –2V and for less than 20ns during transitions. Maximum Voltage may overshoot to V +2V

CC

and for less than 20ns during transitions.

V

Optional Supply Voltage. The V Optional

Low Pin Count (LPC) Bus Operations

PP

Supply Voltage pin is used to select the Fast

Program (see the Quadruple Byte Program

Command description) and Fast Erase options of

the memory and to protect the memory. When

The Low Pin Count (LPC) Interface consists of

four data signals (LAD0-LAD3), one control line

(LFRAME) and a clock (CLK). In addition

protection against accidental or malicious data

corruption can be achieved using two further

signals (TBL and WP). Finally two reset signals

(RP and INIT) are available to put the memory into

a known state.

The data signals, control signal and clock are

designed to be compatible with PCI electrical

specifications. The interface operates with clock

speeds up to 33MHz.

The following operations can be performed using

the appropriate bus cycles: Bus Read, Bus Write,

Standby, Reset and Block Protection.

Bus Read. Bus Read operations read from the

memory cells, specific registers in the Command

Interface or Low Pin Count Registers. A valid Bus

Read operation starts when Input Communication

V

< V

Program and Erase operations

PP

PPLK

cannot be performed and an error is reported in

the Status Register if an attempt to change the

memory contents is made. When V

Program and Erase operations take place as

normal. When V = V Fast Program

operations (using the Quadruple Byte Program

command, 30h, from Table 11) and Fast Erase

operations are used. Any other voltage input to

= V

CC

PP

PPH

V

will result in undefined behavior and should

PP

not be used.

V

should not be set to V

for more than 80

PPH

PP

hours during the life of the memory.

V

age measurements.

Ground. V is the reference for all the volt-

SS

Frame, LFRAME, is Low, V , as Clock rises and

IL

BUS OPERATIONS

the correct Start cycle is on LAD0-LAD3. On the

following clock cycles the Host will send the Cycle

Type + Dir, Address and other control bits on

LAD0-LAD3. The memory responds by outputting

Sync data until the wait-states have elapsed

followed by Data0-Data3 and Data4-Data7.

See Table 6, and to Figure 4, for a description of

the Field definitions for each clock cycle of the

transfer. See Table 22, and Figure 9, for details on

the timings of the signals.

The two interfaces have similar bus operations but

the signals and timings are completely different.

The Low Pin Count (LPC) Interface is the usual

interface and all of the functionality of the part is

available through this interface. Only a subset of

functions are available through the Address/

Address Multiplexed (A/A Mux) Interface.

Follow the section Low Pin Count (LPC) Bus

Operations below and the section Address/

Address Multiplexed (A/A Mux) Interface Bus

Operations below for a description of the bus

operations on each interface.

Bus Write. Bus Write operations write to the

Command Interface or Low Pin Count Registers. A

valid Bus Write operation starts when Input

Communication Frame, LFRAME, is Low, V , as

IL

Clock rises and the correct Start cycle is on LAD0-

6/36

M50LPW116

Table 5. Block Addresses

64

4

0A0000h-0AFFFFh

090000h-09FFFFh

080000h-08FFFFh

070000h-07FFFFh

060000h-06FFFFh

050000h-05FFFFh

040000h-04FFFFh

030000h-03FFFFh

020000h-02FFFFh

010000h-01FFFFh

00F000h-00FFFFh

00E000h-00EFFFh

00D000h-00DFFFh

00C000h-00CFFFh

00B000h-00BFFFh

00A000h-00AFFFh

009000h-009FFFh

008000h-008FFFh

007000h-007FFFh

006000h-006FFFh

005000h-005FFFh

004000h-004FFFh

003000h-003FFFh

002000h-002FFFh

001000h-001FFFh

000000h-000FFFh

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

Main

Size

Block

Number

Block

Type

Address Range

(Kbytes)

Main

16

8

1FC000h-1FFFFFh

1FA000h-1FBFFFh

1F8000h-1F9FFFh

1F0000h-1F7FFFh

1E0000h-1EFFFFh

1D0000h-1DFFFFh

1C0000h-1CFFFFh

1B0000h-1BFFFFh

1A0000h-1AFFFFh

190000h-19FFFFh

180000h-18FFFFh

170000h-17FFFFh

160000h-16FFFFh

150000h-15FFFFh

140000h-14FFFFh

130000h-13FFFFh

120000h-12FFFFh

110000h-11FFFFh

100000h-10FFFFh

0F0000h-0FFFFFh

0E0000h-0EFFFFh

0D0000h-0DFFFFh

0C0000h-0CFFFFh

0B0000h-0BFFFFh

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

Boot (Top)

Parameter

Main

8

Main

32

64

Main

Parameter

Main

4

Main

4

Main

4

Main

4

Main

4

Main

4

Main

4

8

Main

4

7

Main

4

6

Main

4

5

Main

4

Main

4

3

Main

4

2

Main

4

1

Main

4

0

Main

Note: For A21 and A23, refer to Table 2. A22 is set to 1.

LAD3. On the following Clock cycles the Host will

send the Cycle Type + Dir, Address, other control

bits, Data0-Data3 and Data4-Data7 on LAD0-

LAD3. The memory outputs Sync data until the

wait-states have elapsed.

See Table 7, and to Figure 5, for a description of

the Field definitions for each clock cycle of the

transfer. See Table 22, and Figure 9, for details on

the timings of the signals.

Note that, during a Bus Write operation, the

Command Interface starts executing the

command as soon as the data is fully received; a

Bus Abort during the final TAR cycles is not

guaranteed to abort the command; the bus,

however, will be released immediately.

Standby. When LFRAME is High, V , the

IH

memory is put into Standby mode where LAD0-

LAD3 are put into a high-impedance state and the

Supply Current is reduced to the Standby level,

Bus Abort. The Bus Abort operation can be used

to immediately abort the current bus operation. A

Bus Abort occurs when LFRAME is driven Low,

I

.

CC1

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high-impedance. The memory is

in Reset mode when Interface Reset, RP, or CPU

V , during the bus operation; the memory will tri-

IL

state the Input/Output Communication pins,

LAD0-LAD3.

Reset, INIT, is Low, V . RP or INIT must be held

IL

7/36

M50LPW116

Table 6. LPC Bus Read Field Definitions

Clock

Clock Cycle

Number

LAD0- Memory

Cycle

Count

Field

Description

LAD3

I/O

On the rising edge of CLK with LFRAME Low, the contents

of LAD0-LAD3 must be 0000b to indicate the start of a

LPC cycle.

1

2

1

START

0000b

I

Indicates the type of cycle and selects 1-byte reading. Bits

3:2 must be 01b. Bit 1 indicates the direction of transfer: 0b

for read. Bit 0 is reset to 0.

CYCTYPE

+ DIR

0100b

I

A 32-bit address phase is transferred starting with the

most significant nibble first. A26-A31 must be set to 1. A22

= 1 for Array, A22 = 0 for registers access. For A21, A23-

A25 values, refers to Table 2.

3-10

8

ADDR

XXXX

1111b

The host drives LAD0-LAD3 to 1111b to indicate a

turnaround cycle.

11

12

1

TAR

I

1111b

(float)

The LPC Flash Memory takes control of LAD0-LAD3

during this cycle.

O

The LPC Flash Memory drives LAD0-LAD3 to 0101b

(short wait-sync) for two clock cycles, indicating that the

data is not yet available. Two wait-states are always

included.

13-14

15

2

1

WSYNC

RSYNC

0101b

0000b

O

The LPC Flash Memory drives LAD0-LAD3 to 0000b,

indicating that data will be available during the next clock

cycle.

Data transfer is two CLK cycles, starting with the least

significant nibble.

16-17

18

2

1

DATA

TAR

XXXX

1111b

O

The LPC Flash Memory drives LAD0-LAD3 to 1111b to

indicate a turnaround cycle.

1111b

(float)

The LPC Flash Memory floats its outputs, the host takes

control of LAD0-LAD3.

19

N/A

Figure 4. LPC Bus Read Waveforms

CLK

LFRAME

CYCTYPE

+ DIR

LAD0-LAD3

START

1

ADDR

8

TAR

2

SYNC

3

DATA

2

TAR

2

Number of

clock cycles

1

AI04429

8/36

M50LPW116

Table 7. LPC Bus Write Field Definitions

Clock

Cycle

Number Count

Clock

Cycle

LAD0-

LAD3

Memory

I/O

Field

Description

On the rising edge of CLK with LFRAME Low, the contents

of LAD0-LAD3 must be 0000b to indicate the start of a LPC

cycle.

1

2

1

START

0000b

011Xb

I

CYCTY

PE +

DIR

Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1

indicates the direction of transfer: 1b for write. Bit 0 is don’t

care (X).

A 32-bit address phase is transferred starting with the most

significant nibble first. A26-A31 must be set to 1. A22 = 1 for

Array, A22 = 0 for registers access. For A21, A23-A25

values, refers to Table 2.

3-10

8

ADDR

XXXX

I

Data transfer is two cycles, starting with the least significant

nibble.

11-12

13

2

1

DATA

TAR

XXXX

1111b

I

The host drives LAD0-LAD3 to 1111b to indicate a

turnaround cycle.

1111b

(float)

The LPC Flash Memory takes control of LAD0-LAD3 during

this cycle.

14

TAR

O

The LPC Flash Memory drives LAD0-LAD3 to 0000b,

indicating it has received data or a command.

15

SYNC

TAR

0000b

1111b

O

The LPC Flash Memory drives LAD0-LAD3 to 1111b,

indicating a turnaround cycle.

16

O

1111b

(float)

The LPC Flash Memory floats its outputs and the host takes

control of LAD0-LAD3.

17

TAR

N/A

Figure 5. LPC Bus Write Waveforms

CLK

LFRAME

CYCTYPE

+ DIR

LAD0-LAD3

START

1

ADDR

8

DATA

2

TAR

2

SYNC

1

TAR

2

Number of

clock cycles

1

AI04430

Low, V , for t

. The memory resets to Read

PLPH

Write Protect, WP, regardless of the state of the

Lock Registers.

Address/Address Multiplexed (A/A Mux) Bus

Operations

The Address/Address Multiplexed (A/A Mux)

Interface has a more traditional style interface.

The signals consist of a multiplexed address

signals (A0-A10), data signals, (DQ0-DQ7) and

three control signals (RC, G, W). An additional

signal, RP, can be used to reset the memory.

IL

mode upon return from Reset mode and the Lock

Registers return to their default states regardless

of their state before Reset, see Table 15. If RP or

INIT goes Low, V , during a Program or Erase

operation, the operation is aborted and the

memory cells affected no longer contain valid

data; the memory can take up to t

Program or Erase operation.

Block Protection. Block Protection can be

IL

to abort a

PLRH

forced using the signals Top Block Lock, TBL, and

9/36

M50LPW116

Table 8. A/A Mux Bus Operations

V

Operation

Bus Read

G

W

RP

DQ7-DQ0

Data Output

Data Input

Hi-Z

PP

V

IH

V

IH

Don’t Care

V or V

CC

IL

IH

V

IL

V

IH

Bus Write

Output Disable

Reset

PPH

V

IH

V

IH

Don’t Care

V

or V

V

IL

or V

V

Hi-Z

IL

IH

IL

Table 9. Manufacturer and Device Codes

Operation

Manufacturer Code

Device Code

G

W

RP

A20-A1

A0

DQ7-DQ0

20h

V

IL

V

IH

V

IH

V

IL

V

IH

V

IH

V

IH

30h

IL

The Address/Address Multiplexed (A/A Mux)

Interface is included for use by Flash

Programming equipment for faster factory

programming. Only a subset of the features

available to the Low Pin Count (LPC) Interface are

available; these include all the Commands but

exclude the Security features and other registers.

Output Disable. The data outputs are high-im-

pedance when the Output Enable, G, is at V .

IH

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high-impedance. The memory is

in Reset mode when RP is Low, V . RP must be

IL

held Low, V for t

. If RP is goes Low, V ,

IL

PLPH

IL

The following operations can be performed using

the appropriate bus cycles: Bus Read, Bus Write,

Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux)

Interface is selected all the blocks are

unprotected. It is not possible to protect any blocks

through this interface.

Bus Read. Bus Read operations are used to

output the contents of the Memory Array, the

Electronic Signature and the Status Register. A

valid Bus Read operation begins by latching the

Row Address and Column Address signals into

the memory using the Address Inputs, A0-A10,

and the Row/Column Address Select RC. Then

Write Enable (W) and Interface Reset (RP) must

during a Program or Erase operation, the

operation is aborted and the memory cells affected

no longer contain valid data; the memory can take

up to t

to abort a Program or Erase operation.

PLRH

COMMAND INTERFACE

All Bus Write operations to the memory are

interpreted

by

the

Command

Interface.

Commands consist of one or more sequential Bus

Write operations.

After power-up or a Reset operation the memory

enters Read mode.

The commands are summarized in Table 11,

Commands. Refer to Table 11 in conjunction with

the text descriptions below.

be High, V , and Output Enable, G, Low, V , in

IH

IL

Read Memory Array Command. The Read Mem-

ory Array command returns the memory to its

Read mode where it behaves like a ROM or

EPROM. One Bus Write cycle is required to issue

the Read Memory Array command and return the

memory to Read mode. Once the command is is-

sued the memory remains in Read mode until an-

other command is issued. From Read mode Bus

Read operations will access the memory array.

While the Program/Erase Controller is executing a

Program or Erase operation the memory will not

accept the Read Memory Array command until the

operation completes.

order to perform a Bus Read operation. The Data

Inputs/Outputs will output the value, see Figure

11, A/A Mux Interface Read AC Waveforms, and

Table 24, for details of when the output becomes

valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by latching the Row Address and Column

Address signals into the memory using the

Address Inputs, A0-A10, and the Row/Column

Address Select RC. The data should be set up on

the Data Inputs/Outputs; Output Enable, G, and

Interface Reset, RP, must be High, V and Write

IH

Read Status Register Command. The Read Sta-

tus Register command is used to read the Status

Register. One Bus Write cycle is required to issue

the Read Status Register command. Once the

Enable, W, must be Low, V . The Data Inputs/

IL

Outputs are latched on the rising edge of Write

Enable, W. See Figure 12, and Table 25, for

details of the timing requirements.

10/36

M50LPW116

command is issued subsequent Bus Read opera-

tions read the Status Register until another com-

mand is issued. See the section on the Status

Register for details on the definitions of the Status

Register bits.

Table 10. Read Electronic Signature

Code

Manufacturer Code

Device Code

Address

000000h

000001h

Data

20h

30h

Read Electronic Signature Command. The Read

Electronic Signature command is used to read the

Manufacturer Code and the Device Code. One

Bus Write cycle is required to issue the Read

Electronic Signature command. Once the

command is issued subsequent Bus Read

operations read the Manufacturer Code or the

Device Code until another command is issued.

After the Read Electronic Signature Command is

issued the Manufacturer Code and Device Code

can be read using Bus Read operations using the

addresses in Table 10.

Program Command. The Program command

can be used to program a value to one address in

the memory array at a time. Two Bus Write

operations are required to issue the command; the

second Bus Write cycle latches the address and

data in the internal state machine and starts the

Program/Erase Controller. Once the command is

issued subsequent Bus Read operations read the

Status Register. See the section on the Status

Register for details on the definitions of the Status

Register bits.

If the address falls in a protected block then the

Program operation will abort, the data in the

memory array will not be changed and the Status

Register will output the error.

During the Program operation the memory will

only accept the Read Status Register command

and the Program/Erase Suspend command. All

other commands will be ignored. Typical Program

times are given in Table 12.

Note that the Program command cannot change a

bit set at ‘0’ back to ‘1’ and attempting to do so will

not cause any modification on its value. One of the

Erase commands must be used to set all of the

bits in the block to ‘1’.

See Figure 13, for a suggested flowchart on using

the Program command.

Program/Erase Controller. Once the command is

issued subsequent Bus Read operations read the

Status Register. See the section on the Status

Register for details on the definitions of the Status

Register bits.

During the Quadruple Byte Program operation the

memory will only accept the Read Status register

command and the Program/Erase Suspend com-

mand. All other commands will be ignored. Typical

Quadruple Byte Program times are given in Table

12.

Note that the Quadruple Byte Program command

cannot change a bit set to ‘0’ back to ‘1’ and

attempting to do so will not cause any modification

on its value. One of the Erase commands must be

used to set all of the bits in the block to ‘1’.

See Figure 14, for a suggested flowchart on using

the Quadruple Byte Program command.

Chip Erase Command. The Chip Erase Com-

mand can be only used in A/A Mux mode to erase

the entire chip at a time. Erasing should not be at-

tempted when V is not at V

. The operation

PP

PPH

can also be executed if V is below V

, but re-

PPH

PP

sult could be uncertain. Two Bus Write operations

are required to issue the command and start the

Program/Erase Controller. Once the command is

issued subsequent Bus Read operations read the

Status Register. See the section on the Status

Register for details on the definitions of the Status

Register bits. During the Chip Erase operation the

memory will only accept the Read Status Register

command. All other commands will be ignored.

Typical Chip Erase times are given in Table 12.

The Chip Erase command sets all of the bits in the

memory to ‘1’. See Figure 16, Chip Erase Flow-

chart and Pseudo Code (A/A Mux Interface Only),

for a suggested flowchart on using the Chip Erase

command.

Block Erase Command. The Block Erase com-

mand can be used to erase a block. Two Bus Write

operations are required to issue the command; the

second Bus Write cycle latches the block address

in the internal state machine and starts the Pro-

gram/Erase Controller. Once the command is is-

sued subsequent Bus Read operations read the

Status Register. See the section on the Status

Register for details on the definitions of the Status

Register bits.

Quadruple Byte Program Command (A/A Mux

Mode). The Quadruple Byte Program Command

can be used to program four adjacent bytes in the

memory array at a time. The four bytes must differ

only for the addresses A0 and A1. Programming

should not be attempted when V is not at V

.

PP

PPH

Five Bus Write operations are required to issue the

command. The second, the third and the fourth

Bus Write cycle latches respectively the address

and data of the first, the second and the third byte

in the internal state machine. The fifth Bus Write

cycle latches the address and data of the fourth

byte in the internal state machine and starts the

If the block is protected then the Block Erase

operation will abort, the data in the block will not be

11/36

M50LPW116

Table 11. Commands

Bus Write Operations

3rd

Command

1st

2nd

4th

5th

Addr Data Addr Data Addr Data Addr Data Addr Data

Read Memory Array

Read Status Register

1

2

X

FFh

70h

90h

98h

40h

10h

Read Electronic Signature

Program

PA

PD

Quadruple Byte Program

(A/A Mux Mode)

A

1

A

2

A

4

5

X

30h

PD

3

Chip Erase

2

1

X

80h

20h

50h

B0h

D0h

00h

01h

60h

2Fh

C0h

X

10h

D0h

Block Erase

BA

Clear Status Register

Program/Erase Suspend

Program/Erase Resume

Invalid/Reserved

Note: X Don’t Care, PA Program Address, PD Program Data, A

Consecutive Addresses, BA Any address in the Block.

1,2,3,4

Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued.

Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued.

Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another com-

mand is issued.

Block Erase, Program. After these commands read the Status Register until the command completes and another command is is-

sued.

Quadruple Byte Program (A/A Mux Mode). Addresses A , A , A and A must be consecutive addresses differing only for address

1

2

3

4

bit A0 and A1. After this command, the user should repeatedly read the Status Register until the command has completed, at which

point another command can be issued.

Chip Erase. This command is only valid in A/A Mux mode. After this command read the Status Register until the command completes

and another command is issued.

Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’.

Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status

Register, Program (during Erase suspend) and Program/Erase resume commands.

Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the

Status Register until the Program/Erase Controller completes and the memory returns to Read Mode.

Invalid/Reserved. Do not use Invalid or Reserved commands.

12/36

M50LPW116

Table 12. Program and Erase Times

(T = 0 to 70°C or –20 to 85°C; V = 3.0 to 3.6V)

A

CC

(1)

Parameter

Interface

Test Condition

Min

Max

200

Unit

µs

Typ

10

Byte Program

(4)

V

= 12V ± 5%

= V

Quadruple Byte Program

A/A Mux

µs

PP

10

Chip Erase

18

sec

µs

(2)

0.1

5

Block Program (64 Kbytes)

Block Erase (64 Kbytes)

V

0.4

PP

CC

V

= 12V ± 5%

= V

0.75

1

8

PP

V

10

5

PP

CC

(3)

Program/Erase Suspend to Program pause

(3)

30

µs

Program/Erase Suspend to Block Erase pause

Note: 1. T = 25°C, V = 3.3V

A

CC

2. This time is obtained executing the Quadruple Byte Program Command.

3. Sampled only, not 100% tested.

4. Time to program four bytes.

changed and the Status Register will output the

error.

During the Block Erase operation the memory will

only accept the Read Status Register command

and the Program/Erase Suspend command. All

other commands will be ignored. Typical Block

Erase times are given in Table 12.

Controller Status bit to find out when the Program/

Erase Controller has paused; no other commands

will be accepted until the Program/Erase Control-

ler has paused. After the Program/Erase Control-

ler has paused, the memory will continue to output

the Status Register until another command is is-

sued.

During the polling period between issuing the

Program/Erase Suspend command and the

Program/Erase Controller pausing it is possible for

the operation to complete. Once Program/Erase

Controller Status bit indicates that the Program/

Erase Controller is no longer active, the Program

Suspend Status bit or the Erase Suspend Status

bit can be used to determine if the operation has

completed or is suspended. For timing on the

delay between issuing the Program/Erase

Suspend command and the Program/Erase

Controller pausing see Table 12.

During Program/Erase Suspend the Read

Memory Array, Read Status Register, Read

Electronic Signature and Program/Erase Resume

commands will be accepted by the Command

Interface. Additionally, if the suspended operation

was Block Erase then the Program command will

also be accepted; only the blocks not being erased

may be read or programmed correctly.

The Block Erase command sets all of the bits in

the block to ‘1’. All previous data in the block is

lost.

See Figure 17, Block Erase Flowchart and Pseudo

Code, for a suggested flowchart on using the

Erase command.

Clear Status Register Command. The Clear Sta-

tus Register command can be used to reset bits 1,

3, 4 and 5 in the Status Register to ‘0’. One Bus

Write is required to issue the Clear Status Register

command. Once the command is issued the mem-

ory returns to its previous mode, subsequent Bus

Read operations continue to output the same data.

The bits in the Status Register are sticky and do

not automatically return to ‘0’ when a new Program

or Erase command is issued. If an error occurs

then it is essential to clear any error bits in the Sta-

tus Register by issuing the Clear Status Register

command before attempting a new Program or

Erase command.

See Figure 15, Program Suspend and Resume

Flowchart and Pseudo Code, and Figure 18,

Erase Suspend & Resume Flowchart and Pseudo

Code, for suggested flowcharts on using the

Program/Erase Suspend command.

Program/Erase Suspend Command. The

Pro-

gram/Erase Suspend command can be used to

pause a Program or Block Erase operation. One

Bus Write cycle is required to issue the Program/

Erase Suspend command and pause the Pro-

gram/Erase Controller. Once the command is is-

sued it is necessary to poll the Program/Erase

Program/Erase Resume Command. The

gram/Erase Resume command can be used to re-

start the Program/Erase Controller after

Pro-

a

13/36

M50LPW116

Table 13. Status Register Bits

Operation

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

(1)

Program active

‘0’

‘1

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

X

(1)

Program suspended

Program completed successfully

‘1’

Program failure due to V Error

PP

Program failure due to Block Protection (LPC Interface only)

Program failure due to cell failure

Erase active

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

Block Erase suspended

Erase completed successfully

‘1’

‘0’

Erase failure due to V Error

PP

Block Erase failure due to Block Protection (LPC Interface

only)

‘1’

‘0’

‘1’

Erase failure due to failed cell(s)

Sequence command error

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.

Program/Erase Suspend has paused it. One Bus

Write cycle is required to issue the Program/Erase

Resume command. Once the command is issued

subsequent Bus Read operations read the Status

Register.

es. After the Program/Erase Controller pauses the

bit is ‘1’.

During Program and Erase operation the Pro-

gram/Erase Controller Status bit can be polled to

find the end of the operation. The other bits in the

Status Register should not be tested until the Pro-

gram/Erase Controller completes the operation

and the bit is ‘1’.

STATUS REGISTER

The Status Register provides information on the

current or previous Program or Erase operation.

Different bits in the Status Register convey

different information and errors on the operation.

To read the Status Register the Read Status

Register command can be issued. The Status

Register is automatically read after Program,

Erase and Program/Erase Resume commands

are issued. The Status Register can be read from

any address.

The Status Register bits are summarized in Table

13, Status Register Bits. Refer to Table 13 in con-

junction with the text descriptions below.

Program/Erase Controller Status (Bit 7). The Pro-

gram/Erase Controller Status bit indicates whether

the Program/Erase Controller is active or inactive.

When the Program/Erase Controller Status bit is

‘0’, the Program/Erase Controller is active; when

the bit is ‘1’, the Program/Erase Controller is inac-

tive.

After the Program/Erase Controller completes its

operation the Erase Status, Program Status, V

PP

Status and Block Protection Status bits should be

tested for errors.

Erase Suspend Status (Bit 6). The Erase Sus-

pend Status bit indicates that a Block Erase oper-

ation has been suspended and is waiting to be

resumed. The Erase Suspend Status should only

be considered valid when the Program/Erase

Controller Status bit is ‘1’ (Program/Erase Control-

ler inactive); after a Program/Erase Suspend com-

mand is issued the memory may still complete the

operation rather than entering the Suspend mode.

When the Erase Suspend Status bit is ‘0’ the Pro-

gram/Erase Controller is active or has completed

its operation; when the bit is ‘1’ a Program/Erase

Suspend command has been issued and the

memory is waiting for a Program/Erase Resume

command.

The Program/Erase Controller Status is ‘0’ imme-

diately after a Program/Erase Suspend command

is issued until the Program/Erase Controller paus-

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns to ‘0’.

14/36

M50LPW116

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has applied the

maximum number of erase pulses to the block(s)

and still failed to verify that the block(s) has erased

correctly. The Erase Status bit should be read

once the Program/Erase Controller Status bit is ‘1’

(Program/Erase Controller inactive).

When the Erase Status bit is ‘0’ the memory has

successfully verified that the block(s) has erased

correctly; when the Erase Status bit is ‘1’ the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the block(s) and still failed to

verify that the block(s) has erased correctly.

Once the Erase Status bit is set to ‘1’ it can only be

reset to ‘0’ by a Clear Status Register command or

a hardware reset. If it is set to ‘1’ it should be reset

before a new Program or Erase command is is-

sued, otherwise the new command will appear to

fail. (When Bit 4 and Bit 5 are set to ‘1’, a wrong

command sequence has been attempted).

Program Status (Bit 4). The Program Status bit

can be used to identify if the memory has applied

the maximum number of program pulses to the

byte and still failed to verify that the byte has pro-

grammed correctly. The Program Status bit should

be read once the Program/Erase Controller Status

bit is ‘1’ (Program/Erase Controller inactive).

When the Program Status bit is ‘0’ the memory has

successfully verified that the byte has pro-

grammed correctly; when the Program Status bit is

‘1’ the Program/Erase Controller has applied the

maximum number of pulses to the byte and still

failed to verify that the byte has programmed cor-

rectly.

Once the Program Status bit is set to ‘1’ it can only

be reset to ‘0’ by a Clear Status Register com-

mand or a hardware reset. If it is set to ‘1’ it should

be reset before a new Program or Erase command

is issued, otherwise the new command will appear

to fail. (When Bit 4 and Bit 5 are set to ‘1’, a wrong

command sequence has been attempted).

Once the V Status bit set to ‘1’ it can only be re-

PP

set to ‘0’ by a Clear Status Register command or a

hardware reset. If it is set to ‘1’ it should be reset

before a new Program or Erase command is is-

sued, otherwise the new command will appear to

fail.

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper-

ation has been suspended and is waiting to be re-

sumed. The Program Suspend Status should only

be considered valid when the Program/Erase

Controller Status bit is ‘1’ (Program/Erase Control-

ler inactive); after a Program/Erase Suspend com-

mand is issued the memory may still complete the

operation rather than entering the Suspend mode.

When the Program Suspend Status bit is ‘0’ the

Program/Erase Controller is active or has complet-

ed its operation; when the bit is ‘1’ a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns to

‘0’.

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identify if the Pro-

gram or Block Erase operation has tried to modify

the contents of a protected block. When the Block

Protection Status bit is to ‘0’ no Program or Block

Erase operations have been attempted to protect-

ed blocks since the last Clear Status Register

command or hardware reset; when the Block Pro-

tection Status bit is ‘1’ a Program or Block Erase

operation has been attempted on a protected

block.

Once it is set to ‘1’ the Block Protection Status bit

can only be reset to ‘0’ by a Clear Status Register

command or a hardware reset. If it is set to ‘1’ it

should be reset before a new Program or Block

Erase command is issued, otherwise the new

command will appear to fail.

V

Status (Bit 3). The V

Status bit can be

PP

Using the A/A Mux Interface the Block Protection

Status bit is always ‘0’.

PP

used to identify an invalid voltage on the V pin

PP

during Program and Erase operations. The V

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

PP

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value should be masked.

cur if V

Erase operation.

becomes invalid during a Program or

PP

LOW PIN COUNT (LPC) INTERFACE

CONFIGURATION REGISTERS

When the V Status bit is ‘0’ the voltage on the

PP

When the Low Pin Count Interface is selected sev-

eral additional registers can be accessed. These

registers control the protection status of the Blocks

and read the General Purpose Input pins. See Ta-

ble 14 for an example of the Register Configura-

tion map, valid for the boot memory, i.e. ID0-ID3

V

pin was sampled at a valid voltage; when the

PP

Status bit is ‘1’ the V pin has a voltage that

PP

is below the V

Lockout Voltage, V

, the

PP

PPLK

memory is protected; Program and Erase opera-

tion cannot be performed. (The V status bit is ‘1’

PP

if a Quadruple Byte Program command is issued

floating or driven L , V and A21, A23-A25 set

OW

IL

and the V signal has a voltage less than V

PP

PPH

to ‘1’.

applied to it.)

15/36

M50LPW116

(1)

Table 14. Low Pin Count Register Configuration Map

Memory

Address

Default

Value

Mnemonic

Register Name

Access

T_BLOCK_LK

Top Block Lock Register (Block 49)

FFBFC002h

FFBFA002h

FFBF8002h

FFBF0002h

FFBE0002h

FFBD0002h

FFBC0002h

FFBB0002h

FFBA0002h

FFB90002h

FFB80002h

FFB70002h

FFB60002h

FFB50002h

FFB40002h

FFB30002h

FFB20002h

FFB10002h

FFB00002h

FFAF0002h

FFAE0002h

FFAD0002h

FFAC0002h

FFAB0002h

FFAA0002h

FFA90002h

FFA80002h

FFA70002h

FFA60002h

FFA50002h

FFA40002h

FFA30002h

FFA20002h

FFA10002h

FFA00002h

FFBC0000h

FFBC0001h

FFBC0100h

01h

20h

30h

N/A

R/W

R

T_MINUS01_LK Top Block[-01] Lock Register (Block 48)

T_MINUS02_LK Top Block[-02] Lock Register (Block 47)

T_MINUS03_LK Top Block[-03] Lock Register (Block 46)

T_MINUS04_LK Top Block[-04] Lock Register (Block 45)

T_MINUS05_LK Top Block[-05] Lock Register (Block 44)

T_MINUS06_LK Top Block[-06] Lock Register (Block 43)

T_MINUS07_LK Top Block[-07] Lock Register (Block 42)

T_MINUS08_LK Top Block[-08] Lock Register (Block 41)

T_MINUS09_LK Top Block[-09] Lock Register (Block 40)

T_MINUS00_LK Top Block[-10] Lock Register (Block 39)

T_MINUS11_LK Top Block[-11] Lock Register (Block 38)

T_MINUS12_LK Top Block[-12] Lock Register (Block 37)

T_MINUS13_LK Top Block[-13] Lock Register (Block 36)

T_MINUS14_LK Top Block[-14] Lock Register (Block 35)

T_MINUS15_LK Top Block[-15] Lock Register (Block 34)

T_MINUS16_LK Top Block[-16] Lock Register (Block 33)

T_MINUS17_LK Top Block[-17] Lock Register (Block 32)

T_MINUS18_LK Top Block[-18] Lock Register (Block 31)

T_MINUS19_LK Top Block[-19] Lock Register (Block 30)

T_MINUS20_LK Top Block[-20] Lock Register (Block 29)

T_MINUS21_LK Top Block[-21] Lock Register (Block 28)

T_MINUS22_LK Top Block[-22] Lock Register (Block 27)

T_MINUS23_LK Top Block[-23] Lock Register (Block 26)

T_MINUS24_LK Top Block[-24] Lock Register (Block 25)

T_MINUS25_LK Top Block[-25] Lock Register (Block 24)

T_MINUS26_LK Top Block[-26] Lock Register (Block 23)

T_MINUS27_LK Top Block[-27] Lock Register (Block 22)

T_MINUS28_LK Top Block[-28] Lock Register (Block 21)

T_MINUS29_LK Top Block[-29] Lock Register (Block 20)

T_MINUS30_LK Top Block[-30] Lock Register (Block 19)

T_MINUS31_LK Top Block[-31] Lock Register (Block 18)

T_MINUS32_LK Top Block[-32] Lock Register (Block 17)

T_MINUS33_LK Top Block[-33] Lock Register (Block 16)

T_MINUS34_LK Top Block[-34] Lock Register (Block 15 to 0)

MANUF_REG

DEV_REG

GPI_REG

Manufacturer Code Register

Device Code Register

R

General Purpose Input Register

R

Note: 1. This map is referred to the boot memory (ID0-ID3 floating or driven Low, V , and A21,A23-A25 set to ‘1’).

IL

16/36

M50LPW116

(1)

Table 15. Lock Register Bit Definitions

Bit

Bit Name

Value

Function

7-3

Reserved

Bus Read operations in this Block always return 00h.

‘1’

‘0’

2

Read-Lock

Bus read operations in this Block return the Memory Array contents. (Default

value).

Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a

‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset

to ‘0’ following a Reset (using RP or INIT) or after power-up.

‘1’

1

Lock-Down

Write-Lock

Read-Lock and Write-Lock can be changed by writing new values to them. (Default

value).

‘0’

‘1’

‘0’

Program and Block Erase operations in this Block will set an error in the Status

Register. The memory contents will not be changed. (Default value).

0

Program and Block Erase operations in this Block are executed and will modify the

Block contents.

Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-34] Lock

Register (T_MINUS34_LK).

(1)

Table 16. General Purpose Input Register Definition

Bit

Bit Name

Value

Function

7-5

Reserved

Input Pin GPI4 is at V

Input Pin GPI3 is at V

Input Pin GPI2 is at V

Input Pin GPI1 is at V

Input Pin GPI0 is at V

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

IH

IL

IH

IL

IH

IL

IH

IL

IH

IL

4

3

2

1

0

GPI4

GPI3

GPI2

GPI1

GPI0

Note: 1. Applies to the General Purpose Input Register (GPI_REG).

17/36

M50LPW116

Lock Registers

The Lock Registers control the protection status of

the Blocks. Each Block has its own Lock Register.

Blocks 0 to 15 have the same Lock Register.

Three bits within each Lock Register control the

protection of each block, the Write Lock Bit, the

Read Lock Bit and the Lock Down Bit.

The Lock Registers can be read and written,

though care should be taken when writing as, once

the Lock Down Bit is set, ‘1’, further modifications

to the Lock Register cannot be made until cleared,

to ‘0’, by a reset or power-up.

See Table 15 for details on the bit definitions of the

Lock Registers.

Lock Down. The Lock Down Bit provides a

mechanism for protecting software data from sim-

ple hacking and malicious attack. When the Lock

Down Bit is set, ‘1’, further modification to the

Write Lock, Read Lock and Lock Down Bits cannot

be performed. A reset or power-up is required be-

fore changes to these bits can be made. When the

Lock Down Bit is reset, ‘0’, the Write Lock, Read

Lock and Lock Down Bits can be changed.

General Purpose Input Register

The General Purpose Input Register holds the

state of the General Purpose Input pins, GPI0-

GPI4. When this register is read, the state of these

pins is returned. This register is read-only and writ-

ing to it has no effect.

Write Lock. The Write Lock Bit determines

whether the contents of the Block can be modified

(using the Program or Block Erase Command).

When the Write Lock Bit is set, ‘1’, the block is

write protected; any operations that attempt to

change the data in the block will fail and the Status

Register will report the error. When the Write Lock

Bit is reset, ‘0’, the block is not write protected

through the Lock Register and may be modified

unless write protected through some other means.

The signals on the General Purpose Input pins

should remain constant throughout the whole Bus

Read cycle in order to guarantee that the correct

data is read.

When V

is less than V

all blocks are pro-

PP

PPLK

tected and cannot be modified, regardless of the

state of the Write Lock Bit. If Top Block Lock, TBL,

is Low, V , then the Top Block (Block 49) is write

IL

protected and cannot be modified. Similarly, if

Write Protect, WP, is Low, V , then the Blocks 0

IL

to 48 are write protected and cannot be modified.

After power-up or reset the Write Lock Bit is al-

ways set to ‘1’ (write protected).

Read Lock. The Read Lock bit determines

whether the contents of the Block can be read

(from Read mode). When the Read Lock Bit is set,

‘1’, the block is read protected; any operation that

attempts to read the contents of the block will read

00h instead. When the Read Lock Bit is reset, ‘0’,

read operations in the Block return the data pro-

grammed into the block as expected.

After power-up or reset the Read Lock Bit is al-

ways reset to ‘0’ (not read protected).

18/36

M50LPW116

Table 17. LPC Interface AC Measurement Conditions

Parameter

Value

3.0 to 3.6

10

Unit

V

CC

Supply Voltage

Load Capacitance (C )

pF

ns

L

Input Rise and Fall Times

≤ 1.4

0.2 V and 0.6 V

Input Pulse Voltages

V

CC

0.4 V

Input and Output Timing Ref. Voltages

CC

Figure 6. LPC Interface AC Testing Input Output Waveforms

0.6 V

CC

0.4 V

CC

0.2 V

CC

Input and Output AC Testing Waveform

I

< I

I

> I

I

< I

O LO

O

LO

O

LO

Output AC Tri-state Testing Waveform

AI03404

19/36

M50LPW116

Table 18. A/A Mux Interface AC Measurement Conditions

Parameter

Value

3.0 to 3.6

30

Unit

V

CC

Supply Voltage

Load Capacitance (C )

pF

ns

V

L

Input Rise and Fall Times

≤ 10

Input Pulse Voltages

0 to 3

1.5

Input and Output Timing Ref. Voltages

V

Figure 7. A/A Mux Interface AC Testing Input Output Waveform

3V

0V

1.5V

AI01417

Table 19. Impedance

(T = 25 °C, f = 1 MHz)

A

Symbol

Parameter

Test Condition

Min

Max

Unit

(1)

V

= 0V

Input Capacitance

Clock Capacitance

13

12

pF

C

IN

(1)

CLK

3

pF

nH

C

L

Recommended Pin

Inductance

(2)

20

Note: 1. Sampled only, not 100% tested.

2. See PCI Specification.

20/36

M50LPW116

Table 20. DC Characteristics

(T = 0 to 70°C or –20 to 85°C; V = 3.0 to 3.6V)

A

CC

Symbol

Parameter

Interface

LPC

Test Condition

Min

Max

Unit

V

0.5 V

V

+ 0.5

CC

V

IH

Input High Voltage

0.7 V

+ 0.3

A/A Mux

LPC

V

CC

0.3 V

–0.5

-0.5

1.35

–0.5

V

CC

V

IL

Input Low Voltage

A/A Mux

LPC

0.8

+ 0.5

V

IH

(INIT)

V

CC

INIT Input High Voltage

INIT Input Low Voltage

Input Leakage Current

V

V (INIT)

IL

0.2 V

CC

LPC

V

(2)

0V ≤ V ≤ V

±10

µA

I

LI

IN

CC

IC, IDx Input Leakage

Current

I

IC, ID0, ID1, ID2, ID3 = V

CC

200

LI2

IC, IDx Input Pull Low

Resistor

R

20

100

kΩ

IL

0.9 V

LPC

A/A Mux

LPC

I

= –500µA

= –100µA

= 1.5mA

= 1.8mA

V

CC

OH

V

Output High Voltage

OH

V

CC

– 0.4

OH

I

OL

0.1 V

V

CC

V

Output Low Voltage

OL

I

A/A Mux

0.45

±10

3.6

V

OL

I

0V ≤ V

≤ V

OUT CC

Output Leakage Current

µA

V

LO

V

PP1

V

PP

Voltage

3

V

Voltage (Fast

PP

V

11.4

12.6

V

PPH

Program/Fast Erase)

(1)

V

Lockout Voltage

1.5

1.8

V

PP

CC

PPLK

(1)

V

2.3

V

LKO

LFRAME = 0.9 V , V = V

CC

PP

I

All other inputs 0.9 V to 0.1 V

CC

Supply Current (Standby)

LPC

100

µA

mA

CC1

CC

V

CC

= 3.6V, f(CLK) = 33MHz

LFRAME = 0.1 V , V = V

CC

PP

CC

I

All other inputs 0.9 V to 0.1 V

CC

10

60

CC2

CC

V

CC

= 3.6V, f(CLK) = 33MHz

V

CC

= V max, V = V

Supply Current

(Any internal operation

active)

CC

PP

CC

f(CLK) = 33MHz

= 0mA

I

CC3

I

OUT

G = V , f = 6MHz

Supply Current (Read)

A/A Mux

20

mA

CC4

IH

Supply Current

(Program/Erase)

(1)

Program/Erase Controller Active

I

CC5

V

Supply Current

PP

I

V

> V

400

µA

PP

CC

(Read/Standby)

= V

5

µA

PP

CC

V

PP

Supply Current

(1)

PP1

(Program/Erase active)

V

= 12V ± 5%

15

mA

PP

Note: 1. Sampled only, not 100% tested.

2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.

21/36

M50LPW116

Table 21. LPC Interface Clock Characteristics

(T = 0 to 70°C or –20 to 85°C; V = 3.0 to 3.6V)

A

CC

Symbol

Parameter

Test Condition

Value

Unit

(1)

t

Min

30

ns

CYC

CLK Cycle Time

t

CLK High Time

CLK Low Time

Min

Max

11

1

ns

HIGH

t

LOW

V/ns

CLK Slew Rate

peak to peak

4

Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed

by design rather than tested. Refer to PCI Specification.

Figure 8. LPC Interface Clock Waveform

tCYC

tHIGH

tLOW

0.6 V

0.5 V

0.4 V

0.3 V

0.2 V

CC

0.4 V

,

CC p-to-p

(minimum)

AI03403

22/36

M50LPW116

Table 22. LPC Interface AC Signal Timing Characteristics

(T = 0 to 70°C or –20 to 85°C; V

A

= 3.0 to 3.6V)

CC

PCI

Symbol

Parameter

Test Condition

Value

Unit

Min

2

ns

t

val

CLK to Data Out

CHQV

Max

11

CLK to Active

(Float to Active Delay)

(1)

t

Min

Max

Min

2

28

7

ns

t

on

CHQX

CLK to Inactive

(Active to Float Delay)

t

off

CHQZ

t

AVCH

DVCH

(2)

t

su

Input Set-up Time

t

CHAX

CHDX

(2)

t

h

Min

0

ns

Input Hold Time

Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current spec-

ification.

2. Applies to all inputs except CLK.

Figure 9. LPC Interface AC Signal Timing Waveforms

CLK

tCHQV

tCHQZ

tCHQX

tDVCH

tCHDX

VALID

LAD0-LAD3

VALID OUTPUT DATA

FLOAT OUTPUT DATA

VALID INPUT DATA

AI04431

23/36

M50LPW116

Table 23. Reset AC Characteristics

(T = 0 to 70°C or –20 to 85°C; V = 3.0 to 3.6V)

A

CC

Symbol

Parameter

Test Condition

Value

100

30

Unit

ns

t

RP or INIT Reset Pulse Width

Min

Max

Min

PLPH

Program/Erase Inactive

Program/Erase Active

Rising edge only

ns

t

RP or INIT Low to Reset

PLRH

µs

(1)

50

mV/ns

RP or INIT Slew Rate

t

RP or INIT High to LFRAME Low

LPC Interface only

Min

30

50

µs

PHFL

t

RP High to Write Enable or Output

Enable Low

PHWL

A/A Mux Interface only

t

PHGL

Note: 1. See Chapter 4 of the PCI Specification.

Figure 10. Reset AC Waveforms

RP, INIT

tPHWL, tPHGL, tPHFL

tPLPH

W, G, LFRAME

RB

tPLRH

AI04432

24/36

M50LPW116

Table 24. A/A Mux Interface Read AC Characteristics

(T = 0 to 70°C or –20 to 85°C; V = 3.0 to 3.6V)

A

CC

Symbol

Parameter

Test Condition

Value

Unit

ns

t

Read Cycle Time

Min

250

50

AVAV

t

Row Address Valid to RC Low

ns

AVCL

t

RC Low to Row Address Transition

Column Address Valid to RC high

RC High to Column Address Transition

50

ns

CLAX

t

50

ns

AVCH

t

50

ns

CHAX

(1)

RC High to Output Valid

Max

150

ns

t

CHQV

(1)

Output Enable Low to Output Valid

RP High to Row Address Valid

Max

Min

Max

Min

50

1

t

GLQV

t

µs

ns

PHAV

t

Output Enable Low to Output Transition

Output Enable High to Output Hi-Z

Output Hold from Output Enable High

0

GLQX

50

0

GHQZ

GHQX

t

Note: 1. G may be delayed up to t

– t

after the rising edge of RC without impact on t

.

CHQV

GLQV

Figure 11. A/A Mux Interface Read AC Waveforms

tAVAV

A0-A10

ROW ADDR VALID COLUMN ADDR VALID

NEXT ADDR VALID

tAVCL

tAVCH

tCLAX

tCHAX

RC

G

tCHQV

tGLQV

tGLQX

tGHQZ

tGHQX

VALID

DQ0-DQ7

W

tPHAV

RP

AI03406

25/36

M50LPW116

Table 25. A/A Mux Interface Write AC Characteristics

(T = 0 to 70°C or –20 to 85°C; V = 3.0 to 3.6V)

A

CC

Symbol

Parameter

Test Condition

Value

100

50

Unit

ns

t

Write Enable Low to Write Enable High

Data Valid to Write Enable High

Min

WLWH

t

DVWH

t

Write Enable High to Data Transition

Row Address Valid to RC Low

5

WHDX

t

50

AVCL

t

RC Low to Row Address Transition

Column Address Valid to RC High

RC High to Column Address Transition

Write Enable High to Write Enable Low

RC High to Write Enable High

50

CLAX

t

50

AVCH

t

50

CHAX

t

100

50

WHWL

t

CHWH

(1)

V

High to Write Enable High

100

30

0

ns

t

PP

VPHWH

t

Write Enable High to Output Enable Low

Write Enable High to RB Low

WHGL

t

WHRL

(1,2)

QVVPL

Output Valid, RB High to V Low

0

t

PP

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V < 3.6V).

PP

26/36

M50LPW116

Figure 12. A/A Mux Interface Write AC Waveforms

Write erase or

program setup

Write erase confirm or Automated erase

valid address and data or program delay

Read Status

Register Data

Ready to write

another command

A0-A10

RC

R1

C1

R2

C2

tCLAX

tAVCH

tAVCL

tCHAX

tWHWL

tWLWH

tCHWH

W

G

tVPHWH

tWHGL

tWHRL

RB

tQVVPL

V

PP

tDVWH

tWHDX

DQ0-DQ7

D

VALID SRD

IN1

IN2

AI04194

27/36

M50LPW116

Figure 13. Program Flowchart and Pseudo Code

Start

Program command:

– write 40h or 10h

Write 40h or 10h

– write Address & Data

(memory enters read status state after

the Program command)

Write Address

& Data

do:

NO

Read Status

–read Status Register if Program/Erase

Suspend command given execute

suspend program loop

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

YES

while b7 = 1

NO

V

Invalid

If b3 = 1, V

invalid error:

PP

– error handler

b3 = 0

YES

Error (1, 2)

Program

If b4 = 1, Program error:

– error handler

b4 = 0

YES

Error (1, 2)

LPC

Interface

Only

Program to Protected

Block Error (1, 2)

If b1 = 1, Program to protected block error:

– error handler

b1 = 0

YES

End

AI04433

Note: 1. A Status check of b1 (Protected Block), b3 (V invalid) and b4 (Program Error) can be made after each Program operation by

PP

following the correct command sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

28/36

M50LPW116

Figure 14. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

Write 30h

Write Address 1

& Data 1 ⁽³⁾

Quadruple Byte Program command:

– write 30h

– write Address 1 & Data 1 ⁽³⁾

– write Address 2 & Data 2 ⁽³⁾

– write Address 3 & Data 3 ⁽³⁾

– write Address 4 & Data 4 ⁽³⁾

(memory enters read status state after

the Quadruple Byte Program command)

Write Address 2

& Data 2 ⁽³⁾

Write Address 3

& Data 3 ⁽³⁾

Write Address 4

& Data 4 ⁽³⁾

do:

NO

– read Status Register if Program/Erase

Suspend command given execute

suspend program loop

Read Status

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

YES

while b7 = 1

V

Invalid

Error (1, 2)

If b3 = 1, V

invalid error:

PP

– error handler

b3 = 0

YES

Program

Error (1, 2)

If b4 = 1, Program error:

– error handler

b4 = 0

YES

End

AI03982

Note: 1. A Status check of b3 (V invalid) and b4 (Program Error) can be made after each Program operation by following the correct com-

PP

mand sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

3. Address 1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1.

29/36

M50LPW116

Figure 15. Program Suspend and Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

– write B0h

– write 70h

Write 70h

do:

– read Status Register

Read Status

Register

NO

b7 = 1

YES

while b7 = 1

b2 = 1

YES

Program Complete

If b2 = 0 Program completed

Write a read

Command

Read data from

another address

Program/Erase Resume command:

– write D0h to resume the program

– if the Program operation completed

then this is not necessary.

The device returns to Read as

normal (as if the Program/Erase

suspend was not issued).

Write D0h

Write FFh

Read Data

Program Continues

AI03408

30/36

M50LPW116

Figure 16. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

Chip Erase command:

Write 80h

– write 80h

– write 10h

(memory enters read Status Register after

the Chip Erase command)

Write 10h

do:

– read Status Register

Read Status

Register

NO

b7 = 1

YES

while b7 = 1

NO

V

Invalid

If b3 = 1, V

invalid error:

PP

Error (1)

PP

– error handler

b3 = 0

YES

Command

Sequence Error (1)

If b4, b5 = 1, Command sequence error:

– error handler

b4, b5 = 0

YES

If b5 = 1, Erase error:

– error handler

b5 = 0

Erase Error (1)

YES

End

AI04195

Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

31/36

M50LPW116

Figure 17. Block Erase Flowchart and Pseudo Code

Start

Block Erase command:

– write 20h

Write 20h

– write Block Address & D0h

(memory enters read Status Register after

the Block Erase command)

Write Block Address

& D0h

do:

– read Status Register

– if Program/Erase Suspend command

given execute suspend erase loop

NO

Read Status

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

while b7 = 1

YES

NO

V

Invalid

If b3 = 1, V

invalid error:

PP

Error (1)

PP

– error handler

b3 = 0

YES

Command

Sequence Error (1)

If b4, b5 = 1, Command sequence error:

– error handler

b4, b5 = 0

YES

If b5 = 1, Erase error:

– error handler

b5 = 0

YES

Erase Error (1)

LPC

Interface

Only

Erase to Protected

Block Error (1)

If b1 = 1, Erase to protected block error:

– error handler

b1 = 0

YES

End

AI04434

Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

32/36

M50LPW116

Figure 18. Erase Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

– write B0h

– write 70h

Write 70h

do:

Read Status

Register

– read Status Register

NO

b7 = 1

YES

while b7 = 1

b6 = 1

YES

Erase Complete

If b6 = 0, Erase completed

Read data from

another block

or

Program

Program/Erase Resume command:

– write D0h to resume erase

– if the Erase operation completed

then this is not necessary.

The device returns to Read as

normal (as if the Program/Erase

suspend was not issued).

Write D0h

Write FFh

Read Data

Erase Continues

AI03410

33/36

M50LPW116

Table 26. Ordering Information Scheme

Example:

M50LPW116

N

1

T

Device Type

M50

Architecture

LP = Low Pin Count Interface

Operating Voltage

W = 3.0 to 3.6V

Device Function

116 = 16 Mbit (2Mb x8), Boot Block

Package

N = TSOP40: 10 x 20 mm

Temperature Range

1 = 0 to 70 °C

5 = –20 to 85°C

Option

T = Tape & Reel Packing

For a list of available options or for further information on any aspect of this device, please contact the ST

Sales Office nearest to you.

Table 27. Revision History

Date

Version

-01

Revision Details

September 2001

12-Dec-2001

16-Jan-2002

01-Mar-2002

30-Jul-2002

First Issue

-02

Extensions to the descriptions on Quadruple Byte Programming

Device code announced: 30h

-03

-04

RFU pins must be left disconnected

-05

Quadruple Byte Mode, in LPC mode, removed

Revision numbering modified: a minor revision will be indicated by incrementing the

digit after the dot, and a major revision, by incrementing the digit before the dot

(revision version 05 equals 5.0). Document promoted to Product Preview.

22-Nov-2002

13-Feb-2003

5.1

5.2

Datasheet promoted from Product Preview to Preliminary Data status.

34/36

M50LPW116

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

A1

α

L

Note: Drawing is not to scale.

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.150

1.050

0.270

0.210

20.200

18.500

10.100

–

Typ

Max

0.0472

0.0059

0.0413

0.0106

0.0083

0.7953

0.7283

0.3976

–

A

A1

A2

B

0.050

0.950

0.170

0.100

19.800

18.300

9.900

–

0.0020

0.0374

0.0067

0.0039

0.7795

0.7205

0.3898

–

C

D

D1

E

e

0.500

0.0197

L

0.500

0°

0.700

5°

0.0197

0°

0.0276

5°

α

N

40

CP

0.100

0.0039

35/36

M50LPW116

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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36/36


型号：	M50LPW116N
厂家：	ST
描述：	16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory 16兆位的2Mb ×8 ，引导块3V电源低引脚数闪存闪存
文件：	总36页 (文件大小：260K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M50LPW116N [STMICROELECTRONICS]

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