M48Z58-70PC6TR [STMICROELECTRONICS]
64 Kbit 8Kb x 8 ZEROPOWER SRAM; 64 Kbit的是8K ×8 ZEROPOWER SRAM
| 型号： | M48Z58-70PC6TR |
| 厂家： | 
ST |
| 描述： | 64 Kbit 8Kb x 8 ZEROPOWER SRAM |
| 文件： | 总17页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48Z58
M48Z58Y
®
64 Kbit (8Kb x 8) ZEROPOWER SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
SNAPHAT (SH)
Battery
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48Z58: 4.50V ≤ VPFD ≤ 4.75V
– M48Z58Y: 4.20V ≤ VPFD ≤ 4.50V
28
28
1
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
1
PCDIP28 (PC)
Battery CAPHAT
PACKAGING INCLUDES a 28-LEAD SOIC
SOH28 (MH)
and SNAPHAT® TOP
(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
Figure 1. Logic Diagram
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 8K x 8 SRAMs
DESCRIPTION
V
CC
The M48Z58/58Y ZEROPOWER® RAM is an 8K x
8 non-volatile static RAM that integrates power-fail
deselect circuitry and battery control logic on a
single die. The monolithic chip is available in two
special packages to provide a highly integrated
battery backed-up memory solution.
13
8
A0-A12
DQ0-DQ7
W
E
M48Z58
M48Z58Y
Table 1. Signal Names
A0-A12
Address Inputs
Data Inputs / Outputs
Chip Enable
G
DQ0-DQ7
E
G
Output Enable
Write Enable
Supply Voltage
Ground
V
SS
W
AI01176B
VCC
VSS
March 1999
1/17
M48Z58, M48Z58Y
Figure 2A. DIP Pin Connections
Figure 2B. SOIC Pin Connections
NC
A12
A7
1
2
3
4
5
6
7
8
9
28
27
V
CC
W
NC
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
2
26 NC
25 A8
24 A9
23 A11
3
NC
A8
A6
A6
4
A5
A5
5
A9
A4
A4
6
A11
G
A3
22
G
A3
7
M48Z58
M48Z58Y
M48Z58Y
A2
21 A10
A2
8
A10
E
A1
20
E
A1
9
A0 10
DQ0 11
DQ1 12
DQ2 13
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
V
14
V
SS
SS
AI01177B
AI01178B
Warning:
Warning:
NC = Not Connected.
NC = Not Connected.
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Ambient Operating Temperature Grade 1
Value
Unit
0 to 70
–40 to 85
°C
Grade 6
TSTG
Storage Temperature (VCC Off)
–40 to 85
260
°C
°C
V
(2)
TSLD
Lead Solder Temperature for 10 seconds
Input or Output Voltages
Supply Voltage
VIO
VCC
IO
–0.3 to 7
–0.3 to 7
20
V
Output Current
mA
W
PD
Power Dissipation
1
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 3. Operating Modes (1)
Mode
Deselect
Write
VCC
E
VIH
VIL
VIL
VIL
X
G
X
W
X
DQ0-DQ7
High Z
DIN
Power
Standby
4.75V to 5.5V
or
4.5V to 5.5V
X
VIL
VIH
VIH
X
Active
Read
VIL
VIH
X
DOUT
Active
Read
High Z
High Z
High Z
Active
Deselect
Deselect
V
SO to VPFD (min) (2)
CMOS Standby
Battery Back-up Mode
≤ VSO
X
X
X
Notes
: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2. See Table 7 for details.
2/17
M48Z58, M48Z58Y
Figure 3. Block Diagram
A0-A12
LITHIUM
CELL
DQ0-DQ7
E
POWER
8K x 8
SRAM ARRAY
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
V
PFD
W
G
V
V
CC
SS
AI01394
DESCRIPTION
Table 4. AC Measurement Conditions
(cont’d)
The M48Z58/58Y is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0 to 3V
1.5V
Input and Output Timing Ref. Voltages
Note that Output Hi-Z is defined as the point where data is no
longer driven.
The 28 pin 600mil DIP CAPHAT houses the
M48Z58/58Y silicon with a long life lithium button
cell in a single package.
Figure 4. AC Testing Load Circuit
5V
The 28 pin 330mil SOIC provides sockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery. The unique design allows the SNAPHAT
battery package to be mounted on top of the SOIC
package after the completion of the surface mount
process. Insertion of the SNAPHAT housing after
reflow prevents potential batterydamage due to the
high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
1.9kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
C
= 100pF or 5pF
L
The SOIC and battery packages are shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form.
C
includes JIG capacitance
L
AI01030
3/17
M48Z58, M48Z58Y
Table 5. Capacitance (1, 2)
°
(TA = 25 C)
Symbol
Parameter
Input Capacitance
Test Condition
VIN = 0V
Min
Max
10
Unit
pF
CIN
(3)
CIO
Input / Output Capacitance
VOUT = 0V
10
pF
Notes:
1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
°
°
(TA = 0 to 70 C or –40 to 85 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Test Condition
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
Outputs open
E = VIH
Min
Max
Unit
µA
µA
mA
mA
mA
V
±1
ILO
±5
ICC
50
ICC1
ICC2
VIL
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
3
3
E = VCC – 0.2V
–0.3
2.2
0.8
VIH
Input High Voltage
VCC + 0.3
0.4
V
VOL
VOH
Output Low Voltage
IOL = 2.1mA
IOH = –1mA
V
Output High Voltage
2.4
V
Table 7. Power Down/Up Trip Points DC Characteristics (1)
°
°
(TA = 0 to 70 C or –40 to 85 C)
Symbol
VPFD
Parameter
Min
4.5
4.2
Typ
4.6
Max
4.75
4.5
Unit
Power-fail Deselect Voltage (M48Z58/58Y)
Power-fail Deselect Voltage (M48Z58/58YY)
Battery Back-up Switchover Voltage
Expected Data Retention Time
V
VPFD
4.35
3.0
V
V
VSO
(2)
tDR
10
YEARS
Notes:
1. All voltages referenced to VSS
.
2. At 25 °C
DESCRIPTION
(cont’d)
tion. When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system op-
eration brought on by low VCC. As VCC falls below
approximately 3V, the control circuitry connects the
battery which maintains data until valid power re-
turns.
For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is "M4Z28-BR00SH1".
The M48Z58/58Y also has its own Power-fail De-
tect circuit. The controlcircuitry constantly monitors
the single 5V supply for an out of tolerance condi-
4/17
M48Z58, M48Z58Y
Table 8. Power Down/Up Mode AC Characteristics
°
°
(TA = 0 to 70 C or –40 to 85 C)
Symbol
Parameter
Min
0
Max
Unit
µs
tPD
E or W at VIH before Power Down
(1)
tF
VPFD (max) to VPFD (min) VCC Fall Time
VPFD (min) to VSS VCC Fall Time
300
10
10
1
µs
(2)
tFB
µs
tR
tRB
VPFD(min) to VPFD (max) VCC Rise Time
VSS to VPFD (min) VCC Rise Time
VPFD (max) to Inputs Recognized
µs
µs
(3)
tREC
40
200
ms
Notes
µ
: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after
VCC passes VPFD (min).
2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
3. tREC (min) = 20ms for industrial temperature grade 6 device.
Figure 5. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tFB
tRB
tPD
tDR
tREC
RECOGNIZED
RECOGNIZED
INPUTS
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01168C
5/17
M48Z58, M48Z58Y
Table 9. Read Mode AC Characteristics
°
°
(TA = 0 to 70 C or –40 to 85 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z58 / M48Z58Y
-70
Symbol
Parameter
Unit
Min
Max
tAVAV
Read Cycle Time
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
tAVQV
Address Valid to Output Valid
70
70
35
(1)
tELQV
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
(1)
tGLQV
(2)
tELQX
5
5
(2)
tGLQX
(2)
tEHQZ
25
25
(2)
tGHQZ
(1)
tAXQX
10
Notes:
1. CL = 100pF (see Figure 4).
2. CL = 5pF (see Figure 4).
Figure 6. Read Mode AC Waveforms
tAVAV
VALID
A0-A12
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI01385
Note:
Write Enable (W) = High.
6/17
M48Z58, M48Z58Y
Table 10. Write Mode AC Characteristics
°
°
(TA = 0 to 70 C or –40 to 85 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z58 / M48Z58Y
-70
Symbol
Parameter
Unit
Min
70
0
Max
tAVAV
tAVWL
tAVEL
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
0
tWLWH
tELEH
tWHAX
tEHAX
tDVWH
tDVEH
tWHDX
tEHDX
50
55
0
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
0
30
30
5
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable Low to Output Hi-Z
Address Valid to Write Enable High
Address Valid to Chip Enable High
Write Enable High to Output Transition
5
(1, 2)
tWLQZ
25
tAVWH
tAVEH
60
60
5
(1, 2)
tWHQX
Notes:
1. CL = 5pF (see Figure 4).
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
READ MODE
time (tAXQX) but will go indeterminate until the next
Address Access.
The M48Z58/58Y is in the Read Mode whenever
W (Write Enable) is high, E (Chip Enable) is low.
Thus, the unique address specified by the 13 Ad-
dress Inputs defines which one of the 8,192 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (tAVQV) after the last address input signal is
stable, providing that the E and G access times are
also satisfied. If the E and G access times are not
met, valid data will be available after the latter of
the Chip Enable Access time (tELQV) or Output
Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated
before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
WRITE MODE
The M48Z58/58Y is in the Write Mode whenever W
and E are low. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
of tEHAX from Chip Enable or tWHAX from Write
Enable prior to the initiation of another read or write
cycle. Data-in must be valid tDVWH prior to the end
of write and remain valid for tWHDX afterward. G
should be kept high during write cycles to avoid bus
contention; although, if the output bus has been
activated by a low on E and G, a low on W will
disable the outputs tWLQZ after W falls.
7/17
M48Z58, M48Z58Y
Figure 7. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A12
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01386
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A12
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01387B
8/17
M48Z58, M48Z58Y
DATA RETENTION MODE
POWER SUPPLY DECOUPLING and UNDER-
SHOOT PROTECTION
With valid VCC applied, the M48Z58/58Y operates
as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will
automatically power-fail deselect, write protecting
itself when VCC falls within the VPFD(max),
VPFD(min) window. All outputs become high imped-
ance, and all inputs are treated as "don’t care."
ICC transients, including those produced by output
switching, can produce voltage fluctuations, result-
ing in spikes on the VCC bus. These transients can
be reduced if capacitors are used to store energy,
which stabilizes the VCC bus. The energy stored in
the bypass capacitors will be released as low going
spikes are generated or energy will be absorbed
when overshoots occur. A ceramic bypass capaci-
Note:
A power failure during a write cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM’s
content. At voltages below VPFD(min), the user can
be assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48Z58/58Y may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
µ
tor value of 0.1 F (as shown in Figure 9) is recom-
mended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate
negative voltage spikes on VCC that drive it to
values below VSS by as much as one Volt. These
negative spikes can cause data corruption in the
SRAM while in battery backup mode. To protect
from these voltage spikes, it is recommeded to
connect a schottky diode from VCC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data. The internal button cell will maintain
data in the M48Z58/58Y for an accumulated period
of at least 10 years when VCC is less than VSO
.
As system power returns and VCC rises above VSO
,
Figure 9. Supply Voltage Protection
the battery is disconnected, and the power supply
is switched to external VCC. Write protection con-
tinues until VCC reaches VPFD(min) plus tREC(min).
Normal RAM operation can resume tREC after VCC
exceeds VPFD(max).
V
CC
V
CC
For more information on Battery Storage Life refer
to the Application Note AN1012.
0.1µF
DEVICE
V
SS
AI02169
9/17
M48Z58, M48Z58Y
ORDERING INFORMATION SCHEME
Example:
M48Z58Y -70 MH
1
TR
Supply Voltage and Write
Protect Voltage
Speed
Package
Temp. Range
Shipping Method
for SOIC
58 (1) VCC = 4.75V to 5.5V
-70 70ns
PC
PCDIP28
1
0 to 70 °C
blank Tubes
VPFD = 4.5V to 4.75V
MH (2,3)SOH28
6 (4) –40 to 85°C
TR
Tape & Reel
58Y VCC = 4.5V to 5.5V
VPFD = 4.2V to 4.5V
Notes:
1. The M48Z58 part is offered with the PCDIP28 (i.e. CAPHAT) package only.
2. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number
"M4Z28-BR00SH1" in plastic tube or "M4Z28-BR00SH1TR" in Tape & Reel form.
3. Delivery may include either the 2-pin version of the SOIC/SNAPHAT or the 4-pin version of the SOIC/SNAPHAT. Both are
functionally equivalent (see package drawing section for details).
4. Industrial temperature grade available in SOIC package (SOH28) only.
Caution:
Do not place the SNAPHAT battery package "M4Z28-BR00SH1" in conductive foam since this will drain the lithium button-cell
battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
10/17
M48Z58, M48Z58Y
PCDIP28 - 28 pin Plastic DIP, battery CAPHAT
mm
Min
inches
Min
Symb
Typ
Max
9.65
0.76
8.89
0.53
1.78
0.31
39.88
18.34
2.79
36.32
16.00
3.81
Typ
Max
A
A1
A2
B
8.89
0.38
8.38
0.38
1.14
0.20
39.37
17.83
2.29
29.72
15.24
3.05
28
0.350
0.015
0.330
0.015
0.045
0.008
1.550
0.702
0.090
1.170
0.600
0.120
28
0.380
0.030
0.350
0.021
0.070
0.012
1.570
0.722
0.110
1.430
0.630
0.150
B1
C
D
E
e1
e3
eA
L
N
A2
A
L
A1
e1
C
B1
B
eA
e3
D
N
1
E
PCDIP
Drawing is not to scale.
11/17
M48Z58, M48Z58Y
SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Drawing is not to scale.
12/17
M48Z58, M48Z58Y
SOH28 - 28 lead Plastic Small Outline, 2-socket battery SNAPHAT
mm
Min
inches
Symb
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Min
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-B
Drawing is not to scale.
13/17
M48Z58, M48Z58Y
SH - 4-pin SNAPHAT Housing for 49 mAh Battery
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Max
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
A
A1
A2
A3
B
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
A2
A1
A
A3
L
eA
D
B
eB
E
SH
Drawing is not to scale.
14/17
M48Z58, M48Z58Y
SH - 2-pin SNAPHAT Housing for 49 mAh Battery
mm
Min
inches
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
3.61
2.29
Typ
Min
Max
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.142
0.090
A
A1
A2
A3
B
6.73
6.48
0.265
0.255
0.46
21.21
14.22
3.20
0.018
0.835
0.560
0.126
0.080
D
E
eB
L
2.03
A2
A1
A
A3
L
B
eB
D
E
SHZP-A
Drawing is not to scale.
15/17
M48Z58, M48Z58Y
SH - 2-pin SNAPHAT Housing for 130 mAh Battery
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
Typ
Max
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.142
0.090
A
A1
A2
A3
B
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
3.20
0.56
0.018
0.835
0.680
0.126
0.080
D
21.84
18.03
3.61
E
eB
L
2.03
2.29
A2
A1
A
A3
L
B
eB
D
E
SHZP-B
Drawing is not to scale.
16/17
M48Z58, M48Z58Y
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics - All Rights Reserved
® ZEROPOWER and SNAPHAT are registered trademarks of STMicroelectronics
CAPHAT and BYTEWIDE are trademarks of STMicroelectronics
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17/17
相关型号：
M48Z58Y-70MH6E
8KX8 NON-VOLATILE SRAM, 70ns, PDSO28, LEAD FREE, SNAPHAT, PLASTIC, SOIC-28
STMICROELECTR
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