M48Z19PC [STMICROELECTRONICS]
CMOS 8K x 8 ZEROPOWER SRAM; CMOS 8K ×8 ZEROPOWER SRAM
| 型号： | M48Z19PC |
| 厂家： | 
ST |
| 描述： | CMOS 8K x 8 ZEROPOWER SRAM |
| 文件： | 总13页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48Z09
M48Z19
CMOS 8K x 8 ZEROPOWER SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
POWER-FAIL INTERRUPT
28
1
CHOICE of TWO WRITE PROTECT
VOLTAGES:
PCDIP28 (PC)
Battery CAPHAT
– M48Z09: 4.5V ≤ VPFD ≤ 4.75V
– M48Z19: 4.2V ≤ VPFD ≤ 4.5V
SELF CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
11 YEARS of DATA RETENTION in the
ABSENCE of POWER
Figure 1. Logic Diagram
PIN and FUNCTION COMPATIBLE with the
MK48Z09, 19 and JEDEC STANDARD 8K x 8
SRAMs
DESCRIPTION
TheM48Z09,19ZEROPOWER® RAM is an 8K x 8
non-volatile static RAM which is pin and function
compatible with the MK48Z09,19.
V
CC
13
8
A special 28 pin 600mil DIP CAPHAT package
houses the M48Z09,19 silicon with a long life lith-
ium button cell to form a highly integrated battery
backed-up memory solution.
A0-A12
DQ0-DQ7
INT
W
M48Z09
M48Z19
Table 1. Signal Names
E1
E2
G
A0-A12
DQ0-DQ7
INT
Address Inputs
Data Inputs / Outputs
Power Fail Interrupt
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
E1
E2
V
SS
G
AI01184
W
VCC
VSS
Supply Voltage
Ground
November 1994
1/13
M48Z09, M48Z19
Table 2. Absolute Maximum Ratings
Symbol
TA
Parameter
Value
0 to 70
–40 to 85
–0.3 to 7
–0.3 to 7
20
Unit
°C
°C
V
Ambient Operating Temperature
Storage Temperature (VCC Off)
Input or Output Voltages
Supply Voltage
TSTG
VIO
VCC
IO
V
Output Current
mA
W
PD
Power Dissipation
1
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability.
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Mode
Deselect
Deselect
Write
VCC
E1
VIH
X
E2
X
G
X
W
X
DQ0-DQ7
High Z
High Z
DIN
Power
Standby
4.75V to 5.5V
or
4.5V to 5.5V
VIL
VIH
VIH
VIH
X
X
X
Standby
VIL
VIL
VIL
X
X
VIL
VIH
VIH
X
Active
Read
VIL
VIH
X
DOUT
Active
Read
High Z
High Z
High Z
Active
Deselect
Deselect
V
SO to VPFD (min)
CMOS Standby
Battery Back-up Mode
X
X
X
X
≤ VSO
Note: X = VIH or VIL
Figure 2A. DIP Pin Connections
DESCRIPTION (cont’d)
The M48Z09,19 button cell has sufficient capacity
and storage life to maintain data for an accumu-
lated time period of at least 11 years in the absence
of power over the operating temperature range.
INT
A12
A7
1
2
3
4
5
6
7
8
9
28
27
V
CC
W
26 E2
25 A8
24 A9
23 A11
The M48Z09,19 is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
A6
A5
A4
A3
22
G
M48Z09
M49Z19
A2
21 A10
20 E1
A1
The M48Z09,19 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security inthemidst ofunpredictablesystemopera-
tion brought on by low VCC. As VCC falls below
approximately 3V, the control circuitry connects the
battery which maintains data and clock operation
until valid power returns.
A0 10
DQ0 11
DQ1 12
DQ2 13
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
V
14
SS
AI01185
2/13
M48Z09, M48Z19
Figure 3. Block Diagram
A0-A12
DQ0-DQ7
LITHIUM
CELL
8K x 8
SRAM ARRAY
POWER
E1
E2
W
VOLTAGE SENSE
AND
V
SWITCHING
CIRCUITRY
PFD
G
V
INT
V
CC
SS
AI01397
AC MEASUREMENT CONDITIONS
READ MODE
The M48Z09,19 is in the Read Mode whenever W
(Write Enable) is high, E1 (Chip Enable 1) is low,
and E2 (Chip Enable 2) is high. The device archi-
tecture allows ripple- through access of data from
eight of 65,536 locations in the static storage array.
Thus, the unique address specified by the 13 Ad-
dress Inputs defines which one of the 8,192 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within tAVQV (Address
Access Time) after the last address input signal is
stable, providing that the E1, E2, and G access
times are also satisfied. If the E1, E2 and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access Times (tE1LQV
or tE2HQV) or Output Enable Access Time (tGLQV).
Input Rise and Fall Times
≤ 5ns
0 to 3V
1.5V
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Figure 4. AC Testing Load Circuit
5V
1.8kΩ
DEVICE
The state of the eight three-state Data I/O signals
is controlled by E1, E2 and G. If the outputs are
activated before tAVQV, the data lines will be driven
to an indeterminate state until tAVQV. If the Address
Inputs are changed while E1, E2 and G remain
active, output data will remain valid for tAXQX (Out-
put Data Hold Time) but will go indeterminate until
the next Address Access.
UNDER
TEST
OUT
1kΩ
C
= 100pF or 30pF
L
C
includes JIG capacitance
L
AI01398
3/13
M48Z09, M48Z19
Table 4. Capacitance (1) (TA = 25 °C)
Symbol
Parameter
Input Capacitance
Test Condition
VIN = 0V
Min
Max
10
Unit
pF
CIN
(2)
CIO
Input / Output Capacitance
VOUT = 0V
10
pF
Notes: 1. Effective capacitance calculated from the equation C = I∆t/∆V with ∆V = 3V and power supply at 5V.
2. Outputs deselected
Table 5. DC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Test Condition
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
Outputs open
Min
Max
±1
±5
80
3
Unit
µA
ILO
µA
ICC
mA
mA
ICC1
Supply Current (Standby) TTL
E1 = VIH, E2 = VIL
E1 = VCC – 0.2V,
E2 = VSS + 0.2V
ICC2
Supply Current (Standby) CMOS
3
mA
VIL
Input Low Voltage
–0.3
2.2
0.8
VCC + 0.3
0.4
V
V
V
V
V
VIH
Input High Voltage
Output Low Voltage
Output Low Voltage (INT) (1)
Output High Voltage
IOL = 2.1mA
IOL = 0.5mA
IOH = –1mA
VOL
0.4
VOH
2.4
Note: 1. The INT pin is Open Drain.
Table 6. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70°C)
Symbol
VPFD
VPFD
VSO
Parameter
Min
4.5
4.2
Typ
4.6
4.3
3.0
Max
4.75
4.5
Unit
Power-fail Deselect Voltage (M48Z09)
Power-fail Deselect Voltage (M48Z19)
Battery Back-up Switchover Voltage
Expected Data Retention Time
V
V
V
tDR
11
YEARS
Note: 1. All voltages referenced to VSS
.
4/13
M48Z09, M48Z19
Table 7. Power Down/Up Mode AC Characteristics (TA = 0 to 70°C)
Symbol
Parameter
E1 or W at VIH or E2 at VIL before Power Down
VPFD (max) to VPFD (min) VCC Fall Time
VPFD (min) to VSO VCC Fall Time
Min
0
Max
Unit
µs
tPD
(1)
tF
300
10
0
µs
(2)
tFB
µs
tR
VPFD(min) to VPFD (max) VCC Rise Time
VSO to VPFD (min) VCC Rise Time
E1 or W at VIH or E2 at VIL after Power Up
INT Low to Auto Deselect
µs
tRB
1
µs
tREC
tPFX
1
ms
µs
10
40
(3)
tPFH
VPFD (max) to INT High
120
µs
Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
3. INT may go high anytime after VCC exceeds VPFD (min) and is guaranteed to go high tPFH after VCC exceeds VPFD (max).
Figure 5. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tDR
tR
tPD
tFB
tPFX
tRB
tPFH
INT
tREC
RECOGNIZED
NOTE
RECOGNIZED
INPUTS
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI00566
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E1high or E2 low as VCC rises past VPFD(min).
Some systems may performs inadvertent write cycles after VCC rises above VPFD(min) but before normal system operations begins. Even
though a power on reset is being applied to the processor a reset condition may not occur until after the system clock is running.
5/13
M48Z09, M48Z19
Table 8. Read Mode AC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z09 / 19
Symbol
Parameter
Unit
-100
Min
Max
tAVAV
Read Cycle Time
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
tAVQV
Address Valid to Output Valid
100
100
100
50
(1)
tE1LQV
Chip Enable 1 Low to Output Valid
Chip Enable 2 High to Output Valid
Output Enable Low to Output Valid
Chip Enable 1 Low to Output Transition
Chip Enable 2 High to Output Transition
Output Enable Low to Output Transition
Chip Enable 1 High to Output Hi-Z
Chip Enable 2 Low to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
(1)
tE2HQV
(1)
tGLQV
(2)
tE1LQX
10
10
5
(2)
tE2HQX
(2)
tGLQX
(2)
tE1HQZ
50
50
40
(2)
tE2LQZ
(2)
tGHQZ
(1)
tAXQX
5
Notes: 1. CL= 100pF (see Figure 4).
2. CL= 30pF (see Figure 4)
Figure 6. Read Mode AC Waveforms
tAVAV
VALID
A0-A12
tAVQV
tE1LQV
tAXQX
tE1HQZ
E1
E2
tE1LQX
tE2HQV
tE2LQZ
tE2HQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00962
6/13
M48Z09, M48Z19
Table 9. Write Mode AC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z09 / 19
-100
Symbol
Parameter
Unit
Min
Max
tAVAV
tAVWL
Write Cycle Time
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to Write Enable Low
Address Valid to Chip Enable 1 Low
Address Valid to Chip Enable 2 High
Write Enable Pulse Width
tAVE1L
tAVE2H
tWLWH
tE1LE1H
tE2HE2L
tWHAX
tE1HAX
tE2LAX
tDVWH
tDVE1H
tDVE2L
tWHDX
tE1HDX
tE2LDX
0
0
80
80
80
10
10
10
50
50
50
5
Chip Enable 1 Low to Chip Enable 1 High
Chip Enable 2 High to Chip Enable 2 Low
Write Enable High to Address Transition
Chip Enable 1 High to Address Transition
Chip Enable 2 Low to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable 1 High
Input Valid to Chip Enable 2 Low
Write Enable High to Input Transition
Chip Enable 1 High to Input Transition
Chip Enable 2 Low to Input Transition
Write Enable Low to Output Hi-Z
5
5
(1, 2)
tWLQZ
50
tAVWH
tAVE1H
tAVE2L
Address Valid to Write Enable High
Address Valid to Chip Enable 1 High
Address Valid to Chip Enable 2 Low
Write Enable High to Output Transition
80
80
80
10
(1, 2)
tWHQX
Notes: 1. CL= 30pF (see Figure 4).
2. If E1 goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance state.
7/13
M48Z09, M48Z19
Figure 7. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A12
VALID
tAVWH
tAVE1L
tAVE2H
tWHAX
E1
E2
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00963
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A12
VALID
tAVE1H
tE1LE1H
tAVE1L
tAVE2H
tE1HAX
tE2LAX
E1
tAVE2L
tE2HE2L
E2
tAVWL
W
tE1HDX
tE2LDX
DQ0-DQ7
DATA INPUT
tDVE1H
tDVE2L
AI00964B
8/13
M48Z09, M48Z19
write cycles prior to processor stabilization. Normal
RAM operation can resume tREC after VCC exceeds
VPFD(max).
WRITE MODE
The M48Z09,19 is in the Write Mode whenever W,
E1, and E2 are active. The start of a write is refer-
enced from the latter occurring falling edge of W or
E1, or the rising edge of E2. A write is terminated
by the earlier rising edge of W or E1, or the falling
edge of E2. The addresses must be held valid
throughout the cycle. E1 or W must return high or
E2 low for minimum of tE1HAX or tE2LAX from Chip
Enable or tWHAX from Write Enable prior to the
initiation of another read or write cycle. Data-in
must be valid tDVWH prior to the end of write and
remain valid for tWHDX afterward. G should be kept
high during write cycles to avoid bus contention;
although, if the output bus has been activated by a
low on E1 and G and a high on E2, a low on W will
disable the outputs tWLQZ after W falls.
POWER FAIL INTERRUPT PIN
The M48Z09,19 continuously monitors VCC. When
VCC falls to the power-fail detect trip point, an
interrupt is immediately generated. An internal
clock provides a delay of between 10µs and 40µs
before automatically deselecting the M48Z09,19.
The INT pin is an open drain output and requires
an external pull up resistor, even if the interrupt
output function is not being used.
SYSTEM BATTERY LIFE
The useful life of the battery in the M48Z09,19 is
expected to ultimately come to an end for one of
tworeasons:eitherbecauseithasbeendischarged
while providing current to the RAM in the battery
back-up mode, or because the effects of aging
render the cell useless before it can actually be
completelydischarged. The twoeffects are virtually
unrelated allowing discharge, or Capacity Con-
sumption, and the effects of aging, or Storage Life,
to be treated as two independent but simultaneous
mechanisms. The earlier occurring failure mecha-
nism defines the battery system life of the
M48Z09,19.
DATA RETENTION MODE
With valid VCC applied, the M48Z09,19 operates as
a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automat-
ically power-fail deselect, write protecting itself
when VCC falls within the VPFD(max), VPFD(min)
window. All outputs become high impedance, and
all inputs are treated as "don’t care."
Note: A power failure during a write cycle may
corruptdataatthecurrentlyaddressed location,but
does not jeopardize the rest of the RAM’s content.
At voltages below VPFD(min), the user can be as-
sured the memory will be in a write protected state,
provided the VCC fall time is not less than tF. The
M48Z09,19 may respond to transient noise spikes
on VCC that reach into the deselect window during
the time the device is sampling VCC. Therefore,
decoupling of the power supply lines is recom-
mended.
Cell Storage Life
Storage life is primarily a function of temperature.
Figure 9 illustrates the approximate storage life of
the M48Z09,19 battery over temperature. The re-
sults in Figure 9 are derived from temperature
accelerated life test studies performed at SGS-
THOMSON. For the purpose of the testing, a cell
failure is defined as the inability of a cell stabilized
at 25°C to produce a 2.4V closed circuit voltage
across a 250 kΩ load resistor. The two lines, t1%
and t50%, represent different failure rate distribu-
tions for the cell’s storage life. At 70°C, for example,
the t1% line indicates that an M48Z09,19 has a 1%
chance of having a battery failure 28 years into its
life while the t50% shows the part has a 50% chance
of failure at the 50 year mark. The t1% line repre-
sents the practical onset of wear out and can be
considered the worst case Storage Life for the cell.
The t50% can be considered the normal or average
life.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48Z09,19 for
an accumulated period of at least 10 years when
VCC is less than VSO. As system power returns and
VCC rises above VSO, the battery is disconnected,
and the power supply is switched to external VCC
.
Write protection continues until VCC reaches
VPFD(min). E1 should be kept high or E2 low as
VCC rises past VPFD(min) to prevent inadvertent
9/13
M48Z09, M48Z19
Calculating Storage Life
Predicted storage life ≥
1
The following formula can be used to predict stor-
age life:
{[(8322/8760)/200]+[(431/8760)/28]}
1
or 154 years.
{[(TA1/TT)/SL1]+[(TA2/TT)/SL2]+...+[(TAN/TT)/SLN]}
As can be seen from these calculations and the
results, the expected life time of the M48Z09, 19
should exceed most system requirements.
where,
– TA1, TA2, TAN = time at ambient temperature
1, 2, etc.
Estimated System Life
Since either storage life or capacity consumption
can end the battery’s life, the system life is marked
by which ever occurs first.
– TT = total time = TA1+TA2+...+TAN
– SL1, SL2, SLN = storage life at temperature 1,
2, etc.
Reference for System Life
Forexamplean M48Z09,19isexposedto tempera-
tures of 55°C or less for 8322 hrs/yr, and tempera-
tures greater than 60°C but less than 70°C for the
remaining 438 hrs/yr. Reading predicted t1% values
from Figure 9,
Each M48Z09,19 is marked with a nine digit manu-
facturing date code in the form of H99XXYYZZ. For
example, H995B9431 is:
H = fabricated in Carrollton, TX
9 = assembled in Muar, Malaysia,
9 = tested in Muar, Malaysia,
– SL1 200 yrs, SL2 = 28 yrs
– TT = 8760 hrs/yr
5B = lot designator,
– TA1 = 8322 hrs/yr, TA2 = 438 hrs/yr
9431 = assembled in the year 1994, work week 31.
Figure 9. Predicted Battery Storage Life versus Temperature
AI01399
50
40
30
t50% (AVERAGE)
t1%
20
10
8
6
5
4
3
2
1
20
30
40
50
60
70
80
90
TEMPERATURE (Degrees Celsius)
10/13
M48Z09, M48Z19
ORDERING INFORMATION SCHEME
Example:
M48Z09
-100 PC
1
Supply Voltage and Write
Protect Voltage
Speed
100ns
Package
PCDIP28
Temp. Range
09
VCC = 4.75V to 5.5V
-100
PC
1
0 to 70 °C
VPFD = 4.5V to 4.75V
19
V
CC = 4.5V to 5.5V
VPFD = 4.2V to 4.5V
For a list of available options (Supply Voltage, Speed, Package, etc...) refer to the current Memory
Shortform catalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearest to you.
11/13
M48Z09, M48Z19
PCDIP28 - 28 pin Plastic DIP, battery CAPHAT
mm
Min
inches
Symb
Typ
Max
9.65
Typ
Min
Max
A
A1
A2
B
8.89
0.38
8.38
0.38
1.14
0.20
39.37
17.83
2.29
29.72
15.24
3.05
28
0.350
0.015
0.330
0.015
0.045
0.008
1.550
0.702
0.090
1.170
0.600
0.120
28
0.380
0.030
0.350
0.021
0.070
0.012
1.570
0.722
0.110
1.430
0.630
0.150
0.76
8.89
0.53
B1
C
1.78
0.31
D
39.88
18.34
2.79
E
e1
e3
eA
L
36.32
16.00
3.81
N
PCDIP28
A2
A
L
A1
e1
C
B1
B
eA
e3
D
N
1
E
PCDIP
Drawing is not to scale
12/13
M48Z09, M48Z19
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
© 1994 SGS-THOMSON Microelectronics - All Rights Reserved
® ZEROPOWER is a registered trademark of SGS-THOMSON Microelectronics
CAPHAT and BYTEWIDE are trademarks of SGS-THOMSON Microelectronics
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
13/13
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