M48Z12_11 [STMICROELECTRONICS]
5 V, 16 Kbit (2 Kb x 8) ZEROPOWER® SRAM; 5 V ， 16千位（ 2 KB ×8 ） ZEROPOWER® SRAM
| 型号： | M48Z12_11 |
| 厂家： | 
ST |
| 描述： | 5 V, 16 Kbit (2 Kb x 8) ZEROPOWER® SRAM |
| 文件： | 总22页 (文件大小：343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48Z02
M48Z12
5 V, 16 Kbit (2 Kb x 8) ZEROPOWER® SRAM
Features
■ Integrated, ultra low power SRAM and power-
fail control circuit
■ Unlimited WRITE cycles
■ READ cycle time equals WRITE cycle time
■ Automatic power-fail chip deselect and WRITE
protection
■ WRITE protect voltages
(V
= power-fail deselect voltage):
PFD
24
– M48Z02: V = 4.75 to 5.5 V;
CC
1
4.5 V ≤ V
≤ 4.75 V
PFD
– M48Z12: V = 4.5 to 5.5 V;
CC
4.2 V ≤ V
≤ 4.5 V
PFD
■ Self-contained battery in the CAPHAT™ DIP
PCDIP24
Battery CAPHAT™
package
■ Pin and function compatible with JEDEC
standard 2 K x 8 SRAMs
■ RoHS compliant
– Lead-free second level interconnect
June 2011
Doc ID 2420 Rev 9
1/22
www.st.com
1
Contents
M48Z02, M48Z12
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
4
5
6
7
8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/22
Doc ID 2420 Rev 9
M48Z02, M48Z12
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mechanical data . . . . . . . . . 17
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Doc ID 2420 Rev 9
3/22
List of figures
M48Z02, M48Z12
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE enable controlled, WRITE AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Checking the BOK flag status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 17
Figure 12. Shipping tube dimensions for PCDIP24 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4/22
Doc ID 2420 Rev 9
M48Z02, M48Z12
Description
1
Description
®
The M48Z02/12 ZEROPOWER RAM is a 2 K x 8 non-volatile static RAM which is pin and
function compatible with the DS1220.
A special 24-pin, 600 mil DIP CAPHAT™ package houses the M48Z02/12 silicon with a
long-life lithium button cell to form a highly integrated battery-backed memory solution.
The M48Z02/12 button cell has sufficient capacity and storage life to maintain data
functionality for an accumulated time period of at least 10 years in the absence of power
over commercial operating temperature range.
The M48Z02/12 is a non-volatile pin and function equivalent to any JEDEC standard 2 K x 8
SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement for special WRITE timing or limitations on
the number of WRITEs that can be performed.
Figure 1.
Logic diagram
V
CC
11
8
A0-A10
DQ0-DQ7
W
E
M48Z02
M48Z12
G
V
SS
AI01186
Table 1.
Signal names
Address inputs
A0-A10
DQ0-DQ7
Data inputs / outputs
Chip enable
E
G
Output enable
WRITE enable
Supply voltage
Ground
W
VCC
VSS
Doc ID 2420 Rev 9
5/22
Description
Figure 2.
M48Z02, M48Z12
DIP connections
A7
A6
1
2
3
4
5
6
7
8
9
24
V
CC
23 A8
A5
22 A9
A4
21
20
W
G
A3
A2
M48Z02 19 A10
M48Z12
A1
18
E
A0
17 DQ7
16 DQ6
15 DQ5
14 DQ4
13 DQ3
DQ0
DQ1 10
DQ2 11
V
12
SS
AI01187
Figure 3.
Block diagram
A0-A10
LITHIUM
CELL
DQ0-DQ7
E
POWER
2K x 8
SRAM ARRAY
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
V
PFD
W
G
AI01255
V
V
CC
SS
6/22
Doc ID 2420 Rev 9
M48Z02, M48Z12
Operation modes
2
Operation modes
The M48Z02/12 also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When V is out of
CC
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V . As V falls below
CC
CC
approximately 3 V, the control circuitry connects the battery which maintains data operation
until valid power returns.
Table 2.
Mode
Operating modes
VCC
DQ0-
DQ7
E
G
W
Power
Deselect
WRITE
READ
VIH
VIL
VIL
VIL
X
X
X
X
VIL
VIH
VIH
X
High Z
DIN
Standby
Active
4.75 to 5.5 V
or
VIL
VIH
X
DOUT
High Z
High Z
High Z
Active
4.5 to 5.5 V
READ
Active
Deselect
Deselect
VSO to VPFD(min)(1)
CMOS standby
Battery backup mode
(1)
≤ VSO
X
X
X
1. See Table 10 on page 16 for details.
Note:
X = V or V ; V = battery backup switchover voltage.
IH IL SO
2.1
READ mode
The M48Z02/12 is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
16,384 locations in the static storage array. Thus, the unique address specified by the 11
Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (t
) after the last
AVQV
address input signal is stable, providing that the E and G access times are also satisfied. If
the E and G access times are not met, valid data will be available after the latter of the chip
enable access time (t
) or output enable access time (t
).
ELQV
GLQV
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before t , the data lines will be driven to an indeterminate state until t . If
AVQV
AVQV
the address inputs are changed while E and G remain active, output data will remain valid
for output data hold time (t ) but will go indeterminate until the next address access.
AXQX
Doc ID 2420 Rev 9
7/22
Operation modes
Figure 4. READ mode AC waveforms
M48Z02, M48Z12
tAVAV
VALID
A0-A10
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI01330
Note:
WRITE enable (W) = high.
Table 3.
READ mode AC characteristics
Parameter(1)
M48Z02/M48Z12
–150
Symbol
–70
–200
Unit
Min Max Min Max Min Max
tAVAV
tAVQV
tELQV
tGLQV
tELQX
tGLQX
tEHQZ
tGHQZ
tAXQX
READ cycle time
70
150
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to output valid
70
70
35
150
150
75
200
200
80
Chip enable low to output valid
Output enable low to output valid
Chip enable low to output transition
Output enable low to output transition
Chip enable high to output Hi-Z
Output enable high to output Hi-Z
Address transition to output transition
5
5
10
5
10
5
25
25
35
35
40
40
10
5
5
1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
2.2
WRITE mode
The M48Z02/12 is in the WRITE mode whenever W and E are active. The start of a WRITE
is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
from chip enable or t
from WRITE enable prior
EHAX
WHAX
to the initiation of another READ or WRITE cycle. Data-in must be valid t
prior to the
DVWH
end of WRITE and remain valid for t
afterward. G should be kept high during WRITE
WHDX
cycles to avoid bus contention; although, if the output bus has been activated by a low on E
and G, a low on W will disable the outputs t after W falls.
WLQZ
8/22
Doc ID 2420 Rev 9
M48Z02, M48Z12
Figure 5. WRITE enable controlled, WRITE AC waveform
Operation modes
tAVAV
VALID
A0-A10
tAVWH
tAVEL
tWHAX
E
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01331
Figure 6.
Chip enable controlled, WRITE AC waveforms
tAVAV
A0-A10
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01332B
Doc ID 2420 Rev 9
9/22
Operation modes
Table 4. WRITE mode AC characteristics
M48Z02, M48Z12
M48Z02/M48Z12
–150
Symbol
Parameter(1)
–70
–200
Unit
Min Max Min Max Min Max
tAVAV
tAVWL
tAVEL
WRITE cycle time
70
0
150
0
200
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to WRITE enable low
Address valid to chip enable 1 low
WRITE enable pulse width
0
0
0
tWLWH
tELEH
tWHAX
tEHAX
tDVWH
tDVEH
tWHDX
tEHDX
tWLQZ
tAVWH
tAVEH
tWHQX
50
55
0
90
90
10
10
40
40
5
120
120
10
10
60
60
5
Chip enable low to chip enable 1 high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
0
30
30
5
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
5
5
5
25
50
60
60
60
5
120
120
10
140
140
10
1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
2.3
Data retention mode
With valid V applied, the M48Z02/12 operates as a conventional BYTEWIDE™ static
CC
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V falls within the V
(max), V
(min) window. All outputs
CC
PFD
PFD
become high impedance, and all inputs are treated as “don't care.”
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
(min), the
PFD
user can be assured the memory will be in a write protected state, provided the V fall time
CC
is not less than t . The M48Z02/12 may respond to transient noise spikes on V that reach
F
CC
into the deselect window during the time the device is sampling V . Therefore, decoupling
CC
of the power supply lines is recommended.
The power switching circuit connects external V to the RAM and disconnects the battery
CC
when V rises above V . As V rises, the battery voltage is checked. If the voltage is
CC
SO
CC
too low, an internal Battery Not OK (BOK) flag will be set. The BOK flag can be checked
after power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is
automatically cleared after the first WRITE, and normal RAM operation resumes. Figure 7
on page 11 illustrates how a BOK check routine could be structured.
For more information on a battery storage life refer to the application note AN1012.
10/22
Doc ID 2420 Rev 9
M48Z02, M48Z12
Figure 7.
Operation modes
Checking the BOK flag status
POWER-UP
READ DATA
AT ANY ADDRESS
WRITE DATA
COMPLEMENT BACK
TO SAME ADDRESS
READ DATA
AT SAME
ADDRESS AGAIN
IS DATA
COMPLEMENT
OF FIRST
NO (BATTERY LOW)
READ?
NOTIFY SYSTEM
OF LOW BATTERY
(DATA MAY BE
(BATTERY OK)
YES
CORRUPTED)
WRITE ORIGINAL
DATA BACK TO
SAME ADDRESS
CONTINUE
AI00607
Doc ID 2420 Rev 9
11/22
Operation modes
M48Z02, M48Z12
2.4
VCC noise and negative going transients
I
transients, including those produced by output switching, can produce voltage
CC
fluctuations, resulting in spikes on the V bus. These transients can be reduced if
CC
capacitors are used to store energy which stabilizes the V bus. The energy stored in the
CC
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 8) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V that drive it to values below V by as much as
CC
SS
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a Schottky diode from V to V (cathode connected to V , anode to V ).
CC
SS
CC
SS
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.
Figure 8.
Supply voltage protection
V
CC
V
CC
0.1µF
DEVICE
V
SS
AI02169
12/22
Doc ID 2420 Rev 9
M48Z02, M48Z12
Maximum ratings
3
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
TA
Ambient operating temperature
Storage temperature (VCC off, oscillator off)
Lead solder temperature for 10 seconds
Input or output voltages
Grade 1
0 to 70
–40 to 85
260
°C
°C
°C
V
TSTG
(1)
TSLD
VIO
VCC
IO
–0.3 to 7
–0.3 to 7
20
Supply voltage
V
Output current
mA
W
PD
Power dissipation
1
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices
shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST
recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.
Caution:
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Doc ID 2420 Rev 9
13/22
DC and AC parameters
M48Z02, M48Z12
4
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in Table 6:
Operating and AC measurement conditions. Designers should check that the operating
conditions in their projects match the measurement conditions when using the quoted
parameters.
Table 6.
Operating and AC measurement conditions
Parameter M48Z02
M48Z12
Unit
Supply voltage (VCC
)
4.75 to 5.5
0 to 70
100
4.5 to 5.5
0 to 70
100
V
°C
pF
ns
V
Ambient operating temperature (TA)
Load capacitance (CL)
Grade 1
Input rise and fall times
≤ 5
≤ 5
Input pulse voltages
0 to 3
1.5
0 to 3
1.5
Input and output timing ref. voltages
V
Note:
Output Hi-Z is defined as the point where data is no longer driven.
Figure 9.
AC testing load circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
C
L
= 100pF
C
includes JIG capacitance
L
AI01019
Table 7.
Symbol
CIN
Capacitance
Parameter(1)(2)
Min
Max
Unit
Input capacitance
-
-
10
10
pF
pF
(3)
CIO
Input / output capacitance
1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested.
2. At 25°C, f = 1 MHz.
3. Outputs deselected.
14/22
Doc ID 2420 Rev 9
M48Z02, M48Z12
DC and AC parameters
Table 8.
Symbol
ILI
DC characteristics
Parameter
Input leakage current
Test condition(1)
Min
Max
Unit
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
Outputs open
E = VIH
1
µA
µA
mA
mA
mA
V
(2)
ILO
Output leakage current
Supply current
1
ICC
ICC1
ICC2
VIL
80
Supply current (standby) TTL
Supply current (standby) CMOS
Input low voltage
3
3
E = VCC – 0.2 V
–0.3
2.2
0.8
VIH
Input high voltage
VCC + 0.3
0.4
V
VOL
VOH
Output low voltage
IOL = 2.1 mA
IOH = –1 mA
V
Output high voltage
2.4
V
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2. Outputs deselected.
Figure 10. Power down/up mode AC waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tDR
tR
tPD
tFB
tRB
tREC
RECOGNIZED
NOTE
RECOGNIZED
INPUTS
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI00606
Note:
Inputs may or may not be recognized at this time. Caution should be taken to keep E high as
rises past V (min). Some systems may perform inadvertent WRITE cycles after V
CC
V
CC
PFD
rises above V
(min) but before normal system operations begin. Even though a power on
PFD
reset is being applied to the processor, a reset condition may not occur until after the system
is running.
Doc ID 2420 Rev 9
15/22
DC and AC parameters
M48Z02, M48Z12
Table 9.
Symbol
tPD
Power down/up AC characteristics
Parameter(1)
Min
Max
Unit
E or W at VIH before power down
VPFD (max) to VPFD (min) VCC fall time
VPFD (min) to VSS VCC fall time
VPFD (min) to VPFD (max) VCC rise time
VSS to VPFD (min) VCC rise time
E or W at VIH after power up
0
300
10
0
-
-
-
-
-
-
µs
µs
µs
µs
µs
ms
(2)
tF
(3)
tFB
tR
tRB
1
tREC
2
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring
until 200 µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10. Power down/up trip points DC characteristics
Symbol
Parameter(1)(2)
Min
Typ
Max
Unit
M48Z02
M48Z12
4.5
4.2
4.6
4.3
3.0
4.75
4.5
V
VPFD
VSO
Power-fail deselect voltage
V
V
Battery backup switchover voltage
Expected data retention time
(3)
tDR
10
YEARS
1. All voltages referenced to VSS
.
2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
3. At 25 °C, VCC = 0 V.
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Package mechanical data
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline
A2
A
L
A1
e1
C
B1
B
eA
e3
D
N
1
E
PCDIP
Note:
Drawing is not to scale.
Table 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mechanical
data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
A1
A2
B
8.89
0.38
8.38
0.38
1.14
0.20
34.29
17.83
2.29
9.65
0.76
8.89
0.53
1.78
0.31
34.80
18.34
2.79
0.350
0.015
0.330
0.015
0.045
0.008
1.350
0.702
0.090
0.380
0.030
0.350
0.021
0.070
0.012
1.370
0.722
0.110
B1
C
D
E
e1
e3
eA
L
27.94
1.1
15.24
3.05
24
16.00
3.81
0.600
0.120
24
0.630
0.150
N
Doc ID 2420 Rev 9
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Package mechanical data
M48Z02, M48Z12
Figure 12. Shipping tube dimensions for PCDIP24 package
1011292_E
Note:
All dimensions are in inches.
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M48Z02, M48Z12
Part numbering
6
Part numbering
Table 12. Ordering information scheme
Example:
M48Z
02
–70
PC
1
Device type
M48Z
Supply voltage and write protect voltage
02 = VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V
12 = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V
Speed
–70 = 70 ns (M48Z02/12)
–150 = 150 ns (M48Z02/12)
–200 = 200 ns (M48Z02/12)(1)
Package
PC = PCDIP24
Temperature range
1 = 0 to 70 °C
1. Not recommended for new design. Contact local ST sales office for availability.
For a list of available options (e.g., speed, package) or for further information on any aspect
of this device, please contact the ST sales office nearest you.
Doc ID 2420 Rev 9
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Environmental information
M48Z02, M48Z12
7
Environmental information
Figure 13. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
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Revision history
8
Revision history
Table 13. Document revision history
Date
Revision
Changes
May-1999
1
First issue
Reformatted; temperature information added to tables (Table 5, 6, 7, 8,
3, 4, 9, 10); Figure updated (Figure 10)
09-Jul-2001
2
17-Dec-2001
20-May-2002
01-Apr-2003
22-Apr-2003
2.1
2.2
3
Remove references to “clock” in document
Updated VCC noise and negative going transients text
v2.2 template applied; test condition updated (Table 10)
Fix error in ordering information (Table 12)
3.1
Update template, Lead-free text, and remove references to ‘crystal’ and
footnote (Table 8, 12)
12-Dec-2005
4
Reformatted document; added lead-free second level interconnect
information to cover page and Section 5: Package mechanical data;
updated Table 5, 6, 8, 9, 10, 12.
02-Nov-2007
5
03-Dec-2008
27-May-2010
6
7
Added Section 7: Environmental information; minor formatting changes.
Updated Section 3, Table 11, text in Section 5; reformatted document.
Updated Table 12: Ordering information scheme for 200 ns version of
devices; updated Section 7; added Figure 12; minor textual updates.
21-Jan-2011
07-Jun-2011
8
9
Updated footnote of Table 5: Absolute maximum ratings.
Doc ID 2420 Rev 9
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M48Z02, M48Z12
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