M48T59Y-70MH1TR [STMICROELECTRONICS]

64 Kbit 8Kb x8 TIMEKEEPER SRAM; 64 Kbit的是8K ×8 TIMEKEEPER SRAM


型号：	M48T59Y-70MH1TR
厂家：	ST
描述：	64 Kbit 8Kb x8 TIMEKEEPER SRAM 64 Kbit的是8K ×8 TIMEKEEPER SRAM 计时器或实时时钟微控制器和处理器外围集成电路静态存储器光电二极管双倍数据速率
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M48T58

M48T58Y

64 Kbit (8Kb x8) TIMEKEEPER SRAM

INTEGRATED ULTRA LOW POWER SRAM,

REAL TIME CLOCK, POWER-FAIL CONTROL

CIRCUIT and BATTERY

BYTEWIDE RAM-LIKE CLOCK ACCESS

SNAPHAT (SH)

Battery/Crystal

BCD CODED YEAR, MONTH, DAY, DATE,

HOURS, MINUTES and SECONDS

FREQUENCY TEST OUTPUT for REAL TIME

CLOCK

AUTOMATIC POWER-FAIL CHIP DESELECT and

WRITE PROTECTION

WRITE PROTECT VOLTAGES

(V_PFD= Power-fail Deselect Voltage):

– M48T58: 4.5V ≤ V_PFD≤ 4.75V

– M48T58Y: 4.2V ≤ V_PFD≤ 4.5V

SELF-CONTAINED BATTERY and CRYSTAL

in the CAPHAT DIP PACKAGE

PCDIP28 (PC)

Battery/Crystal

CAPHAT

SOH28 (MH)

PACKAGING INCLUDES a 28-LEAD SOIC

and SNAPHAT^®TOP

(to be Ordered Separately)

Figure 1. Logic Diagram

SOIC PACKAGE PROVIDES DIRECT

CONNECTION for a SNAPHAT TOP which

CONTAINS the BATTERY and CRYSTAL

PIN and FUNCTION COMPATIBLE with

JEDEC STANDARD 8K x 8 SRAMs

DESCRIPTION

The M48T58/58Y TIMEKEEPER^®RAM is an 8K x

8 non-volatile static RAM and real time clock. The

monolithic chip is available in two special packages

to provide a highly integrated battery backed-up

memory and real time clock solution.

A0-A12

DQ0-DQ7

M48T58

M48T58Y

Table 1. Signal Names

A0-A12

DQ0-DQ7

Address Inputs

Data Inputs / Outputs

Frequency Test Output (Open Drain)

Chip Enable 1

Chip Enable 2

Output Enable

AI01374B

Write Enable

V_CC

V_SS

Supply Voltage

Ground

July 1999

1/17

M48T58, M48T58Y

Figure 2A. DIP Pin Connections

Figure 2B. SOIC Pin Connections

A12

26 E2

25 A8

24 A9

23 A11

A11

M48T58

M48T58Y

21 A10

20 E1

A10

A0 10

DQ0 11

DQ1 12

DQ2 13

19 DQ7

18 DQ6

17 DQ5

16 DQ4

15 DQ3

DQ7

DQ6

DQ5

DQ4

DQ3

DQ0

DQ1

DQ2

AI01375B

AI01376B

Table 2. Absolute Maximum Ratings ⁽¹⁾

Symbol

T_A

Parameter

Value

Unit

Ambient Operating Temperature

Storage Temperature (V_CCOff, Oscillator Off)

Lead Solder Temperature for 10 seconds

Input or Output Voltages

0 to 70

°C

T_STG

–40 to 85

260

(2)

T_SLD

V_IO

V_CC

I_O

–0.3 to 7

Supply Voltage

Output Current

P_D

Power Dissipation

Notes:

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may

affect reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.

CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

Table 3. Operating Modes ⁽¹⁾

Mode

Deselect

Write

V_CC

V_IH

DQ0-DQ7

High Z

D_IN

Power

Standby

V_IL

V_IH

Standby

4.75V to 5.5V

4.5V to 5.5V

V_IL

V_IH

Active

Read

V_IL

V_IH

D_OUT

Active

Read

High Z

Active

Deselect

V_SOto V_PFD(min) ⁽²⁾

CMOS Standby

Battery Back-up Mode

≤ V_SO

Notes

: 1. X = V_IHor V_IL; V_SO= Battery Back-up Switchover Voltage.

2. See Table 7 for details.

2/17

M48T58, M48T58Y

Figure 3. Block Diagram

OSCILLATOR AND

CLOCK CHAIN

8 x 8 BiPORT

SRAM ARRAY

32,768 Hz

CRYSTAL

A0-A12

POWER

DQ0-DQ7

8184 x 8

SRAM ARRAY

LITHIUM

CELL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

PFD

AI01377C

DESCRIPTION

Table 4. AC Measurement Conditions

(cont’d)

The M48T58/58Y is a non-volatile pin and function

equivalent to any JEDEC standard 8K x 8 SRAM.

It also easily fits into many ROM, EPROM, and

EEPROM sockets, providing the non-volatility of

PROMs without any requirement for special write

timing or limitations on the number of writes that

can be performed.

Input Rise and Fall Times

≤ 5ns

Input Pulse Voltages

0 to 3V

1.5V

Input and Output Timing Ref. Voltages

Note that Output Hi-Z is defined as the point where data is no

longer driven.

The 28 pin 600mil DIP CAPHAT houses the

M48T58/58Y silicon with a quartz crystal and a long

life lithium button cell in a single package.

Figure 4. AC Testing Load Circuit

The 28 pin 330mil SOIC provides sockets with gold

plated contacts at both ends for direct connection

to a separate SNAPHAT housing containing the

battery and crystal. The unique design allows the

SNAPHAT battery package to be mounted on top

of the SOIC package after the completion of the

surface mount process. Insertion of the SNAPHAT

housing after reflow prevents potential battery and

crystal damage due to the high temperatures re-

quired for device surface-mounting. The SNAPHAT

housing is keyed to prevent reverse insertion.

1.9kΩ

DEVICE

UNDER

OUT

TEST

1kΩ

= 100pF or 5pF

The SOIC and battery/crystal packages are

shipped separately in plastic anti-static tubes or in

Tape & Reel form.

includes JIG capacitance

AI01030

3/17

M48T58, M48T58Y

Table 5. Capacitance ^{(1, 2)}

(T_A= 25 C, f = 1 MHz )

Symbol

Parameter

Test Condition

V_IN= 0V

Min

Max

Unit

C_IN

Input Capacitance

(3)

C_IO

Input / Output Capacitance

V_OUT= 0V

Notes:

1. Effective capacitance measured with power supply at 5V.

2. Sampled only, not 100% tested.

3. Outputs deselected

Table 6. DC Characteristics

(T_A= 0 to 70 C; V_CC= 4.75V to 5.5V or 4.5V to 5.5V)

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Supply Current

Test Condition

0V ≤ V_IN≤ V_CC

0V ≤ V_OUT≤ V_CC

Outputs open

Min

Max

Unit

µA

(1)

I_LI

±1

±5

(1)

I_LO

µA

I_CC

I_CC1

Supply Current (Standby) TTL

E1 = V_IH, E2 = V_IL

E1 = V_CC– 0.2V,

E2 = V_SS+ 0.2V

I_CC2

Supply Current (Standby) CMOS

(2)

V_IL

Input Low Voltage

–0.3

2.2

0.8

V_CC+ 0.3

0.4

V_IH

Input High Voltage

Output Low Voltage

Output Low Voltage (FT) ⁽³⁾

Output High Voltage

I_OL= 2.1mA

I_OL= 10mA

I_OH= –1mA

V_OL

0.4

V_OH

2.4

Notes:

1. Outputs Deselected.

2. Negative spikes of –1V allowed for up to 10ns once per Cycle.

3. The FT pin is Open Drain.

Table 7. Power Down/Up Trip Points DC Characteristics ⁽¹⁾

(T_A= 0 to 70 C)

Symbol

Parameter

Min

4.5

4.2

Typ

4.6

Max

4.75

4.5

Unit

V_PFD

V_SO

Power-fail Deselect Voltage (M48T58)

Power-fail Deselect Voltage (M48T58Y)

Battery Back-up Switchover Voltage

Expected Data Retention Time

4.35

3.0

(2)

t_DR

YEARS

Notes:

1. All voltages referenced to V_SS

2. At 25°C

DESCRIPTION

(cont’d)

BYTEWIDE clock information in the bytes with

addresses 1FF8h-1FFFh. The clock locations con-

tain the year, month, date, day, hour, minute, and

second in 24 hour BCD format. Corrections for 28,

29 (leap year), 30, and 31 day months are made

automatically. Byte 1FF8h is the clock control reg-

ister. This byte controls user access to the clock

information and also stores the clock calibration

setting.

For the 28 lead SOIC, the battery/crystal package

(i.e. SNAPHAT) part number is "M4T28-

BR12SH1".

As Figure 3 shows, the static memory array and the

quartz controlled clock oscillator of the

M48T58/58Y are integrated on one silicon chip.

The two circuits are interconnected at the upper

eight memory locations to provide user accessible

4/17

M48T58, M48T58Y

Table 8. Power Down/Up Mode AC Characteristics

(T_A= 0 to 70 C)

Symbol

Parameter

Min

Max

Unit

µs

t_PD

E1 or W at V_IHor E2 at V_ILbefore Power Down

V_PFD(max) to V_PFD(min) V_CCFall Time

V_PFD(min) to V_SOV_CCFall Time

(1)

t_F

300

µs

(2)

t_FB

t_R

µs

V_PFD(min) to V_PFD(max) V_CCRise Time

V_SOto V_PFD(min) V_CCRise Time

µs

t_RB

µs

t_REC

V_PFD(max) to Inputs Recognized

200

Notes

: 1. V_PFD(max) to V_PFD(min) fall time of less than t_Fmay result in deselection/write protection not occurring until 200 s after

V_CCpasses V_PFD(min).

2. V_PFD(min) to V_SOfall time of less than t_FBmay cause corruption of RAM data.

Figure 5. Power Down/Up Mode AC Waveforms

(max)

(min)

PFD

tFB

tRB

tPD

tDR

tREC

RECOGNIZED

INPUTS

DON'T CARE

HIGH-Z

OUTPUTS

VALID

(PER CONTROL INPUT)

AI01168C

5/17

M48T58, M48T58Y

Table 9. Read Mode AC Characteristics

(T_A= 0 to 70 C; V_CC= 4.75V to 5.5V or 4.5V to 5.5V)

M48T58 / M48T58Y

-70

Symbol

Parameter

Unit

Min

Max

t_AVAV

Read Cycle Time

(1)

t_AVQV

Address Valid to Output Valid

(1)

t_E1LQV

Chip Enable 1 Low to Output Valid

Chip Enable 2 High to Output Valid

Output Enable Low to Output Valid

Chip Enable 1 Low to Output Transition

Chip Enable 2 High to Output Transition

Output Enable Low to Output Transition

Chip Enable 1 High to Output Hi-Z

Chip Enable 2 Low to Output Hi-Z

Output Enable High to Output Hi-Z

Address Transition to Output Transition

(1)

t_E2HQV

(1)

t_GLQV

(2)

t_E1LQX

(2)

t_E2HQX

(2)

t_GLQX

(2)

t_E1HQZ

(2)

t_E2LQZ

(2)

t_GHQZ

(1)

t_AXQX

Notes:

1. C_L= 100pF (see Figure 4).

2. C_L= 5pF (see Figure 4).

Figure 6. Read Mode AC Waveforms

tAVAV

VALID

A0-A12

tAVQV

tE1LQV

tAXQX

tE1HQZ

tE1LQX

tE2HQV

tE2LQZ

tE2HQX

tGLQV

tGHQZ

tGLQX

DQ0-DQ7

VALID

AI00962

Note:

Write Enable (W) = High.

6/17

M48T58, M48T58Y

Table 10. Write Mode AC Characteristics

(T_A= 0 to 70 C; V_CC= 4.75V to 5.5V or 4.5V to 5.5V)

M48T58 / M48T58Y

-70

Symbol

Parameter

Unit

Min

Max

t_AVAV

t_AVWL

Write Cycle Time

Address Valid to Write Enable Low

Address Valid to Chip Enable 1 Low

Address Valid to Chip Enable 2 High

Write Enable Pulse Width

t_AVE1L

t_AVE2H

t_WLWH

t_E1LE1H

t_E2HE2L

t_WHAX

t_E1HAX

t_E2LAX

t_DVWH

t_DVE1H

t_DVE2L

t_WHDX

t_E1HDX

t_E2LDX

Chip Enable 1 Low to Chip Enable 1 High

Chip Enable 2 High to Chip Enable 2 Low

Write Enable High to Address Transition

Chip Enable 1 High to Address Transition

Chip Enable 2 Low to Address Transition

Input Valid to Write Enable High

Input Valid to Chip Enable 1 High

Input Valid to Chip Enable 2 Low

Write Enable High to Input Transition

Chip Enable 1 High to Input Transition

Chip Enable 2 Low to Input Transition

Write Enable Low to Output Hi-Z

(1, 2)

t_WLQZ

t_AVWH

t_AVE1H

t_AVE2L

Address Valid to Write Enable High

Address Valid to Chip Enable 1 High

Address Valid to Chip Enable 2 Low

Write Enable High to Output Transition

(1, 2)

t_WHQX

Notes:

1. C_L= 5pF (see Figure 4).

2. If E1 goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance state.

7/17

M48T58, M48T58Y

Figure 7. Write Enable Controlled, Write AC Waveforms

tAVAV

A0-A12

VALID

tAVWH

tAVE1L

tAVE2H

tWHAX

tWLWH

tAVWL

tWLQZ

tWHQX

tWHDX

DQ0-DQ7

DATA INPUT

tDVWH

AI00963

Figure 8. Chip Enable Controlled, Write AC Waveforms

tAVAV

A0-A12

VALID

tAVE1H

tE1LE1H

tAVE1L

tAVE2H

tE1HAX

tE2LAX

tAVE2L

tE2HE2L

tAVWL

tE1HDX

tE2LDX

DQ0-DQ7

DATA INPUT

tDVE1H

tDVE2L

AI00964B

8/17

M48T58, M48T58Y

DESCRIPTION

E2 and G access times are not met, valid data will

be available after the latter of the Chip Enable

Access times (t_E1LQVor t_E2HQV) or Output Enable

Access time (t_GLQV).

(cont’d)

The eight clock bytes are not the actual clock

counters themselves; they are memory locations

consisting of BiPORT read/write memory cells.

The M48T58/58Y includes a clock control circuit

which updates the clock bytes with current informa-

tion once per second. The information can be

accessed by the user in the same manner as any

other location in the static memory array.

The state of the eight three-state Data I/O signals

is controlled by E1, E2 and G. If the outputs are

activated before t_AVQV, the data lines will be driven

to an indeterminate state until t_AVQV. If the Address

Inputs are changed while E1, E2 and G remain

active, output data will remain valid for Output Data

Hold time (t_AXQX) but will go indeterminate until the

next Address Access.

The M48T58/58Y also has its own Power-fail De-

tect circuit. The control circuitry constantly monitors

the single 5V supply for an out of tolerance condi-

tion. When V_CCis out of tolerance, the circuit write

protects the SRAM, providing a high degree of data

security in the midst of unpredictable system op-

eration brought on by low V_CC. As V_CCfalls below

approximately 3V, the control circuitry connects the

battery which maintains data and clock operation

until valid power returns.

WRITE MODE

The M48T58/58Y is in the Write Mode whenever W

and E1 are low and E2 is high. The start of a write

is referenced from the latter occurring falling edge

of W or E1, or the rising edge of E2. A write is

terminated by the earlier rising edge of W or E1, or

the falling edge of E2. The addresses must be held

valid throughoutthe cycle. E1 orWmust return high

or E2 low for a minimum of t_E1HAXor t_E2LAXfrom

Chip Enable or t_WHAXfrom Write Enable prior to the

initiation of another read or write cycle. Data-in

must be valid t_DVWHprior to the end of write and

remain valid for t_WHDXafterward. G should be kept

high during write cycles to avoid bus contention;

although, if the output bus has been activated by a

low on E1 and G and a high on E2, a low on W will

disable the outputs t_WLQZafter W falls.

READ MODE

The M48T58/58Y is in the Read Mode whenever

W (Write Enable) is high, E1 (Chip Enable 1) is low,

and E2 (Chip Enable 2) is high. The unique address

specified by the 13 Address Inputs defines which

one of the 8,192 bytes of data is to be accessed.

Valid data will be available at the Data I/O pins

within Address Access time (t_AVQV) after the last

address input signal is stable, providing that the E1,

E2, and G access times are also satisfied. If the E1,

Table 11. Register Map

Data

Function/Range

BCD Format

Address

10 M.

1FFFh

1FFEh

1FFDh

1FFCh

1FFBh

1FFAh

1FF9h

1FF8h

10 Years

Year

Month

Date

Year

Month

Date

00-99

01-12

01-31

01-07

00-23

00-59

10 Date

Day

Hours

Day

10 Hours

Hour

10 Minutes

10 Seconds

Minutes

Seconds

Control

Seconds

Calibration

Keys:

= SIGN Bit

FT = FREQUENCY TEST Bit (Must be set to ’0’ upon power, for normal clock operation)

= READ Bit

W = WRITE Bit

ST = STOP Bit

= Must be set to ’0’

9/17

M48T58, M48T58Y

DATA RETENTION MODE

CLOCK OPERATIONS

Reading the Clock

With valid V_CCapplied, the M48T58/58Y operates

as a conventional BYTEWIDE static RAM. Should

the supply voltage decay, the RAM will automat-

ically power-fail deselect, write protecting itself

when V_CCfalls within the V_PFD(max), V_PFD(min)

window. All outputs become high impedance, and

all inputs are treated as "don’t care."

Updates to the TIMEKEEPER registers should be

halted before clock data is read to prevent reading

data in transition. Because the BiPORT TIME-

KEEPER cells in the RAM array are only data

registers, and not the actual clock counters, updat-

ing the registers can be halted without disturbing

the clock itself.

Note:

A power failure during a write cycle may

corrupt data at the currently addressed location,

but does not jeopardize the rest of the RAM’s

content. At voltages below V_PFD(min), the user can

be assured the memory will be in a write protected

state, provided the V_CCfall time is not less than t_F.

The M48T58/58Y may respond to transient noise

spikes on V_CCthat reach into the deselect window

during the time the device is sampling V_CC. There-

fore, decoupling of the power supply lines is rec-

ommended.

Updating is halted when a ’1’ is written to the READ

bit, D6 in the Control register (1FF8h). As long as

a ’1’ remains in that position, updating is halted.

After a halt is issued, the registers reflect the count;

that is, the day, date, and the time that were current

at the moment the halt command was issued.

All of the TIMEKEEPER registers are updated si-

multaneously. A halt will not interrupt an update in

progress. Updating is within a second after the bit

is reset to a ’0’.

When V_CCdrops below V_SO, the control circuit

switches power to the internal battery which pre-

serves data and powers the clock. The internal

button cell will maintain data in the M48T58/58Yfor

an accumulated period ofat least7 yearswhen V_CC

is less than V_SO. As system power returns and V_CC

rises above V_SO, the battery is disconnected, and

the power supply is switched to external V_CC. Write

protection continues until V_CCreaches V_PFD(min)

plus t_REC(min). E1 should be kept high or E2 low

as V_CCrises past V_PFD(min) to prevent inadvertent

write cycles prior to system stabilization. Normal

RAM operation can resume t_RECafter V_CCexceeds

Setting the Clock

Bit D7 of the Control register (1FF8h) is the WRITE

bit. Setting the WRITE bit to a ’1’, like the READ bit,

halts updates to the TIMEKEEPER registers. The

user can then load them with the correct day, date,

and time data in 24 hour BCD format (see Table

10). Resetting the WRITE bit to a ’0’ then transfers

the values of all time registers (1FF9h-1FFFh) to

the actual TIMEKEEPER counters and allows nor-

mal operation to resume. The FT bit and the bits

marked as ’0’ in Table 10 must be written to ’0’ to

allow for normal TIMEKEEPER and RAM opera-

tion. After the WRITE bit is reset, the next clock

update will occur within one second.

V_PFD(max).

For more information on Battery Storage Life refer

to the Application Note AN1012.

See the Application Note AN923 "TIMEKEEPER

rolling into the 21st century" for information on

Century Rollover.

Figure 9. Clock Calibration

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

AI00594B

10/17

M48T58, M48T58Y

Stopping and Starting the Oscillator

tracted, negative calibration) or split (added, posi-

tive calibration) depends upon the value loaded

into the five Calibration bits found in the Control

tracting counts slows the clock down.

The oscillator may be stopped at any time. If the

device is going to spend a significant amount of

time on the shelf, the oscillator can be turned off to

minimize current drain on the battery. The STOP

bit is the MSB of the seconds register. Setting it to

a ’1’ stops the oscillator. The M48T58/58Y is

shipped from STMicroelectronics with the STOP bit

set to a ’1’. When reset to a ’0’, the M48T58

oscillator starts within one second.

The Calibration byte occupies the five lower order

bits (D4-D0) in the Control register (1FF8h). These

bits can be set to represent any value between 0

and 31 in binary form. Bit D5 is a Sign bit; ’1’

indicates positive calibration, ’0’ indicates negative

calibration. Calibration occurs within a 64 minute

cycle. The first 62 minutes in the cycle may, once

per minute, have one second either shortened by

128 or lengthened by 256 oscillator cycles. If a

binary ’1’ is loaded into the register, only the first 2

minutes in the 64 minute cycle will be modified; if a

binary 6 is loaded, the first 12 will be affected, and

so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 oscillator cycles for

every 125,829,120 actual oscillator cycles; that is

+4.068 or -2.034 ppm of adjustment per calibration

step in the calibration register. Assuming that the

oscillator is in fact running at exactly 32,768 Hz,

each of the 31 increments in the Calibration byte

would represent +10.7 or - 5.35 seconds per month

which corresponds to a total range of +5.5 or - 2.75

minutes per month.

Calibrating the Clock

The M48T58/58Y is driven by a quartz controlled

oscillator with a nominal frequency of 32,768 Hz.

The devices are tested not to exceed 35 ppm (parts

per million) oscillator frequency error at 25 C,

which equates to about 1.53 minutes per month.

With the calibration bits properly set, the accuracy

of each M48T58 improves to better than 4 ppm at

25 C.

The oscillation rate of any crystal changes with

temperature (see Figure 10). Mostclock chips com-

pensate for crystal frequency and temperature shift

error with cumbersome trim capacitors. The

M48T58/58Y design, however, employs periodic

counter correction. The calibration circuit adds or

subtracts counts from the oscillator divider circuit

at the divide by 256 stage, as shown in Figure 9.

The number of times pulses are blanked (sub-

Figure 10. Crystal Accuracy Across Temperature

ppm

-20

-40

∆F

ppm

C²

= -0.038

(T - T₀) ± 10%

-60

-80

T₀= 25 °C

-100

10 15 20 25 30 35 40 45 50 55 60 65 70

AI02124

°C

11/17

M48T58, M48T58Y

CLOCK OPERATIONS

POWER SUPPLY DECOUPLING and UNDER-

SHOOT PROTECTION

(cont’d)

Two methods are available for ascertaining how

much calibration a given M48T58/58Ymay require.

The first involves simply setting the clock, letting it

run for a month and comparing it to a known

accurate reference (like WWV broadcasts). While

that may seem crude, it allows the designer to give

the end user the ability to calibrate his clock as his

environment may require, even after the final prod-

uct is packaged in a non-user serviceable enclo-

sure. All the designer has to do is provide a simple

utility that accesses the Calibration byte.

I_CCtransients, including those produced by output

switching, can produce voltage fluctuations, result-

ing in spikes on the V_CCbus. These transients can

be reduced if capacitors are used to store energy,

which stabilizes the V_CCbus. The energy stored in

the bypass capacitors will be released as low going

spikes are generated or energy will be absorbed

when overshoots occur. A ceramic bypass capaci-

tor value of 0.1 F (as shown in Figure 11) is rec-

ommended in order to provide the needed filtering.

The second approach is better suited to a manu-

facturing environment, and involves the use of

some test equipment. When the Frequency Test

(FT) bit, the seventh-most significant bit in the Day

at 32,768 Hz, the Frequency Test (Pin 1) will toggle

at 512 Hz. Any deviation from 512 Hz indicates the

degree and direction of oscillator frequency shift at

the test temperature. For example, a reading of

512.01024 Hz would indicate a +20 ppm oscillator

frequency error, requiring a -10 (WR001010) to be

loaded into the Calibration Byte for correction. Note

that setting or changing the Calibration Byte does

not affect the Frequency test output frequency.

In addition to transients that are caused by normal

SRAM operation, power cycling can generate

negative voltage spikes on V_CCthat drive it to

values below V_SSby as much as one Volt. These

negative spikes can cause data corruption in the

SRAM while in battery backup mode. To protect

from these voltage spikes, it is recommeded to

connect a schottky diode from V_CCto V_SS(cathode

connected to V_CC, anode to V_SS). Schottky diode

1N5817 is recommended for through hole and

MBRS120T3 is recommended for surface mount.

Figure 11. Supply Voltage Protection

The FTbit must be set using the same method used

to set the clock, using the Write bit.

The Frequency Test pin is an open drain output

which requires a pull-up resistor for proper opera-

Ω

tion. A500-10k resistor is recommended in order

to control the rise time.

0.1µF

DEVICE

For more information on calibration, see the Appli-

cation Note AN934 "TIMEKEEPER Calibration".

AI02169

12/17

M48T58, M48T58Y

ORDERING INFORMATION SCHEME

Example:

M48T58Y

-70 MH

Supply Voltage and Write

Protect Voltage

58 ⁽¹⁾V_CC= 4.75V to 5.5V

Speed

Package

Temp. Range

0 to 70 °C

Shipping Method

for SOIC

-70 70ns

PCDIP28

blank Tubes

V_PFD= 4.5V to 4.75V

MH ⁽²⁾SOH28

Tape & Reel

58Y V_CC= 4.5V to 5.5V

V_PFD= 4.2V to 4.5V

Notes:

1. The M48T58 part is offered with the PCDIP28 (i.e. CAPHAT) package only.

2. The SOIC package (SOH28) requires the battery/crystal package (SNAPHAT) which is ordered separately under the part number

"M4T28-BR12SH1" in plastic tube or "M4T28-BR12SH1TR" in Tape & Reel form.

Caution:

Do not place the SNAPHAT battery/crystal package "M4T28-BR12SH1" in conductive foam since this will drain the lithium

button-cell battery.

For a list of available options (Speed, Package, etc...) or for further informationon any aspect of this device,

please contact the STMicroelectronics Sales Office nearest to you.

13/17

M48T58, M48T58Y

PCDIP28 - 28 pin Plastic DIP, battery CAPHAT

Min

inches

Symb

Typ

Max

9.65

0.76

8.89

0.53

1.78

0.31

39.88

18.34

2.79

36.32

16.00

3.81

Typ

Min

Max

8.89

0.38

8.38

0.38

1.14

0.20

39.37

17.83

2.29

29.72

15.24

3.05

0.350

0.015

0.330

0.015

0.045

0.008

1.550

0.702

0.090

1.170

0.600

0.120

0.380

0.030

0.350

0.021

0.070

0.012

1.570

0.722

0.110

1.430

0.630

0.150

PCDIP

Drawing is not to scale.

14/17

M48T58, M48T58Y

SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT

Min

inches

Symb

Typ

Max

3.05

0.36

2.69

0.51

0.32

18.49

8.89

–

Typ

Min

Max

0.120

0.014

0.106

0.020

0.012

0.728

0.350

–

0.05

2.34

0.36

0.15

17.71

8.23

–

0.002

0.092

0.014

0.006

0.697

0.324

–

1.27

0.050

3.20

11.51

0.41

0°

3.61

12.70

1.27

8°

0.126

0.453

0.016

0°

0.142

0.500

0.050

8°

0.10

0.004

SOH-A

Drawing is not to scale.

15/17

M48T58, M48T58Y

SH - 4-pin SNAPHAT Housing for 49mAh Battery

Min

inches

Min

Symb

Typ

Max

9.78

7.24

6.99

0.38

0.56

21.84

14.99

15.95

3.61

2.29

Typ

Max

0.385

0.285

0.275

0.015

0.022

0.860

0.590

0.628

0.142

0.090

6.73

6.48

0.265

0.255

0.46

21.21

14.22

15.55

3.20

0.018

0.835

0.560

0.612

0.126

0.080

2.03

SHTK-A

Drawing is not to scale.

16/17

M48T58, M48T58Y

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

® TIMEKEEPER and SNAPHAT are registered trademarks of STMicroelectronics

CAPHAT, BYTEWIDE and BiPORT are trademarks of STMicroelectronics

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta

Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

17/17

M48T59Y-70MH1TR [STMICROELECTRONICS]

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