M48T512V-85PM1 [STMICROELECTRONICS]
3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM; 3.3V - 5V 4兆位512KB X8 TIMEKEEPER SRAM
| 型号： | M48T512V-85PM1 |
| 厂家： | 
ST |
| 描述： | 3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| 文件： | 总14页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T512Y
M48T512V
®
3.3V-5V 4 Mbit (512Kb x8) TIMEKEEPER SRAM
■ INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT, BATTERY, and CRYSTAL
■ BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, and SECONDS
■ AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
32
■ WRITE PROTECT VOLTAGES:
1
(V
PFD
= Power-fail Deselect Voltage)
– M48T512Y: 4.2V ≤ V
– M48T512V: 2.7V ≤ V
≤ 4.5V
≤ 3.0V
PFD
PMDIP32 (PM)
Module
PFD
■ CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
■ SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY
APPLICATIONS
Figure 1. Logic Diagram
■ 10 YEARS of DATA RETENTION and CLOCK
OPERATION in the ABSENCE OF POWER
■ PIN and FUNCTION COMPATIBLE with
INDUSTRY STANDARD 512K X 8 SRAMS
■ SELF-CONTAINED BATTERY and CRYSTAL
V
CC
in DIP PACKAGE
DESCRIPTION
19
8
The M48T512Y/V TIMEKEEPER RAM is a 512Kb
x 8 non-volatile static RAM and real time clock or-
ganized as 524,288 words by 8 bits. The special
DIP package provides a fully integrated battery
back-up memory and real time clock solution.
A0-A18
DQ0-DQ7
W
E
M48T512Y
M48T512V
Table 1. Signal Names
G
A0-A18
Address Inputs
Data Inputs / Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Supply Voltage
Ground
DQ0-DQ7
E
V
SS
G
W
AI02262
V
CC
V
SS
December 1999
1/14
M48T512Y, M48T512V
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
0 to 70
Unit
°C
T
A
Ambient Operating Temperature
T
Storage Temperature (V Off, Oscillator Off)
–40 to 85
°C
STG
CC
(2)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
260
°C
T
SLD
V
–0.3 to V +0.3
V
V
IO
CC
M48T512Y
M48T512V
–0.3 to 7.0
V
Supply Voltage
CC
–0.3 to 4.6
V
I
Output Current
20
1
mA
W
O
P
Power Dissipation
D
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
Figure 2. DIP Connections
The 32 pin 600 mil DIP Hybrid houses a controller
chip, SRAM, quartz crystal, and a long life lithium
button cell in a single package. Figure 3 illustrates
the static memory array and the quartz controlled
clock oscillator. The clock locations contain the
year, month, date, day, hour, minute, and second
in 24 hour BCD format. Corrections for 28, 29
(leap year - compliant until the year 2100), 30, and
31 day months are made automatically. Byte
7FFF8h is the clock control register. This byte con-
trols user access to the clock information and also
stores the clock calibration setting. The seven
clock bytes (7FFFFh-7FFF9h) are not the actual
clock counters, they are memory locations consist-
ing of BiPORT™ read/write memory cells within
the static RAM array. The M48T512Y/V includes a
clock control circuit which updates the clock bytes
with current information once per second. The in-
formation can be accessed by the user in the
same manner as any other location in the static
memory array. The M48T512Y/V also has its own
Power-Fail Detect circuit. This control circuitry
constantly monitors the supply voltage for an out
A18
A16
A14
A12
A7
1
2
3
4
5
6
7
8
9
32
V
CC
31 A15
30 A17
29
W
28 A13
27 A8
A6
A5
26 A9
A4
M48T512Y 25 A11
M48T512V
A3
24
23 A10
22
G
A2 10
A1 11
E
A0 12
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
DQ0 13
DQ1 14
DQ2 15
of tolerance condition. When V
is out of toler-
CC
ance, the circuit write protects the TIMEKEEPER
register data and external SRAM, providing data
security in the midst of unpredictable system oper-
V
16
SS
AI02263
ation. As V
falls, the control circuitry automati-
CC
cally switches to the battery, maintaining data and
clock operation until valid power is restored.
READ MODE
The M48T512Y/V is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 19 Ad-
dress Inputs defines which one of the 524,288
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within Address Ac-
The M48T512Y/V directly replaces industry stan-
dard 512Kb x 8 SRAMs. It also provides the non-
volatility of Flash without any requirement for spe-
cial write timing or limitations on the number of
writes that can be performed.
2/14
M48T512Y, M48T512V
(1)
Table 3. Operating Modes
V
Mode
Deselect
Write
E
G
X
X
W
DQ0-DQ7
Power
Standby
Active
CC
V
X
High Z
IH
4.5V to 5.5V
or
3.0V to 3.6V
V
IL
V
IL
V
IL
V
D
IL
IH
IH
IN
V
IL
V
V
D
Read
Active
OUT
V
IH
Read
High Z
High Z
High Z
Active
(2)
Deselect
X
X
X
CMOS Standby
V
to V
(min)
PFD
SO
(2)
Deselect
X
X
X
Battery Back-up Mode
≤ V
SO
Note: 1. X = V or V .
IH
IL
2. See Table 7 for details.
cess Time (t
) after the last address input sig-
Table 4. AC Measurement Conditions
AVQV
nal is stable, providing the E and G access times
are also satisfied. If the E and G access times are
not met, valid data will be available after the latter
Input Rise and Fall Times
≤ 5ns
0 to 3V
1.5V
Input Pulse Voltages
of the Chip Enable Access Times (t
) or Output
ELQV
Input and Output Timing Ref. Voltages
Enable Access Time (t
). The state of the eight
GLQV
Note that Output Hi-Z is defined as the point where data is no longer
driven.
three-state Data I/O signals is controlled by E and
G. If the outputs are activated before t , the
AVQV
data lines will be driven to an indeterminate state
until t . If the Address Inputs are changed
Figure 3. AC Testing Load Circuit
AVQV
while E and G remain active, output data will re-
main valid for Output Data Hold Time (t ) but
AXQX
will go indeterminate until the next Address Ac-
cess.
650Ω
DEVICE
UNDER
TEST
WRITE MODE
The M48T512Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are low
state after the address inputs are stable. The start
of a write is referenced from the latter occurring
falling edge of W or E. A write is terminated by the
earlier rising edge of W or E. The addresses must
be held valid throughout the cycle. E or W must re-
1.75V
C
= 100pF
L
turn high for a minimum of t
from Chip Enable
EHAX
or t
from Write Enable prior to the initiation of
WHAX
another read or write cycle. Data-in must be valid
C
includes JIG capacitance
t
t
prior to the end of write and remain valid for
afterward. G should be kept high during
L
DVWH
WHDX
AI01803C
write cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G a low on W will disable the outputs t
ter W falls.
af-
WLQZ
3/14
M48T512Y, M48T512V
Figure 4. Block Diagram
8 x 8
TIMEKEEPER
REGISTERS
OSCILLATOR AND
CLOCK CHAIN
32,768 Hz
CRYSTAL
A0-A18
POWER
DQ0-DQ7
524,280 x 8
SRAM ARRAY
LITHIUM
CELL
E
VOLTAGE SENSE
AND
W
G
V
PFD
SWITCHING
CIRCUITRY
V
V
CC
SS
AI02384
DATA RETENTION MODE
switched to external V . Write protection contin-
CC
ues until V
reaches V
(min) plus t (min).
PFD ER
CC
With valid V applied, the M48T512Y/V operates
CC
Normal RAM operation can resume t after V
ER
CC
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically deselect, write protecting itself when
exceeds V
(max). Refer to Application Note
PFD
(AN1012) on the ST Web Site for more information
on battery life.
V
falls between V
(max), V
(min) win-
CC
PFD
PFD
dow. All outputs become high impedance and all
inputs are treated as "don't care".
Note: A power failure during a write cycle may cor-
rupt data at the current addressed location, but
does not jeopardize the rest of the RAM's content.
CLOCK OPERATIONS
Reading the Clock Updates to the TIMEKEEPER
registers should be halted before clock data is
read to prevent reading data in transition. Because
the BiPORT TIMEKEEPER cells in the RAM array
are only data registers, and not the actual clock
counters, updating the registers can be halted
without disturbing the clock itself. Updating is halt-
ed when a '1' is written to the READ bit, D6 in the
Control Register (7FFF8h). As long as a '1' re-
mains in that position, updating is halted. After a
halt is issued, the registers reflect the count; that
is, the day, date, and time that were current at the
moment the halt command was issued. All of the
TIMEKEEPER registers are updated simulta-
neously. A halt will not interrupt an update in
progress. Updating occurs 1 second after the
READ bit is reset to a '0'.
At voltages below V
in a write protected state, provided the V
(min), the memory will be
PFD
fall
CC
time is not less than t . The M48T512Y/V may re-
F
spond to transient noise spikes on V
that cross
CC
into the deselect window during the time the de-
vice is sampling V .Therefore, decoupling of the
CC
power supply lines is recommended. When V
CC
drops below V , the control circuit switches pow-
SO
er to the internal battery, preserving data and pow-
ering the clock. The internal energy source will
maintain data in the M48T512Y/V for an accumu-
lated period of at least 10 years at room tempera-
ture. As system power rises above V , the
SO
battery is disconnected, and the power supply is
4/14
M48T512Y, M48T512V
(1)
Table 5. Capacitance
(T = 25 °C, f = 1 MHz)
A
Symbol
Parameter
Input Capacitance
Test Condition
Min
Max
Unit
C
V
= 0V
= 0V
20
pF
IN
(2)
IN
V
OUT
Input / Output Capacitance
20
pF
C
IO
Note: 1. Effective capacitance measured with power supply at 5V (M48T512Y) or 3.3V (M48T512V). Sampled only, not 100% tested.
2. Outputs deselected.
Table 6A. DC Characteristics
(T = 0 to 70 °C; V = 4.5V to 5.5V)
A
CC
Symbol
Parameter
Test Condition
Min
Max
Unit
(1)
0V ≤ V ≤ V
Input Leakage Current
±2
µA
I
IN
CC
LI
(1)
0V ≤ V
≤ V
CC
Output Leakage Current
Supply Current
±2
115
8
µA
mA
mA
mA
I
OUT
LO
I
Outputs open
CC
I
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
CC1
IH
E = V – 0.2V
4
CC2
CC
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.3
2.2
0.8
V
V
V
V
V
IL
V
V
V
+ 0.3
IH
CC
I
= 2.1mA
= –1mA
0.4
OL
OL
V
OH
I
OH
2.4
Note: 1. Outputs deselected.
Table 6B. DC Characteristics
(T = 0 to 70 °C; V = 3.0V to 3.6V)
A
CC
Symbol
Parameter
Test Condition
Min
Max
Unit
(1)
0V ≤ V ≤ V
Input Leakage Current
±2
µA
I
IN
CC
LI
(1)
0V ≤ V
≤ V
CC
Output Leakage Current
Supply Current
±2
60
4
µA
mA
mA
mA
I
OUT
LO
I
Outputs open
CC
I
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
CC1
CC2
IH
E = V – 0.2V
3
CC
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.3
2.2
0.4
V
V
V
V
V
IL
V
V
V
+ 0.3
IH
CC
I
= 2.1mA
= –1mA
0.4
OL
OL
V
OH
I
OH
2.2
Note: 1. Outputs deselected.
5/14
M48T512Y, M48T512V
Figure 5. Power Down/Up Mode AC Waveforms
tF
V
V
CC
PFD
(max)
(min)
V
PFD
V
V
SO
SS
tWP
tDR
tR
tFB
tRB
DON'T CARE
tER
INPUTS
RECOGNIZED
RECOGNIZED
(Including E)
HIGH-Z
OUTPUTS
VALID
VALID
AI02385
(1)
Table 7. Power Down/Up Trip Points DC Characteristics
(T = 0 to 70 °C)
A
Symbol
Parameter
Power-fail Deselect Voltage
Min
4.2
2.7
Typ
4.35
2.9
Max
4.5
Unit
V
M48T512Y
M48T512V
M48T512Y
M48T512V
V
PFD
3.0
V
3.0
V
V
SO
Battery Back-up Switchover Voltage
V
–100mV
PFD
(2)
Expected Data Retention Time
10
YEARS
t
DR
Note: 1. All voltages referenced to V
.
SS
2. At 25°C.
Table 8. Power Down/Up AC Characteristics
(T = 0 to 70 °C)
A
Symbol
Parameter
Min
Max
Unit
(1)
V
(max) to V
(min) to V
(min) V Fall Time
300
µs
t
PFD
PFD
CC
F
M48T512Y
M48T512V
10
150
10
1
µs
µs
µs
µs
µs
ms
(2)
V
PFD
V
Fall Time
t
SS CC
FB
t
V
V
(min) to V
(max) V Rise Time
PFD CC
R
PFD
t
to V (min) V Rise Time
PFD CC
RB
SS
t
Write Protect Time on V = V
PFD
40
40
150
200
WP
CC
t
E Recovery Time
ER
Note: 1. V
(max) to V
(min) fall time of less than t may result in deselection/write protection not occurring until 200µs after V pass-
F CC
PFD
PFD
es V
(min).
PFD
2. V
(min) to V fall time of less than t may cause corruption of RAM data.
SS FB
PFD
6/14
M48T512Y, M48T512V
Table 9. Read Mode AC Characteristics
(T = 0 to 70 °C)
A
M48T512Y
-70
M48T512V
Symbol
Parameter
-85
Unit
Min
Max
Min
Max
t
Read Cycle Time
70
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(1)
Address Valid to Output Valid
70
70
40
85
85
55
t
t
AVQV
ELQV
GLQV
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
t
5
5
5
5
t
ELQX
GLQX
EHQZ
GHQZ
t
t
25
25
30
30
t
10
5
t
AXQX
Note: 1. C = 100pF.
L
2. C = 5pF.
L
Figure 6. Address Controlled, Read Mode AC Waveforms
tAVAV
A0-A16
VALID
tAVQV
tAXQX
DQ0-DQ7
DATA VALID
DATA VALID
AI02324
Setting the Clock. Bit D7 of the Control Register
(7FFF8h) is the WRITE bit. Setting the WRITE bit
to a '1', like the READ bit, halts updates to the
TIMEKEEPER registers. The user can then load
them with the correct day, date, and time data in
24 hour BCD format (see Table 11). Resetting the
WRITE bit to a '0' then transfers the values of all
time registers 7FFFFh-7FFF9h to the actual TIME-
KEEPER counters and allows normal operation to
resume. After the WRITE bit is reset, the next
clock update will occur approximately one second
later. See Application Note, AN923, (TIMEKEEP-
ERS "ROLLING INTO" THE 21ST CENTURY) on
the ST Web Site for more information on Century
Rollover.
Note: Upon power-up, both the WRITE bit and the
READ bit will be reset to '0'.
Stopping and Starting the Oscillator. The os-
cillator may be stopped at any time. If the device is
going to spend a significant amount of time on the
shelf, the oscillator can be turned off to minimize
current drain on the battery. The STOP bit is locat-
ed at Bit D7 within 7FFF9h. Setting it to a '1' stops
the oscillator. The M48T512Y/V is shipped from
STMicroelectronics with the STOP bit set to a '1'.
When reset to a '0', the M48T512Y/V oscillator
starts after approximately one second.
Note: It is not necessary to set the WRITE bit
when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).
7/14
M48T512Y, M48T512V
Table 10. Write Mode AC Characteristics
(T = 0 to 70 °C)
A
M48T512Y
-70
M48T512V
-85
Symbol
Parameter
Unit
Min
Max
Min
Max
t
Write Cycle Time
70
0
85
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
AVWL
t
0
0
AVEL
t
50
55
5
60
65
5
WLWH
t
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
ELEH
t
WHAX
t
10
30
30
5
15
35
35
5
EHAX
t
DVWH
t
DVEH
t
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable Low to Output Hi-Z
WHDX
t
10
15
EHDX
(1, 2)
25
30
t
WLQZ
t
Address Valid to Write Enable High
Address Valid to Chip Enable High
Write Enable High to Output Transition
60
60
5
70
70
5
ns
ns
ns
AVWH
t
AVE1H
(1, 2)
t
WHQX
Note: 1. C = 5pF.
L
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Calibrating the Clock. The M48T512Y/V is driv-
en by a quartz controlled oscillator with a nominal
frequency of 32,768Hz. The devices are factory
calibrated at 25°C and tested for accuracy. Clock
accuracy will not exceed 35 ppm (parts per million)
oscillator frequency error at 25°C, which equates
to about ±1.53 minutes per month. When the Cal-
ibration circuit is properly employed, accuracy im-
proves to better than +4 ppm at 25°C. The
oscillation rate of crystals changes with tempera-
ture. The M48T512Y/V design employs periodic
counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 10.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down. The Calibra-
tion bits occupy the five lower order bits (D4-D0) in
the Control Register 7FFF8h. These bits can be
set to represent any value between 0 and 31 in bi-
nary form. Bit D5 is a Sign bit; '1' indicates positive
calibration, '0' indicates negative calibration. Cali-
bration occurs within a 64 minute cycle. The first
62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or
lengthened by 256 oscillator cycles. If a binary '1'
is loaded into the register, only the first 2 minutes
in the 64 minute cycle will be modified; if a binary
6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125, 829, 120 actual oscillator cycles; that
is, +4.068 or –2.034 ppm of adjustment per cali-
bration step in the calibration register.
8/14
M48T512Y, M48T512V
Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV
VALID
A0-A18
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI02389
Figure 8. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A18
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DATA INPUT
tDVWH
DQ0-DQ7
AI02386
9/14
M48T512Y, M48T512V
Figure 9. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A18
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI02387
Assuming that the oscillator is running at exactly
32,768Hz, each of the 31 increments in the Cali-
bration byte would represent +10.7 or –5.35 sec-
onds per month which corresponds to a total range
of +5.5 or –2.75 minutes per month. Figure 10 il-
lustrates a TIMEKEEPER calibration waveform.
POWER SUPPLY DECOUPLING
and UNDERSHOOT PROTECTION
Note: I transients, including those produced by
CC
output switching, can produce voltage fluctua-
tions, resulting in spikes on the V
bus. These
CC
transients can be reduced if capacitors are used to
One method for ascertaining how much calibration
a given M48T512Y/V may require involves setting
the clock, letting it run for a month and comparing
it to a known accurate reference and recording de-
viation over a fixed period of time.
Calibration values, including the number of sec-
onds lost or gained in a given period, can be found
in STMicroelectronics Application Note: TIME-
KEEPER CALIBRATION. This allows the designer
to give the end user the ability to calibrate the
clock as the environment requires, even if the final
product is packaged in a non-user serviceable en-
closure. The designer could provide a simple utility
that accesses the Calibration bits. For more infor-
mation on calibration, see Application Note (TIME-
KEEPER CALIBRATION) on the ST Web Site.
store energy, which stabilizes the V bus. The
CC
energy stored in the bypass capacitors will be re-
leased as low going spikes are generated or ener-
gy will be absorbed when overshoots occur. A
ceramic bypass capacitor value of 0.1µF is recom-
mended in order to provide the needed filtering. In
addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V
that drive it to values
CC
below V by as much as one volt. These negative
SS
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, ST recommends connecting
a schottky diode from V
to V
(cathode con-
CC
SS
nected to V , anode to V ). (Schottky diode
CC
SS
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount).
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M48T512Y, M48T512V
Table 11. Register Map
Address
Data
Function/Range
BCD Format
D7
D6
D5
D4
D3
D2
D1
D0
7FFFFh
7FFFEh
7FFFDh
7FFFCh
7FFFBh
7FFFAh
7FFF9h
7FFF8h
10 Years
Year
Month
Date
Year
Month
Date
00-99
01-12
01-31
01-07
00-23
00-59
00-59
0
0
0
0
0
0
0
10 M
10 Date
0
0
0
0
Day
Hours
Day
0
10 Hours
Hour
0
10 Minutes
10 Seconds
S
Minutes
Minutes
Seconds
Control
ST
W
Seconds
R
Calibration
Keys: S = SIGN Bit
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to zero
Figure 10. Calibration Waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
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M48T512Y, M48T512V
Table 12. Ordering Information Scheme
Example:
M48T512Y
-70 PM
1
Device Type
M48T
Supply Voltage and Write Protect Voltage
512Y = V = 4.5V to 5.5V; V
= 4.2V to 4.5V
= 2.7V to 3.0V
CC
PFD
512V = V = 3.0V to 3.6V; V
CC
PFD
Speed
-70 = 70ns
-85 = 85 ns
Package
PM = PMDIP32
Temperature Range
1 = 0 to 70 °C
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
Table 13. Revision History
Date
Revision Details
June 1998
First Issue
M48T512Y: V
(Min) changed
PFD
Figure 3 changed
12/03/99
t
changed (Figure 5, Table 8)
FB
t
changed (Figure 5, Table 8)
RB
12/14
M48T512Y, M48T512V
Table 14. PMDIP32 - 32 pin Plastic Module DIP, Package Mechanical Data
mm
inches
Symb
Typ
Min
9.27
0.38
0.43
0.20
42.42
18.03
2.29
34.29
14.99
3.05
1.91
32
Max
9.52
–
Typ
Min
Max
0.375
–
A
A1
B
0.365
0.015
0.017
0.008
1.670
0.710
0.090
1.350
0.590
0.120
0.075
32
0.59
0.33
43.18
18.80
2.79
41.91
16.00
3.81
2.79
0.023
0.013
1.700
0.740
0.110
1.650
0.630
0.150
0.110
C
D
E
e1
e3
eA
L
S
N
Figure 11. PMDIP32 - 32 pin Plastic Module DIP, Package Outline
A
A1
e1
L
C
eA
S
B
e3
D
N
1
E
PMDIP
Drawing is not to scale.
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M48T512Y, M48T512V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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