M48T37V-70MH1F [STMICROELECTRONICS]
3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM; 3.3V - 5V 256 Kbit的32Kb的X8 TIMEKEEPER SRAM
| 型号： | M48T37V-70MH1F |
| 厂家： | 
ST |
| 描述： | 3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| 文件： | 总29页 (文件大小：513K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T37Y
M48T37V
®
5.0 or 3.3V, 256 Kbit (32 Kbit x8) TIMEKEEPER SRAM
FEATURES SUMMARY
■
INTEGRATED ULTRA-LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
Figure 1. Package
CONTROL CIRCUIT, AND BATTERY
■
FREQUENCY TEST OUTPUT FOR REAL
TIME CLOCK SOFTWARE CALIBRATION
SNAPHAT (SH)
Battery/Crystal
■
■
YEAR 2000 COMPLIANT
AUTOMATIC POWER-FAIL CHIP
DESELECT and WRITE PROTECTION
■
■
WATCHDOG TIMER
WRITE PROTECT VOLTAGE
(V
= Power-Fail Deselect Voltage):
PFD
–
M48T37Y: V = 4.5 to 5.5V
CC
4.2V ≤ V
≤ 4.5V
PFD
44
–
M48T37V: V = 3.0 to 3.6V
CC
1
2.7V ≤ V
≤ 3.0V
PFD
SOH44 (MH)
44-pin SOIC
■
■
PACKAGING INCLUDES A 44-LEAD SOIC
AND SNAPHAT TOP (to be ordered
®
separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY AND
CRYSTAL
■
■
MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
PROGRAMMABLE ALARM OUTPUT
ACTIVE IN THE BATTERY BACK-UP MODE
■
■
BATTERY LOW FLAG
RoHS COMPLIANCE
Lead-free components are compliant with the
RoHS directive.
Rev 6.0
1/29
February 2006
M48T37Y, M48T37V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Alarm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Programmable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Battery Low Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
V
CC
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/29
M48T37Y, M48T37V
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15.SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Outline. . . . . . . 24
Table 14. SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Mech. Data . . . 24
Figure 16.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 25
Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 25
Figure 17.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 26
Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 18. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
M48T37Y, M48T37V
SUMMARY DESCRIPTION
®
The M48T37Y/V TIMEKEEPER RAM is a 32 Kb
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is keyed
to prevent reverse insertion.
The SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape &Reel
form. For the 44-lead SOIC, the battery/crystal
package (e.g., SNAPHAT) part number is “M4T28-
BR12SH” or “M4T32-BR12SH” (see Table
18., page 27).
x8 non-volatile static RAM and real time clock. The
monolithic chip is available in a special package
which provides a highly integrated battery backed-
up memory and real time clock solution.
The 44-lead, 330mil SOIC package provides sock-
ets with gold-plated contacts at both ends for di-
rect connection to a separate SNAPHAT housing
containing the battery and crystal. The unique de-
sign allows the SNAPHAT battery/crystal pack-
age to be mounted on top of the SOIC package
after the completion of the surface mount process.
®
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A14
DQ0-DQ7
RST
Address Inputs
V
CC
Data Inputs / Outputs
Reset Output (Open Drain)
15
8
A0-A14
DQ0-DQ7
Interrupt / Frequency Test Output
(Open Drain)
IRQ/FT
W
E
RST
M48T37Y
M48T37V
WDI
E
Watchdog Input
Chip Enable
IRQ/FT
G
G
Output Enable
WRITE Enable
Supply Voltage
Ground
WDI
W
V
CC
V
SS
AI02172
V
SS
NC
Not connected Internally
4/29
M48T37Y, M48T37V
Figure 3. SOIC Connections
NC
RST
NC
NC
A14
A12
A7
1
44
43
42
41
40
39
38
37
36
35
34
V
CC
NC
2
3
NC
4
NC
5
IRQ/FT
W
6
7
A13
A8
A6
8
A5
9
A9
A4
10
11
A11
G
A3
M48T37Y
NC
NC
WDI
A2
12 M48T37V 33
NC
13
14
15
16
17
18
19
20
21
22
32
31
NC
A10
E
30
A1
29
NC
A0
28
DQ7
DQ6
DQ5
DQ4
DQ3
NC
DQ0
DQ1
DQ2
NC
27
26
25
24
V
23
SS
AI02174
5/29
M48T37Y, M48T37V
Figure 4. Block Diagram
IRQ/FT
WDI
OSCILLATOR AND
CLOCK CHAIN
16 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
POWER
A0-A14
LITHIUM
CELL
32,752 x 8
SRAM ARRAY
DQ0-DQ7
VOLTAGE SENSE
AND
V
E
PFD
SWITCHING
CIRCUITRY
W
G
V
RST
V
CC
SS
AI03253
6/29
M48T37Y, M48T37V
OPERATION MODES
As Figure 4., page 6 shows, the static memory ar-
ray and the quartz controlled clock oscillator of the
M48T37Y/V are integrated on one silicon chip.
The memory locations that provide user accessi-
ble BYTEWIDE™ clock information are in the
bytes with addresses 7FF1 and 7FF9h-7FFFh (lo-
cated in Table 5., page 13). The clock locations
contain the century, year, month, date, day, hour,
minute, and second in 24 hour BCD format. Cor-
rections for 28, 29 (leap year - valid until the year
2100), 30, and 31 day months are made automat-
ically.
the IRQ/FT pin when the alarm bytes match the
date, hours, minutes, and seconds of the clock.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ READ/WRITE memory
cells. The M48T37Y/V includes a clock control cir-
cuit which updates the clock bytes with current in-
formation once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T37Y/V also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
Byte 7FF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
Byte 7FF7h contains the watchdog timer setting.
The watchdog timer redirects an out-of-control mi-
croprocessor and provides a reset or interrupt to it.
Bytes 7FF2h-7FF5h are reserved for clock alarm
programming. These bytes can be used to set the
alarm. This will generate an active low signal on
tors the single V
condition. When V is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V . As V falls
below the Battery Back-up Switchover Voltage
supply for an out of tolerance
CC
CC
CC
CC
(V ), the control circuitry connects the battery
SO
which maintains data and clock operation until val-
id power returns.
Table 2. Operating Modes
V
Mode
Deselect
WRITE
READ
E
G
X
X
W
DQ0-DQ7
Power
Standby
Active
CC
V
IH
X
High Z
4.5 to 5.5V
or
3.0 to 3.6V
V
IL
V
IL
V
IL
V
D
IL
IH
IH
IN
V
V
V
D
Active
IL
OUT
V
IH
READ
High Z
High Z
High Z
Active
(1)
Deselect
Deselect
X
X
X
CMOS Standby
V
to V
(min)
SO
PFD
(1)
X
X
X
Battery Back-up Mode
≤ V
SO
Note: X = V or V ; V = Battery Back-up Switchover Voltage.
IH
IL SO
1. See Table 13., page 23 for details.
7/29
M48T37Y, M48T37V
READ Mode
The M48T37Y/V is in the READ Mode whenever
WRITE Enable (W) is high and Chip Enable (E) is
low. The unique address specified by the 15 Ad-
dress Inputs defines which one of the 32,752 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
after the latter of the Chip Enable Access time
(t ) or Output Enable Access time (t ).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ELQV
GLQV
ed before t
indeterminate state until t
, the data lines will be driven to an
AVQV
.
AVQV
time (t
) after the last address input signal is
AVQV
If the Address Inputs are changed while E and G
remain active, output data will remain valid for Out-
stable, providing that the E and Output Enable (G)
access times are also satisfied. If the E and G ac-
cess times are not met, valid data will be available
put Data Hold time (t
) but will be indetermi-
AXQX
nate until the next Address Access.
Figure 5. READ Mode AC Waveforms
tAVAV
VALID
A0-A14
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00925
Note: WRITE Enable (W) = High.
Table 3. READ Mode AC Characteristics
M48T37Y
–70
M48T37V
–100
(1)
Symbol
Unit
Parameter
Min
Max
Min
Max
t
READ Cycle Time
70
100
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Output Valid
70
70
35
100
100
50
AVQV
t
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
ELQV
t
GLQV
(2)
5
5
10
5
t
ELQX
GLQX
EHQZ
(2)
(2)
(2)
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
ns
ns
ns
ns
t
t
25
25
50
40
Output Enable High to Output Hi-Z
Address Transition to Output Transition
t
GHQZ
t
10
10
AXQX
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. C = 5pF.
L
8/29
M48T37Y, M48T37V
WRITE Mode
The M48T37Y/V is in the WRITE Mode whenever
W and E are low. The start of a WRITE is refer-
enced from the latter occurring falling edge of W or
E. A WRITE is terminated by the earlier rising
edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
er READ or WRITE cycle. Data-in must be valid t
D-
prior to the end of WRITE and remain valid for
VWH
t
afterward. G should be kept high during
WHDX
WRITE cycles to avoid bus contention; however, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
after W falls.
WLQZ
a minimum of t
from Chip Enable or t
EHAX
WHAX
from WRITE Enable prior to the initiation of anoth-
Figure 6. WRITE Enable Controlled, WRITE AC Waveform
tAVAV
A0-A14
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00926
Figure 7. Chip Enable Controlled, WRITE AC Waveforms
tAVAV
A0-A14
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI00927
9/29
M48T37Y, M48T37V
Table 4. WRITE Mode AC Characteristics
M48T37Y
–70
M48T37V
–100
(1)
Symbol
Unit
Parameter
Min
Max
Min
Max
t
WRITE Cycle Time
70
0
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to WRITE Enable Low
Address Valid to Chip Enable Low
WRITE Enable Pulse Width
AVWL
t
0
0
AVEL
t
50
55
0
80
80
10
10
50
50
5
WLWH
t
Chip Enable Low to Chip Enable High
WRITE Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to WRITE Enable High
Input Valid to Chip Enable High
ELEH
t
WHAX
t
0
EHAX
t
30
30
5
DVWH
t
DVEH
t
WRITE Enable High to Input Transition
Chip Enable High to Input Transition
WHDX
t
5
5
EHDX
(2,3)
WRITE Enable Low to Output Hi-Z
Address Valid to WRITE Enable High
Address Valid to Chip Enable High
WRITE Enable High to Output Transition
25
50
ns
ns
ns
ns
t
WLQZ
t
60
60
5
80
80
10
AVWH
t
AVEH
(2,3)
t
WHQX
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. C = 5pF.
L
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
10/29
M48T37Y, M48T37V
Data Retention Mode
With valid V applied, the M48T37Y/V operates
as a conventional BYTEWIDE™ static RAM.
Should the Supply Voltage decay, the RAM will
automatically power-fail deselect, write protecting
during the time the device is sampling V . There-
fore, decoupling of the power supply lines is rec-
ommended.
CC
CC
When V
drops below V , the control circuit
SO
CC
itself when V
falls within the V
(max), V
PFD PFD
CC
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T37Y/V for
an accumulated period of at least 7 years at room
(min) window. All outputs become high imped-
ance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
temperature when V
tem power returns and V
is less than V . As sys-
CC
SO
rises above V , the
SO
CC
tent. At voltages below V
(min), the user can be
battery is disconnected and the power supply is
PFD
assured the memory will be in a write protected
state, provided the V fall time is not less than t .
switched to external V . Normal RAM operation
CC
can resume t
after V reaches V
(max).
PFD
CC
F
REC
CC
The M48T37Y/V may respond to transient noise
spikes on V that reach into the deselect window
For more information on Battery Storage Life refer
to the Application Note AN1012.
CC
11/29
M48T37Y, M48T37V
CLOCK OPERATIONS
Reading the Clock
®
Updates to the TIMEKEEPER registers should
be halted before clock data is read to prevent
reading data in transition. The BiPORT™ TIME-
KEEPER cells in the RAM array are only data reg-
isters and not the actual clock counters, so
updating the registers can be halted without dis-
turbing the clock itself.
rect day, date, and time data in 24 hour BCD
format (see Table 5., page 13). Resetting the
WRITE Bit to a '0' then transfers the values of all
time registers (7FF1h, 7FF9h-7FFFh) to the actual
TIMEKEEPER counters and allows normal opera-
tion to resume. After the WRITE Bit is reset, the
next clock update will occur in approximately one
second.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register 7FF8h. As
long as a '1' remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and the time that
were current at the moment the halt command was
issued.
Note: Upon power-up following a power failure,
both the WRITE Bit and the READ Bit will be reset
to '0.'
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. When reset to a '0,' the
M48T37Y/V oscillator starts within one second.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating will resume within a second af-
ter the bit is reset to a '0.'
Setting the Clock
Bit D7 of the Control Register (7FF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
Note: It is not necessary to set the WRITE Bit
when setting or resetting the FREQUENCY TEST
Bit (FT) or the STOP Bit (ST).
12/29
M48T37Y, M48T37V
Table 5. Register Map
Address
Data
Function/Range
BCD Format
D7
D6
D5
D4
D3
D2
D1
D0
7FFFh
7FFEh
7FFDh
7FFCh
7FFBh
7FFAh
7FF9h
7FF8h
7FF7h
7FF6h
7FF5h
7FF4h
7FF3h
7FF2h
7FF1h
7FF0h
10 Years
Year
Year
Month
00-99
01-12
01-31
01-7
0
0
0
0
0
10 M
Month
10 Date
Date: Day of Month
Day of Week
Hours
Date
0
FT
0
0
0
0
Day
0
10 Hours
Hours
00-23
00-59
00-59
0
10 Minutes
10 Seconds
S
Minutes
Min
ST
Seconds
Sec
W
R
Calibration
Control
Watchdog
Interrupts
Alarm Date
Alarm Hour
Alarm Min
Alarm Sec
Century
Flags
WDS
AFE
RPT4
RPT3
RPT2
RPT1
BMB4
BMB3
BMB2
0
BMB1
0
BMB0
0
RB1
0
RB0
0
0
0
0
ABE
AIarm 10 Date
AIarm 10 Hours
Alarm Date
01-31
00-23
00-59
00-59
00-99
Alarm Hours
Alarm Minutes
Alarm Seconds
100 Year
Alarm 10 Minutes
Alarm 10 Seconds
1000 Year
WDF
AF
Z
BL
Z
Z
Z
Z
Keys: S = Sign Bit
FT = Frequency Test Bit
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
R = READ Bit
W = WRITE Bit
ST = Stop Bit
0 = Must be set to '0'
BL = Battery Low Flag (Read only)
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT4 = Alarm Repeat Mode Bits
WDF = Watchdog Flag (Read only)
AF = Alarm Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier Bits
Z = '0' and are Read only
13/29
M48T37Y, M48T37V
Setting the Alarm Clock
Registers 7FF5h-7FF2h contain the alarm set-
tings. The alarm can be configured to go off at a
predetermined time on a specific day of the month
or repeat every day, hour, minute, or second. It
can also be programmed to go off while the
M48T37Y/V is in the battery back-up mode of op-
eration to serve as a system wake-up call.
RPT1-RPT4 put the alarm in the repeat mode of
operation. Table 6 shows the possible configura-
tions. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
Note: User must transition address (or toggle chip
enable) to see Flag Bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT1-RPT4, AF is set. If AFE is also set, the
alarm condition activates the IRQ/FT pin. To dis-
able alarm, write '0' to the Alarm Date registers
and RPT1-4. The alarm flag and the IRQ/FT out-
put are cleared by a READ to the Flags Register
as shown in Figure 8. A subsequent READ of the
Flags Register is necessary to see that the value
of the Alarm Flag has been reset to '0.'
The IRQ/FT pin can also be activated in the bat-
tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both the Alarm in Battery Back-
up Mode Enable (ABE) and the AFE are set. The
ABE and AFE bits are reset during power-up,
therefore an alarm generated during power-up will
only set AF. The user can read the Flag Register
at system boot-up to determine if an alarm was
generated while the M48T37Y/V was in the dese-
lect mode during power-up. Figure 9., page 15 il-
lustrates the back-up mode alarm timing.
Figure 8. Alarm Interrupt Reset Waveform
A0-A14
ADDRESS 7FF0h
15ns Min
ACTIVE FLAG BIT
IRQ/FT
AI01677B
Table 6. Alarm Repeat Modes
RPT4
RPT3
RPT2
RPT1
Alarm Activated
Once per Second
Once per Minute
Once per Hour
Once per Day
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Once per Month
14/29
M48T37Y, M48T37V
Figure 9. Back-up Mode Alarm Waveforms
tREC
V
CC
V
V
(max)
(min)
PFD
PFD
V
SO
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT
HIGH-Z
HIGH-Z
AI03254B
Calibrating the Clock
The M48T37Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not to exceed ±35 PPM
(parts per million) oscillator frequency error at
25 °C, which equates to about ±1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M48T37Y/V improves to better
than +1/–2 PPM at 25 °C.
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125, 829, 120 (64 minutes x 60 seconds/
minute x 32,768 cycles/second) actual oscillator
cycles, that is +4.068 or –2.034 PPM of adjust-
ment per calibration step in the calibration register.
Assuming that the oscillator is in fact running at ex-
actly 32,768 Hz, each of the 31 increments in the
Calibration Byte would represent +10.7 or –5.35
seconds per month which corresponds to a total
range of +5.5 or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T37Y/V may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference (like WWW broadcasts). While that
may seem crude, it allows the designer to give the
end user the ability to calibrate his clock as his en-
vironment may require, even after the final product
is packaged in a non-user serviceable enclosure.
All the designer has to do is provide a simple utility
that accesses the Calibration Byte.
The oscillation rate of any crystal changes with
temperature (see Figure 11., page 19). Most clock
chips compensate for crystal frequency and tem-
perature shift error with cumbersome trim capaci-
tors. The M48T37Y/V design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure 12., page 19. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five-bit Calibration byte found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order
bits (D4-D0) in the Control Register 7FF8h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is the Sign Bit; '1' in-
dicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
15/29
M48T37Y, M48T37V
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512 Hz when the
Stop Bit (ST, D7 of 7FF9h) is '0' the Frequency
Test Bit (FT, D6 of 7FFCh) is '1,' the Alarm Flag
Enable Bit (AFE, D7 of 7FF6h) is '0,' and the
Watchdog Steering Bit (WDS, D7 of 7FF7h) is '1'
or the Watchdog Register is reset (7FF7h=0).
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024
Hz would indicate a +20 PPM oscillator frequency
error, requiring a –10(WR001010) to be loaded
into the Calibration Byte for correction.
rupt or a microprocessor reset. WDF is reset by
reading the Flags Register (Address 7FF0h).
Note: User must transition address (or toggle chip
enable) to see Flag Bit change.
Reset will not occur unless the addresses are sta-
ble at the flag location for at least 15ns while the
device is in the READ Mode as shown in Figure
10., page 18.
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit. When set to a '0,' the
watchdog will activate the IRQ/FT pin when timed-
out. When WDS is set to a '1,' the watchdog will
output a negative pulse on the RST pin for a dura-
tion of t
. The Watchdog Register, the FT Bit,
REC
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output fre-
quency.
AFE Bit, and ABE Bit will reset to a '0' at the end of
a Watchdog time-out when the WDS bit is set to a
'1.'
The IRQ/FT pin is an open drain output which re-
quires a pull-up resistor for proper operation. A
500-10kΩ resistor is recommended in order to
control the rise time. The FT Bit is cleared on pow-
er-down.
The watchdog timer resets when the microproces-
sor performs a re-write of the Watchdog Register
or an edge transition (low to high / high to low) on
the WDI pin occurs. The time-out period then
starts over.
For more information on calibration, see the Appli-
cation Note AN934, “TIMEKEEPER Calibration.”
The watchdog timer is disabled by writing a value
of 00000000 to the eight bits in the Watchdog Reg-
ister. Should the watchdog timer time-out, a value
of 00h needs to be written to the Watchdog Regis-
ter in order to clear the IRQ/FT pin.
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied. The WDI
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the eight-bit Watchdog Register, ad-
dress 7FF7h. The five bits (BMB4-BMB0) that
store a binary multiplier and the two lower order
bits (RB1-RB0) select the resolution, where
1
1
pin should be connected to V if not used.
SS
00 = / second, 01 = / second, 10 = 1 second,
16
4
and 11 = 4 seconds. The amount of time-out is
then determined to be the multiplication of the five-
bit multiplier value with the resolution. (For exam-
ple: writing 00001110 in the Watchdog Register =
3x1, or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
Power-on Reset
The M48T37Y/V continuously monitors V
.
CC
When V
falls to the power fail detect trip point,
CC
the RST pulls low (open drain) and remains low on
power-up for t
after V
passes V
. RST is
conditions. The RST pin is an
REC
CC
PFD
valid for all V
CC
If the processor does not reset the timer within the
specified period, the M48T37Y/V sets the Watch-
dog Flag (WDF) and generates a watchdog inter-
open drain output and an appropriate resistor to
V
should be chosen to control rise time (see
CC
Figure 14., page 23).
16/29
M48T37Y, M48T37V
Programmable Interrupts
The M48T37Y/V provides two programmable in-
terrupts: an alarm and a watchdog. When an inter-
rupt condition occurs, the M48T37Y/V sets the
appropriate flag bit in the Flag Register 7FF0h.
The interrupt enable bits (AFE and ABE) in 7FF6h
and the Watchdog Steering (WDS) Bit in 7FF7h al-
low the interrupt to activate the IRQ/FT pin.
The Alarm flag and the IRQ/FT output are cleared
by a READ to the Flags Register. An interrupt con-
dition reset will not occur unless the addresses are
stable at the flag location for at least 15ns while
the device is in the READ Mode as shown in Fig-
ure 8., page 14.
tery low monitoring tests during the next power-up
sequence.
If a battery low is generated during a power-up se-
quence, this indicates the battery voltage is below
2.5V (approximately), which may be insufficient to
maintain data integrity. Data should be considered
suspect and verified as correct. A fresh battery
should be installed. The SNAPHAT top may be re-
placed while VCC is applied to the device.
Note: This will cause the clock to lose time during
the interval the battery/crystal is removed.
Note: Battery monitoring is a useful technique only
when performed periodically. The M48T37Y/V
The IRQ/FT pin is an open drain output and re-
quires a pull-up resistor (10kΩ recommended) to
only monitors the battery when a nominal V
is
CC
applied to the device. Thus applications which re-
quire extensive durations in the battery back-up
mode should be powered-up periodically (at least
once every few months) in order for this technique
to be beneficial. Additionally, if a battery low is in-
dicated, data integrity should be verified upon
power-up via a checksum or other technique.
V
. The pin remains in the high impedance state
CC
unless an interrupt occurs or the Frequency Test
Mode is enabled.
Battery Low Flag
The M48T37Y/V automatically performs periodic
battery voltage monitoring upon power-up. The
Battery Low Flag (BL), Bit D4 of the Flags Register
Initial Power-on Defaults
®
7FF0h, will be asserted high if the SNAPHAT
Upon application of power to the device, the fol-
lowing register bits are set to a '0' state: WDS;
BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; and FT
(see Table 7).
battery is found to be less than approximately
2.5V. The BL Flag will remain active until comple-
tion of battery replacement and subsequent bat-
Table 7. Default Values
WATCHDOG
Condition
W
R
FT
AFE
ABE
(1)
Register
Initial Power-up
(Battery Attach for SNAPHAT)
0
0
0
0
0
0
(2)
(3)
0
0
0
0
0
0
0
1
0
1
0
0
Subsequent Power-up / RESET
(4)
Power-down
Note: 1. WDS, BMB0-BMB4, RBO, RB1.
2. State of other control bits undefined.
3. State of other control bits remains unchanged.
4. Assuming these bits set to '1' prior to power-down.
17/29
M48T37Y, M48T37V
V
Noise And Negative Going Transients
Figure 10. Supply Voltage Protection
CC
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
can be reduced if capacitors are used to store en-
ergy which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
10) is recommended in order to provide the need-
ed filtering.
V
CC
V
CC
0.1µF
DEVICE
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V
that drive it to values
V
CC
SS
below V by as much as one volt. These negative
SS
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to con-
AI02169
nect a schottky diode from V
to V
(cathode
CC
SS
connected to V , anode to V ). Schottky diode
CC
SS
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
18/29
M48T37Y, M48T37V
Figure 11. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
2
∆F
F
ppm
C2
= -0.038
(T - T0) ± 10%
–100
–120
–140
–160
T0 = 25 °C
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
Figure 12. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
19/29
M48T37Y, M48T37V
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 8. Absolute Maximum Ratings
Symbol
Parameter
Value
0 to 70
Unit
°C
Grade 1
Grade 6
T
A
Ambient Operating Temperature
–40 to 85
°C
®
–40 to 85
–55 to 150
260
°C
°C
°C
SNAPHAT
SOIC
Storage Temperature (V Off, Oscillator
Off)
CC
T
STG
(1,2)
Lead Solder Temperature for 10 seconds
T
SLD
M48T37Y
M48T37V
M48T37Y
M48T37V
–0.3 to 7
–0.3 to 4.6
–0.3 to 7
–0.3 to 4.6
10
V
V
V
Input or Output Voltages
Supply Voltage
IO
V
V
CC
V
I
O
Output Current
mA
W
P
Power Dissipation
1
D
Note: 1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds).
2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
20/29
M48T37Y, M48T37V
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 9. Operating and AC Measurement Conditions
Parameter
M48T37Y
4.5 to 5.5
0 to 70
–40 to 85
100
M48T37V
3.0 to 3.6
0 to 70
–40 to 85
50
Unit
V
Supply Voltage (V
)
CC
Grade 1
Grade 6
°C
°C
pF
ns
V
Ambient Operating Temperature (T )
A
Load Capacitance (C )
L
Input Rise and Fall Times
≤ 10
≤ 10
Input Pulse Voltages
0 to 3
0 to 3
Input and Output Timing Ref. Voltages
1.5
1.5
V
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 13. AC Testing Load Circuit
645Ω
DEVICE
UNDER
TEST
(1)
1.75V
C
= 100pF
L
C
includes JIG capacitance
L
AI02325
Note: Excluding open-drain output pins
1. ; 50pF for M48T37V.
Table 10. Capacitance
Symbol
(1,2)
Min
Max
10
Unit
pF
Parameter
C
Input Capacitance
Input / Output Capacitance
IN
(3)
10
pF
C
IO
Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
21/29
M48T37Y, M48T37V
Table 11. DC Characteristics
M48T37Y
–70
M48T37V
–100
(1)
Symbol
Parameter
Unit
Test Condition
Min
Max
Min
Max
(2)
0V ≤ V ≤ V
Input Leakage Current
±1
±1
µA
I
IN
CC
LI
(3)
0V ≤ V
≤ V
CC
Output Leakage Current
Supply Current
±1
50
3
±1
33
2
µA
mA
mA
I
OUT
LO
I
Outputs open
CC
I
E = V
Supply Current (Standby) TTL
CC1
IH
Supply Current (Standby)
CMOS
I
E = V – 0.2V
3
2
mA
CC2
CC
V
Input Low Voltage
Input High Voltage
–0.3
2.2
0.8
–0.3
2.2
0.8
V
V
IL
V
IH
V
+ 0.3
V
+ 0.3
CC
CC
Output Low Voltage
(standard)
I
= 2.1mA
0.4
0.4
0.4
0.4
V
OL
V
OL
Output Low Voltage
(open drain)
I
= 10mA
= –1mA
V
V
OL
V
OH
I
Output High Voltage
2.4
2.4
OH
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
2. WDI internally pulled down to VSS through a 100kΩ resistor.
3. Outputs deselected.
CC
22/29
M48T37Y, M48T37V
Figure 14. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tFB
tRB
tDR
tREC
RST
VALID
INPUTS
DON'T CARE
HIGH-Z
VALID
OUTPUTS
VALID
VALID
AI03078
Table 12. Power Down/Up AC Characteristics
(1)
Symbol
Min
Max
Unit
Parameter
(2)
V
(max) to V
(min) to V
(min) V Fall Time
300
µs
t
PFD
PFD
CC
F
(3)
V
V
V
V
V
Fall Time
10
10
1
µs
µs
µs
t
PFD
PFD
SS CC
FB
t
(min) to V
(max) V Rise Time
PFD CC
R
t
to V
(min) V Rise Time
PFD CC
RB
SS
(4)
(max) to RST High
40
200
ms
t
PFD
REC
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. V
(max) to V
(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after V pass-
PFD CC
PFD
es V
(min).
PFD
3. V
4. t
(min) to V fall time of less than t may cause corruption of RAM data.
(min) = 20ms for Industrial Temperature Range - Grade 6 device.
PFD
REC
SS FB
Table 13. Power Down/Up Trip Points DC Characteristics
(1)
Symbol
Min
4.2
2.7
Typ
4.4
2.9
Max
4.5
Unit
Parameter
M48T37Y
M48T37V
M48T37Y
M48T37V
Grade 1
V
V
PFD
Power-fail Deselect Voltage
3.0
V
V
V
BAT
V
Battery Back-up Switchover Voltage
Expected Data Retention Time
SO
V
PFD
–100mV
V
5
7
YEARS
YEARS
(3)
t
DR
(2)
Grade 6
10
Note: All voltages referenced to V
.
SS
1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - Grade 6 device).
3. At 25°C, V = 0V.
CC
23/29
M48T37Y, M48T37V
PACKAGE MECHANICAL INFORMATION
Figure 15. SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 14. SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Mech. Data
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.46
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.018
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
0.81
0.032
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
44
44
CP
0.10
0.004
24/29
M48T37Y, M48T37V
Figure 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
25/29
M48T37Y, M48T37V
Figure 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
Typ
Max
A
A1
A2
A3
B
0.415
.0335
0.315
0.015
0.022
0.860
.0710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
26/29
M48T37Y, M48T37V
PART NUMBERING
Table 17. Ordering Information Scheme
Example:
M48T
37Y
–70
MH
1
E
Device Type
M48T
Supply Voltage and Write Protect Voltage
37Y = V = 4.5 to 5.5V; V
= 4.2 to 4.5V
= 2.7 to 3.0V
CC
PFD
PFD
37V = V = 3.0 to 3.6V; V
CC
Speed
–70 = 70ns (37Y)
–10 = 100ns (37V)
Package
(1)
MH = SOH44
Temperature Range
1 = 0 to 70°C
6 = –40 to 85°C
Shipping Method
blank = Tubes (Not for New Design - Use E)
E = ECOPACK Package, Tubes
F = ECOPACK Package, Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
®
Note: 1. The SOIC package (SOH44) requires the SNAPHAT battery package which is ordered separately under the part number “M4TXX-
BR12SH” in plastic tube or “M4TXX-BR12SHTR” in Tape & Reel form (see Table 18).
Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell bat-
tery.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
Table 18. SNAPHAT Battery Table
Part Number
M4T28-BR12SH
M4T32-BR12SH
Description
Lithium Battery (48mAh) SNAPHAT
Lithium Battery (120mAh) SNAPHAT
Package
SH
SH
27/29
M48T37Y, M48T37V
REVISION HISTORY
Table 19. Document Revision History
Date
Version
Revision Details
December 1999
1.0
First Issue
From Preliminary Data to Data Sheet; Battery Low Flag paragraph changed; 100ns
speed class identifier changed (Tables 3, 4)
07-Feb-00
2.0
t
changed (Table 12); watchdog timer paragraph changed
11-Jul-00
19-Jun-01
06-Aug-01
15-Jan-02
20-May-02
31-Mar-03
01-Apr-04
08-Feb-06
2.1
3.0
3.1
3.2
3.3
4.0
5.0
6.0
FB
Reformatted; added temp./voltage info. to tables (Table 10, 11, 3, 4, 12, 13)
Fix text for Setting the Alarm Clock (Figure 8)
Fix footnote numbering (Table 17)
Modify reflow time and temperature footnote (Table 8)
v2.2 template applied; data retention condition updated (Table 13)
Reformatted; updated with Lead-free package information (Table 8, 17)
New template; updated Lead-free text; fixed DC Characteristics (Table 8, 11, 17)
28/29
M48T37Y, M48T37V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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