M48T36Y-70MH1 [STMICROELECTRONICS]
CMOS 32K x 8 TIMEKEEPER SRAM; CMOS 32K ×8 TIMEKEEPER SRAM
| 型号： | M48T36Y-70MH1 |
| 厂家： | 
ST |
| 描述： | CMOS 32K x 8 TIMEKEEPER SRAM |
| 文件： | 总17页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T36
CMOS 32K x 8 TIMEKEEPER SRAM
PRODUCT PREVIEW
INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
FREQUENCY TEST OUTPUT for REAL TIME
CLOCK
AUTOMATICPOWER-FAIL CHIP DESELECTand
WRITE PROTECTION
WRITE PROTECT VOLTAGE:
44
– M48T36Y: 4.2V ≤ VPFD ≤ 4.5V
1
SMALL OUTLINE PACKAGE PROVIDES
DIRECT CONNECTION for a SNAPHAT
HOUSING CONTAINING the BATTERY and
CRYSTAL
SOH44 (MH)
Battery SNAPHAT
SNAPHAT HOUSING (BATTERY and
CRYSTAL) REPLACEABLE
MICROPROCESSOR POWER-ON RESET
PROGRAMMABLE ALARM OUTPUT ACTIVE
in the BATTERY BACK-UP MODE
Figure 1. Logic Diagram
BATTERY LOW WARNING
V
V
CCQ
CC
15
8
A0-A14
DQ0-DQ7
Table 1. Signal Names
WDI
W
A0-A14
Address Inputs
M48T36
DQ0-DQ7
Data Inputs / Outputs
Interrupt / Frequency Test Output
(Open Drain)
E
IRQ/FT
RST
IRQ/FT
G
RST
WDI
E
Power Fail Reset Output (Open Drain)
Watchdog Interrupt
Chip Enable
G
Output Enable
V
V
SSQ
SS
W
Write Enable
AI01624
VCC
VCCQ
VSS
VSSQ
Supply Voltage
Supply Voltage (DQ)
Ground
Ground (DQ)
July 1995
1/17
This is preliminary informationon a new product now in development. Details are subject to changewithout notice.
M48T36
Table 2. Absolute Maximum Ratings
Symbol
TA
Parameter
Value
0 to 70
–40 to 85
–0.3 to 7
–0.3 to 7
20
Unit
°C
°C
V
Ambient Operating Temperature
Storage Temperature (VCC Off, Oscillator Off)
Input or Output Voltages
Supply Voltage
TSTG
VIO
VCC
IO
V
Output Current
mA
W
PD
Power Dissipation
1
Note: Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability.
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
provide a highly integrated battery backed-up
memory and real time clock solution. The M48T36
is a non-volatilepin and functionequivalent to any
JEDEC standard 32K x 8 SRAM. It also easily fits
into many ROM, EPROM, and EEPROM sockets,
providing the non-volatility of PROMs without any
requirementforspecial writetimingor limitations on
the number of writes that can be performed.
The 44 pin 330mil SO provides sockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery and crystal. The unique design allows the
SNAPHAT battery package to be mounted on top
of the SO package after the completion of the
surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential batteryand crystal damage due
to the high temperatures required for device sur-
face-mounting.The SNAPHAT housingis keyed to
prevent reverse insertion.
The SO and battery packages are shipped sepa-
rately in plastic anti-static tubes. The SO package
is also available to ship in Tape & Reel form. For
the 44 lead SO, the battery package (i.e.
SNAPHAT) part number is ”M4T44-BR12SH1”.
As Figure 3shows,the staticmemory arrayandthe
quartzcontrolledclock oscillatorof theM48T36 are
integratedon one silicon chip. The two circuits are
interconnectedattheuppereight memorylocations
to provide user accessible BYTEWIDE clock in-
formation in the bytes with addresses 7FF9h-
7FFFh. The clock locations contain the year,
month, date, day, hour, minute, and second in 24
hour BCD format. Corrections for 28, 29 (leap
year), 30, and 31 day months are made automat-
ically.
Figure 2A. DIP Pin Connections
A14
A12
A7
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
AI01625
V
V
CC
2
CCQ
3
W
A6
4
A13
A8
NC
5
NC
6
NC
NC
A9
A5
7
A4
8
A3
9
A11
G
IRQ/FT
RST
WDI
A2
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
A10
E
M48T36
A1
A0
DQ7
NC
NC
NC
DQ6
DQ5
DQ4
DQ3
NC
NC
DQ0
DQ1
DQ2
V
SSQ
V
SS
Warning: NC = Not Connected
DESCRIPTION
The M48T36 TIMEKEEPER RAM is a 32K x 8
non-volatile static RAM and real time clock. The
monolithic chip is available in a special package to
2/17
M48T36
Figure 3. Block Diagram
IRQ/FT
WDI
OSCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
8 x 8 ALARM
WATCHDOG
FLAGS
POWER
BATTERY LOW
A0-A14
32,752 x 8
SRAM ARRAY
LITHIUM
CELL
DQ0-DQ7
VOLTAGE SENSE
AND
V
E
PFD
SWITCHING
CIRCUITRY
W
G
V
RST
V
CC
SS
AI01626
Table 3. Operating Modes (1)
Mode
Deselect
Write
VCC
E
VIH
VIL
VIL
VIL
X
G
X
W
DQ0-DQ7
High Z
DIN
Power
Standby
X
VIL
VIH
VIH
X
X
Active
4.5V to 5.5V
Read
VIL
VIH
X
DOUT
Active
Read
High Z
High Z
High Z
Active
Deselect
V
SO to VPFD (min) (2)
CMOS Standby
Battery Back-up Mode
Deselect
X
X
X
≤ VSO
Notes: 1. X = VIH or VIL
2. See Table 6 for details.
3/17
M48T36
AC MEASUREMENT CONDITIONS
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
5V
≤ 5ns
0 to 3V
1.5V
Input Pulse Voltages
Input and Output Timing Ref. Voltages
1.9kΩ
Note that Output Hi-Z is defined as the point where data
is no longer driven.
DEVICE
UNDER
TEST
OUT
1kΩ
C
= 100pF or 5pF
L
C
includes JIG capacitance
L
AI01030
Table 4. Capacitance (1, 2) (TA = 25 °C, f = 1 MHz )
Symbol
Parameter
Input Capacitance
Test Condition
VIN = 0V
Min
Max
10
Unit
pF
CIN
(3)
CIO
Input / Output Capacitance
VOUT = 0V
10
pF
Notes: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputsdeselected
Table 5. DC Characteristics (TA = 0 to 70°C; VCC = 4.5V to 5.5V)
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Test Condition
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
Outputs open
E = VIH
Min
Max
±1
±5
50
3
Unit
µA
µA
mA
mA
mA
V
(1)
ILI
(1)
ILO
ICC
ICC1
ICC2
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
E = VCC – 0.2V
3
(2)
VIL
–0.3
2.2
0.8
VIH
Input High Voltage
VCC + 0.3
0.4
V
V
Output Low Voltage
IOL = 2.1mA
IOL = 10mA
IOH = –1mA
VOL
Output Low Voltage (IRQ/FT and
RST) (3)
0.4
V
V
VOH
Output High Voltage
2.4
Notes: 1. OutputsDeselected.
2. Negative spikes of –1V allowed for up to 10ns once per Cycle.
3. The IRQ/FT and RST pins are Open Drain.
4/17
M48T36
Table 6. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70°C)
Symbol
VPFD
Parameter
Min
Typ
4.35
3.0
Max
Unit
Power-fail Deselect Voltage (M48T36Y)
Battery Back-up Switchover Voltage
Expected Data Retention Time
4.2
4.5
V
V
VSO
(2)
tDR
7
YEARS
Notes: 1. All voltages referenced to VSS
2. @ 25°C
.
Table 7. Power Down/Up Mode AC Characteristics (TA = 0 to 70°C)
Symbol
Parameter
E or W at VIH before Power Down
Min
0
Max
Unit
tPD
µs
(1)
tF
VPFD (max) to VPFD (min) VCC Fall Time
VPFD (min) to VSO VCC Fall Time
VPFD(min) to VPFD (max) VCC Rise Time
VSO to VPFD (min) VCC Rise Time
VPFD (max) to RST High
300
10
10
1
µ
µ
s
s
(2)
tFB
tR
µs
tRB
µ
s
tREC
40
200
ms
Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Figure 5. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tDR
tR
tPD
tFB
tRB
tREC
RST
RECOGNIZED
RECOGNIZED
INPUTS
DON’T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01384C
5/17
M48T36
Table 8. Read Mode AC Characteristics
(TA = 0 to 70°C; VCC = 4.5V to 5.5V)
M48T36Y
-70
Symbol
Parameter
Unit
Min
Max
tAVAV
Read Cycle Time
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
tAVQV
Address Valid to Output Valid
70
70
35
(1)
tELQV
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
(1)
tGLQV
(2)
tELQX
5
5
(2)
tGLQX
(2)
tEHQZ
25
25
(2)
tGHQZ
(1)
tAXQX
10
Notes: 1. CL = 100pF (see Figure 4).
2. CL = 5pF (see Figure 4).
Figure 6. Read Mode AC Waveforms
tAVAV
VALID
A0-A14
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00925
Note: Write Enable (W) = High
6/17
M48T36
Table 9. Write Mode AC Characteristics
(TA = 0 to 70°C; VCC = 4.5V to 5.5V)
M48T36Y
-70
Symbol
Parameter
Unit
Min
Max
tAVAV
tAVWL
tAVEL
Write Cycle Time
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Validto Write Enable Low
Address Validto Chip Enable Low
Write Enable Pulse Width
0
tWLWH
tELEH
tWHAX
tEHAX
tDVWH
tDVEH
tWHDX
tEHDX
50
55
0
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable Low to Output Hi-Z
Address Validto Write Enable High
Address Validto Chip Enable High
Write Enable High to Output Transition
0
30
30
5
5
(1, 2)
tWLQZ
25
tAVWH
tAVE1H
60
60
5
(1, 2)
tWHQX
Notes: 1. CL = 5pF (see Figure 4).
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
DESCRIPTION (cont’d)
The M48T36 also has its own Power-fail Detect
circuit. The controlcircuitry constantlymonitors the
single 5V supply for an out of tolerance condition.
When VCC is out of tolerance, the circuit write
protectsthe SRAM, providingahigh degree ofdata
securityinthemidst ofunpredictablesystemopera-
tion brought on by low VCC. As VCC falls below
approximately3V, the controlcircuitry connectsthe
battery which maintains data and clock operation
until valid power returns.
Byte 7FF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
Byte 7FF7h contains the watchdog timer setting.
The watchdog timer detects an out-of-control mi-
croprocessor and provides a reset or interrupt to it.
Byte 7FF2h-7FF5h are reserved for clock alarm
programming. These bytes can be used to set the
alarm. This will generatean active low signalon the
IRQ/FT pin when the alarm bytes match the date,
hours, minutes and seconds of the clock.
READ MODE
The M48T36 is in the Read Mode whenever W
(Write Enable) is high and E (Chip Enable) is low.
The unique address specified by the 15 Address
Inputs defines which one of the 32,768 bytes of
data is to be accessed. Valid data will be available
at the Data I/O pins within tAVQV (Address Access
Time) after the last address input signal is stable,
providing that the E and G access times are also
satisfied. If the E and G access times are not met,
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT read/write memory cells.
The M48T36 includes a clock control circuit which
updates the clock bytes with current information
once per second. The information can be ac-
cessed by the user in the same manner as any
other location in the static memory array.
7/17
M48T36
Figure 7. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A14
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00926
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A14
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI00927
8/17
M48T36
READ MODE (cont’d)
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T36 for an
accumulatedperiod of atleast 7 years when VCC is
less than VSO. As system power returns and VCC
rises above VSO, the battery is disconnected,and
the power supply is switched to external VCC. De-
select continues for tREC after VCC reaches
validdatawill beavailableafter thelatterof theChip
Enable Access Time (tELQV) or OutputEnable Ac-
cess Time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled byE andG. If the outputsareactivated
before tAVQV, the data lines will be driven to an
indeterminatestateuntiltAVQV. IftheAddressInputs
are changed while E and G remain active, output
data will remain valid for tAXQX (Output Data Hold
Time) but will go indeterminate until the next Ad-
dressAccess.
V
PFD(max).
POWER-ON RESET
The M48T36 continuously monitors VCC. When
VCC falls to the power fail detecttrip point, the RST
pullslow (opendrain)andremainslowonpower-up
for 40ms to 200ms after VCC passes VPFD. A1kΩ
resistor is recommendedin orderto control the rise
time. The reset pulse remains active with VCC at
VSS.
WRITE MODE
The M48T36 is in the Write Mode whenever W and
E arelow. The startofa write is referencedfrom the
latter occurring falling edge of W or E. A write is
terminated by the earlierrising edge of W or E. The
addressesmust be held valid throughoutthe cycle.
E or Wmust returnhigh for a minimumoftEHAX from
Chip Enableor tWHAX from Write Enablepriorto the
initiation of another read or write cycle. Data-in
must be valid tDVWH prior to the end of write and
remain valid for tWHDX afterward. G should be kept
high during write cycles to avoid bus contention;
although,if the output bus has been activated by a
low on E and G a low on W will disable the outputs
tWLQZ after W falls.
PROGRAMMABLE INTERRUPTS
The M48T36 has two programmable interrupts: an
alarm and a watchdog.When an interrupt condition
occurs, the M48T36 sets the appropriateflag bit in
the flagregister 7FF0h.The interrupt enable bits in
7FF6h and the WDS (Watchdog Steering) bit in
7FF7hallowthe interrupttoactivatetheIRQ/FTpin.
The interrupt flags and the IRQ/FT output are
cleared by a read to the flags register. An interrupt
conditionreset will not occur unless the addresses
are stableatthe flaglocation for atleast 15ns while
the device is in the read mode as shown in Figure
10.
DATA RETENTION MODE
With valid VCC applied, the M48T36 operates as a
conventional BYTEWIDE static RAM. Should the
supply voltage decay, the RAM will automatically
power-fail deselect,write protecting itselfwhen VCC
falls within the VPFD(max), VPFD(min) window. All
outputsbecomehigh impedance,and all inputsare
treated as ”don’t care.”
The IRQ/FT pin is an open drain output and re-
quiresapull-up resistor. The pinremainsinthe high
impedance state unless an interrupt occurs or the
frequency test mode is enabled.
Note: A power failure during a write cycle may
corruptdataat thecurrentlyaddressedlocation,but
does not jeopardize the rest of the RAM’s content.
At voltages below VPFD(min), the user can be as-
sured the memory will be in a write protectedstate,
provided the VCC fall time is not less than tF. The
M48T36 may respond to transient noise spikes on
VCC thatreach into the deselect window during the
timethe device is sampling VCC. Therefore,decou-
pling of the power supply lines is recommended.
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data
registers, and not the actual clock counters,updat-
ing the registers can be halted without disturbing
the clock itself.
9/17
M48T36
CLOCK OPERATIONS (cont’d)
user can then load them with the correct day,date,
and time data in 24 hour BCD format (see Table
10). Resetting the WRITE bit to a ’0’ then transfers
the values of all time registers 7FF9h-7FFFh tothe
actual TIMEKEEPER counters and allows normal
operationto resume. After the WRITE bit is reset,
the next clock update will occur in one second.
Updatingis haltedwhen a’1’ is written to the READ
bit, D6 in the Control Register 7FF8h. As long as a
’1’remains in that position, updatingis halted.After
a halt is issued, the registers reflect the count;that
is, the day,date, and the time that were current at
the moment the halt command was issued.
Stopping and Starting the Oscillator
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a ’0’.
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drainon the battery.The STOPbit
is the MSB of theseconds register. Setting it to a’1’
stops the oscillator. The M48T36 is shipped from
SGS-THOMSON with the STOP bit set to a ’1’.
Setting the Clock
Bit D7 of the Control Register 7FF8h is the WRITE
bit. Setting theWRITE bit to a ’1’, like the READ bit,
halts updates to the TIMEKEEPER registers. The
Table 10. Register Map
Data
Function/Range
BCD Format
Address
D7
D6
D5
D4
10 M.
0
D3
D2
D1
D0
7FFFh
7FFEh
7FFDh
7FFCh
7FFBh
7FFAh
7FF9h
7FF8h
7FF7h
7FF6h
7FF5h
7FF4h
7FF3h
7FF2h
7FF1h
7FF0h
10 Years
Year
Month
Date
Year
Month
00-99
01-12
01-31
01-07
00-23
00-59
00-59
0
0
0
0
0
10 Date
Date
0
FT
0
0
0
Day
Hours
Day
0
10 Hours
Hour
0
10 Minutes
10 Seconds
S
Minutes
Minutes
Seconds
Control
ST
Seconds
W
R
Calibration
WDS
AFE
RPT4
RPT3
RPT2
RPT1
Y
BMB4 BMB3 BMB2 BMB1 BMB0
RB1
Y
RB0
Y
Watchdog
Interrupts
Alarm Date
Alarm Hours
Alarm Minutes
Y
Y
Y
ABE
Y
Y
Y
Al. 10 Date
Alarm Date
Alarm Hours
01-31
00-23
00-59
Al. 10 Hours
Alarm 10 Minutes
Alarm 10 Seconds
Alarm Minutes
Alarm Seconds
Alarm Seconds 00-59
Y
Y
Z
Y
Y
Z
Y
Z
Y
Z
Y
Z
Unused
Flags
WDF
AF
BL
WDS = Watchdog Steering Bit
Keys: S = SIGN Bit
BMB0–BMB4 = Watchdog Multiplier Bits
RB0–RB1 = Watchdog Resolution Bits
AFE = Alarm Flag Enable
FT = FREQUENCY TEST Bit
R = READ Bit
W = WRITE Bit
ABE = Alarm in Battery Back-up Mode Enable
RPT1–RPT4 = Alarm Repeat Mode Bits
WDF = Watchdog Flag
ST = STOP Bit
0 = Must be set to ’0’
Y = ’1’ or ’0’
Z = ’0’ and are Read only
AF = Alarm Flag
BL = Battery Low
10/17
M48T36
When reset to a ’0’, the M48T36 oscillator starts
within 1 second.
Therefore, each calibration step has the effect of
adding 512 or subtracting256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068or -2.034PPMofadjustment percalibration
step in the calibration register. Assuming that the
oscillator is in fact running at exactly 32,768 Hz,
each of the 31 increments in the Calibration byte
would represent+10.7or - 5.35seconds permonth
which correspondsto a total range of+5.5 or - 2.75
minutes per month.
Two methods are available for ascertaining how
much calibrationa given M48T36may require. The
first involves simply setting the clock, letting it run
for a month and comparing it to a known accurate
reference (like WWV broadcasts). While that may
seem crude, it allows the designer to give the end
user the ability to calibrate his clock as his environ-
ment may require, even after the final product is
packaged in a non-userserviceable enclosure. All
the designerhas to do is provide asimple utility that
accesses the Calibration byte. The utility could
even be menu driven and made foolproof.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz when the
Stop bit (D7 of 7FF9h) is ’0’, the FT bit (D6 of
7FFCh) is ’1’, the AFE bit (D7 of 7FF6h) is ’0’, and
the Watchdog Steering bit (D7 of 7FF7h) is ’1’ or
the WatchdogRegister is reset (7FF7h = 0).
Anydeviationfrom 512Hz indicatesthedegreeand
direction of oscillator frequency shift at the test
temperature.For example, a reading of 512.01024
Hz would indicate a +20 PPM oscillator frequency
error, requiring a -10(001010) to be loaded into the
Calibration Byte for correction. Note that setting or
changing the Calibration Byte does not affect the
Frequency test output frequency.
Calibrating the Clock
The M48T36 is driven by a quartz controlled oscil-
lator with a nominal frequency of 32,768 Hz. The
devices are testednot to exceed 35 PPM (parts per
million) oscillator frequency error at 25°C, which
equates to about ± 1.53 minutes per month. With
the calibration bits properly set, the accuracy of
each M48T36 improves to better than ±4 PPM at
25°C.
Ofcoursetheoscillationrateofany crystal changes
withtemperature.Most clock chipscompensatefor
crystal frequency and temperature shift error with
cumbersometrim capacitors. The M48T36 design,
however, employs periodic counter correction. The
calibration circuit addsor subtracts countsfrom the
oscillator divider circuit at the divide by 128 stage,
as shown in Figure 9. The number of times pulses
are blanked (subtracted, negative calibration) or
split(added,positive calibration)dependsuponthe
value loadedinto the five bit Calibration byte found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control Register 7FF8h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; ’1’
indicates positive calibration, ’0’ indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a
binary ’1’ is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and
so on.
Figure 9. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594
11/17
M48T36
CLOCK OPERATIONS (cont’d)
IRQ/FT output are cleared by a read to the Flags
register as shown in Figure 10.
The IRQ/FT pin is an open drain output which
requires a pull-up resistor for proper operation. A
500-10kΩ resistor is recommended inordertocon-
trol the rise time. The FTbitis cleared on power-up.
TheIRQ/FT pin can also be activated in the battery
back-up mode. The IRQ/FTwill go low if an alarm
occurs and both ABE (Alarm in Battery Back-up
Mode Enable)and AFE are set. The ABE andAFE
bits are resetduring power-up, therefore an alarm
generated during power-up will only set AF. The
user can read the Flag Register at system boot-up
to determine if an alarm was generated while the
M48T36 was in the deselect mode during power-
up. Figure 11 illustrates the back-up mode alarm
timing.
SETTING ALARM CLOCK
Registers7FF5h-7FF2hcontainthe alarmsettings.
The alarm can be configured to go off at a pre-
scribed time on a specific day of the month or
repeat every day, hour, minute, or second. It can
also be programmed to go off while the M48T36 is
in the battery back-up mode of operation to serve
as a system wake-up call.
Table 11. Alarm Repeat Mode
RPT1-RPT4 put the alarm in the repeat mode of
operation. Table 11 shows the possible configura-
tions. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
RPT4
RPT3
RPT2 RPT1
Alarm Activated
Once per Second
Once per Minute
Once per Hour
Once per Day
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT1-RPT4, AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable)is also set, the alarm condition
activates the IRQ/FT pin. The alarm flag and the
Once per Month
Figure 10. Interrupt Reset Waveforms
15ns Min
ADDRESS 1FF0h
A0-A14
ACTIVE FLAG BIT
IRQ/FT
HIGH-Z
AI01627
12/17
M48T36
WATCHDOG TIMER
The watchdogtimer resets when the microproces-
sor performsa read ofthe Watchdog Register. The
time-out period then starts over. The watchdog
timer is disabled by writing a value of 00000000 to
the eight bits in the WatchdogRegister.Thewatch-
dog functionis automaticallydisabled upon power-
up and the Watchdog Register is cleared. If the
watchdogfunctionis setto outputto theIRQ/FT pin
and the frequency test function is activated, the
watchdog function prevails and the frequency test
function is denied. The WDI pin containsa pull-up
resistor which is greater than100kΩ, and therefore
can be left unconnectedif not used.
The watchdog timer can be used to detect an
out-of-controlmicroprocessor. The user programs
the watchdog timer by setting the desired amount
of time-out into the eight bit Watchdog Register,
address 7FF7h. The five bits (BMB4-BMB0) store
a binary multiplier and the two lower order bits
(RB1-RB0) select the resolution, where 00=1/16
second, 01=1/4 second, 10=1 second, and 11=4
seconds. The amount of time-out is then deter-
mined to be the multiplication of the five bit multi-
plier value with the resolution. (For example:
writing 00001110in the Watchdog Register = 3 x 1
or 3 seconds). Ifthe processor does not reset the
timer within the specified period, the M48T36 sets
the WDF (Watchdog Flag) and generatesa watch-
dog interrupt or a microprocessor reset.
The most significant bit of the Watchdog Register
is the WatchdogSteeringBit. When settoa ’0’, the
watchdogwill activate the IRQ/FT pin when timed-
out. When WDS is set to a ’1’, the watchdog will
output a negative pulse on the RST pin for a dura-
tion of 40msto200ms. TheWatchdogregister and
the FT bit will resetto a ’0’ at the end ofa watchdog
time-out when the WDS bit is set to a ’1’.
BATTERY LOW WARNING
The M48T36 checks it’s battery voltage on power-
up. The BL (Battery Low) bit D4 of 7FF0h will be
set on power-up if the battery voltage is less than
2.5V (typical).
POWER-ON DEFAULTS
Upon application ofpowerto the device, the follow-
ing register bits are set to a ’0’ state: WDS = 0;
BMB0-BMB4= 0; RB0-RB1 = 0;AFE =0; ABE = 0.
Figure 11. Back-up Mode Alarm Waveforms
V
V
CC
PFD
(max)
(min)
V
PFD
AFE
AF
IRQ/FT
HIGH-Z
HIGH-Z
AI01389B
13/17
M48T36
ORDERING INFORMATION SCHEME
Example:
M48T36Y
-70
MH
1
Supply Voltage and Write
Protect Voltage
Speed
70ns
Package
SOH44
Temp. Range
36Y
V
V
CC = 4.5V to 5.5V
PFD = 4.2V to 4.5V
-70
MH
1
0 to 70 °C
The SO and battery packages are shipped separately in plastic anti-static tubes. The SO package is also
available to ship in Tape& Reel form. For the 44 lead SO, the batterypackage (i.e. SNAPHAT) partnumber
is ”M4T44-BR12SH1”.
For a list of available options (Supply Voltage, Speed, Package, etc...) refer to the current Memory
Shortformcatalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearest to you.
14/17
M48T36
SOH44 - 44 lead Plastic Small Outline, battery SNAPHAT
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.51
0.32
–
Typ
Max
0.120
0.014
0.106
0.020
0.012
–
A
A1
A2
B
0.05
2.34
0.36
0.15
–
0.002
0.092
0.014
0.006
–
C
D
–
–
E
8.23
–
8.89
–
0.324
–
0.350
–
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
44
44
CP
0.10
0.004
SOH44
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH
Drawing is not to scale
15/17
M48T36
SH44 - SNAPHAT Housing for 44 lead Plastic Small Outline
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
–
Typ
Max
0.385
0.285
0.275
0.015
0.022
–
A
A1
A2
A3
B
6.73
6.48
0.265
0.255
0.46
–
0.018
–
D
–
–
–
–
E
14.22
–
14.99
–
0.560
–
0.590
–
eA
eB
3.20
2.03
3.61
2.29
0.126
0.080
0.142
0.090
L
SH44
A2
A1
A
A3
L
eA
D
B
eB
E
SH
Drawing is not to scale
16/17
M48T36
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringementof patents or other rights ofthird parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1995 SGS-THOMSON Microelectronics - All Rights Reserved
TIMEKEEPER, SNAPHAT, BYTEWIDE and BiPORT are trademarks of SGS-THOMSON Microelectronics
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
17/17
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