M48T35AV_11 [STMICROELECTRONICS]
3.3 V, 256 Kbit (32 Kbit x 8) TIMEKEEPER® SRAM; 3.3 V ， 256千位（ 32千位×8 ） TIMEKEEPER® SRAM
| 型号： | M48T35AV_11 |
| 厂家： | 
ST |
| 描述： | 3.3 V, 256 Kbit (32 Kbit x 8) TIMEKEEPER® SRAM |
| 文件： | 总29页 (文件大小：498K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T35AV
3.3 V, 256 Kbit (32 Kbit x 8) TIMEKEEPER® SRAM
Features
■ Integrated, ultra low power SRAM, real-time
clock, power-fail control circuit and battery
™
■ BYTEWIDE RAM-like clock access
■ BCD coded year, month, day, date, hours,
minutes, and seconds
28
1
■ Battery low flag (BOK)
■ Frequency test output for real-time clock
PCDIP28
battery/crystal
CAPHAT™
■ Automatic power-fail chip deselect and WRITE
protection
■ WRITE protect voltage
(V
= power-fail deselect voltage):
PFD
®
SNAPHAT
– M48T35AV: V = 3.0 to 3.6 V;
CC
battery/crystal
2.7 V ≤ V
≤ 3.0 V
PFD
■ Self-contained battery and crystal in the
™
CAPHAT DIP package
■ SOIC package provides direct connection for a
®
SNAPHAT housing containing the battery and
crystal
®
■ SNAPHAT housing (battery and crystal) is
28
replaceable
1
■ Pin and function compatible with JEDEC
standard 32 Kbit x 8 SRAMs
SOH28
■ RoHS compliant
– Lead-free second level interconnect
June 2011
Doc ID 6845 Rev 9
1/29
www.st.com
1
Contents
M48T35AV
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
3.3
3.4
3.5
3.6
Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
5
6
7
8
9
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29
Doc ID 6845 Rev 9
M48T35AV
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, pack. mech. data . . . . . . . . . . . . . . . . 22
®
SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT , pack. mech. data. . 23
®
SH – 4-pin SNAPHAT housing for 48 mAh battery & crystal, pack. mech. data . . . . . . . 24
®
SH – 4-pin SNAPHAT housing for 120 mAh battery & crystal, pack. mech. data . . . . . . 25
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
®
SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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List of figures
M48T35AV
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SOIC connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WRITE enable controlled, WRITE mode AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Checking the BOK flag status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 22
®
Figure 15. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT , package outline. . . 23
®
Figure 16. SH – 4-pin SNAPHAT housing for 48 mAh battery & crystal, pack. outline . . . . . . . . . . . 24
®
Figure 17. SH – 4-pin SNAPHAT housing for 120 mAh battery & crystal, pack. outline . . . . . . . . . . 25
Figure 18. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Doc ID 6845 Rev 9
M48T35AV
Description
1
Description
®
The M48T35AV TIMEKEEPER RAM is a 32 Kbit x 8 non-volatile static RAM and real-time
clock. The monolithic chip is available in two special packages to provide a highly integrated
battery-backed memory and real-time clock solution.
The M48T35AV is a non-volatile pin and function equivalent to any JEDEC standard
32 Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets,
providing the non-volatility of PROMs without any requirement for special WRITE timing or
limitations on the number of WRITEs that can be performed.
™
The 28-pin, 600 mil DIP CAPHAT houses the M48T35AV silicon with a quartz crystal and
a long-life lithium button cell in a single package.
The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct
®
connection to a separate SNAPHAT housing containing the battery and crystal. The
unique design allows the SNAPHAT battery package to be mounted on top of the SOIC
package after the completion of the surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery and crystal damage due to the high
temperatures required for device surface-mounting. The SNAPHAT housing is keyed to
prevent reverse insertion.
The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or
in tape & reel form.
For the 28-lead SOIC, the battery/crystal package part numbers are M4T28-BR12SH1 (48
mAh lithium battery SNAPHAT), M4T32-BR12SH1 (120 mAh lithium battery SNAPHAT),
and M4T32-BR12SH6 (120 mAh lithium battery SNAPHAT, –40 to +85 °C crystal).
Figure 1.
Logic diagram
V
CC
15
8
A0-A14
DQ0-DQ7
W
E
M48T35AV
G
V
SS
AI02797B
Doc ID 6845 Rev 9
5/29
Description
M48T35AV
Table 1.
Signal names
A0-A14
Address inputs
Data inputs / outputs
Chip enable
DQ0-DQ7
E
G
Output enable
WRITE enable
Supply voltage
Ground
W
VCC
VSS
Figure 2.
DIP connections
A14
A12
A7
1
2
3
4
5
6
7
8
9
28
27
V
CC
W
26 A13
25 A8
24 A9
23 A11
A6
A5
A4
A3
22
G
M48T35AV
A2
21 A10
20
A1
E
A0 10
DQ0 11
DQ1 12
DQ2 13
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
V
14
SS
AI02798B
Figure 3.
SOIC connections
A14
A12
A7
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
A13
A8
A6
A5
A9
A4
A11
G
A3
M48T35AV
A2
A10
E
A1
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
V
SS
AI02799
6/29
Doc ID 6845 Rev 9
M48T35AV
Figure 4.
Description
Block diagram
OSCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
A0-A14
POWER
DQ0-DQ7
32,760 x 8
SRAM ARRAY
LITHIUM
CELL
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
W
G
V
PFD
AI01623
V
V
CC
SS
Doc ID 6845 Rev 9
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Operation modes
M48T35AV
2
Operation modes
As Figure 4 on page 7 shows, the static memory array and the quartz controlled clock
oscillator of the M48T35AV are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with addresses 7FF8h-7FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour
BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are
made automatically. Byte 7FF8h is the clock control register. This byte controls user access
to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T35AV includes a
clock control circuit which updates the clock bytes with current information once per second.
The information can be accessed by the user in the same manner as any other location in
the static memory array.
The M48T35AV also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 3 V supply for an out of tolerance condition. When V is out of
CC
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V . As V falls below the
CC
CC
battery backup switchover voltage (V ), the control circuitry connects the battery which
SO
maintains data and clock operation until valid power returns.
Table 2.
Mode
Operating modes
VCC
E
G
W
DQ0-DQ7
Power
Standby
Deselect
WRITE
READ
VIH
X
X
High Z
DIN
VIL
VIL
VIL
X
X
VIL
VIH
VIH
X
Active
3.0 to 3.6 V
VIL
DOUT
High Z
High Z
Active
READ
VIH
X
Active
Deselect
VSO to VPFD (min)(1)
CMOS standby
Battery backup
mode
(1)
Deselect
≤ VSO
X
X
X
High Z
1. See Table 11 on page 21 for details.
Note:
X = V or V ; V = Battery backup switchover voltage.
IH IL SO
2.1
READ mode
The M48T35AV is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The unique address specified by the 15 address inputs defines which one of
the 32,768 bytes of data is to be accessed. Valid data will be available at the data I/O pins
within address access time (t
) after the last address input signal is stable, providing that
AVQV
the E and G access times are also satisfied.
If the E and G access times are not met, valid data will be available after the latter of the chip
enable access time (t
) or output enable access time (t
).
ELQV
GLQV
8/29
Doc ID 6845 Rev 9
M48T35AV
Operation modes
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before t
, the data lines will be driven to an indeterminate state until t
. If
AVQV
AVQV
the Address Inputs are changed while E and G remain active, output data will remain valid
for output data hold time (t ) but will go indeterminate until the next address access.
AXQX
Figure 5.
READ mode AC waveforms
tAVAV
VALID
A0-A14
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00925
Note:
WRITE enable (W) = High.
Table 3. READ mode AC characteristics
M48T35AV
–100
Symbol
Parameter(1)
Unit
Min
Max
tAVAV
tAVQV
tELQV
tGLQV
READ cycle time
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to output valid
Chip enable low to output valid
Output enable low to output valid
100
100
50
(2)
tELQX
tGLQX
tEHQZ
tGHQZ
Chip enable low to output transition
Output enable low to output transition
Chip enable high to output Hi-Z
10
5
(2)
(2)
(2)
50
40
Output enable high to output Hi-Z
Address transition to output transition
tAXQX
10
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).
2. CL = 5 pF.
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Operation modes
M48T35AV
2.2
WRITE mode
The M48T35AV is in the WRITE mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
from chip enable or t
from WRITE enable prior
EHAX
WHAX
to the initiation of another READ or WRITE cycle. Data-in must be valid t
prior to the
DVWH
end of WRITE and remain valid for t
afterward. G should be kept high during WRITE
WHDX
cycles to avoid bus contention; however, if the output bus has been activated by a low on E
and G, a low on W will disable the outputs t after W falls.
WLQZ
Figure 6.
WRITE enable controlled, WRITE mode AC waveform
tAVAV
VALID
A0-A14
tAVWH
tAVEL
tWHAX
E
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00926
Figure 7.
Chip enable controlled, WRITE mode AC waveforms
tAVAV
VALID
A0-A14
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI00927
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Doc ID 6845 Rev 9
M48T35AV
Operation modes
Table 4.
Symbol
WRITE mode AC characteristics
Parameter(1)
M48T35AV
Unit
Min
Max
tAVAV
tAVWL
tAVEL
WRITE cycle time
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to WRITE enable low
Address valid to chip enable low
WRITE enable pulse width
0
tWLWH
tELEH
tWHAX
tEHAX
tDVWH
tDVEH
tWHDX
tEHDX
80
80
10
10
50
50
5
Chip enable low to chip enable high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
5
(2)(3)
tWLQZ
tAVWH
tAVEH
50
80
80
10
(2)(3)
tWHQX
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid V applied, the M48T35AV operates as a conventional BYTEWIDE™ static
CC
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V falls within the V
(max), V
(min) window (see Figure 13,
CC
PFD
PFD
Table 10, and Table 11 on page 21). All outputs become high impedance, and all inputs are
treated as “don't care.”
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
(min), the
PFD
user can be assured the memory will be in a write protected state, provided the V fall time
CC
is not less than t . The M48T35AV may respond to transient noise spikes on V that reach
F
CC
into the deselect window during the time the device is sampling V . Therefore, decoupling
CC
of the power supply lines is recommended.
When V drops below V , the control circuit switches power to the internal battery which
CC
SO
preserves data and powers the clock. The internal button cell will maintain data in the
M48T35AV for an accumulated period of at least 7 years when V is less than V . As
CC
SO
system power returns and V rises above V , the battery is disconnected and the power
CC
SO
supply is switched to external V . Write protection continues until V reaches V (min)
CC
CC
PFD
plus t (min). E should be kept high as V rises past V (min) to prevent inadvertent
rec
CC
PFD
WRITE cycles prior to processor stabilization. Normal RAM operation can resume t after
rec
V
exceeds V
(max).
CC
PFD
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Operation modes
M48T35AV
Also, as V rises, the battery voltage is checked. If the voltage is less than approximately
CC
2.5 V, an internal battery not OK (BOK) flag will be set. The BOK flag can be checked after
power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is
automatically cleared after the first WRITE, and normal RAM operation resumes. Figure 8
illustrates how a BOK check routine could be structured.
For more information on battery storage life refer to the application note AN1012.
Figure 8.
Checking the BOK flag status
POWER-UP
READ DATA
AT ANY ADDRESS
WRITE DATA
COMPLEMENT BACK
TO SAME ADDRESS
READ DATA
AT SAME
ADDRESS AGAIN
IS DATA
COMPLEMENT
OF FIRST
NO (BATTERY LOW)
READ?
NOTIFY SYSTEM
OF LOW BATTERY
(DATA MAY BE
(BATTERY OK)
YES
CORRUPTED)
WRITE ORIGINAL
DATA BACK TO
SAME ADDRESS
CONTINUE
AI00607
12/29
Doc ID 6845 Rev 9
M48T35AV
Clock operations
3
Clock operations
3.1
Reading the clock
®
Updates to the TIMEKEEPER registers (see Table 5) should be halted before clock data is
read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM
array are only data registers and not the actual clock counters, so updating the registers can
be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, D6 in the control register 7FF8h. As
long as a '1' remains in that position, updating is halted.
After a halt is issued, the registers reflect the count; that is, the day, date, and the time that
were current at the moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating is within a second after the bit is reset to a '0.'
3.2
Setting the clock
Bit D7 of the control register 7FF8h is the WRITE bit. Setting the WRITE bit to a '1,' like the
®
READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with
the correct day, date, and time data in 24-hour BCD format (seeTable 5). Resetting the
WRITE bit to a '0' then transfers the values of all time registers 7FF9h-7FFFh to the actual
TIMEKEEPER counters and allows normal operation to resume. The FT bit and the bits
marked as '0' in Table 5 must be written to '0' to allow for normal TIMEKEEPER and RAM
operation. After the WRITE bit is reset, the next clock update will occur within one second.
®
st
See the application note AN923, “TIMEKEEPER rolling into the 21 century” for
information on century rollover.
3.3
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP bit is the MSB of the seconds register. Setting it to a '1' stops the
oscillator. The M48T35AV is shipped from STMicroelectronics with the STOP bit set to a '1.'
When reset to a '0,' the M48T35AV oscillator starts within 1 second.
Doc ID 6845 Rev 9
13/29
Clock operations
Table 5.
M48T35AV
Register map
Data
D4
Function/range
BCD format
Address
D7
D6
D5
D3
D2
D1
Year
D0
7FFFh
7FFEh
7FFDh
7FFCh
7FFBh
7FFAh
7FF9h
7FF8h
10 years
Year
00-99
01-12
01-31
0
0
0
0
0
10 M.
CB
Month
Date
Month
Date
10 date
0
FT
0
CEB
0
Day
Century/day 00-01/01-07
0
10 hours
Hours
Minutes
Seconds
Hours
Minutes
Seconds
Control
00-23
00-59
00-59
0
10 minutes
10 seconds
S
ST
W
R
Calibration
Keys:
S = SIGN bit
FT = FREQUENCY TEST bit (must be set to '0' upon power for normal operation)
R = READ bit
W = WRITE bit
ST = STOP bit
0 = Must be set to '0'
CEB = CENTURY ENABLE bit
CB = CENTURY bit
Note:
When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century
(dependent upon the initial value set).
When CEB is set to '0,' CB will not toggle. The WRITE bit does not need to be set to write to
CEB.
3.4
Calibrating the clock
The M48T35AV is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator
frequency error at 25°C, which equates to about 1.53 minutes per month. With the
calibration bits properly set, the accuracy of each M48T35AV improves to better than
+1/–2 ppm at 25°C.
The oscillation rate of any crystal changes with temperature (see Figure 9 on page 16).
Most clock chips compensate for crystal frequency and temperature shift error with
cumbersome “trim” capacitors. The M48T35AV design, however, employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 10 on page 16. The number of times pulses
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five calibration bits found in the control register. Adding
counts speeds the clock up, subtracting counts slows the clock down.
The calibration byte occupies the five lower order bits (D4-D0) in the control register 7FF8h.
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is the
SIGN bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration
14/29
Doc ID 6845 Rev 9
M48T35AV
Clock operations
occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register. Assuming that the oscillator is in
fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –
2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M48T35AV may
require. The first involves simply setting the clock, letting it run for a month and comparing it
to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows
the designer to give the end user the ability to calibrate his clock as his environment may
require, even after the final product is packaged in a non-user serviceable enclosure.
The second approach is better suited to a manufacturing environment, and involves the use
of some test equipment. When the FREQUENCY TEST (FT) bit, the seventh-most
significant bit in the day register is set to a '1,' and D7 of the seconds register is a '0'
(oscillator running), DQ0 will toggle at 512 Hz during a READ of the seconds register. Any
deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the
test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (WR001010) to be loaded into the calibration byte
for correction.
Note:
Setting or changing the calibration byte does not affect the frequency test output frequency.
The FT bit MUST be reset to '0' for normal clock operations to resume. The FT bit is
automatically reset on power-down.
®
For more information on calibration, see application note AN934, “TIMEKEEPER
Calibration.”
3.5
Century bit
Bit D5 and D4 of clock register 7FFCh contain the CENTURY ENABLE bit (CEB) and the
CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or
from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle.
Note:
The WRITE bit must be set in order to write to the CENTURY bit.
Doc ID 6845 Rev 9
15/29
Clock operations
Figure 9.
M48T35AV
Crystal accuracy across temperature
ppm
20
0
-20
-40
-60
-80
-100
2
ΔF
F
ppm
C2
= -0.038
(T - T0)
10%
T0 = 25 °C
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
°C
AI02124
Figure 10. Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
16/29
Doc ID 6845 Rev 9
M48T35AV
Clock operations
3.6
VCC noise and negative going transients
I
transients, including those produced by output switching, can produce voltage
CC
fluctuations, resulting in spikes on the V bus. These transients can be reduced if
CC
capacitors are used to store energy which stabilizes the V bus. The energy stored in the
CC
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A bypass capacitor value of 0.1 µF (as shown in
Figure 11) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V that drive it to values below V by as much as
CC
SS
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
Schottky diode from V to V (cathode connected to V , anode to V ). Schottky diode
CC
SS
CC
SS
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
mount.
Figure 11. Supply voltage protection
V
CC
V
CC
0.1µF
DEVICE
V
SS
AI02169
Doc ID 6845 Rev 9
17/29
Maximum ratings
M48T35AV
4
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 6.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
TA
Ambient operating temperature
0 to 70
–40 to 85
260
°C
°C
°C
V
TSTG
Storage temperature (VCC off, oscillator off)
Lead solder temperature for 10 seconds
Input or output voltages
(1)(2)(3)
TSLD
VIO
–0.3 to 4.6
VCC
Supply voltage
Output current
Power dissipation
–0.3 to 4.6
V
mA
W
IO
20
1
PD
1. For DIP package, soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds.
Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of
wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat
damage to the batteries.
2. For DIP packaged devices, ultrasonic vibrations should not be used for post-solder cleaning to avoid
damaging the crystal.
3. For SOH28 package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260 °C (the time above
255 °C must not exceed 30 seconds).
Caution:
Caution:
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
®
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
18/29
Doc ID 6845 Rev 9
M48T35AV
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 7.
Operating and AC measurement conditions
Parameter
M48T35AV
Unit
Supply voltage (VCC
)
3.0 to 3.6
0 to 70
50
V
°C
pF
ns
V
Ambient operating temperature (TA)
Load capacitance (CL)
Input rise and fall times
≤ 5
Input pulse voltages
0 to 3
1.5
Input and output timing ref. voltages
V
Note:
Output Hi-Z is defined as the point where data is no longer driven.
Figure 12. AC measurement load circuit
DEVICE
UNDER
TEST
C
= 50pF
(or 5pF)
1.75V
L
C
includes JIG capacitance
L
AI02586
Table 8.
Symbol
Capacitance
Parameter(1)(2)
Min
Max
Unit
CIN
Input capacitance
-
-
10
10
pF
pF
(3)
COUT
Output capacitance
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. At 25 °C, f = 1 MHz.
3. Outputs deselected.
Doc ID 6845 Rev 9
19/29
DC and AC parameters
Table 9. DC characteristics
Symbol
ILI
M48T35AV
Unit
M48T35AV
Max
Parameter
Test condition(1)
Min
Input leakage current
Output leakage current
Supply current
0 V ≤ VIN ≤ VCC
0 V ≤ VOUT ≤ VCC
Outputs open
E = VIH
1
µA
µA
mA
mA
mA
V
(2)
ILO
1
ICC
ICC1
ICC2
30
Supply current (standby) TTL
Supply current (standby) CMOS
Input low voltage
2
2
E = VCC – 0.2 V
(3)
VIL
–0.3
2.2
0.8
VIH
VOL
VOH
Input high voltage
VCC + 0.3
0.4
V
Output low voltage
IOL = 2.1 mA
IOH = –1 mA
V
Output high voltage
2.4
V
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).
2. Outputs deselected.
3. Negative spikes of –1 V allowed for up to 10 ns once per cycle.
Figure 13. Power down/up mode AC waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tFB
tRB
tPD
tDR
trec
RECOGNIZED
RECOGNIZED
INPUTS
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01168C
20/29
Doc ID 6845 Rev 9
M48T35AV
DC and AC parameters
Table 10. Power down/up AC characteristics
Symbol
Parameter(1)
Min
Max
Unit
tPD
E or W at VIH before power down
0
µs
µs
(2)
tF
VPFD (max) to VPFD (min) VCC fall time
VPFD (min) to VSS VCC fall time
300
(3)
150
µs
tFB
tR
VPFD (min) to VPFD (max) VCC rise time
VSS to VPFD (min) VCC rise time
VPFD (max) to inputs recognized
10
1
µs
µs
tRB
trec
40
200
ms
1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 11. Power down/up trip points DC characteristics
Symbol
Parameter(1)(2)
Min
Typ
Max
Unit
VPFD
VSO
Power-fail deselect voltage
2.7
2.9
3.0
V
V
Battery backup switchover voltage
Expected data retention time
VPFD –100mV
tDR
10(4)
Years
(3)
1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. All voltages referenced to VSS
3. At 25 °C, VCC = 0 V.
.
4. CAPHAT™ and M4T32-BR12SH1 SNAPHAT® only, M4T28-BR12SH1 SNAPHAT® top tDR = 7 years (typ).
Doc ID 6845 Rev 9
21/29
Package mechanical data
M48T35AV
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 14. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline
A2
A
L
A1
e1
C
B1
B
eA
e3
D
N
1
E
PCDIP
Note:
Drawing is not to scale.
Table 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, pack. mech. data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
A1
A2
B
8.89
0.38
8.38
0.38
1.14
0.20
39.37
17.83
2.29
9.65
0.76
8.89
0.53
1.78
0.31
39.88
18.34
2.79
0.350
0.015
0.330
0.015
0.045
0.008
1.550
0.702
0.090
0.380
0.030
0.350
0.021
0.070
0.012
1.570
0.722
0.110
B1
C
D
E
e1
e3
eA
L
33.02
1.3
15.24
3.05
28
16.00
3.81
0.600
0.120
28
0.630
0.150
N
22/29
Doc ID 6845 Rev 9
M48T35AV
Package mechanical data
®
Figure 15. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT ,
package outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note:
Drawing is not to scale.
®
Table 13. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT , pack.
mech. data
mm
Min
inches
Min
Symb
Typ
Max
Typ
Max
A
A1
A2
B
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
a
N
28
28
CP
0.10
0.004
Doc ID 6845 Rev 9
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Package mechanical data
M48T35AV
®
Figure 16. SH – 4-pin SNAPHAT housing for 48 mAh battery & crystal, pack. outline
A2
A1
A
A3
eA
D
B
L
eB
E
SHTK-A
Note:
Drawing is not to scale.
®
Table 14. SH – 4-pin SNAPHAT housing for 48 mAh battery & crystal, pack. mech.
data
mm
Min
inches
Min
Symb
Typ
Max
Typ
Max
A
A1
A2
A3
B
9.78
7.24
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
6.99
0.38
0.46
21.21
14.22
15.55
3.20
0.56
21.84
14.99
15.95
3.61
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
2.29
24/29
Doc ID 6845 Rev 9
M48T35AV
Package mechanical data
®
Figure 17. SH – 4-pin SNAPHAT housing for 120 mAh battery & crystal, pack. outline
A2
A1
A
A3
eA
D
B
L
eB
E
SHTK-A
Note:
Drawing is not to scale.
®
Table 15. SH – 4-pin SNAPHAT housing for 120 mAh battery & crystal, pack. mech.
data
mm
Min
inches
Min
Symb
Typ
Max
Typ
Max
A
A1
A2
A3
B
10.54
8.51
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
Doc ID 6845 Rev 9
25/29
Part numbering
M48T35AV
7
Part numbering
Table 16. Ordering information scheme
Example:
M48T
35AV
–10
MH
1
E
Device type
M48T
Supply voltage and write protect voltage
35AV = VCC = 3.0 to 3.6 V; VPFD = 2.7 to 3.0 V
Speed
–10 = 100 ns (35AV)
Package
PC = PCDIP28
MH(1) = SOH28
Temperature range
1 = 0 to 70°C
Shipping method
For SOH28:
E = Lead-free package (ECOPACK®), tubes
F = Lead-free package (ECOPACK®), tape & reel
For PCDIP28:
blank = tubes
1. The SOIC package (SOH28) requires the SNAPHAT® battery package which is ordered separately under
the part number “M4TXX-BR12SHx” in plastic tubes (see Table 17).
®
Caution:
Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it
will drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
®
Table 17. SNAPHAT battery table
Part number
Description
Package
®
M4T28-BR12SH1
M4T32-BR12SH1
M4T32-BR12SH6
Lithium battery (48 mAh) SNAPHAT
Lithium battery (120 mAh) SNAPHAT
SH
SH
SH
®
®
Lithium battery (120 mAh) SNAPHAT , –40 to +85 °C crystal
26/29
Doc ID 6845 Rev 9
M48T35AV
Environmental information
8
Environmental information
Figure 18. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
Doc ID 6845 Rev 9
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Revision history
M48T35AV
9
Revision history
Table 18. Document revision history
Date
Revision
Changes
Nov-1999
21-Apr-2000
29-May-2000
1
2
First issue
From preliminary data to datasheet
2.1
tFB change (Table 10)
Reformatted; temp./voltage info. added to tables (Table 8, 9, 3, 4, 10,
11); add century bit text
20-Jul-2001
3
20-May-2002
31-Mar-2003
01-Apr-2004
3.1
4
Modify reflow time and temperature footnotes (Table 6)
v2.2 template applied; data retention condition updated (Table 11)
Reformatted; updated with lead-free package information (Table 6, 16)
5
Reformatted document; added lead-free second level interconnect
information to cover page and Section 6: Package mechanical data,
updated Table 16, 17; removed M48T35AY and all references.
21-Nov-2007
6
Updated Table 6, Section 6: Package mechanical data; added
Section 8: Environmental information; minor formatting changes.
23-Mar-2009
21-Oct-2010
24-Jun-2011
7
8
9
Updated Section 4, Table 12; reformatted document.
Updated footnote 1 of Table 6: Absolute maximum ratings; updated
Features and Section 8: Environmental information.
28/29
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M48T35AV
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