M48T35AV-10PH1TR [STMICROELECTRONICS]
5.0 or 3.3V, 256 Kbit (32 Kb x8) TIMEKEEPER㈢ SRAM; 5.0或3.3V ， 256千位（ 32 KB ×8 ） TIMEKEEPER㈢ SRAM
| 型号： | M48T35AV-10PH1TR |
| 厂家： | 
ST |
| 描述： | 5.0 or 3.3V, 256 Kbit (32 Kb x8) TIMEKEEPER㈢ SRAM |
| 文件： | 总25页 (文件大小：511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T35AY
M48T35AV
®
5.0 or 3.3V, 256 Kbit (32 Kb x8) TIMEKEEPER SRAM
FEATURES SUMMARY
■
INTEGRATED, ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
Figure 1. 28-pin, PCDIP CAPHAT™ Package
CONTROL CIRCUIT AND BATTERY
■
■
BYTEWIDE™ RAM-LIKE CLOCK ACCESS
BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, AND SECONDS
■
■
BATTERY LOW FLAG (BOK)
FREQUENCY TEST OUTPUT FOR REAL
TIME CLOCK
28
■
■
AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION
WRITE PROTECT VOLTAGES
1
PCDIP28 (PC)
Battery/Crystal
CAPHAT
(V
–
= Power-fail Deselect Voltage):
PFD
M48T35AY: V = 4.5 to 5.5V
CC
4.2V ≤ V
≤ 4.5V
PFD
–
M48T35AV: V = 3.0 to 3.6V
CC
2.7V ≤ V
≤ 3.0V
PFD
Figure 2. 28-pin SOIC Package
■
■
SELF-CONTAINED BATTERY AND
CRYSTAL IN THE CAPHAT™ DIP
PACKAGE
SNAPHAT (SH)
Battery/Crystal
SOIC PACKAGE PROVIDES DIRECT
®
CONNECTION FOR A SNAPHAT
HOUSING CONTAINING THE BATTERY
AND CRYSTAL
®
■
■
SNAPHAT HOUSING (BATTERY AND
CRYSTAL) IS REPLACEABLE
PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 32Kb x8 SRAMs
28
1
SOH28 (MH)
April 2004
1/25
M48T35AY, M48T35AV
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 28-pin, PCDIP CAPHAT™ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. WRITE Enable Controlled, WRITE Mode AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 9. Chip Enable Controlled, WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10.Checking the BOK Flag Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
V
CC
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/25
M48T35AY, M48T35AV
Figure 15.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Outline . . . . . . . . . . . . . . 19
Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Mechanical Data . . . . . . . 19
Figure 17.SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline. 20
Table 13. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Pack. Mech. Data20
Figure 18.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 21
Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 21
Figure 19.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 22
Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 22
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3/25
M48T35AY, M48T35AV
SUMMARY DESCRIPTION
The M48T35AY/V TIMEKEEPER RAM is a 32Kb
®
®
nection to a separate SNAPHAT housing con-
x 8 non-volatile static RAM and real time clock.
The monolithic chip is available in two special
packages to provide a highly integrated battery
backed-up memory and real time clock solution.
The M48T35AY/V is a non-volatile pin and func-
tion equivalent to any JEDEC standard 32Kb x 8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
The 28-pin, 600mil DIP CAPHAT™ houses the
M48T35AY/V silicon with a quartz crystal and a
long-life lithium button cell in a single package.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
taining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form.
For the 28-lead SOIC, the battery/crystal package
(e.g. SNAPHAT) part number is “M4T28-BR12SH”
(see Table 17., page 23).
Figure 3. Logic Diagram
Table 1. Signal Names
V
CC
A0-A14
Address Inputs
Data Inputs / Outputs
Chip Enable
DQ0-DQ7
15
8
E
A0-A14
DQ0-DQ7
G
W
Output Enable
WRITE Enable
Supply Voltage
Ground
W
E
M48T35AY
M48T35AV
V
CC
V
SS
G
V
SS
AI02797B
4/25
M48T35AY, M48T35AV
Figure 4. DIP Connections
Figure 5. SOIC Connections
A14
A12
A7
1
2
3
4
5
6
28
27
V
CC
W
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
2
26 A13
25 A8
24 A9
23 A11
3
A13
A8
A6
A6
4
A5
A5
5
A9
A4
A4
6
A11
G
A3 7 M48T35AY 22
G
A3
7
M48T35AY
M48T35AV
M48T35AV
A2
A1
8
9
21 A10
A2
8
A10
E
20
E
A1
9
A0 10
DQ0 11
DQ1 12
DQ2 13
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
V
14
SS
V
SS
AI02798B
AI02799
Figure 6. Block Diagram
OSCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
A0-A14
POWER
DQ0-DQ7
32,760 x 8
SRAM ARRAY
LITHIUM
CELL
E
VOLTAGE SENSE
AND
W
G
V
PFD
SWITCHING
CIRCUITRY
V
V
CC
SS
AI01623
5/25
M48T35AY, M48T35AV
OPERATION MODES
As Figure 6., page 5 shows, the static memory ar-
ray and the quartz controlled clock oscillator of the
M48T35AY/V are integrated on one silicon chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with
addresses 7FF8h-7FFFh.
The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD for-
mat. Corrections for 28, 29 (leap year - valid until
2100), 30, and 31 day months are made automat-
ically. Byte 7FF8h is the clock control register. This
byte controls user access to the clock information
and also stores the clock calibration setting.
cells. The M48T35AY/V includes a clock control
circuit which updates the clock bytes with current
information once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T35AY/V also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single 3V supply for an out of tolerance
condition. When V is out of tolerance, the circuit
CC
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V . As V falls
CC
CC
below the Battery Back-up Switchover Voltage
(V ), the control circuitry connects the battery
SO
which maintains data and clock operation until val-
id power returns.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ READ/WRITE memory
Table 2. Operating Modes
V
Mode
Deselect
WRITE
READ
E
G
X
X
W
DQ0-DQ7
Power
Standby
Active
CC
V
IH
X
High Z
4.5 to 5.5V
or
3.0 to 3.6V
V
V
V
V
D
IL
IL
IL
IL
IH
IH
IN
V
IL
V
V
D
Active
OUT
V
IH
READ
High Z
High Z
High Z
Active
(1)
Deselect
X
X
X
CMOS Standby
V
SO
to V
(min)
PFD
(1)
Deselect
X
X
X
Battery Back-up Mode
≤ V
SO
Note: X = V or V ; V = Battery Back-up Switchover Voltage.
IH
IL
SO
1. See Table 11., page 18 for details.
6/25
M48T35AY, M48T35AV
READ Mode
The M48T35AY/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 15 ad-
dress inputs defines which one of the 32,768 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
Access time (t
) or Output Enable Access time
ELQV
(t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
, the data lines will be driven to an
AVQV
indeterminate state until t
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
. If the Address In-
AVQV
time (t
) after the last address input signal is
AVQV
stable, providing that the E and G access times
are also satisfied.
time (t
) but will go indeterminate until the next
AXQX
If the E and G access times are not met, valid data
will be available after the latter of the Chip Enable
Address Access.
Figure 7. READ Mode AC Waveforms
tAVAV
VALID
A0-A14
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00925
Note: WRITE Enable (W) = High.
Table 3. READ Mode AC Characteristics
M48T35AY
–70
M48T35AV
–100
(1)
Symbol
Unit
Parameter
Min
Max
Min
Max
t
READ Cycle Time
70
100
ns
ns
ns
ns
AVAV
t
Address Valid to Output Valid
70
70
35
100
100
50
AVQV
t
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
ELQV
t
GLQV
(2)
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
5
5
10
5
ns
ns
ns
ns
ns
t
ELQX
GLQX
EHQZ
(2)
(2)
(2)
t
t
25
25
50
40
Output Enable High to Output Hi-Z
Address Transition to Output Transition
t
GHQZ
t
10
10
AXQX
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. C = 5pF.
L
7/25
M48T35AY, M48T35AV
WRITE Mode
The M48T35AY/V is in the WRITE Mode whenev-
er W and E are low. The start of a WRITE is refer-
enced from the latter occurring falling edge of W or
E. A WRITE is terminated by the earlier rising
edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
er READ or WRITE cycle. Data-in must be valid t
D-
prior to the end of WRITE and remain valid for
VWH
t
afterward. G should be kept high during
WHDX
WRITE cycles to avoid bus contention; however, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
after W falls.
WLQZ
a minimum of t
from Chip Enable or t
EHAX
WHAX
from WRITE Enable prior to the initiation of anoth-
Figure 8. WRITE Enable Controlled, WRITE Mode AC Waveform
tAVAV
A0-A14
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00926
Figure 9. Chip Enable Controlled, WRITE Mode AC Waveforms
tAVAV
A0-A14
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI00927
8/25
M48T35AY, M48T35AV
Table 4. WRITE Mode AC Characteristics
M48T35AY
–70
M48T35AV
(1)
Symbol
–100
Unit
Parameter
Min
Max
Min
100
0
Max
t
WRITE Cycle Time
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to WRITE Enable Low
Address Valid to Chip Enable Low
WRITE Enable Pulse Width
AVWL
t
0
0
AVEL
t
50
55
0
80
80
10
10
50
50
5
WLWH
t
Chip Enable Low to Chip Enable High
WRITE Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to WRITE Enable High
Input Valid to Chip Enable High
ELEH
t
WHAX
t
0
EHAX
t
30
30
5
DVWH
t
DVEH
t
WRITE Enable High to Input Transition
Chip Enable High to Input Transition
WHDX
t
5
5
EHDX
(2,3)
WRITE Enable Low to Output Hi-Z
Address Valid to WRITE Enable High
Address Valid to Chip Enable High
WRITE Enable High to Output Transition
25
50
ns
ns
ns
ns
t
WLQZ
t
60
60
5
80
80
10
AVWH
t
AVEH
(2,3)
t
WHQX
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. C = 5pF.
L
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
9/25
M48T35AY, M48T35AV
Data Retention Mode
Figure 10. Checking the BOK Flag Status
With valid V applied, the M48T35AY/V operates
CC
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when V
falls within the V
(max), VPFD
CC
PFD
(min) window (see Figure 15, Table 10, and Table
11., page 18). All outputs become high imped-
ance, and all inputs are treated as “don't care.”
POWER-UP
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
READ DATA
AT ANY ADDRESS
tent. At voltages below V
(min), the user can be
PFD
WRITE DATA
COMPLEMENT BACK
TO SAME ADDRESS
assured the memory will be in a write protected
state, provided the V fall time is not less than t .
CC
F
The M48T35AY/V may respond to transient noise
spikes on V that reach into the deselect window
CC
during the time the device is sampling V . There-
fore, decoupling of the power supply lines is rec-
ommended.
CC
READ DATA
AT SAME
ADDRESS AGAIN
When V
drops below V , the control circuit
SO
CC
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T35AY/V
for an accumulated period of at least 7 years when
IS DATA
COMPLEMENT
OF FIRST
NO (BATTERY LOW)
V
is less than V . As system power returns
CC
SO
READ?
and V
rises above V , the battery is discon-
SO
CC
NOTIFY SYSTEM
OF LOW BATTERY
(DATA MAY BE
CORRUPTED)
nected and the power supply is switched to exter-
(BATTERY OK) YES
nal V . Write protection continues until V
CC
CC
reaches V
(min) plus t
(min). E should be
PFD
rec
kept high as V rises past V
inadvertent WRITE cycles prior to processor stabi-
lization. Normal RAM operation can resume t af-
(min) to prevent
CC
PFD
WRITE ORIGINAL
DATA BACK TO
SAME ADDRESS
rec
ter V exceeds V
(max).
PFD
CC
Also, as V rises, the battery voltage is checked.
CC
CONTINUE
If the voltage is less than approximately 2.5V, an
internal Battery Not OK (BOK) flag will be set. The
BOK flag can be checked after power up. If the
BOK flag is set, the first WRITE attempted will be
blocked. The flag is automatically cleared after the
first WRITE, and normal RAM operation resumes.
Figure 10 illustrates how a BOK check routine
could be structured.
AI00607
For more information on Battery Storage Life refer
to the Application Note AN1012.
10/25
M48T35AY, M48T35AV
CLOCK OPERATIONS
Reading the Clock
®
Updates to the TIMEKEEPER registers (see Ta-
ble 5) should be halted before clock data is read to
prevent reading data in transition. The BiPORT™
TIMEKEEPER cells in the RAM array are only
data registers and not the actual clock counters,
so updating the registers can be halted without
disturbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register 7FF8h. As
long as a '1' remains in that position, updating is
halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and the time that were
current at the moment the halt command was is-
sued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a '0.'
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (see
Table 5). Resetting the WRITE Bit to a '0' then
transfers the values of all time registers 7FF9h-
7FFFh to the actual TIMEKEEPER counters and
allows normal operation to resume. The FT Bit and
the bits marked as '0' in Table 5 must be written to
'0' to allow for normal TIMEKEEPER and RAM op-
eration. After the WRITE Bit is reset, the next clock
update will occur within one second.
®
See the Application Note AN923, “TIMEKEEPER
st
Rolling Into the 21 Century” for information on
Century Rollover.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. The M48T35AY/V is
shipped from STMicroelectronics with the STOP
Bit set to a '1.' When reset to a '0,' the M48T35AY/
V oscillator starts within 1 second.
Setting the Clock
Bit D7 of the Control Register 7FF8h is the WRITE
Bit. Setting the WRITE Bit to a '1,' like the READ
®
Bit, halts updates to the TIMEKEEPER registers.
Table 5. Register Map
Data
Function/Range
BCD Format
Address
D7
D6
D5
D4
10 M.
CB
D3
D2
D1
D0
7FFFh
7FFEh
7FFDh
7FFCh
7FFBh
7FFAh
7FF9h
7FF8h
10 Years
Year
Month
Date
Year
Month
Date
00-99
01-12
01-31
0
0
0
0
0
10 Date
0
FT
0
CEB
0
Day
Hours
Century/Day 00-01/01-07
0
10 Hours
Hours
Minutes
Seconds
Control
00-23
00-59
00-59
0
10 Minutes
10 Seconds
S
Minutes
ST
W
Seconds
R
Calibration
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit (Must be set to '0' upon power
for normal operation)
R = READ Bit
ST = STOP Bit
0 = Must be set to '0'
CEB = Century Enable Bit
CB = Century Bit
W = WRITE Bit
Note: When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set).
When CEB is set to '0,' CB will not toggle. The WRITE Bit does not need to be set to write to CEB.
11/25
M48T35AY, M48T35AV
Calibrating the Clock
The M48T35AY/V is driven by a quartz-controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not to exceed 35 ppm
(parts per million) oscillator frequency error at
25°C, which equates to about ±1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M48T35AY/V improves to better
than +1/–2 ppm at 25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 11., page 13). Most clock
chips compensate for crystal frequency and tem-
perature shift error with cumbersome “trim” capac-
itors. The M48T35AY/V design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure 12., page 13. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five calibration bits found in
the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order
bits (D4-D0) in the Control Register 7FF8h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is the Sign Bit; '1' in-
dicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T35AY/V may re-
quire. The first involves simply setting the clock,
letting it run for a month and comparing it to a
known accurate reference (like WWV broadcasts).
While that may seem crude, it allows the designer
to give the end user the ability to calibrate his clock
as his environment may require, even after the fi-
nal product is packaged in a non-user serviceable
enclosure.
The second approach is better suited to a manu-
facturing environment, and involves the use of
some test equipment. When the Frequency Test
(FT) Bit, the seventh-most significant bit in the Day
Register is set to a '1,' and D7 of the Seconds Reg-
ister is a '0' (Oscillator Running), DQ0 will toggle at
512 Hz during a READ of the Seconds Register.
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024
Hz would indicate a +20 ppm oscillator frequency
error, requiring a –10 (WR001010) to be loaded
into the Calibration Byte for correction.
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output fre-
quency.
The FT Bit MUST be reset to '0' for normal clock
operations to resume. The FT Bit is automatically
Reset on power-down.
For more information on calibration, see Applica-
®
tion Note AN934, “TIMEKEEPER Calibration.”
Century Bit
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768
Hz, each of the 31 increments in the Calibration
Byte would represent +10.7 or –5.35 seconds per
Bit D5 and D4 of Clock Register 7FFCh contain
the CENTURY ENABLE Bit (CEB) and the CEN-
TURY Bit (CB). Setting CEB to a '1' will cause CB
to toggle, either from a '0' to '1' or from '1' to '0' at
the turn of the century (depending upon its initial
state). If CEB is set to a '0,' CB will not toggle.
Note: The WRITE Bit must be set in order to write
to the CENTURY Bit.
12/25
M48T35AY, M48T35AV
Figure 11. Crystal Accuracy Across Temperature
ppm
20
0
-20
-40
2
∆F
F
ppm
C2
= -0.038
(T - T0) ± 10%
-60
-80
T0 = 25 °C
-100
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
°C
AI02124
Figure 12. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
13/25
M48T35AY, M48T35AV
V
Noise And Negative Going Transients
Figure 13. Supply Voltage Protection
CC
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
can be reduced if capacitors are used to store en-
ergy which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A bypass ca-
pacitor value of 0.1µF (as shown in Figure 13) is
recommended in order to provide the needed fil-
tering.
V
CC
V
CC
0.1µF
DEVICE
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V
that drive it to values
CC
V
SS
below V by as much as one volt. These negative
SS
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to con-
AI02169
nect a schottky diode from V
to V
(cathode
CC
SS
connected to V , anode to V ). Schottky diode
CC
SS
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
14/25
M48T35AY, M48T35AV
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 6. Absolute Maximum Ratings
Symbol
Parameter
Value
0 to 70
Unit
°C
Grade 1
Grade 6
T
A
Ambient Operating Temperature
–40 to 85
–40 to 85
°C
T
Storage Temperature (V Off, Oscillator Off)
°C
STG
CC
(1,2,3)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
260
°C
T
SLD
M48T35AY
M48T35AV
M48T35AY
M48T35AV
–0.3 to 7
–0.3 to 4.6
–0.3 to 7
–0.3 to 4.6
20
V
V
V
IO
V
V
Supply Voltage
CC
V
I
Output Current
mA
W
O
P
Power Dissipation
1
D
Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer
than 30 seconds).
2. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds).
3. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
15/25
M48T35AY, M48T35AV
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 7. Operating and AC Measurement Conditions
Parameter
M48T35AY
4.5 to 5.5
0 to 70
–40 to 85
100
M48T35AV
3.0 to 3.6
0 to 70
–40 to 85
50
Unit
V
Supply Voltage (V
)
CC
Grade 1
Grade 6
°C
Ambient Operating Temperature (T )
A
Load Capacitance (C )
pF
ns
V
L
Input Rise and Fall Times
≤ 5
≤ 5
Input Pulse Voltages
0 to 3
0 to 3
Input and Output Timing Ref. Voltages
1.5
1.5
V
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 14. AC Measurement Load Circuit
645Ω
DEVICE
UNDER
TEST
C
= 100pF
(or 5pF)
1.75V
L
C
includes JIG capacitance
L
AI02586
Note: 50pF for M48T35AV.
Table 8. Capacitance
Symbol
(1,2)
Min
Max
10
Unit
Parameter
C
Input Capacitance
Output Capacitance
pF
pF
IN
(3)
10
C
OUT
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
16/25
M48T35AY, M48T35AV
Table 9. DC Characteristics
M48T35AY
–70
M48T35AV
(1)
Symbol
Parameter
–100
Unit
Test Condition
Min
Max
Min
Max
I
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
Supply Current
±1
±1
50
±1
µA
µA
LI
IN
CC
(2)
0V ≤ V
≤ V
CC
±1
30
I
OUT
LO
I
Outputs open
mA
CC
Supply Current (Standby)
TTL
I
E = V
3
2
mA
mA
CC1
IH
Supply Current (Standby)
CMOS
I
E = V – 0.2V
3
2
CC2
CC
(3)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.3
2.2
0.8
–0.3
2.2
0.8
V
V
V
V
V
IL
V
V
+ 0.3
V
+ 0.3
IH
CC
CC
V
V
I
= 2.1mA
= –1mA
OH
0.4
0.4
OL
OL
I
2.4
2.4
OH
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. Outputs deselected.
3. Negative spikes of –1V allowed for up to 10ns once per Cycle.
17/25
M48T35AY, M48T35AV
Figure 15. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tFB
tRB
tPD
tDR
trec
RECOGNIZED
RECOGNIZED
INPUTS
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01168C
Table 10. Power Down/Up AC Characteristics
(1)
Symbol
Min
0
Max
Unit
Parameter
t
E or W at V before Power Down
µs
µs
PD
IH
(2)
V
V
(max) to V
(min) V Fall Time
PFD CC
300
t
F
PFD
M48T35AY
M48T35AV
10
150
10
1
µs
µs
µs
µs
(3)
(min) to V
(min) to V
V
Fall Time
t
FB
PFD
PFD
SS CC
t
R
V
V
V
(max) V Rise Time
PFD CC
t
to V
(min) V Rise Time
PFD CC
RB
(4)
SS
(max) to Inputs Recognized
40
200
ms
t
PFD
rec
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. V
(max) to V
(min) fall time of less than t may result in deselection/write protection not occurring until 200µs after V pass-
PFD F CC
PFD
es V
(min).
PFD
3. V
(min) to V fall time of less than t may cause corruption of RAM data.
PFD
SS FB
4. t (min) = 20ms for industrial temperature Grade 6 device.
rec
Table 11. Power Down/Up Trip Points DC Characteristics
(1,2)
Symbol
Min
Typ
Max
Unit
Parameter
M48T35AY
M48T35AV
M48T35AY
M48T35AV
4.2
2.7
4.35
2.9
4.5
3.0
V
V
V
V
V
Power-fail Deselect Voltage
PFD
3.0
V
Battery Back-up Switchover Voltage
Expected Data Retention Time
SO
V
–100mV
PFD
(3)
Grade 1
Grade 6
YEARS
YEARS
10
(5)
t
DR
(4)
10
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. All voltages referenced to V
.
SS
3. CAPHAT and M4T32-BR12SH1 SNAPHAT only, M4T28-BR12SH1 SNAPHAT top t = 7 years (typ).
DR
4. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - Grade 6 device).
5. At 25°C, V = 0V.
CC
18/25
M48T35AY, M48T35AV
PACKAGE MECHANICAL INFORMATION
Figure 16. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Outline
A2
A
L
A1
e1
C
B1
B
eA
e3
D
N
1
E
PCDIP
Note: Drawing is not to scale.
Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.65
0.76
8.89
0.53
1.78
0.31
39.88
18.34
2.79
36.32
16.00
3.81
Typ
Max
A
A1
A2
B
8.89
0.38
8.38
0.38
1.14
0.20
39.37
17.83
2.29
29.72
15.24
3.05
28
0.350
0.015
0.330
0.015
0.045
0.008
1.550
0.702
0.090
1.170
0.600
0.120
28
0.380
0.030
0.350
0.021
0.070
0.012
1.570
0.722
0.110
1.430
0.630
0.150
B1
C
D
E
e1
e3
eA
L
N
19/25
M48T35AY, M48T35AV
Figure 17. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 13. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Pack. Mech. Data
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
20/25
M48T35AY, M48T35AV
Figure 18. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
21/25
M48T35AY, M48T35AV
Figure 19. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
Typ
Max
A
A1
A2
A3
B
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
22/25
M48T35AY, M48T35AV
PART NUMBERING
Table 16. Ordering Information Scheme
Example:
M48T
35AY
–70
MH
1
E
Device Type
M48T
Supply Voltage and Write Protect Voltage
35AY = V = 4.5 to 5.5V; V
= 4.2 to 4.5V
= 2.7 to 3.0V
CC
PFD
PFD
35AV = V = 3.0 to 3.6V; V
CC
Speed
–70 = 70ns (35AY)
–10 = 100ns (35AV)
Package
PC = PCDIP28
(1)
MH = SOH28
Temperature Range
1 = 0 to 70°C
(2)
6 = –40 to 85°C
Shipping Method
For SOH28:
blank = Tubes (Not for New Design - Use E)
®
E = Lead-free Package (ECO PACK ), Tubes
®
F = Lead-free Package (ECO PACK ), Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
For PCDIP28:
blank = Tubes
®
Note: 1. The SOIC package (SOH28) requires the SNAPHAT battery package which is ordered separately under the part number “M4TXX-
BR12SH” in plastic tube or “M4TXX-BR12SHTR” in Tape & Reel form (see Table 17).
2. Available in SOIC package only.
Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell bat-
tery.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
Table 17. SNAPHAT Battery Table
Part Number
M4T28-BR12SH
M4T32-BR12SH
Description
Lithium Battery (48mAh) SNAPHAT
Lithium Battery (120mAh) SNAPHAT
Package
SH
SH
23/25
M48T35AY, M48T35AV
REVISION HISTORY
Table 18. Document Revision History
Date
Rev. #
1.0
Revision Details
November 1999
21-Apr-00
First Issue
From Preliminary Data to Data Sheet
change (Table 10)
2.0
t
29-May-00
2.1
FB
Reformatted; temp./voltage info. added to tables (Table 8, 9, 3, 4, 10, 11); add Century
Bit text
20-Jul-01
3.0
20-May-02
31-Mar-03
01-Apr-04
3.1
4.0
5.0
Modify reflow time and temperature footnotes (Table 6)
v2.2 template applied; data retention condition updated (Table 11)
Reformatted; updated with Lead-free package information (Table 6, 16)
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M48T35AY, M48T35AV
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