M48T212V-70MH1TR [STMICROELECTRONICS]
5V/3.3V TIMEKEEPER[ CONTROLLER; 5V / 3.3V TIMEKEEPER [控制器
| 型号： | M48T212V-70MH1TR |
| 厂家： | 
ST |
| 描述： | 5V/3.3V TIMEKEEPER[ CONTROLLER |
| 文件： | 总23页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T212Y
M48T212V
5V/3.3V TIMEKEEPER CONTROLLER
■ CONVERTS LOW POWER SRAM into
SNAPHAT (SH)
Battery
NVRAMs
■ YEAR 2000 COMPLIANT (4-Digit Year)
■ BATTERY LOW FLAG
■ INTEGRATED REAL TIME CLOCK,
POWER-FAIL CONTROL CIRCUIT, BATTERY
and CRYSTAL
■ AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
44
■ WATCHDOG TIMER
1
■ CHOICE of WRITE PROTECT VOLTAGES
(V
= Power-fail Deselect Voltage):
PFD
SOH44 (MH)
– M48T212Y: 4.2V ≤ V
– M48T212V: 2.7V ≤ V
≤ 4.5V
≤ 3.0V
PFD
PFD
Figure 1. Logic Diagram
■ MICROPROCESSOR POWER-ON RESET
■ PROGRAMMABLE ALARM OUTPUT ACTIVE
in the BATTERY BACKED-UP MODE
V
V
CCSW
■ PACKAGING INCLUDES a44-LEAD SOIC and
CC
SNAPHAT TOP (to be Ordered Separately)
4
8
DESCRIPTION
The M48T212Y/V are self-contained devices that
include a real time clock (RTC), programmable
alarms, a watchdog timer, and two external chip
enable outputs which provide control of up to four
(two in parallel) external low-power static RAMs.
Access to all TIMEKEEPER functions and the
external RAM is the same as conventional byte-
wide SRAM. The 16 TIMEKEEPER Registers offer
Century, Year, Month, Date, Day, Hour, Minute,
Second, Calibration, Alarm, Watchdog, and Flags.
Externally attached static RAMs are controlled by
A0-A3
DQ0-DQ7
A
E
IRQ/FT
RST
EX
M48T212Y
M48T212V
W
E1
E2
CON
CON
G
WDI
RSTIN1
RSTIN2
the M48T212Y/V via the E1
nals (see Table 4).
and E2
sig-
CON
CON
V
OUT
The 44 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.
V
SS
AI03019
April 2000
1/23
M48T212Y, M48T212V
Figure 2. SOIC Connections
Table 1. Signal Names
A0-A3
DQ0-DQ7
RSTIN1
RSTIN2
RST
WDI
A
Address Inputs
RSTIN1
RSTIN2
RST
NC
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
V
V
CC
Data Inputs/Outputs
Reset 1 Input
2
OUT
3
CCSW
Reset 2 Input
4
IRQ/FT
EX
NC
NC
NC
NC
NC
G
NC
5
Reset Output (Open Drain)
Watchdog Input
NC
6
NC
7
Bank Select Input
NC
8
A
9
E
Chip Enable Input
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
EX
External Chip Enable Input
Output Enable Input
Write Enable Input
M48T212Y
M48T212V
NC
G
NC
W
A3
NC
NC
E
W
A2
E1
RAM Chip Enable 1 Output
RAM Chip Enable 2 Output
Int/Freq Test Output (Open Drain)
CON
A1
E2
CON
A0
E1
CON
WDI
DQ7
DQ6
DQ5
DQ4
DQ3
NC
IRQ/FT
Vccsw
E2
CON
DQ0
V
Switch Output
CC
V
OUT
Supply Voltage Output
Supply Voltage
DQ1
DQ2
V
CC
V
SS
V
Ground
SS
AI03020
NC
Not Connected internally
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is keyed
to prevent reverse insertion.
adjusted for months with less than 31 days and
corrects for leap years. The internal watchdog tim-
er provides programmable alarm windows.
The nine clock bytes (Fh - 9h and 1h) are not the
actual clock counters, they are memory locations
TM
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 44 lead SOIC, the bat-
tery/crystal package (i.e. SNAPHAT) part number
is ”M4TXX-BR12SH” (see Table 15).
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
consisting of BiPORT
read/write memory cells
within the static RAM array. Clock circuitry up-
dates the clock bytes with current information once
per second. The information can be accessed by
the user in the same manner as any other location
in the static memory array.
Byte 8h is the clock control register. This byte con-
trols user access to the clock information and also
stores the clock calibration setting. Byte 7h con-
tains the watchdog timer setting. The watchdog
timer can generate either a reset or an interrupt,
depending on the state of the Watchdog Steering
bit (WDS). Bytes 6h-2h include bits that, when pro-
grammed, provide for clock alarm functionality.
Automatic backup and write protection for an ex-
ternal SRAM is provided through V
, E1
OUT
CON
and E2
pins. (Users are urged to insure that
CON
voltage specifications, for both the controller chip
and external SRAM chosen, are similar). The
SNAPHAT containing the lithium energy source
used to permanently power the real time clock is
also used to retain RAM data in the absence of
Alarms are activated when the register content
matches the month, date, hours, minutes, and
seconds of the clock registers. Byte 1h contains
century information. Byte 0h contains additional
flag information pertaining to the watchdog timer,
alarm and battery status.
V
power through the V
pin.
CC
OUT
The chip enable outputs to RAM (E1
and
CON
E2
) are controlled during power transients to
CON
prevent data corruption. The date is automatically
2/23
M48T212Y, M48T212V
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
°C
Storage Temperature (V Off, Oscillator Off) SNAPHAT
–40 to 85
–55 to 125
CC
T
°C
STG
SOIC
Lead Solder Temperature for 10 sec
Input or Output Voltages
(2)
260
°C
T
SLD
V
–0.3 to V
+0.3
V
IO
CC
Supply Voltage
M48T212Y
M48T212V
–0.3 to 7
–0.3 to 4.6
V
V
CC
I
Output Current
20
1
mA
W
O
P
Power Dissipation
D
Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
(1)
Table 3. Operating Modes
V
Mode
Deselect
Write
E
G
X
X
W
DQ7-DQ0
Power
Standby
Active
CC
V
X
High-Z
IH
4.5V to 5.5V
or
3.0V to 3.6V
V
V
V
V
D
IL
IL
IL
IL
IH
IH
IN
V
V
V
D
OUT
Read
Active
IL
V
Read
High-Z
High-Z
High-Z
Active
IH
(2)
Deselect
Deselect
X
X
X
CMOS Standby
Battery Back-Up
V
to V
(min)
PFD
SO
(2)
X
X
X
≤ V
SO
Note: 1. X = V or V
.
IL
IH
2. V = Battery Back-up Switchover Voltage. (See Tables 7A and 7B for details).
SO
(1)
Table 4. Truth Table for SRAM Bank Select
Mode
V
EX
Low
Low
High
A
Low
High
X
E1
E2
CON
Power
Active
CC
CON
Low
High
4.5V to 5.5V
or
3.0V to 3.6V
Select
High
High
Low
Active
Deselect
Deselect
High
Standby
(2)
X
X
X
X
High
High
High
High
CMOS Standby
Battery Back-Up
V
to V
(min)
PFD
SO
(2)
Deselect
≤ V
SO
Note: 1. X = V or V
.
IL
IH
2. V = Battery Back-up Switchover Voltage. (See Tables 7A and 7B for details).
SO
3/23
M48T212Y, M48T212V
Figure 3. Hardware Hookup
A0-A18
MOTOROLA
MTD20P06HDL
5V/3.3V
A0-A3
V
CCSW
V
CC
A0-Axx
0.1µF
1N5817 (1)
V
V
OUT
CC
A
E
0.1µF
CMOS
SRAM
E
EX
W
E1
CON
Note 2
G
E2
CON
WDI
RSTIN1
RSTIN2
A0-Axx
RST
V
CC
DQ0-DQ7
IRQ/FT
CMOS
SRAM
V
E
SS
M48T212Y/V
AI03046
Note: 1. See description in Power Supply Decoupling and Undershoot Protection.
2. Traces connecting E1 and E2 to external SRAM should be as short as possible.
CON
CON
Figure 4. AC Testing Load Circuit
Table 5. AC Measurement Conditions
Input Rise and Fall Times
≤ 5ns
0 to 3V
1.5V
Input Pulse Voltages
645Ω
DEVICE
UNDER
TEST
Input and Output Timing Ref. Voltages
Note that Output Hi-Z is defined as the point where data
is no longer driven.
C
C
= 100pF or 5pF (1)
= 30 pF (2)
1.75V
L
L
C
includes JIG capacitance
L
AI03239
Note: 1. DQ0-DQ7
2. E1 and E2
CON
CON
4/23
M48T212Y, M48T212V
(1)
Table 6. Capacitance
A
(T = 25 °C, f = 1 MHz)
Symbol
Parameter
Input Capacitance
Test Condition
Min
Max
Unit
C
V
= 0V
= 0V
10
pF
IN
IN
(2)
V
Input/Output Capacitance
10
pF
C
OUT
OUT
Note: 1. Sampled only, not 100% tested.
2. Outputs deselected.
Table 7A. DC Characteristics for M48T212V
(T = 0 to 70°C; V = 3V to 3.6V)
A
CC
Symbol
Parameter
Test Condition
0V ≤ V ≤ V
Min
Typ
Max
Unit
(1,2)
Input Leakage Current
Output Leakage Current
±1
±1
µA
µA
I
LI
IN
CC
(1)
0V ≤ V
≤ V
CC
I
OUT
LO
I
Supply Current
Outputs open
4
10
3
mA
mA
mA
nA
nA
V
CC
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Battery Current OSC ON
Battery Current OSC OFF
Input Low Voltage
CC1
IH
I
E = V –0.2
2
CC2
CC
575
800
100
0.8
I
BAT
V
V
–0.3
2.0
IL
V
+ 0.3
CC
Input High Voltage
V
IH
Output Low Voltage
I
= 2.1mA
= 10mA
0.4
0.4
V
OL
V
OL
(3)
I
V
V
V
OL
Output Low Voltage (open drain)
Output High Voltage
V
I
= –1.0mA
= –1.0µA
2.4
2.0
OH
OH
(4)
(5)
V
Battery Back-up
Current (Active)
I
OUT2
3.6
V
I
OH
OHB
V
OUT
V
> V –0.3
70
100
3.0
mA
µA
V
OUT1 CC
OUT1
I
V
OUT
Current (Battery Back-up)
V
> V
–0.3
BAT
OUT2
OUT2
V
Power-fail Deselect Voltage
2.7
2.9
PFD
V
V
–100mV
PFD
Battery Back-up Switchover Voltage
Battery Voltage
V
SO
V
3.0
V
BAT
Note: 1. Outputs deselected.
2. RSTIN1 and RSTIN2 internally pulled-up to V through 100KΩ resistor. WDI internally pulled-down to V through 100KΩ resistor.
CC
SS
3. For IRQ/FT & RST pins (Open Drain).
4. Conditioned outputs (E1 - E2 ) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage cur-
CON
CON
rents will reduce battery life.
5. External SRAM must match TIMEKEEPER Controller chip V specification.
CC
5/23
M48T212Y, M48T212V
Table 7B. DC Characteristics for M48T212Y
(T = 0 to 70°C; V = 4.5V to 5.5V)
A
CC
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
(1,2)
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
±1
µA
I
IN
CC
LI
(1)
0V ≤ V
≤ V
CC
±1
µA
I
OUT
LO
I
Supply Current
Outputs open
8
15
5
mA
mA
mA
nA
nA
V
CC
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Battery Current OSC ON
Battery Current OSC OFF
Input Low Voltage
CC1
IH
I
E = V –0.2
3
CC2
CC
575
800
100
0.8
I
BAT
V
–0.3
2.2
IL
V
V
+ 0.3
CC
Input High Voltage
V
IH
I
= 2.1mA
= 10mA
OL
Output Low Voltage
0.4
0.4
V
OL
V
OL
(3)
I
V
V
V
Output Low Voltage (open drain)
Output High Voltage
V
I
= –1.0mA
OH
2.4
2.0
OH
(4)
(5)
V
Battery Back-up
Current (Active)
I = –1.0µA
OUT2
3.6
V
OH
OHB
V
V
V
> V –0.3
100
100
4.5
mA
µA
V
I
OUT
OUT1
CC
OUT1
I
Current (Battery Back-up)
V
> V
–0.3
BAT
OUT2
OUT
OUT2
V
Power-fail Deselect Voltage
4.2
4.35
3.0
PFD
V
Battery Back-up Switchover Voltage
Battery Voltage
V
SO
V
3.0
V
BAT
Note: 1. Outputs deselected.
2. RSTIN1 and RSTIN2 internally pulled-up to V through 100KΩ resistor. WDI internally pulled-down to V through 100KΩ resistor.
CC
SS
3. For IRQ/FT & RST pins (Open Drain).
4. Conditioned outputs (E1 - E2 ) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage cur-
CON
CON
rents will reduce battery life.
5. External SRAM must match TIMEKEEPER Controller chip V specification.
CC
The M48T212Y/V also has its own Power-Fail De-
tect circuit. This control circuitry constantly moni-
tors the supply voltage for an out of tolerance
Address Decoding
The M48T212Y/V accommodates 4 address lines
(A3-A0) which allow access to the sixteen bytes of
the TIMEKEEPER clock registers. All TIMEKEEP-
ER registers reside in the controller chip itself. All
TIMEKEEPER registers are accessed by enabling
E (Chip Enable).
condition. When V is out of tolerance, the circuit
CC
write protects the TIMEKEEPER register data and
external SRAM, providing data security in the
midst of unpredictable system operation. As V
CC
falls, the control circuitry automatically switches to
the battery, maintaining data and clock operation
until valid power is restored.
6/23
M48T212Y, M48T212V
Figure 5. Power Down/Up AC Waveform
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tFB
tRB
tREC
INPUTS
VALID
DON’T CARE
VALID
VALID
HIGH-Z
OUTPUTS
VALID
RST
V
CCSW
AI02638
Table 8. Power Down/Up AC Characteristics
(T = 0 to 70°C)
A
Symbol
Parameter
Min
Max
Unit
V
(max) to V
(min) V Fall Time
300
µs
t
PFD
PFD
PFD
CC
F
M48T212Y
M48T212V
10
150
10
40
1
µs
µs
µs
ms
µs
t
FB
V
(min) to V
(min) to V
V
Fall Time
SS CC
t
V
V
V
(max) V
Rise Time
CC
R
PFD
PFD
PFD
t
(max) to RST High
to V (min) V Rise Time
200
REC
t
RB
SS
PFD
CC
7/23
M48T212Y, M48T212V
Figure 6. Chip Enable Control and Bank Select Timing
EX
tEXPD
tAPD
A
tEXPD
E1
CON
E2
CON
AI02639
Table 9. Chip Enable Control and Bank Select Characteristics
(T = 0 to 70°C)
A
M48T212Y
-70
M48T212V
-85
Symbol
Parameter
Unit
Min
Max
Min
Max
t
EX to E1
or E2
(Low or High)
10
10
15
15
ns
ns
EXPD
CON
CON
t
A to E1
or E2
(Low or High)
APD
CON
CON
8/23
M48T212Y, M48T212V
READ MODE
viding that the E and G access times are also sat-
isfied.If they are not, then data access must be
measured from the latter occurring signal (E or G)
The M48T212Y/V executes a read cycle whenev-
er W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the address
inputs (A3-A0) defines which one of the on-chip
TIMEKEEPER registers is to be accessed. When
the address presented to the M48T212Y/V is in
the range of 0h-Fh, one of the on-board TIME-
KEEPER registers is accessed and valid data will
be available to the eight data output drivers within
and the limiting parameter is either t
GLQV
for E or
ELQV
t
for G rather than the address access time.
When EX input is low, an external SRAM location
will be selected.
Note: Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten-
tion.
t
after the address input signal is stable, pro-
AVQV
Figure 7. Read Cycle Timing: RTC Control Signals
READ
tAVAV
READ
tAVAV
WRITE
tAVAV
ADDRESS
tELQV
tELQX
tAVQV
tAVWL
tWHAX
E
tGLQV
G
tWLWH
W
tGLQX
tAXQX
tGHQZ
DATA OUT
VALID
DATA OUT
VALID
DATA IN
VALID
DQ7-DQ0
AI02640
Table 10. Read Mode Characteristics
(T = 0 to 70°C)
A
M48T212Y
-70
M48T212V
-85
Symbol
Parameter
Unit
Min
Max
Min
Max
t
Read Cycle Time
70
85
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Output Valid
70
70
25
85
85
35
AVQV
t
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
ELQV
GLQV
t
(1)
(1)
(1)
(1)
5
0
5
0
t
ELQX
GLQX
EHQZ
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
ns
ns
ns
ns
t
t
20
20
25
25
Output Enable High to Output Hi-Z
Address Transition to Output Transition
t
GHQZ
t
5
5
AXQX
Note: 1. C = 5pF
L
9/23
M48T212Y, M48T212V
WRITE MODE
The M48T212Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are in a low
state after the address inputs are stable. The start
of a write is referenced from the latter occurring
falling edge of W or E. A write is terminated by the
earlier rising edge of W or E. The addresses must
be heldvalid throughout the cycle. E or W must re-
G should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G alow on W will
disable the outputs t
after W falls.
WLQZ
When E is low during the write, one of the on-
board TIMEKEEPER registers will be selected and
data will be written into the device. When EX is low
(and E is high) an external SRAM location is se-
lected.
Note: Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten-
tion.
turn high for a minimum of t
from Chip Enable
EHAX
or t
from Write Enable prior to the initiation of
WHAX
another read or write cycle. Data-in must be valid
t
t
prior to the end of write and remain valid for
afterward.
DVWH
WHDX
Figure 8. Write Cycle Timing: RTC Control Signals
WRITE
tAVAV
WRITE
tAVAV
READ
tAVAV
ADDRESS
tAVEH
tELEH
tAVWH
tEHAX tWHAX
tAVEL
tAVQV
E
tGLQV
G
tEHDX
tAVWL
tWLWH
tWHQX
tWLQZ
W
tEHQZ
tDVEH tDVWH
tWHDX
DATA OUT
VALID
DATA IN
VALID
DATA IN
VALID
DATA OUT
VALID
DQ0-DQ7
AI02641
10/23
M48T212Y, M48T212V
Table 11. Write Mode AC Characteristics
(T = 0 to 70°C)
A
M48T212Y
-70
M48T212V
Symbol
Parameter
-85
Unit
Min
Max
Min
85
0
Max
t
Write Cycle Time
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
AVWL
t
0
0
AVEL
t
t
t
t
45
50
0
55
60
0
WLWH
t
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
ELEH
WHAX
t
0
0
EHAX
DVWH
25
25
0
30
30
0
t
DVEH
WHDX
Write Enable High to Input Transition
Chip Enable High to Input Transition
t
0
0
EHDX
(1,2)
Write Enable Low to Output High-Z
Address Valid to Write Enable High
Address Valid to Chip Enable High
Write Enable High to Output Transition
20
25
ns
ns
ns
ns
t
WLQZ
t
55
55
5
65
65
5
AVWH
t
AVEH
(1,2)
t
WHQX
Note: 1. C = 5pF.
L
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
DATA RETENTION MODE
With valid V applied, the M48T212Y/V can be
accessed as described above with read or write
cycles. Should the supply voltage decay, the
M48T212Y/V will automatically deselect, write
protecting itself (and any external SRAM) when
pedance. The V
pin is capable of supplying
OUT
100µA of current to the attached memory with less
CC
than 0.3V drop under this condition. On power up,
when V returns to a nominal value, write protec-
CC
tion continues for 200ms (max) by inhibiting
E1
or E2
.
CON
CON
V
falls between V
(max) and V (min).
The RST signal also remains active during this
time (see Figure 5).
CC
PFD
PFD
This is accomplished by internally inhibiting ac-
cess to the clock registers via the E signal. At this
time, the Reset pin (RST) is driven active and will
Note: Most low power SRAMs on the market to-
day can be used with the M48T212Y/V TIME-
KEEPER Controller. There are, however some
criteria which should be used in making the final
choice of an SRAM to use. The SRAM must be de-
signed in a way where the chip enable input dis-
ables all other inputs to the SRAM. This allows
inputs to the M48T212Y/V and SRAMs to be Don’t
remain active until V returns to nominal levels.
CC
External RAM access is inhibited in a similar man-
ner by forcing E1
This level is within 0.2 volts of the V
and E2
to a high level.
CON
CON
. E1
BAT CON
and E2
will remain at this level as long as V
CON
CC
remains at an out-of tolerance condition.
Care once V falls below V
(min). The SRAM
CC
PFD
When V falls below the level of the battery
CC
should also guarantee data retention down to
= 2.0V. The chip enable access time must be
(V
), power input is switched from the V pin
BAT
CC
V
CC
to the SNAPHAT battery and the clock registers
and external SRAM are maintained from the at-
tached battery supply. All outputs become high im-
sufficient to meet the system needs with the chip
enable output propagation delays included.
11/23
M48T212Y, M48T212V
Figure 9. Alarm Interrupt Reset Waveforms
A0-A3
1h
ADDRESS 0h
Fh
ACTIVE FLAG BIT
IRQ/FT
HIGH-Z
AI03021
Table 12. Alarm Repeat Modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
Once per Second
Once per Minute
Once per Hour
Once per Day
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Once per Month
Once per Year
If the SRAM includes a second chip enable pin
(E2), this pin should be tied to V
The data retention current value of the SRAMs can
then be added to the I value of the M48T212Y/
V to determine the total current requirements for
data retention. The available battery capacity for
the SNAPHAT of your choice can then be divided
by this current to determine the amount of data re-
tention available (see Table 15).
.
OUT
BAT
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use.
For afurther more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
12/23
M48T212Y, M48T212V
Figure 10. Back-Up Mode Alarm Waveforms
tREC
V
CC
V
V
(max)
(min)
PFD
PFD
AFE bit/ABE bit
AF bit in Flags Register
IRQ/FT
HIGH-Z
HIGH-Z
AI03622
TIMEKEEPER REGISTERS
current at the moment the halt command was is-
sued.
The M48T212Y/V offers 16 internal registers
which contain TIMEKEEPER, Alarm, Watchdog,
Flag, and Control data. These registers are mem-
ory locations which contain external (user accessi-
ble) and internal copies of the data (usually
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating occurs 1 second after the
READ bit is reset to a ‘0’.
TM
referred to as BiPORT TIMEKEEPER cells).
Setting the Clock
The external copies are independent of internal
functions except that they are updated periodically
by the simultaneous transfer of the incremented
internal copy. TIMEKEEPER and Alarm Registers
store data in BCD. Control, Watchdog and Flags
Registers store data in Binary Format.
Bit D7 of the Control Register (8h) is the WRITE
bit. Setting the WRITE bit to a ‘1’, like the READ
bit, halts updates to the TIMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (see
Table 13).
Resetting the WRITE bit to a ‘0’ then transfers the
values of all time registers (Fh-9h, 1h) to the actual
TIMEKEEPER counters and allows normal opera-
tion to resume. After the WRITE bit is reset, the
next clock update will occur one second later.
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data reg-
isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
Note: Upon power-up following a power failure,
the READ bit will automatically be set to a ‘1’. This
will prevent the clock from updating the TIME-
KEEPER registers, and will allow the user to read
the exact time of the power-down event.
Updating is halted when a ‘1’ is written to the
READ bit, D6 in the Control Register (8h). As long
as a ‘1’ remains in that position, updating is halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and time that were
Resetting the READ Bitto a ‘0’ will allow the clock
to update these registers with the current time.
The WRITE Bit will be reset to a ‘0’ upon power-
up.
13/23
M48T212Y, M48T212V
Stopping and Starting the Oscillator
WATCHDOG TIMER
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is located at Bit D7 within the Seconds Register
(9h). Setting it to a ‘1’ stops the oscillator. Whenre-
set to a ‘0’, the M48T212Y/V oscillator starts within
one second.
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 7h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolu-
tion, where 00=1/16 second, 01=1/4 second, 10=1
second, and 11=4 seconds. The amount of time-
out is then determined to be the multiplication of
the five bit multiplier value with the resolution. (For
example: writing 00001110 in the Watchdog Reg-
ister = 3*1 or 3 seconds).
Note: It is not necessary to set the WRITE bit
when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).
SETTING ALARM CLOCK
Note: Accuracy of timer is within ± the selected
Address locations 6h-2h contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second or repeat every year, month,
day, hour, minute, or second. It can also be pro-
grammed to go off while the M48T212Y/V is in the
battery back-up to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 12 shows the possible config-
urations. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
resolution.
If the processor does not reset the timer within the
specified period, the M48T212Y/V sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset. WDF is reset by
reading the Flags Register (Address 0h).
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a ‘0’, the watchdog will activate the IRQ/FT pin
when timed-out. When WDS is set to a ‘1’, the
watchdog will output a negative pulse on the RST
pin for 40 to 200 ms. The Watchdog register and
the FT bit will reset to a ‘0’ at the end of a Watch-
dog time-out when the WDS bit is set to a ‘1’.
Note: User must transition address (or toggle chip
enable) to see Flag bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set.
The watchdog timer can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or
If AFE (Alarm Flag Enable) is also set, the alarm
condition activates the IRQ/FT pin. To disable
alarm, write ’0’ to the Alarm Date registers and
RPT1-4. The IRQ/FT output is cleared by a read to
the Flags register as shown in Figure 9. A subse-
quent read of the Flags register will reset the
Alarm Flag (D6; Register 0h).
2. the microprocessor can perform a write of the
Watchdog Register.
The time-out period then starts over. The WDI pin
should be tied to V if not used. The watchdog
SS
will be reset on each transition (edge) seen by the
WDI pin. In the order to perform a software reset
of the watchdog timer, the original time-out period
can be written into the Watchdog Register, effec-
tively restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT pin. This will also dis-
able the watchdog function until it is again pro-
grammed correctly. A read of the Flags Register
will reset the Watchdog Flag (Bit D7; Register 0h).
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied.
The IRQ/FT pin can also be activated in the bat-
tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T212Y/V was in the deselect mode
during power-up. Figure 10 illustrates the back-up
mode alarm timing.
14/23
M48T212Y, M48T212V
Table 13. TIMEKEEPER Register Map
Address
Function/Range
BCD Format
D7
D6
D5
D4
10M
0
D3
D2
D1
D0
Fh
Eh
Dh
Ch
Bh
Ah
9h
8h
7h
6h
5h
4h
3h
2h
1h
0h
10 Years
Year
Year
Month
Date
00-99
01-12
01-31
01-7
0
0
0
0
0
Month
10 Date
Date: Day of Month
Day of Week
0
FT
0
0
0
Day
0
10 Hours
Hours (24 Hour Format)
Minutes
Hour
00-23
00-59
00-59
0
10 Minutes
10 Seconds
S
Min
ST
Seconds
Sec
W
R
BMB4
0
Calibration
Control
Watchdog
A Month
A Date
A Hour
A Min
A Sec
Century
Flag
WDS
AFE
RPT4
RPT3
RPT2
RPT1
BMB3
BMB2
BMB1
BMB0
RB1
RB0
ABE
Al 10M
Alarm Month
Alarm Date
01-12
01-31
00-23
00-59
00-59
00-99
RPT5
0
AI 10 Date
AI 10 Hour
Alarm Hour
Alarm 10 Minutes
Alarm 10 Seconds
1000 Year
Alarm Minutes
Alarm Seconds
100 Year
WDF
AF
Y
BL
Y
Y
Y
Y
Keys: S = Sign Bit
FT = Frequency Test Bit
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
R = Read Bit
W = Write Bit
ST = Stop Bit
0 = Must be set to zero
BL = Battery Low Flag
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog flag
AF = Alarm flag
BMB0-BMB4 = Watchdog Multiplier Bits
Y = ‘1’ or ‘0’
V
SWITCH OUTPUT
The RST pin is an open drain output and an appro-
CC
priate pull-up resistor to V should be chosen to
CC
Vccsw output goes low when V
switches to
OUT
control rise time.
V
turning on a customer supplied P-Channel
CC
MOSFET (see Figure 3). The Motorola
Note: If the RST output is fed back into either of
the RSTIN inputs (for a microprocessor with a bi-
directional reset) then a 1kΩ (max) pull-up resistor
is recommended.
MTD20P06HDL is recommended. This MOSFET
in turn connects V
the current requirement is greater than I
to a separate supply when
OUT
(see
OUT1
Tables 7A and 7B). This output may also be used
simply to indicate the status of the internal battery
switchover comparator, which controls the source
Reset Inputs (RSTIN1 & RSTIN2)
The M48T212Y/V provides two independent in-
puts which can generate an output reset. The du-
ration and function of these resets is identical to a
reset generated by a power cycle. Table 14 and
Figure 12 illustrate the AC reset characteristics of
this function. During the time RST is enabled
(V or battery) of the V
output.
CC
OUT
POWER-ON RESET
The M48T212Y/V continuously monitors V
.
CC
When V
falls to the power fail detect trip point,
CC
(t
& t
), the Reset Inputs are ignored.
R1HRH
R2HRH
the RST pulls low (open drain) and remains low on
Note: RSTIN1 and RSTIN2 are each internally
pulled up to V through a 100KΩ resistor.
power-up for 40 to 200ms after V passes V
.
PFD
CC
CC
15/23
M48T212Y, M48T212V
Figure 11. Calibration Waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
Calibrating the Clock
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
The M48T212Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not to exceed ±35 PPM
(parts per million) oscillator frequency error at
25°C, which equates to about ±1.53 minutes per
month. When the Calibration circuit is properly em-
ployed, accuracy improves to better than +1/–2
PPM at 25°C.
The oscillation rate of crystals changes with tem-
perature. The M48T212Y/V design employs peri-
odic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure 11. The number of times pulses which are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five Calibration bits found in
the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration bits occupy the five lower order
bits (D4-D0) in the Control Register 8h. These bits
can be set to represent any value between 0 and
31 in binary form. Bit D5 is a Sign bit; ‘1’ indicates
positive calibration, ‘0’ indicates negative calibra-
tion. Calibration occurs within a 64 minute cycle.
The first 62 minutes in the cycle may, once per
minute, have one second either shortened by 128
or lengthened by 256 oscillator cycles.
Two methods are available for ascertaining how
much calibration a given M48T212Y/V may re-
quire. The first involves setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference and recording deviation over a fixed
period of time. Calibration values, including the
number of seconds lost or gained in a given peri-
od, can be found in Application Note AN934:
TIMEKEEPER Calibration.
This allows the designer to give the end user the
ability to calibrate the clock as the environment re-
quires, even if the final product is packaged in a
non-user serviceable enclosure. The designer
could provide a simple utility that accesses the
Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz, when the
Stop bit (ST, D7 of 9h) is ‘0’,the Frequency Test bit
(FT, D6 of Ch) is ‘1’, the Alarm Flag Enable bit
(AFE, D7 of 6h) is ‘0’, and the Watchdog Steering
bit (WDS, D7 of 7h) is ‘1’ or the Watchdog Register
(7h=0) is reset.
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example,
a
reading of
If a binary ‘1’ is loaded into the register, only the
first 2 minutes in the 64 minute cycle will be modi-
fied; if a binary 6 is loaded, the first 12 will be af-
fected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 PPM of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is running at exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would
512.010124 Hz would indicate a +20 PPM oscilla-
tor frequency error, requiring a –10 (WR001010)
to be loaded into the Calibration Byte for correc-
tion. Note that setting or changing the Calibration
Byte does not affect the Frequency test output fre-
quency.
The IRQ/FT pin is an open drain output which re-
quires a pull-up resistor to V for proper opera-
CC
tion. A 500-10kΩ resistor is recommended in order
to control the rise time. The FT bit is cleared on
power-up.
16/23
M48T212Y, M48T212V
Table 14. Reset AC Characteristics
(T = 0 to 70°C; V = 3V to 3.6V or V = 4.5V to 5.5V)
A
CC
CC
Symbol
Parameter
Min
Max
Unit
(1)
RSTIN1 Low to RSTIN1 High
RSTIN2 Low to RSTIN2 High
RSTIN1 High to RST High
RSTIN2 High to RST High
200
ns
t
t
R1
R2
(2)
100
40
ms
ms
ms
(3)
(3)
200
200
t
t
R1HRH
R2HRH
40
Note: 1. Pulse width less than 50ns will result in no RESET(for noise immunity).
2. Pulse width less than 20ms will result in no RESET (for noise immunity).
3. C = 5pF (see Figure 4).
L
Table 15. SNAPHAT Battery Table
Part Number
Description
Package
M4T28-BR12SH
M4T32-BR12SH
Lithium Battery (48mAh) SNAPHAT
Lithium Battery (120mAh) SNAPHAT
SH
SH
Figure 12. RSTIN1 & RSTIN2 Timing Waveforms
RSTIN1
tR1
RSTIN2
tR2
(1)
RST
tR1HRH
tR2HRH
AI02642
BATTERY LOW WARNING
tery is near end of life. However, data is not com-
promised due to the fact that a nominal Vcc is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT bat-
The M48T212Y/V automatically performs battery
voltage monitoring upon power-up and at factory-
programmed time intervals of approximately 24
hours. The Battery Low (BL) bit, Bit D4 of Flags
Register 0h, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL bit will remain asserted until completion of bat-
tery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery lowis generated during a power-up se-
quence, this indicates that the battery is below ap-
proximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
tery/crystal top should be replaced with V pow-
CC
ering the device to avoid data loss.
Note: this will cause the clock to lose time during
the time interval the battery crystal is removed.
The M48T212Y/V only monitors the battery when
a nominal Vcc is applied to the device. Thus appli-
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial.
Additionally, if a battery low is indicated, data in-
tegrity should be verified upon power-up via a
checksum or other technique.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
17/23
M48T212Y, M48T212V
INITIAL POWER-ON DEFAULTS
Figure 13. Supply Voltage Protection
Upon application of power to the device, the fol-
lowing register bits are set to a ‘0’ state: WDS,
BMB0-BMB4, RB0-RB1, AFE, ABE, W and FT.
(See Table 16)
V
CC
POWER SUPPLY DECOUPLING
AND UNDERSHOOT PROTECTION
V
CC
Note: I transients, including those produced by
CC
output switching, can produce voltage fluctua-
0.1µF
DEVICE
tions, resulting in spikes on the V
bus. These
CC
transients can be reduced if capacitors are used to
store energy, which stabilizes the V bus. The
energy stored in the bypass capacitors will be re-
leased as low going spikes are generated or ener-
gy will be absorbed when overshoots occur.
CC
V
SS
AI02169
A ceramic bypass capacitor value of 0.1µF is rec-
ommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V that drive it to values
CC
V
SS
(cathode connected to V , anode to V ).
CC SS
below V by as much as one volt. These negative
SS
(Schottky diode 1N5817 is recommended for
through hole and MBRS120T3 is recommended
for surface mount).
spikes can cause data corruption in the SRAM
while in battery backup mode.
To protect from these voltage spikes, ST recom-
mends connecting a schottky diode from V
to
CC
Table 16. Default Values
WATCHDOG
Condition
W
R
FT
AFE
ABE
(1)
Register
Initial Power-up
(Battery Attach for SNAPHAT)
0
0
0
0
0
0
(2)
(3)
0
0
0
0
0
0
0
1
0
1
0
0
Subsequent Power-up / RESET
(4)
Power-down
Note: 1. WDS, BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. State of other control bits remains unchanged.
4. Assuming these bits set to ‘1’ prior to power-down.
18/23
M48T212Y, M48T212V
Table 17. Ordering Information Scheme
Example:
M48T212Y
-70 MH
1
TR
Device Type
M48T
Supply Voltage and Write Protect Voltage
212Y = V = 4.5V to 5.5V; V
= 4.2V to 4.5V
= 2.7V to 3.0V
CC
PFD
PFD
212V = V = 3.0V to 3.6V; V
CC
Speed
-70 = 70ns (for M48T212Y)
-85 = 85ns (for M48T212V)
Package
(1)
MH
= SOH44
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The SOIC package (SOH44) requires the battery package (SNAPHAT) which is ordered separately under the part number
“M4Txx-BR12SH1” in plastic tube or ”M4Txx-BR12SH1TR” in Tape & Reel form.
Caution: Do not place the SNAPHAT battery package ”M4Txx-BR12SH1” in conductive foam since will drain the lithium button-cell battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
Table 18. Revision History
Date
Revision Details
October 1999
First Issue
Document Layout changed
Default Values table added (Table 16)
03/01/00
04/21/00
From Preliminary Data to Data Sheet
19/23
M48T212Y, M48T212V
Table 19. SOH44 - 44 lead Plastic Small Outline, SNAPHAT, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.46
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.018
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
0.81
0.032
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
44
44
CP
0.10
0.004
Figure 14. SOH44 - 44 lead Plastic Small Outline, SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Drawing is not to scale.
20/23
M48T212Y, M48T212V
Table 20. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
Figure 15. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Drawing is not to scale.
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M48T212Y, M48T212V
Table 21. M4T32-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
Typ
Max
A
A1
A2
A3
B
0.415
.0335
0.315
0.015
0.022
0.860
.0710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
Figure 16. M4T32-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Drawing is not to scale.
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M48T212Y, M48T212V
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