M40Z300WMH1TR [STMICROELECTRONICS]
NVRAM CONTROLLER for up to EIGHT LPSRAM; NVRAM控制器，多达八个LPSRAM
| 型号： | M40Z300WMH1TR |
| 厂家： | 
ST |
| 描述： | NVRAM CONTROLLER for up to EIGHT LPSRAM |
| 文件： | 总16页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M40Z300
M40Z300W
NVRAM CONTROLLER for up to EIGHT LPSRAM
■ CONVERT LOW POWER SRAMs into
NVRAMs
SNAPHAT (SH)
Battery
■ PRECISION POWER MONITORING and
POWER SWITCHING CIRCUITRY
■ AUTOMATIC WRITE-PROTECTION when V
CC
is OUT-OF-TOLERANCE
16
■ TWO INPUT DECODER ALLOWS CONTROL
for up to 8 SRAMs (with 2 devices active in
parallel)
28
1
■ CHOICE of SUPPLY VOLTAGES and
1
POWER-FAIL DESELECT VOLTAGES:
SO16 (MQ)
SOH28 (MH)
– M40Z300:
V
= 4.5V to 5.5V
CC
THS = V 4.5V ≤ V
≤ 4.75V
PFD
SS
THS = V
4.2V ≤ V
≤ 4.5V
OUT
PFD
– M40Z300W:
= 3.0V to 3.6V
Figure 1. Logic Diagram
V
CC
THS = V 2.8V ≤ V
≤ 3.0V
≤ 2.7V
SS
PFD
V
= 2.7V to 3.3V
CC
V
B+(1)
CC
THS = V
2.5 ≤ V
OUT
PFD
■ RESET OUTPUT (RST) for POWER ON
RESET
■ LESS THAN 12ns CHIP ENABLE ACCESS
THS
E
V
OUT
PROPAGATION DELAY (for 5.0V device)
BL
E1
E2
E3
E4
■ PACKAGING INCLUDES a 28-LEAD SOIC
®
and SNAPHAT TOP, or a 16-LEAD SOIC
B
(to be Ordered Separately)
CON
CON
CON
CON
M40Z300
M40Z300W
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY
A
■ BATTERY LOW PIN (BL)
DESCRIPTION
RST
The M40Z300/W NVRAM Controller is a self-con-
tained device which converts a standard low-pow-
er SRAM into a non-volatile memory. A precision
voltage reference and comparator monitors the
V
B–(1)
V
input for an out-of-tolerance condition.
SS
CC
NOTE: 1. For 16-pin SOIC package only.
AI02242
March 2000
1/16
M40Z300, M40Z300W
Figure 2A. SOIC28 Connections
Figure 2B. SOIC16 Connections
V
1
28
V
E
OUT
NC
CC
2
27
NC
RST
NC
A
3
26
NC
NC
NC
E1
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
B+ (B–)
OUT
NC
4
25
5
24
23
RST
A
E
6
E1
CON
M40Z300
M40Z300W
CON
NC
B
7
M40Z300 22
E2
B
E2
CON
CON
M40Z300W
8
21
20
19
18
17
16
15
NC
E3
BL
THS
E3
CON
NC
BL
9
E4
CON
CON
10
11
12
13
14
NC
NC
NC
E4
V
B– (B+)
SS
NC
NC
THS
( ) = M40Z300W
AI03624
CON
V
NC
SS
AI02243
Table 1. Signal Names
When an invalid V
tioned chip enable outputs (E1
forced inactive to write-protect the stored data in
the SRAM. During a power failure, the SRAM is
switched from the V pin to the lithium cell within
condition occurs, the condi-
CC
to E4
) are
CON
CON
THS
E
Threshold Select Input
Chip Enable Input
CC
the SNAPHAT to provide the energy required for
data retention. On a subsequent power-up, the
SRAM remains write protected until a valid power
condition returns.
E1
-E4
CON CON
Conditioned Chip Enable Output
Decoder Inputs
A, B
RST
BL
Reset Output (Open Drain)
Battery Low Output (Open Drain)
Supply Voltage Output
Supply Voltage
The 28 pin, 330 mil SOIC provides sockets with
gold plated contacts for direct connection to a sep-
arate SNAPHAT housing containing the battery.
The SNAPHAT housing has gold plated pins
which mate with the sockets, ensuring reliable
connection. The housing is keyed to prevent im-
proper insertion. This unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process which greatly reduces the
board manufacturing process complexity of either
directly soldering or inserting a battery into a sol-
dered holder. Providing non-volatility becomes a
"SNAP".
V
OUT
V
CC
V
SS
Ground
B+
B–
NC
Positive Battery Pin
Negative Battery Pin
Not Connected Internally
The 16 pin SOIC provides battery pins for an ex-
ternal user supplied battery.
2/16
M40Z300, M40Z300W
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
°C
Storage Temperature (V Off)
SNAPHAT
SOIC
–40 to 85
–55 to 125
CC
T
°C
V
STG
V
–0.3 to V +0.3
Input or Output Voltages
Supply Voltage
IO
CC
M40Z300
M40Z300W
–0.3 to 7
–0.3 to 4.6
V
V
CC
I
Output Current
20
1
mA
W
O
P
Power Dissipation
D
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
OPERATION
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
The M40Z300/W, as shown in Figure 4, can con-
trol up to four (eight, if placed in parallel) standard
low-power SRAMs. These SRAMs must be config-
ured to have the chip enable input disable all other
input signals. Most slow, low-power SRAMs are
configured like this, however many fast SRAMs
are not. During normal operating conditions, the
conditioned chip enable (E1
pins follow the chip enable (E) input pin with timing
shown in Table 7. An internal switch connects V
memory cycle is not terminated within time t
,
WPT
E1
to E4
are unconditionally driven high,
CON
CON
write protecting the SRAM. A power failure during
a write cycle may corrupt data at the currently ad-
dressed location, but does not jeopardize the rest
of the SRAM’s contents. At voltages below V
PFD
to E4
) output
CON
CON
(min), the user can be assured the memory will be
write protected within the Write Protect Time
CC
(t
) provided the V fall time exceeds t (See
WPT
CC F
to
This switch has a voltage drop of less than 0.3V
(I ).
V
.
OUT
Table 7).
As V continues to degrade, the internal switch
CC
OUT1
disconnects V and connects the internal battery
CC
When V
degrades during a power failure,
CC
to V
. This occurs at the switchover voltage
OUT
E1
to E4
are forced inactive independent
CON
CON
(V ). Below the V , the battery provides a volt-
SO
SO
of E. In this situation, the SRAM is unconditionally
write protected as V falls below an out-of-toler-
ance threshold (V
er fail detection value associated with V
selected by the Threshold Select (THS) pin and is
shown in Table 6A. For the M40Z300W, the THS
age V
to the SRAM and can supply current
OHB
CC
PFD
I
(see Table 6A/6B).
OUT2
). For the M40Z300 the pow-
When V
rises above V , V
is switched
CC
SO
OUT
is
PFD
back to the supply voltage. Outputs E1
to
CON
E4
are held inactive for t
(120ms maxi-
CON
CER
mum) after the power supply has reached V
,
PFD
pin selects both the supply voltage and V
shown in Table 6B.
as
PFD
independent of the E input, to allow for processor
stabilization (see Figure 6).
Note: In either case, THS pin must be connected
to either V or V
.
OUT
SS
3/16
M40Z300, M40Z300W
Table 3. Truth Table
Inputs
Outputs
E1
E2
E3
E4
CON
E
H
L
L
L
L
B
X
L
A
X
L
CON
CON
CON
H
H
H
L
H
H
H
L
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
H
H
Table 4. AC Measurement Conditions
Figure 3. AC Testing Load Circuit
Input Rise and Fall Times
≤ 5ns
0 to 3V
1.5V
Input Pulse Voltages
Input and Output Timing Ref. Voltages
333Ω
DEVICE
UNDER
TEST
DATA RETENTION LIFETIME CALCULATION
Most low power SRAMs on the market today can
be used with the M40Z300/W NVRAM Controller.
There are, however some criteria which should be
used in making the final choice of which SRAM to
use. The SRAM must be designed in a way where
the chip enable input disables all other inputs to
the SRAM. This allows inputs to the M40Z300/W
1.73V
C
= 50pF
L
and SRAMs to be Don’t Care once V falls below
CC
V
(min). The SRAM should also guarantee
PFD
C
includes JIG capacitance
L
data retention down to V
= 2.0V. The chip en-
CC
AI02393
able access time must be sufficient to meet the
system needs with the chip enable propagation
delays included. If the SRAM includes a second
Chip Enable pin (E2), this pin should be tied to
the M40Z300/W to determine the total current re-
quirements for data retention. The available bat-
tery capacity for the SNAPHAT of your choice can
then be divided by this current to determine the
amount of data retention available (see Table 8).
V
.
OUT
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use. The data retention current value of the
CAUTION: Take care to avoid inadvertent dis-
charge through V
and E1
-E4
after bat-
OUT
CON
CON
tery has been attached.
For a further more detailed review of lifetime cal-
culations, please see Application Note AN1012.
SRAMs can then be added to the I
value of
CCDR
4/16
M40Z300, M40Z300W
Figure 4. Hardware Hookup
3.0V, 3.3V or 5V
V
V
OUT
CC
V
V
V
V
CC
CMOS
CC
CMOS
CC
CMOS
CC
0.1µF
M40Z300
M40Z300W
CMOS
SRAM
SRAM
SRAM
SRAM
0.1µF
0.1µF
0.1µF
0.1µF
E
E
E
E
E1
CON
A
B
E
E2
E3
E4
CON
CON
CON
Threshold
THS
RST
BL
To Microprocessor
V
To Battery Monitor Circuit
SS
AI02395
POWER-ON RESET OUTPUT
Once V
exceeds the power failure detect volt-
CC
, an internal timer keeps RST low for
age V
PFD
All microprocessors have a reset input which forc-
es them to a known state when starting. The
M40Z300/W has a reset output (RST) pin which is
t
to allow the power supply to stabilize.
REC
TWO TO FOUR DECODE
guaranteed to be low within t
of V
(See Ta-
WPT
PFD
The M40Z300/W includes a 2 input (A, B) decoder
which allows the control of up to 4 independent
SRAMs. The Truth Table for these inputs is shown
in Table 3.
ble 7). This signal is an open drain configuration.
An appropriate pull-up resistor should be chosen
to control the rise time. This signal will be valid for
all voltage conditions, even when V equals V
.
SS
CC
5/16
M40Z300, M40Z300W
(1)
Table 5. Capacitance
(T = 25 °C, f = 1 MHz)
A
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
8
Unit
pF
C
V
= 0V
= 0V
IN
IN
C
V
OUT
10
pF
OUT
Note: 1. Sampled only, not 100% tested.
2. Outputs deselected.
Table 6A. DC Characteristics for M40Z300
(T = 0 to 70°C; V = 4.75V to 5.5V or 4.5V to 5.5V)
A
CC
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
(1)
0V ≤ V ≤ V
Input Leakage Current
Supply Current
±1
6
µA
mA
V
I
IN
CC
LI
I
Outputs open
3
CC
V
Input Low Voltage
Input High Voltage
Output Low Voltage
–0.3
2.2
0.8
IL
V
V
+ 0.3
V
IH
CC
I
= 4.0mA
= 10mA
0.4
0.4
V
OL
V
V
OL
(2)
I
V
OL
Output Low Voltage (open drain)
I
= –2.0mA
= –1.0µA
OUT2
Output High Voltage
2.4
2.0
V
OH
OH
(3)
V
I
V
V
V
2.9
3.6
250
150
V
mA
mA
µA
nA
V
V
V
V
Battery Back-up
OHB
OH
> V –0.3
OUT
OUT
CC
I
I
Current (Active)
OUT1
OUT
OUT
> V –0.2
CC
Current (Battery Back-up)
> V
–0.3
100
OUT2
OUT
BAT
(4)
I
100
CCDR
Data Retention Mode Current
Threshold Select Voltage
V
SS
V
OUT
THS
Power-fail Deselect Voltage (THS = V
Power-fail Deselect Voltage (THS = V
Battery Back-up Switchover Voltage
)
4.5
4.2
4.6
4.35
3.0
4.75
V
SS
V
PFD
)
4.5
V
OUT
V
V
SO
Note: 1. Outputs deselected.
2. For RST & BL pins (Open Drain).
3. Chip Enable outputs (E1
- E4 ) can only sustain CMOS leakage currents in the battery back-up mode.
CON
CON
Higher leakage currents will reduce battery life.
4. Measured with V and E1 - E4 open.
OUT
CON
CON
6/16
M40Z300, M40Z300W
Table 6B. DC Characteristics for M40Z300W
(T = 0 to 70°C; V = 3V to 3.6V or 2.7V to 3.3V)
A
CC
Symbol
Parameter
Test Condition
Min
Typ
Max
±1
Unit
µA
mA
V
(1)
0V ≤ V ≤ V
Input Leakage Current
Supply Current
I
IN
CC
LI
I
Outputs open
2
4
CC
V
Input Low Voltage
Input High Voltage
Output Low Voltage
–0.3
2.0
0.8
IL
V
IH
V
+ 0.3
CC
V
I
= 4.0mA
= 10mA
0.4
0.4
V
OL
V
V
OL
(2)
I
V
OL
Output Low Voltage (open drain)
I
= –2.0mA
= –1.0µA
OUT2
Output High Voltage
2.4
2.0
V
OH
OH
(3)
V
OHB
I
2.9
3.6
150
100
V
V
V
V
Battery Back-up
OH
V
V
V
> V –0.3
CC
mA
mA
µA
nA
V
OUT
OUT
I
I
Current (Active)
OUT1
OUT
OUT
> V –0.2
CC
Current (Battery Back-up)
> V
–0.3
100
OUT2
OUT
BAT
(4)
I
100
CCDR
Data Retention Mode Current
Threshold Select Voltage
V
SS
V
OUT
THS
Power-fail Deselect Voltage (THS = V
Power-fail Deselect Voltage (THS = V
Battery Back-up Switchover Voltage
)
2.8
2.5
2.9
2.6
2.5
3.0
V
SS
V
PFD
)
2.7
V
OUT
V
V
SO
Note: 1. Outputs deselected.
2. For RST & BL pins (Open Drain).
3. Chip Enable outputs (E1
- E4 ) can only sustain CMOS leakage currents in the battery back-up mode.
CON
CON
Higher leakage currents will reduce battery life.
4. Measured with V and E1 - E4 open.
OUT
CON
CON
7/16
M40Z300, M40Z300W
Table 7. Power Down/Up AC Characteristics
(T = 0 to 70°C)
A
Symbol
Parameter
Min
Max
Unit
(1)
V
PFD
(max) to V
(min) V Fall Time
300
µs
t
F
PFD
CC
(2)
V
PFD
V
PFD
(min) to V
V
Fall Time
150
10
µs
t
SS CC
FB
t
(min) to V
(max) V Rise Time
PFD CC
µs
ns
ns
ns
ns
ns
ms
ms
µs
µs
µs
R
M40Z300
12
20
10
20
t
t
Chip Enable Propagation Delay Low
Chip Enable Propagation Delay High
EDL
M40Z300W
M40Z300
EDH
M40Z300W
t
A, B set up to E
0
AS
t
t
Chip Enable Recovery
40
40
40
40
1
120
120
150
250
CER
REC
V
PFD
(max) to RST High
M40Z300
t
Write Protect Time
WPT
M40Z300W
t
V
SS
to V
(min) V Rise Time
PFD CC
RB
Note: 1. V
(max) to V
(min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
PFD
PFD
V
passes V
(min)..
CC
PFD
2. V
(min) to V fall time of less than tFB may cause corruption of RAM data.
PFD
SS
BATTERY LOW PIN
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
The M40Z300/W automatically performs battery
voltage monitoring upon power-up, and at factory-
programmed time intervals of at least 24 hours.
The Battery Low (BL) pin will be asserted if the
battery voltage is found to be less than approxi-
mately 2.5V. The BL pin will remain asserted until
completion of battery replacement and subse-
quent battery low monitoring tests, either during
the next power-up sequence or the next scheduled
24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below
2.5V and may not be able to maintain data integrity
in the SRAM. Data should be considered suspect,
and verified as correct. A fresh battery should be
installed.
promised due to the fact that a nominal V
is
CC
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. SNAPHAT top should
be replaced with valid V applied to the device.
CC
The M40Z300/W only monitors the battery when a
nominal V
is applied to the device. Thus appli-
CC
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique. The BL pin is an open drain output and
an appropriate pull-up resistor to V
chosen to control the rise time.
should be
CC
8/16
M40Z300, M40Z300W
Figure 5. Power Down Timing
V
CC
V
V
V
V
(max)
(min)
PFD
PFD
PFD
SO
tF
tFB
E
tWPT
V
OHB
E1
E4
CON
CON
-
RST
AI02398B
Figure 6. Power Up Timing
V
CC
V
V
V
(max)
(min)
PFD
PFD
PFD
V
SO
tR
tRB
tCER
E
tEDH
tEDL
V
OHB
E1
E4
CON
CON
-
tREC
RST
AI02399B
9/16
M40Z300, M40Z300W
Figure 7. Address-Decode Time
A, B
tAS
E
tEDL
tEDH or tEDL
E1
-E4
CON
CON
AI02551
Note: During system design, compliance with the SRAM timing parameters must comprehend the propagation delay
between E and EX
CON
Table 8. Battery Table
Part Number
Description
Package
SH
M4Z28-BR00SH
M4Z32-BR00SH
Lithium Battery (48mAh) SNAPHAT
Lithium Battery (120mAh) SNAPHAT
SH
V
CC
NOISE AND NEGATIVE GOING TRANSIENTS
Figure 8. Supply Voltage Protection
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
can be reduced if capacitors are used to store en-
V
CC
ergy, which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur.
V
CC
0.1µF
DEVICE
A ceramic bypass capacitor value of 0.1µF (as
shown in figure 8) is recommended in order to pro-
vide the needed filtering.
V
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
SS
ative voltage spikes on V
that drive it to values
CC
AI00622
below V by as much as one volt. These negative
SS
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, STMicroelectronics recom-
mends connecting a schottky diode from V
to
CC
V
(cathode connected to V , anode to V ).
SS
CC SS
Schottky diode 1N5817 is recommended for
through hole and MBRS120T3 is recommended
for surface mount.
10/16
M40Z300, M40Z300W
Table 9. Ordering Information Scheme
Example:
M40Z300W
MH
1
TR
Supply Voltage and Write Protect Voltage
300 = V = 4.5V to 5.5V
CC
THS = V
THS = V
4.5V ≤ V
4.2V ≤ V
≤ 4.75V
≤ 4.5V
PFD
SS
PFD
OUT
300W = V = 3.0V to 3.6V
CC
THS = V
2.8V ≤ V
≤ 3.0V
SS
PFD
V
CC
= 2.7V to 3.3V
THS = V
2.5V ≤ V
≤ 2.7V
PFD
OUT
Package
(1,2)
MH
= SOH28
MQ = SO16
Temperature Range
1 = 0 to 70 °C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number
“M4Zxx-BR00SH1" in plastic tube or "M4Zxx-BR00SH1TR" in Tape & Reel form.
2. Delivery may include either the 2-pin version of the SOIC/SNAPHAT or the 4-pin version of the SOIC/SNAPHAT. Both are function-
ally equivalent (see package drawing section for details).
Caution: Do not place the SNAPHAT battery package "M4Zxx-BR00SH1" in conductive foam since will drain the lithium button-cell battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
Table 10. Revision History
Date
Revision Details
March 1999
First Issue
Document Layout changed
SO16 package added
03/08/00
Battery Capacity changed (Table 8)
11/16
M40Z300, M40Z300W
Table 11. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
Figure 9. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Drawing is not to scale.
12/16
M40Z300, M40Z300W
Table 12. M4Z28-BR00SH SNAPHAT Housing for 48 mAh Battery, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
Figure 10. M4Z28-BR00SH SNAPHAT Housing for 48 mAh Battery, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHZP-A
Drawing is not to scale.
13/16
M40Z300, M40Z300W
Table 13. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
Typ
Max
A
A1
A2
A3
B
0.415
.0335
0.315
0.015
0.022
0.860
.0710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
Figure 11. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHZP-A
Drawing is not to scale.
14/16
M40Z300, M40Z300W
Table 14. SO16 - 16 lead Plastic Small Outline, 300 mils body width
mm
inches
Symb.
Typ.
Min.
Max.
2.59
0.30
0.51
0.25
10.49
7.54
–
Typ.
Min.
Max.
0.102
0.012
0.020
0.010
0.413
0.297
–
A
A1
B
0.10
0.38
0.23
10.11
7.44
–
0.004
0.015
0.009
0.398
0.293
–
C
D
E
e
1.27
0.050
0.015
H
h
10.16
10.41
0.400
0.410
0.38
L
0.41
0°
1027
8°
0.016
0°
0.050
8°
α
N
CP
16
16
0.10
0.004
Figure 12. SO16 - 16 lead Plastic Small Outline, 300 mils body width, Package Outline
h x 45˚
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Drawing is not to scale.
15/16
M40Z300, M40Z300W
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