M36W0R6050T1ZAQF [STMICROELECTRONICS]
64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package; 64兆位（ 4兆】 16 ，多银行，连拍），闪存和32兆（2 MB 】 16 ） PSRAM ，多芯片封装
| 型号： | M36W0R6050T1ZAQF |
| 厂家： | 
ST |
| 描述： | 64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package |
| 文件： | 总22页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M36W0R6050T1
M36W0R6050B1
64 Mbit (4 Mb ×16, Multiple Bank, Burst) Flash memory
and 32 Mbit (2 Mb ×16) PSRAM, multi-chip package
Features
■ Multi-Chip Package
– 1 die of 64 Mbit (4 Mb × 16) Flash memory
– 1 die of 32 Mbit (2 Mb × 16) Pseudo SRAM
FBGA
■ Supply voltage
– V
= V
= V
= 1.7 V to 1.95 V
DDQF
DDF
DDP
Stacked TFBGA88
(ZA)
■ Low power consumption
■ Electronic signature
– Manufacturer Code: 20h
– Device code (top flash configuration),
M36W0R6050T1: 8810h
■ Block locking
– Device code (bottom flash configuration),
M36W0R6050B1: 8811h
– All blocks locked at Power-up
– Any combination of blocks can be locked
■ Package
– WP for Block Lock-Down
F
– ECOPACK®
■ Security
– 128-bit user programmable OTP cells
– 64-bit unique device number
Flash memory
■ Programming time
■ Common Flash Interface (CFI)
– 8 µs by Word typical for Fast Factory
Program
■ 100 000 program/erase cycles per block
– Double/Quadruple Word Program option
– Enhanced Factory Program options
PSRAM
■ Access time: 70 ns
■ Memory blocks
■ Asynchronous Page Read
– Page size: 8 words
– Multiple Bank memory array: 4 Mbit Banks
– Parameter Blocks (Top or Bottom location)
– First access within page: 70 ns
– Subsequent read within page: 20 ns
■ Synchronous / Asynchronous Read
– Synchronous Burst Read mode: 66 MHz
■ Three Power-down modes
– Deep Power-Down
– Asynchronous/ Synchronous Page Read
mode
– Random Access: 70 ns
– Partial Array Refresh of 4 Mbits
– Partial Array Refresh of 8 Mbits
■ Dual operations
– Program Erase in one Bank while Read in
others
– No delay between Read and Write
operations
January 2007
1
1/22
www.st.com
1
Contents
M36W0R6050T1, M36W0R6050B1
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Address inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data inputs/outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Latch Enable (LF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Clock (KF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10 Flash Wait (WAITF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.11 PSRAM Chip Enable (E1P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.12 PSRAM Chip Enable (E2P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.13 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.14 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.15 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.16 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.17
VDDF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.18 VDDP supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.19
2.20
V
V
DDQF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PPF program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.21 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
4
5
6
2/22
M36W0R6050T1, M36W0R6050B1
Contents
7
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
List of tables
M36W0R6050T1, M36W0R6050B1
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stacked TFBGA88 8 × 10 mm - 8 × 10 ball array, 0.8 mm pitch, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7.
Table 8.
4/22
M36W0R6050T1, M36W0R6050B1
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch, package outline. . 18
5/22
Description
M36W0R6050T1, M36W0R6050B1
1
Description
The M36W0R6050T1 and M36W0R6050B1 combine two memories in a Multi-Chip
Package:
■
■
a 64-Mbit, Multiple Bank Flash memory, the M58WR064HT/B, and
a 32-Mbit Pseudo SRAM, the M69KB048BD.
The purpose of this document is to describe how the two memory components operate with
respect to each other. It must be read in conjunction with the M58WR064HT/B and
M69KB048BD datasheets, where all specifications required to operate the Flash memory
and PSRAM components are fully detailed. These datasheets are available from the ST web
site: www.st.com.
Recommended operating conditions do not allow more than one memory to be active at the
same time.
The memory is offered in a Stacked TFBGA88 (8 ×10 mm, 8 × 10 ball array, 0.8 mm pitch)
package. It is supplied with all the bits erased (set to ‘1’).
Figure 1.
Logic diagram
V
V
PPF
DDQF
V
V
DDF
DDP
22
16
DQ0-DQ15
A0-A21
E
G
F
F
F
WAIT
F
W
RP
F
WP
F
L
F
M36W0R6050T1
M36W0R6050B1
K
F
E1
P
G
P
W
P
E2
P
UB
LB
P
P
V
SS
Ai12035
6/22
M36W0R6050T1, M36W0R6050B1
Description
Table 1.
Signal names
A0-A21(1)
Address Inputs
DQ0-DQ15
VDDF
VDDQF
VPPF
VSS
Common Data Inputs/Outputs
Flash Memory Power Supply
Flash memory Power Supply for I/O Buffers
Common Flash Optional Supply Voltage for Fast Program & Erase
Ground
VDDP
NC
PSRAM Power Supply
Not Connected Internally
DU
Do Not Use as Internally Connected
Flash memory control functions
LF
Latch Enable input
EF
Chip Enable input
Output Enable input
Write Enable input
Reset input
GF
WF
RPF
WPF
Write Protect input
Burst Clock
KF
WAITF
Wait Data in Burst Mode
PSRAM control functions
E1P
GP
Chip Enable input
Output Enable input
Write Enable input
WP
E2P
UBP
LBP
Power-down input
Upper Byte Enable input
Lower Byte Enable input
1. A21 is an address input for the Flash memory component only.
7/22
Description
Figure 2.
M36W0R6050T1, M36W0R6050B1
TFBGA connections (top view through package)
1
2
3
4
5
6
7
8
A
DU
A4
A5
A3
A2
A1
A0
DU
A21
NC
DU
DU
A11
A12
A13
A15
A16
NC
B
C
D
E
F
A18
A19
NC
NC
NC
V
V
NC
V
SS
SS
DDF
LB
P
NC
K
F
A17
A7
V
W
P
E
P
A9
PPF
WP
L
F
A20
A8
A10
A14
WAIT
F
A6
UB
P
RP
W
F
F
G
H
J
DQ8
DQ0
DQ2
DQ1
DQ9
NC
DQ10
DQ3
DQ11
NC
DQ5
DQ12
DQ4
DQ13
DQ14
DQ6
NC
F
G
P
DQ7
NC
NC
G
F
DQ15
V
DDQF
E
F
K
L
NC
V
V
E2
P
DDP
DDQF
V
V
V
V
V
V
V
V
SS
SS
DDQF
DDF
SS
SS
SS
SS
DU
DU
M
DU
DU
AI12037
8/22
M36W0R6050T1, M36W0R6050B1
Signal descriptions
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-A21)
Addresses A0-A21 are common inputs for the Flash memory and PSRAM components,
whereas A21 is an address input for the Flash memory component only. The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus
Write operations they control the commands sent to the Command Interface of the Flash
memory Program/Erase Controller, and they select the cells to access in the PSRAM.
2.2
Data inputs/outputs (DQ0-DQ15)
For the Flash memory, the Data I/O outputs the data stored at the selected address during a
Bus Read operation or inputs a command or the data to be programmed during a Write Bus
operation.
For the PSRAM, the Upper Byte Data Inputs/Outputs carry the data to or from the upper
part of the selected address during a Write or Read operation, when Upper Byte Enable
(UB ) is driven Low.
P
Likewise, the Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the
selected address during a Write or Read operation, when Lower Byte Enable (LB ) is driven
P
Low.
2.3
Flash Chip Enable (EF)
The Chip Enable inputs activate the memory control logics, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, V , and Reset is High, V , the device is in
IL
IH
active mode. When Chip Enable is at V the Flash memory is deselected, the outputs are
IH
high impedance and the power consumption is reduced to the standby level.
2.4
2.5
Flash Output Enable (GF)
The Output Enable pins control data outputs during Flash memory Bus Read operations.
Flash Write Enable (WF)
The Write Enable controls the Bus Write operation of the Flash memories’ Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
9/22
Signal descriptions
M36W0R6050T1, M36W0R6050B1
2.6
Flash Write Protect (WPF)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is Low, V , Lock-Down is enabled and the protection status of the Locked-
IL
Down blocks cannot be changed. When Write Protect is at High, V , Lock-Down is disabled
IH
and the Locked-Down blocks can be locked or unlocked. (Refer to Lock Status Table in
M58WR064HT/B datasheet).
2.7
Flash Reset (RPF)
The Reset input provides a hardware reset of the memory. When Reset is at V , the
IL
memory is in Reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current I
. Refer to the M58WR064HT/B datasheet, for the
DD2
value of I
. After Reset all blocks are in the Locked state and the Configuration Register is
DD2
reset. When Reset is at V , the device is in normal operation. Exiting Reset mode the
IH
device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch
Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
to V
(refer to the M58WR064HT/B datasheet).
RPH
2.8
Flash Latch Enable (LF)
Latch Enable latches the address bits on its rising edge. The address latch is transparent
when Latch Enable is Low, V , and it is inhibited when Latch Enable is High, V . Latch
IL
IH
Enable can be kept Low (also at board level) when the Latch Enable function is not required
or supported.
2.9
Flash Clock (KF)
The Clock input synchronizes the Flash memory to the microcontroller during synchronous
read operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at V . Clock is don't care during Asynchronous
IL
Read and in write operations.
2.10
2.11
10/22
Flash Wait (WAITF)
WAIT is a Flash output signal used during Synchronous Read to indicate whether the data
on the output bus are valid. This output is high impedance when Flash Chip Enable is at V
IH
or Flash Reset is at V . It can be configured to be active during the wait cycle or one clock
IL
cycle in advance. The WAIT signal is not gated by Output Enable.
F
PSRAM Chip Enable (E1P)
When asserted (Low), the Chip Enable, E1 , activates the memory state machine, address
P
buffers and decoders, allowing Read and Write operations to be performed. When de-
asserted (High), all other pins are ignored, and the device is automatically put in Standby
mode.
M36W0R6050T1, M36W0R6050B1
Signal descriptions
2.12
PSRAM Chip Enable (E2P)
When de-asserted (Low), the Chip Enable input E2 , puts the device in Power-Down mode.
P
This is the lowest power mode according to the Configuration Register settings (see
M69KB048BD datasheet).
2.13
2.14
2.15
2.16
2.17
2.18
2.19
PSRAM Output Enable (GP)
The Output Enable, G , provides a high speed tri-state control, allowing fast read/write
P
cycles to be achieved with the common I/O data bus.
PSRAM Write Enable (WP)
The Write Enable, W , controls the Bus Write operation of the memory’s Command
P
Interface.
PSRAM Upper Byte Enable (UBP)
The Upper Byte Enable, UB , gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
P
DQ15) to or from the upper part of the selected address during a Write or Read operation.
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LB , gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
P
DQ7) to or from the lower part of the selected address during a Write or Read operation.
VDDF supply voltage
V
provides the power supply to the internal core of the Flash memory component. It is
DDF
the main power supplies for all Flash memory operations (Read, Program and Erase).
VDDP supply voltage
The V
Supply Voltage supplies the power for all operations (Read or Write) and for
DDP
driving the refresh logic, even when the device is not being accessed.
VDDQF supply voltage
V
provides the power supply for the Flash memory I/O pins. This allows all Outputs to
DDQF
be powered independently of the Flash memory core power supply, V
.
DDF
11/22
Signal descriptions
M36W0R6050T1, M36W0R6050B1
2.20
VPPF program supply voltage
V
is both a Flash Memory control input and a Flash Memory power supply pin. The two
PPF
functions are selected by the voltage range applied to the pin.
If V is kept in a low voltage range (0V to V ) V is seen as a control input. In this
PPF
DDQF
PPF
case a voltage lower than V
gives an absolute protection against Program or Erase,
PPLKF
while V
> V
enables these functions (see the M58WR064HT/B datasheet for the
PPF
PP1F
relevant values). V
is only sampled at the beginning of a Program or Erase; a change in
PPF
its value after the operation has started does not have any effect and Program or Erase
operations continue.
If V
is in the range of V
it acts as a power supply pin. In this condition V
must be
PPF
PPHF
PPF
stable until the Program/Erase algorithm is completed.
2.21
VSS ground
V
is the common ground reference for all voltage measurements in the Flash memory
SS
(core and I/O Buffers) and PSRAM components.
Note:
Each Flash memory device in a system should have its supply voltages (V
, V
) and
DDF DDQF
the program supply voltage V
decoupled with a 0.1µF ceramic capacitor close to the pin
PPF
(high frequency, inherently low inductance capacitors should be as close as possible to the
package). See Figure 5: AC measurement load circuit. The PCB track widths should be
sufficient to carry the required V
program and erase currents.
PPF
12/22
M36W0R6050T1, M36W0R6050B1
Functional description
3
Functional description
The Flash memory and PSRAM components have separate power supplies but share the
same grounds. They are distinguished by three Chip Enable inputs: E for the Flash
F
memory and E1 and E2 for the PSRAM.
P
P
Recommended operating conditions do not allow more than one device to be active at a
time. The most common example is simultaneous read operations on the Flash memory and
the PSRAM which would result in a data bus contention. Therefore it is recommended to put
the other devices in the high impedance state when reading the selected device.
Figure 3.
Functional block diagram
V
V
V
DDQF
DDF
PPF
A21
E
F
64 Mbit
Flash
G
F
Memory
W
WAIT
F
F
L
F
K
F
RP
F
WP
F
A0-A20
DQ0-DQ15
V
DDP
E1
P
32 Mbit
PSRAM
G
P
W
P
E2
P
UB
P
LB
P
V
SS
AI12.36
13/22
Functional description
M36W0R6050T1, M36W0R6050B1
Table 2.
Main operating modes
EF GP WP LF
(4)
Operation
RPF WAITF
E1P E2P GP WP UBP LBP DQ15-DQ0
Flash Data
Out
Flash Read
Flash Write
VIL VIL VIH VIL(2) VIH
VIL VIH VIL VIL(2) VIH
Flash Data In
PSRAM must be disabled
Flash Data
Flash Address
Latch
VIL
X
VIH
VIL
X
VIH
VIH
Out or Hi-Z
(3)
Flash Output
Disable
VIL VIH VIH
Flash Hi-Z
Any PSRAM mode is allowed
Flash Hi-Z
Flash Standby
Flash Reset
VIH
X
X
X
X
X
X
X
VIH
VIL
Hi-Z
Hi-Z
Flash Hi-Z
PSRAM data
PSRAM Read
PSRAM Write
VIL VIH VIL VIH VIL VIL
VIL VIH VIH VIL VIL VIL
out
Flash Memory must be disabled
Any Flash mode is allowed.
PSRAM data
in
Output Disable
VIL VIH VIH VIH
X
X
X
X
PSRAM Hi-Z
PSRAM Hi-Z
PSRAM Standby
VIH VIH
VIL
X
X
X
X
PSRAM Deep
Power-Down
X
X
X
PSRAM Hi-Z
1. X = Don't care.
2. LF can be tied to VIH if the valid address has been previously latched.
3. Depends on GF.
4. WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR064HT/B datasheet for
details.
14/22
M36W0R6050T1, M36W0R6050B1
Maximum rating
4
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
Min
Max
TA
TBIAS
TSTG
VIO
Ambient Operating Temperature
Temperature Under Bias
–30
–40
85
125
125
°C
°C
°C
V
Storage Temperature
–55
Input or Output Voltage
–0.5
–0.2
–0.2
–0.5
–0.2
VDDQF+0.6
2.45
2.45
3.6
VDDF
VDDQF
VDDP
VPPF
IO
Flash Memory Core Supply Voltage
Input/Output Supply Voltage
PSRAM Supply Voltage
V
V
V
Flash Memory Program Voltage
Output Short Circuit Current
Time for VPPF at VPPFH
14
V
100
mA
hours
tVPPFH
100
15/22
DC and ac parameters
M36W0R6050T1, M36W0R6050B1
5
DC and ac parameters
This section summarizes the operating measurement conditions, and the dc and ac
characteristics of the device. The parameters in the dc and ac characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 4: Operating and ac measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 4.
Operating and ac measurement conditions
Flash memory
Parameter
PSRAM
Unit
Min
Max
Min
Max
VDDF Supply Voltage
VDDP Supply Voltage
1.7
–
1.95
–
–
1.7
–
–
1.95
–
V
V
V
V
VDDQF Supply Voltage
1.7
11.4
1.95
12.6
VPPF Supply Voltage (Factory environment)
–
–
VPPF Supply Voltage (Application
environment)
–0.4
–30
VDDQF +0.4
85
–
–
V
Ambient Operating Temperature
Load Capacitance (CL)
–30
85
°C
pF
ns
V
30
50
Input Rise and Fall Times
Input Pulse Voltages
5
0 to VDDQF
DDQF/2
0 to VDDP
VDDP/2
Input and Output Timing Ref. Voltages
V
V
Figure 4.
AC measurement I/O waveform
V
DDQF
0V
V
/2
DDQF
AI12057
16/22
M36W0R6050T1, M36W0R6050B1
DC and ac parameters
Figure 5.
AC measurement load circuit
VDDQF
VDDF
VDDQF
16.7kΩ
DEVICE
UNDER
TEST
CL
0.1µF
16.7kΩ
0.1µF
CL includes JIG capacitance
AI12058
Table 5.
Symbol
Device capacitance
Parameter
Test condition
Min
Max
Unit
CIN
Input Capacitance
Output Capacitance
VIN = 0V
12
15
pF
pF
COUT
VOUT = 0V
1. Sampled only, not 100% tested.
Please refer to the M58WR064HT/B and M69KB048BD datasheets for further dc and ac
characteristics values and illustrations.
17/22
Package mechanical
M36W0R6050T1, M36W0R6050B1
6
Package mechanical
In order to meet environmental requirements, ST offers the M36W0R6050T1 and
M36W0R6050B1 devices in ECOPACK® packages. These packages have a Lead-free
second-level interconnect. The category of Second-Level Interconnect is marked on the
package and on the inner box label, in compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 6.
Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch,
package outline
D
D1
e
SE
E
E2 E1
b
BALL "A1"
ddd
FE FE1
FD
SD
A
A2
A1
BGA-Z42
1. Drawing is not to scale.
18/22
M36W0R6050T1, M36W0R6050B1
Package mechanical
Table 6.
Stacked TFBGA88 8 × 10 mm - 8 × 10 ball array, 0.8 mm pitch, package
mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.200
0.0079
0.850
0.350
8.000
5.600
0.0335
0.0138
0.3150
0.2205
0.300
7.900
0.400
8.100
0.0118
0.3110
0.0157
0.3189
D
D1
ddd
E
0.100
0.0039
0.3976
10.000
7.200
8.800
0.800
1.200
1.400
0.600
0.400
0.400
9.900
–
10.100
0.3937
0.2835
0.3465
0.0315
0.0472
0.0551
0.0236
0.0157
0.0157
0.3898
E1
E2
e
–
–
–
FD
FE
FE1
SD
SE
19/22
Part numbering
M36W0R6050T1, M36W0R6050B1
7
Part numbering
Table 7.
Ordering information scheme
Example:
M36 W0 R 6 0 5 0 T 1 ZAQ E
Device Type
M36 = Multiple Memory Product (Multiple Flash + RAM)
Flash 1 Architecture
W = Multiple Bank, Burst mode
Flash 2 Architecture
0 = none present
Operating Voltage
R = VDDF = VDDQF = VDDP = 1.7 V to 1.95 V
Flash 1 Density
6 = 64 Mbit
Flash 2 Density
0 = none present
RAM 1 Density
5 = 32 Mbit
RAM 0 Density
0 = none present
Parameter Blocks Location
T = Top Boot Block Flash
B = Bottom Boot Block Flash
Product Version
1 = 90 nm Flash technology, 70 ns; 0.13 µm RAM, 70 ns speed
Package
ZAQ = Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch
Option
E = ECOPACK® Package, Standard Packing
F = ECOPACK® Package, Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of
available options (Speed, Package, etc.) or for further information on any aspect of this
device, please contact the STMicroelectronics Sales Office nearest to you.
20/22
M36W0R6050T1, M36W0R6050B1
Revision history
8
Revision history
Table 8.
Date
Document revision history
Revision
Changes
06-Dec-2005
12-Jan-2007
0.1
Initial release.
Document status promoted to Full Datasheet. Small text
changes.
1
21/22
M36W0R6050T1, M36W0R6050B1
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22/22
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