M36DR432B100ZA6T_技术文档

M36DR432A

M36DR432B

32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory

and 4 Mbit (256K x16) SRAM, Multiple Memory Product

FEATURES SUMMARY

■ SUPPLY VOLTAGE

Figure 1. Packages

– V

= V

=1.65V to 2.2V

DDF

PPF

DDS

= 12V for Fast Program (optional)

■ ACCESS TIME: 100,120ns

■ LOW POWER CONSUMPTION

■ ELECTRONIC SIGNATURE

FBGA

– Manufacturer Code: 20h

– Top Device Code, M36DR432A: 00A0h

– Bottom Device Code, M36DR432B: 00A1h

Stacked LFBGA66 (ZA)

8 x 8 ball array

FLASH MEMORY

■ 32 Mbit (2Mb x16) BOOT BLOCK

– Parameter Blocks (Top or Bottom Location)

■ PROGRAMMING TIME

– 10µs typical

– Double Word Programming Option

■ ASYNCRONOUS PAGE MODE READ

– Page width: 4 Word

– Page Mode Access Time: 35ns

■ DUAL BANK OPERATION

– Read within one Bank while Program or

Erase within the other

– No Delay between Read and Write

Operations

■ BLOCK PROTECTION ON ALL BLOCKS

– WPF for Block Locking

■ COMMON FLASH INTERFACE

– 64 bit Security Code

SRAM

■ 4 Mbit (256K x 16 bit)

■ LOW V

DATA RETENTION: 1V

DDS

■ POWER DOWN FEATURES USING TWO

CHIP ENABLE INPUTS

November 2001

1/46

M36DR432A, M36DR432B

DESCRIPTION

The M36DR432 is a multichip memory device con-

taining a 32 Mbit boot block Flash memory and a

4 Mbit of SRAM. The device is offered in a Stacked

LFBGA66 (0.8 mm pitch) package.

The two components are distinguished by use with

three chip enable inputs: EF for the Flash memory

and, E1S and E2S for the SRAM. The two compo-

nents are also separately power supplied and

grounded.

Table 1. Signal Names

A0-A17

Address Inputs

A18-A20

DQ0-DQ15

Address Inputs for Flash Chip only

Data Input/Output

V

Flash Power Supply

DDF

Flash Optional Supply Voltage for Fast

Program & Erase

V

PPF

Figure 2. Logic Diagram

V

Flash Ground

SSF

DDS

SSS

SRAM Power Supply

SRAM Ground

V

DDF

DDS

PPF

21

16

NC

Not Connected Internally

A0-A20

DQ0-DQ15

Flash control functions

EF

GF

EF

Chip Enable input

GF

Output Enable input

Write Enable input

Reset input

WF

RPF

WPF

WF

RPF

WPF

M36DR432A

M36DR432B

Write Protect input

E1S

E2S

GS

SRAM control functions

E1S, E2S

GS

Chip Enable input

WS

Output Enable input

Write Enable input

UBS

LBS

WS

UBS

Upper Byte Enable input

Lower Byte Enable input

V

LBS

SSF

SSS

AI90203

2/46

M36DR432A, M36DR432B

Figure 3. LFBGA Connections (Top view through package)

#1

#2

1

2

3

4

5

6

7

8

#3

#4

A15

A10

A14

A9

A

B

C

D

E

F

NC

A20

A16

WF

A11

A8

A13

A12

WS

V

NC

SSF

DQ15

DQ13

DQ12

DQ14

DQ4

DQ7

DQ5

NC

DQ6

E2S

DQ10

DQ8

A2

RPF

V

SSS

DDS

DDF

WPF

V

A19

GS

A7

DQ11

DQ2

DQ0

A1

DQ3

PPF

LBS

A18

NC

UBS

DQ9

A3

DQ1

E1S

NC

G

H

A17

A5

A6

A0

NC

A4

EF

V

GF

NC

SSF

AI90204

3/46

M36DR432A, M36DR432B

(1)

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

V

(3)

T

A

–40 to 85

–40 to 125

Ambient Operating Temperature

T

Temperature Under Bias

Storage Temperature

BIAS

T

–55 to 150

STG

(2)

(4)

Input or Output Voltage

Flash Chip Supply Voltage

SRAM Chip Supply Voltage

Program Voltage

V

IO

–0.2 to V

+ 0.3

DD

V

–0.5 to 2.7

V

DDF

DDS

V

–0.2 to 2.6

V

–0.5 to 13.0

V

PPF

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Minimum voltage may undershoot to –2V during transition and for less than 20ns.

3. Depends on range.

4. V = V

= V

.

DD

DDS

DDF

Figure 4. Functional Block Diagram

V

PPF

DDF

EF

GF

WF

RPF

WPF

Flash Memory

32 Mbit (x16)

A18-A20

A0-A17

V

SSF

V

DQ0-DQ15

DDS

E1S

E2S

GS

SRAM

4 Mbit (x16)

WS

UBS

LBS

V

SSS

AI90205

4/46

M36DR432A, M36DR432B

SIGNAL DESCRIPTIONS

See Figure 2 and Table 1.

en, if the memory is in Read, Erase Suspend Read

or Standby, it will output new valid data in t

PHQ7V1

Address Inputs (A0-A17). Addresses A0 to A17

are common inputs for the Flash chip and the

SRAM chip. The address inputs for the Flash

memory are latched during a write operation on

the falling edge of the Flash Chip Enable (EF) or

Write Enable (WF), while address inputs for the

SRAM array are latched during a write operation

on the falling edge of the SRAM Chip Enable lines

(E1S or E2S) or Write Enable (WS).

Address Inputs (A18-A20). Address A18 to A20

are address inputs for the Flash chip. They are

latched during a write operation on the falling edge

of Flash Chip Enable (EF) or Write Enable (WF).

after the rising edge of RPF. If the memory is in

Erase or Program modes, the operation will be

aborted and the reset recovery will take a maxi-

mum of t

Power Down (when enabled) in t

. The memory will recover from

PLQ7V

after the

PHQ7V2

rising edge of RPF. See Tables 1, 26 and Figure

11.

Flash Write Protect (WPF). Write Protect is an

input to protect or unprotect the two lockable pa-

rameter blocks of the Flash memory. When WPF

is at V , the lockable blocks are protected. Pro-

IL

gram or erase operations are not achievable.

When WPF is at V , the lockable blocks are un-

IH

Data Input/Outputs (DQ0-DQ15). The input is

data to be programmed in the Flash or SRAM

memory array or a command to be written to the

C.I. of the Flash chip. Both are latched on the ris-

ing edge of Flash Chip Enable (EF) or Write En-

able (WF) and, SRAM Chip Enable lines (E1S or

E2S) or Write Enable (WS). The output is data

from the Flash memory or SRAM array, the Elec-

tronic Signature Manufacturer or Device codes or

the Status register Data Polling bit DQ7, the Tog-

gle Bits DQ6 and DQ2, the Error bit DQ5 or the

Erase Timer bit DQ3. Outputs are valid when

Flash Chip Enable (EF) and Output Enable (GF) or

SRAM Chip Enable lines (E1S or E2S) and Output

Enable (GS) are active. The output is high imped-

ance when the both the Flash chip and the SRAM

chip are deselected or the outputs are disabled

protected and they can be programmed or erased

(refer to Table 17).

SRAM Chip Enable (E1S, E2S). The Chip En-

able inputs for SRAM activate the memory control

logic, input buffers and decoders. E1S at V or

IH

E2S at V deselects the memory and reduces the

IL

power consumption to the standby level. E1S and

E2S can also be used to control writing to the

SRAM memory array, while WS remains at V . It

IL

is not allowed to set EF at V , E1S at V and E2S

IL

at V at the same time.

IH

SRAM Write Enable (WS). The Write Enable in-

put controls writing to the SRAM memory array.

WS is active low.

SRAM Output Enable (GS). The Output Enable

gates the outputs through the data buffers during

a read operation of the SRAM chip. GS is active

low.

and when Reset (RPF) is at a V .

IL

Flash Chip Enable (EF). The Chip Enable input

for Flash activates the memory control logic, input

SRAM Upper Byte Enable (UBS). Enable

upper bytes for SRAM (DQ8-DQ15). UBS is active

low.

SRAM Lower Byte Enable (LBS). Enable the

lower bytes for SRAM (DQ0-DQ7). LBS is active

low.

the

buffers, decoders and sense amplifiers. EF at V

IH

deselects the memory and reduces the power con-

sumption to the standby level and output do Hi-Z.

EF can also be used to control writing to the com-

mand register and to the Flash memory array,

while WF remains at V . It is not allowed to set EF

IL

V

DDF

Supply Voltage (1.65V to 2.2V). Flash memo-

at V , E1S at V and E2S at V at the same time.

IL

IH

ry power supply for all operations (Read, Program and

Erase).

Flash Write Enable (WF). The Write Enable in-

put controls writing to the Command Register of

the Flash chip and Address/Data latches. Data are

latched on the rising edge of WF.

Flash Output Enable (GF). The Output Enable

gates the outputs through the data buffers during

a read operation of the Flash chip. When GF and

WF are High the outputs are High impedance.

V

PPF

Programming Voltage (11.4V to 12.6V).

Used to provide high voltage for fast factory pro-

gramming. High voltage on V pin is required to

PPF

use the Double Word Program instruction. It is

also possible to perform word program or erase in-

structions with V

pin grounded.

PPF

V

Supply Voltage (1.65V to 2.2V). SRAM

DDS

Flash Reset/Power Down Input (RPF). The RPF

input provides hardware reset of the memory

(without affecting the Configuration Register sta-

tus), and/or Power Down functions, depending on

the Configuration Register status. Reset/Power

Down of the memory is achieved by pulling RPF to

power supply for all operations (Read, Program).

V

reference for all voltage measurements respec-

tively in the Flash and SRAM chips.

and V Ground. V and V are the

SSF

SSS

SSF

SSS

V

for at least t

. When the reset pulse is giv-

IL

PLPH

5/46

M36DR432A, M36DR432B

Table 3. Main Operation Modes

Operation

(1)

V

EF

GF WF RPF WPF

E1S E2S GS WS

SRAM must be disabled

DQ15-DQ0

PPF

UBS, LBS

Mode

Data

Output

V

IL

V

Read

X

Don't care

or

IL

IH

V

CCF

V

IH

V

IL

V

IH

Write

SRAM must be disabled

Data Input

X

IL

V

PPFH

Block

Locking

V

IL

X

Don't care

IL

IH

V

IH

Standby

Reset

X

Don't care

Any SRAM mode is allowable

Hi-Z

IH

V

X

IL

Output

Disable

V

IH

V

IH

V

Don't care

Any SRAM mode is allowable

Hi-Z

IL

IH

Data out

Word Read

V

Read

Write

Flash must be disabled

IL

IH

IL

IH

IL

Data in

Word Write

V

IL

V

IL

IH

X

Hi-Z

IH

Standby/

Power

Down

V

Any Flash mode is allowable

X

IL

V

X

IH

V

X

IH

Data

Retention

V

X

IL

V

X

IH

Output

Disable

V

IL

V

IH

V

IH

Any Flash mode is allowable

Note: X = V or V , V = 12V ± 5%.

PPFH

X

Hi-Z

IH

IL

IH

1. If UBS and LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBS and LBS separately.

6/46

M36DR432A, M36DR432B

FLASH MEMORY COMPONENT

Organization

The Flash Chip is organized as 2Mb x16 bits. A0-

A20 are the address lines, DQ0-DQ15 are the

Data Input/Output. Memory control is provided by

Chip Enable EF, Output Enable GF and Write En-

able WF inputs.

Reset RPF is used to reset all the memory circuitry

and to set the chip in power down mode if this

function is enabled by a proper setting of the Con-

figuration Register. Erase and Program operations

are controlled by an internal Program/Erase Con-

troller (P/E.C.). Status Register data output on

DQ7 provides a Data Polling signal, DQ6 and DQ2

provide Toggle signals and DQ5 provides error bit

to indicate the state of the P/E.C operations.

and is addressed by A0-A1 address inputs. Read

operations of the Electronic Signature, the Status

Register, the CFI, the Block Protection Status, the

Configuration Register status and the Security

Code are performed as single asynchronous read

cycles (Random Read). Both Chip Enable EF and

Output Enable GF must be at V in order to read

IL

the output of the memory.

Write. Write operations are used to give Instruc-

tion Commands to the memory or to latch Input

Data to be programmed. A write operation is initi-

ated when Chip Enable EF and Write Enable WF

are at V with Output Enable GF at V . Address-

IL

IH

es are latched on the falling edge of WF or EF

whichever occurs last. Commands and Input Data

are latched on the rising edge of WF or EF which-

ever occurs first. Noise pulses of less than 5ns typ-

ical on EF, WF and GF signals do not start a write

cycle.

Dual Bank Operations. The Dual Bank allows to

read data from one bank of memory while a pro-

gram or erase operation is in progress in the other

bank of the memory. Read and Write cycles can

be initiated for simultaneous operations in different

banks without any delay. Status Register during

Program or Erase must be monitored using an ad-

dress within the bank being modified.

Memory Blocks

The device features asymmetrically blocked archi-

tecture. The Flash Chip has an array of 71 blocks

and is divided into two banks A and B, providing

Dual Bank operations. While programming or

erasing in Bank A, read operations are possible

into Bank B or vice versa. The memory also fea-

tures an erase suspend allowing to read or pro-

gram in another block within the same bank. Once

suspended the erase can be resumed. The Bank

Size and Sectorization are summarized in Table 4.

Parameter Blocks are located at the top of the

memory address space for the Top version, and at

the bottom for the Bottom version. The memory

maps are shown in Tables 5, 6, 7 and 8.

The Program and Erase operations are managed

automatically by the P/E.C. Block protection

against Program or Erase provides additional data

security. All blocks are protected at Power Up. In-

structions are provided to protect or unprotect any

block in the application. A second register locks

the protection status while WPF is low (see Block

Locking description). The Reset command does

not affect the configuration of unprotected blocks

and the Configuration Register status.

Output Disable. The data outputs are high im-

pedance when the Output Enable GF is at V with

IH

Write Enable WF at V .

IH

Standby. The memory is in standby when Chip

Enable EF is at V and the P/E.C. is idle. The

IH

power consumption is reduced to the standby level

and the outputs are high impedance, independent

of the Output Enable GF or Write Enable WF in-

puts.

Automatic Standby. When in Read mode, after

150ns of bus inactivity and when CMOS levels are

driving the addresses, the chip automatically en-

ters a pseudo-standby mode where consumption

is reduced to the CMOS standby value, while out-

puts still drive the bus.

Device Operations

The following operations can be performed using

the appropriate bus cycles: Read Array (Random,

and Page Modes), Write command, Output Dis-

able, Standby, Reset/Power Down and Block

Locking. See Table 9.

Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig-

nature, the Status Register, the CFI, the Block

Protection Status or the Configuration Register

status. Read operation of the memory array is per-

formed in asynchronous page mode, that provides

fast access time. Data is internally read and stored

in a page buffer. The page has a size of 4 words

Power Down. The memory is in Power Down

when the Configuration Register is set for Power

Down and RPF is at V . The power consumption

IL

is reduced to the Power Down level, and Outputs

are in high impedance, independent of the Chip

Enable EF, Output Enable GF or Write Enable WF

inputs.

Block Locking. Any combination of blocks can

be temporarily protected against Program or

Erase by setting the lock register and pulling WPF

to V (see Block Lock instruction).

IL

7/46

M36DR432A, M36DR432B

Table 4. Bank Size and Sectorization

Bank Size

Parameter Blocks

Main Blocks

Bank A

Bank B

4 Mbit

8 blocks of 4 KWord

-

7 blocks of 32 KWord

56 blocks of 32 KWord

28 Mbit

Table 5. Bank A, Top Boot Block Addresses

M36DR432A

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

32

130000h-137FFFh

128000h-12FFFFh

120000h-127FFFh

118000h-11FFFFh

110000h-117FFFh

108000h-10FFFFh

100000h-107FFFh

0F8000h-0FFFFFh

0F0000h-0F7FFFh

0E8000h-0EFFFFh

0E0000h-0E7FFFh

0D8000h-0DFFFFh

0D0000h-0D7FFFh

0C8000h-0CFFFFh

0C0000h-0C7FFFh

0B8000h-0BFFFFh

0B0000h-0B7FFFh

0A8000h-0AFFFFh

0A0000h-0A7FFFh

098000h-09FFFFh

090000h-097FFFh

088000h-08FFFFh

080000h-087FFFh

078000h-07FFFFh

070000h-077FFFh

068000h-06FFFFh

060000h-067FFFh

058000h-05FFFFh

050000h-057FFFh

048000h-04FFFFh

040000h-047FFFh

038000h-03FFFFh

030000h-037FFFh

028000h-02FFFFh

020000h-027FFFh

018000h-01FFFFh

010000h-017FFFh

008000h-00FFFFh

000000h-007FFFh

Size

(KWord)

#

Address Range

0

1

4

1FF000h-1FFFFFh

1FE000h-1FEFFFh

1FD000h-1FDFFFh

1FC000h-1FCFFFh

1FB000h-1FBFFFh

1FA000h-1FAFFFh

1F9000h-1F9FFFh

1F8000h-1F8FFFh

1F0000h-1F7FFFh

1E8000h-1EFFFFh

1E0000h-1E7FFFh

1D8000h-1DFFFFh

1D0000h-1D7FFFh

1C8000h-1CFFFFh

1C0000h-1C7FFFh

2

4

3

4

5

4

6

4

7

4

8

32

9

10

11

12

13

14

Table 6. Bank B, Top Boot Block Addresses

M36DR432A

Size

(KWord)

#

Address Range

0

1

32

1B8000h-1BFFFFh

1B0000h-1B7FFFh

1A8000h-1AFFFFh

1A0000h-1A7FFFh

198000h-19FFFFh

190000h-197FFFh

188000h-18FFFFh

180000h-187FFFh

178000h-17FFFFh

170000h-177FFFh

168000h-16FFFFh

160000h-167FFFh

158000h-15FFFFh

150000h-157FFFh

148000h-14FFFFh

140000h-147FFFh

138000h-13FFFFh

32

2

32

3

32

4

32

5

32

6

32

7

32

8

32

9

32

10

11

12

13

14

15

16

32

8/46

M36DR432A, M36DR432B

Table 7. Bank B, Bottom Boot Block Addresses

M36DR432B

18

17

16

15

14

13

12

11

10

9

32

0D0000h-0D7FFFh

0C8000h-0CFFFFh

0C0000h-0C7FFFh

0B8000h-0BFFFFh

0B0000h-0B7FFFh

0A8000h-0AFFFFh

0A0000h-0A7FFFh

098000h-09FFFFh

090000h-097FFFh

088000h-08FFFFh

080000h-087FFFh

078000h-07FFFFh

070000h-077FFFh

068000h-06FFFFh

060000h-067FFFh

058000h-05FFFFh

050000h-057FFFh

048000h-04FFFFh

040000h-047FFFh

Size

#

Address Range

(KWord)

32

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

1F8000h-1FFFFFh

1F0000h-1F7FFFh

1E8000h-1EFFFFh

1E0000h-1E7FFFh

1D8000h-1DFFFFh

1D0000h-1D7FFFh

1C8000h-1CFFFFh

1C0000h-1C7FFFh

1B8000h-1BFFFFh

1B0000h-1B7FFFh

1A8000h-1AFFFFh

1A0000h-1A7FFFh

198000h-19FFFFh

190000h-197FFFh

188000h-18FFFFh

180000h-187FFFh

178000h-17FFFFh

170000h-177FFFh

168000h-16FFFFh

160000h-167FFFh

158000h-15FFFFh

150000h-157FFFh

148000h-14FFFFh

140000h-147FFFh

138000h-13FFFFh

130000h-137FFFh

128000h-12FFFFh

120000h-127FFFh

118000h-11FFFFh

110000h-117FFFh

108000h-10FFFFh

100000h-107FFFh

0F8000h-0FFFFFh

0F0000h-0F7FFFh

0E8000h-0EFFFFh

0E0000h-0E7FFFh

0D8000h-0DFFFFh

8

7

6

5

4

3

2

1

0

Table 8. Bank A, Bottom Boot Block Addresses

M36DR432B

Size

(KWord)

#

Address Range

14

13

12

11

10

9

32

4

038000h-03FFFFh

030000h-037FFFh

028000h-02FFFFh

020000h-027FFFh

018000h-01FFFFh

010000h-017FFFh

008000h-00FFFFh

007000h-007FFFh

006000h-006FFFh

005000h-005FFFh

004000h-004FFFh

003000h-003FFFh

002000h-002FFFh

001000h-001FFFh

000000h-000FFFh

8

7

6

4

5

4

3

4

2

4

1

4

0

4

9/46

M36DR432A, M36DR432B

Table 9. User Bus Operations

(1)

Operation

EF

GF

WF

RPF

WPF

DQ0-DQ15

Data Input

Hi-Z

V

IH

V

IL

V

IH

V

IH

Write

IL

V

IH

V

IH

V

IH

V

IH

Output Disable

Standby

IL

V

IH

V

IH

X

Hi-Z

IH

V

IH

Reset / Power Down

X

Hi-Z

IL

V

IH

V

IL

Block Locking

X

IL

Note: 1. X = Don't care.

Table 10. Read Electronic Signature (AS and Read CFI instructions)

Other

Addresses

Code

Device

EF

GF

WF

A0

A1 A2-A7

DQ0-DQ7 DQ8-DQ15

V

Manufacturer Code

0

Don't Care

20h

A0h

A1h

00h

IL

IH

IL

V

IL

V

IH

M36DR432A

M36DR432B

IL

IH

Device Code

V

IL

V

IH

IL

IH

Table 11. Read Block Protection (AS and Read CFI instructions)

Other

Block Status

EF GF WF A0 A1 A2-A7

A12-A20

DQ0 DQ1 DQ2-DQ15

Addresses

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

Protected Block

Unprotected Block

Locked Block

0

Don't Care Block Address

1

0

X

0

1

0000h

IL

Table 12. Read Configuration Register (AS and Read CFI instructions)

DQ0-DQ9

DQ11-DQ15

RPF Function

EF

GF

WF

A0

A1 A2-A7 Other Addresses

DQ10

V

Reset

Reset/Power Down

0

Don't Care

0

1

Don't Care

IL

IH

V

IH

V

IH

IL

IH

10/46

M36DR432A, M36DR432B

INSTRUCTIONS AND COMMANDS

Seventeen instructions are defined (see Table

15), and the internal P/E.C. automatically handles

all timing and verification of the Program and

Erase operations. The Status Register Data Poll-

ing, Toggle, Error bits can be read at any time, dur-

ing programming or erase, to monitor the progress

of the operation.

Table 13. Commands

Hex Code

00h

Command

Bypass Reset

10h

Bank Erase Confirm

Unlock Bypass

20h

Instructions, made up of one or more commands

written in cycles, can be given to the Program/

Erase Controller through a Command Interface

(C.I.). The C.I. latches commands written to the

memory. Commands are made of address and

data sequences. Two Coded Cycles unlock the

Command Interface. They are followed by an input

command or a confirmation command. The Coded

Sequence consists of writing the data AAh at the

address 555h during the first cycle and the data

55h at the address 2AAh during the second cycle.

30h

Block Erase Resume/Confirm

Double Word Program

40h

Block Protect, or

Block Unprotect, or

Block Lock, or

Write Configuration Register

60h

80h

90h

Set-up Erase

Read Electronic Signature, or

Block Protection Status, or

Configuration Register Status

Instructions are composed of up to six cycles. The

first two cycles input a Coded Sequence to the

Command Interface which is common to all in-

structions (see Table 15). The third cycle inputs

the instruction set-up command. Subsequent cy-

cles output the addressed data, Electronic Signa-

ture, Block Protection, Configuration Register

Status or CFI Query for Read operations. In order

to give additional data protection, the instructions

for Block Erase and Bank Erase require further

command inputs. For a Program instruction, the

fourth command cycle inputs the address and data

to be programmed. For a Double Word Program-

ming instruction, the fourth and fifth command cy-

cles input the address and data to be

programmed. For a Block Erase and Bank Erase

instructions, the fourth and fifth cycles input a fur-

ther Coded Sequence before the Erase confirm

command on the sixth cycle. Any combination of

blocks of the same memory bank can be erased.

Erasure of a memory block may be suspended, in

order to read data from another block or to pro-

gram data in another block, and then resumed.

When power is first applied the command interface

is reset to Read Array.

98h

A0h

B0h

F0h

CFI Query

Program

Erase Suspend

Read Array/Reset

Read/Reset (RD) Instruction. The Read/Reset

instruction consists of one write cycle giving the

command F0h. It can be optionally preceded by

the two Coded Cycles. Subsequent read opera-

tions will read the memory array addressed and

output the data read.

CFI Query (RCFI) Instruction. Common Flash

Interface Query mode is entered writing 98h at ad-

dress 55h. The CFI data structure gives informa-

tion on the device, such as the sectorization, the

command set and some electrical specifications.

Table 18, 19, 20 and 21 show the addresses used

to retrieve each data. The CFI data structure con-

tains also a security area; in this section, a 64 bit

unique security number is written, starting at ad-

dress 80h. This area can be accessed only in read

mode by the final user and there are no ways of

changing the code after it has been written by ST.

Write a read instruction (RD) to return to Read

mode.

Command sequencing must be followed exactly.

Any invalid combination of commands will reset

the device to Read Array. The increased number

of cycles has been chosen to ensure maximum

data security.

Auto Select (AS) Instruction. This instruction uses

two Coded Cycles followed by one write cycle giv-

ing the command 90h to address 555h for com-

mand set-up. A subsequent read will output the

Manufacturer or the Device Code (Electronic Sig-

nature), the Block Protection status or the Config-

uration Register status depending on the levels of

A0 and A1 (see Table 10, 11 and 12). A7-A2 must

be at V , while other address input are ignored.

IL

11/46

M36DR432A, M36DR432B

The bank address is don’t care for this instruction.

The Electronic Signature can be read from the

memory allowing programming equipment or ap-

plications to automatically match their interface to

the characteristics of Flash Chip. The Manufactur-

er Code is output when the address lines A0 and

es the Address on the falling edge of WF or EF and

the Data to be written on the rising edge and starts

the P/E.C. Read operations within the same bank

output the Status Register bits after the program-

ming has started. Memory programming is made

only by writing '0' in place of '1'. Status bits DQ6

and DQ7 determine if programming is on-going

and DQ5 allows verification of any possible error.

A1 are at V , the Device Code is output when A0

IL

is at V with A1 at V .

IH

IL

The codes are output on DQ0-DQ7 with DQ8-

DQ15 at 00h. The AS instruction also allows the

access to the Block Protection Status. After giving

Program (PG) Instruction. This instruction uses

four write cycles. The Program command A0h is

written to address 555h on the third cycle after two

Coded Cycles. A fourth write operation latches the

Address and the Data to be written and starts the

P/E.C. Read operations within the same bank out-

put the Status Register bits after the programming

has started. Memory programming is made only

by writing '0' in place of '1'. Status bits DQ6 and

DQ7 determine if programming is on-going and

DQ5 allows verification of any possible error. Pro-

gramming at an address not in blocks being

erased is also possible during erase suspend.

the AS instruction, A0 is set to V with A1 at V ,

IL

IH

while A12-A20 define the address of the block to

be verified. A read in these conditions will output a

01h if the block is protected and a 00h if the block

is not protected.

The AS Instruction finally allows the access to the

Configuration Register status if both A0 and A1

are set to V . If DQ10 is '0' only the Reset function

IH

is active as RPF is set to V (default at power-up).

IL

If DQ10 is '1' both the Reset and the Power Down

functions will be achieved by pulling RPF to V .

Double Word Program (DPG) Instruction. This

feature is offered to improve the programming

throughput, writing a page of two adjacent words

IL

The other bits of the Configuration Register are re-

served and must be ignored. A reset command

puts the device in read array mode.

in parallel. High voltage (11.4V to 12.6V) on V

PP

pin is required. This instruction uses five write cy-

cles. The double word program command 40h is

written to address 555h on the third cycle after two

Coded Cycles. A fourth write cycle latches the ad-

dress and data to be written to the first location. A

fifth write cycle latches the new data to be written

to the second location and starts the P/E.C.. Note

that the two locations must have the same address

except for the address bit A0. The Double Word

Program can be executed in Bypass mode (DPG-

BY) to skip the two coded cycles at the beginning

of each command.

Block Protect (BP), Block Unprotect (BU),

Block Lock (BL) Instructions. All blocks are

protected at power-up. Each block of the array has

two levels of protection against program or erase

operation. The first level is set by the Block Protect

instruction; a protected block cannot be pro-

grammed or erased until a Block Unprotect in-

struction is given for that block. A second level of

protection is set by the Block Lock instruction, and

requires the use of the WPF pin, according to the

following scheme:

Write Configuration Register (CR) Instruc-

tion. This instruction uses two Coded Cycles fol-

lowed by one write cycle giving the command 60h

to address 555h. A further write cycle giving the

command 03h writes the contents of address bits

A0-A15 to the 16 bits configuration register. Bits

written by inputs A0-A9 and A11-A15 are reserved

for future use. Address input A10 defines the sta-

tus of the Reset/Power Down functions. It must be

set to V to enable only the Reset function and to

IL

V

to enable also the Power Down function. At

IH

Power Up all the Configuration Register bits are

reset to '0'.

Enter Bypass Mode (EBY) Instruction. This in-

struction uses the two Coded cycles followed by

one write cycle giving the command 20h to ad-

dress 555h for mode set-up. Once in Bypass

mode, the device will accept the Exit Bypass

(XBY) and Program or Double Word Program in

Bypass mode (PGBY, DPGBY) commands. The

Bypass mode allows to reduce the overall pro-

gramming time when large memory arrays need to

be programmed.

– when WPF is at V , the Lock status is overrid-

IH

Exit Bypass Mode (XBY) Instruction. This in-

struction uses two write cycles. The first inputs to

the memory the command 90h and the second in-

puts the Exit Bypass mode confirm (00h). After the

XBY instruction, the device resets to Read Memo-

ry Array mode.

Program in Bypass Mode (PGBY) Instruc-

tion. This instruction uses two write cycles. The

Program command A0h is written to any Address

on the first cycle and the second write cycle latch-

den and all blocks can be protected or unpro-

tected;

– when WPF is at V , Lock status is enabled; the

IL

locked blocks are protected, regardless of their

previous protect state, and protection status

cannot be changed. Blocks that are not locked

can still change their protection status, and pro-

gram or erase accordingly;

12/46

M36DR432A, M36DR432B

– the lock status is cleared for all blocks at power

up; once a block has been locked state can be

cleared only with a reset command. The protec-

tion and lock status can be monitored for each

block using the Autoselect (AS) instruction. Pro-

tected blocks will output a ‘1’ on DQ0 and locked

blocks will output a ‘1’ on DQ1.

case of erase failure, a Read/Reset RD instruction

is necessary in order to reset the P/E.C.

Bank Erase (BKE) Instruction. This instruction

uses six write cycles and is used to erase all the

blocks belonging to the selected bank. The Erase

Set-up command 80h is written to address 555h

on the third cycle after the two Coded cycles. The

Bank Erase Confirm command 10h is similarly

written on the sixth cycle after another two Coded

cycles at an address within the selected bank. If

the second command given is not an erase con-

firm or if the Coded cycles are wrong, the instruc-

tion aborts and the device is reset to Read Array.

It is not necessary to program the array with 00h

first as the P/E.C. will automatically do this before

erasing it to FFh. Read operations within the same

bank after the sixth rising edge of WF or EF output

the Status Register bits. During the execution of

the erase by the P/E.C., Data Polling bit DQ7 re-

turns '0', then '1' on completion. The Toggle bit

DQ6 toggles during erase operation and stops

when erase is completed. After completion the

Status Register bit DQ5 returns '1' if there has

been an Erase Failure.

Refer to Table 14 for a list of the protection states.

Block Erase (BE) Instruction. This instruction

uses a minimum of six write cycles. The Erase

Set-up command 80h is written to address 555h

on third cycle after the two Coded cycles. The

Block Erase Confirm command 30h is similarly

written on the sixth cycle after another two Coded

cycles and an address within the block to be

erased is given and latched into the memory.

Additional block Erase Confirm commands and

block addresses can be written subsequently to

erase other blocks in parallel, without further Cod-

ed cycles. All blocks must belong to the same

bank of memory; if a new block belonging to the

other bank is given, the operation is aborted. The

erase will start after an erase timeout period of

100µs. Thus, additional Erase Confirm commands

for other blocks must be given within this delay.

The input of a new Erase Confirm command will

restart the timeout period. The status of the inter-

nal timer can be monitored through the level of

DQ3, if DQ3 is '0' the Block Erase Command has

been given and the timeout is running, if DQ3 is '1',

the timeout has expired and the P/E.C. is erasing

the Block(s). If the second command given is not

an erase confirm or if the Coded cycles are wrong,

the instruction aborts, and the device is reset to

Read Array. It is not necessary to program the

block with 00h as the P/E.C. will do this automati-

cally before erasing to FFh. Read operations with-

in the same bank, after the sixth rising edge of WF

or EF, output the status register bits.

Erase Suspend (ES) Instruction. In a dual bank

memory the Erase Suspend instruction is used to

read data within the bank where erase is in

progress. It is also possible to program data in

blocks not being erased.

The Erase Suspend instruction consists of writing

the command B0h without any specific address.

No Coded Cycles are required. Erase suspend is

accepted only during the Block Erase instruction

execution. The Toggle bit DQ6 stops toggling

when the P/E.C. is suspended within 15µs after

the Erase Suspend (ES) command has been writ-

ten. The device will then automatically be set to

Read Memory Array mode. When erase is sus-

pended, a Read from blocks being erased will out-

put DQ2 toggling and DQ6 at '1'. A Read from a

block not being erased returns valid data. During

suspension the memory will respond only to the

Erase Resume ER and the Program PG instruc-

tions. A Program operation can be initiated during

erase suspend in one of the blocks not being

erased. It will result in DQ6 toggling when the data

is being programmed.

During the execution of the erase by the P/E.C.,

the memory accepts only the Erase Suspend ES

instruction; the Read/Reset RD instruction is ac-

cepted during the 100µs time-out period. Data

Polling bit DQ7 returns '0' while the erasure is in

progress and '1' when it has completed. The Tog-

gle bit DQ6 toggles during the erase operation,

and stops when erase is completed.

Erase Resume (ER) Instruction. If an Erase

Suspend instruction was previously executed, the

erase operation may be resumed by giving the

command 30h, at an address within the bank be-

ing erased and without any Coded Cycle.

After completion the Status Register bit DQ5 re-

turns '1' if there has been an erase failure. In such

a situation, the Toggle bit DQ2 can be used to de-

termine which block is not correctly erased. In the

13/46

M36DR432A, M36DR432B

(1)

Table 14. Protection States

(3)

(2)

Next State After Event

Program/Erase

Allowed

Current State

(WP, DQ1, DQ0)

Protect

101

Unprotect

100

Lock

111

WP transition

100

101

110

111

000

001

yes

no

000

001

011

100

101

100

111

011

yes

no

111

110

111

110

yes

no

001

000

001

000

(4)

011

no

011

111 or 110

Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WPF status.

2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by

DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Autoselect instruction with A1 = V and A0 = V

.

IL

IH

3. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WPF has

changed its logic value.

4. A WPF transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.

IH

(1,2)

Table 15. Instructions

Mne.

Instr.

Cyc.

1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc.

(3)

X

Addr.

Data

1+

Read Memory Array until a new write cycle is initiated.

F0h

Read/Reset

Memory Array

(4)

RD

Addr.

Data

555h

AAh

55h

2AAh

55h

555h

F0h

Read Memory Array until a new

write cycle is initiated.

3+

1+

Addr.

Data

RCFI CFI Query

Read CFI data until a new write cycle is initiated.

98h

Addr.

555h

2AAh

55h

555h

90h

Read electronic Signature or

Block Protection or Configuration

Register Status until a new cycle

is initiated.

(4)

Auto Select

3+

4

AS

Data

AAh

Configura-

tion Data

Addr.

Data

555h

AAh

2AAh

55h

555h

60h

Configuration

Register Write

CR

03h

Program

Address

Addr.

555h

2AAh

555h

Read Data Polling or

Toggle Bit until

Program completes.

PG

Program

4

Program

Data

Addr.

Data

AAh

555h

AAh

55h

2AAh

55h

A0h

555h

40h

Program Program

Address 1 Address 2

Double Word

Program

DPG

EBY

5

3

Note 6, 7

Program Program

Data 1

Data 2

Addr.

Data

555h

AAh

2AAh

55h

555h

20h

Enter Bypass

Mode

14/46

M36DR432A, M36DR432B

Mne.

Instr.

Cyc.

1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc.

Addr.

Data

X

Exit Bypass

Mode

XBY

2

90h

00h

Program

Address

Addr.

Data

Addr.

Data

X

A0h

X

Program in

Bypass Mode

Read Data Polling or Toggle Bit until Program

completes.

PGBY

2

3

Program

Data

Program Program

Address 1 Address 2

Double Word

DPGBY Program in

Note 6, 7

Program Program

Bypass Mode

40h

Data 1

2AAh

55h

Data 2

555h

60h

Block

Address

Addr.

Data

Addr.

Data

Addr.

Data

Addr.

Data

Addr.

Data

555h

AAh

BP

BU

BL

BE

Block Protect

Block Unprotect

Block Lock

4

1

01h

Block

Address

555h

AAh

2AAh

55h

555h

60h

D0h

Block

Address

555h

AAh

2AAh

55h

555h

60h

4

2Fh

555h

AAh

555h

AAh

Block

Address

555h

AAh

2AAh

55h

555h

80h

2AAh

55h

Block Erase

6+

30h

Bank

Address

555h

2AAh

55h

555h

80h

2AAh

55h

BKE Bank Erase

6

1

AAh

X

10h

(3)

Addr.

Data

Read until Toggle stops, then read all the data needed

from any Blocks not being erased then Resume Erase.

ES

ER

Erase Suspend

Erase Resume

B0h

Bank

Address

Addr.

Read Data Polling or Toggle Bits until Erase completes or

Erase is suspended another time

Data

30h

Note: 1. Commands not interpreted in this table will default to read array mode.

2. For Coded cycles address inputs A11-A20 are don't care.

3. X = Don't Care.

4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-

mand cycles.

5. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.

6. Program Address 1 and Program Address 2 must be consecutive addresses differing only for address bit A0.

7. High voltage on V

(11.4V to 12.6V) is required for the proper execution of the Double Word Program instruction.

PPF

15/46

M36DR432A, M36DR432B

STATUS REGISTER BITS

P/E.C. status is indicated during execution by Data

Polling on DQ7, detection of Toggle on DQ6 and

DQ2, or Error on DQ5 bits. Any read attempt within

the Bank being modified and during Program or

Erase command execution will automatically out-

put these five Status Register bits. The P/E.C. au-

tomatically sets bits DQ2, DQ5, DQ6 and DQ7.

Other bits (DQ0, DQ1 and DQ4) are reserved for

future use and should be masked (see Tables 17

and 16). Read attempts within the bank not being

modified will output array data.

Data Polling Bit (DQ7). When Programming op-

erations are in progress, this bit outputs the com-

plement of the bit being programmed on DQ7. In

case of a double word program operation, the

complement is done on DQ7 of the last word writ-

ten to the command interface, i.e. the data written

in the fifth cycle. During Erase operation, it outputs

a '0'. After completion of the operation, DQ7 will

output the bit last programmed or a '1' after eras-

ing. Data Polling is valid and only effective during

P/E.C. operation, that is after the fourth WF pulse

for programming or after the sixth WF pulse for

erase. It must be performed at the address being

programmed or at an address within the block be-

ing erased. See Figure 25 for the Data Polling

flowchart and Figure 12 for the Data Polling wave-

forms. DQ7 will also flag the Erase Suspend mode

by switching from '0' to '1' at the start of the Erase

Suspend. In order to monitor DQ7 in the Erase

Suspend mode an address within a block being

erased must be provided. For a Read Operation in

Suspend mode, DQ7 will output '1' if the read is at-

tempted on a block being erased and the data val-

ue on other blocks. During Program operation in

Erase Suspend Mode, DQ7 will have the same be-

havior as in the normal program execution outside

of the suspend mode.

pend block. When erase is suspended DQ6 will

toggle during programming operations in a block

different from the block in Erase Suspend. Either

EF or GF toggling will cause DQ6 to toggle. See

Figure 25 for Toggle Bit flowchart and Figure 13

for Toggle Bit waveforms.

Toggle Bit (DQ2). This toggle bit, together with

DQ6, can be used to determine the device status

during the Erase operations. During Erase Sus-

pend a read from a block being erased will cause

DQ2 to toggle. A read from a block not being

erased will output data. DQ2 will be set to '1' during

program operation and to ‘0’ in Erase operation.

After erase completion and if the error bit DQ5 is

set to '1', DQ2 will toggle if the faulty block is ad-

dressed.

Error Bit (DQ5). This bit is set to '1' by the P/E.C.

when there is a failure of programming or block

erase, that results in invalid data in the memory

block. In case of an error in block erase or pro-

gram, the block in which the error occurred or to

which the programmed data belongs, must be dis-

carded. Other Blocks may still be used. The error

bit resets after a Read/Reset (RD) instruction. In

case of success of Program or Erase, the error bit

will be set to '0'.

Erase Timer Bit (DQ3). This bit is set to ‘0’ by the

P/E.C. when the last block Erase command has

been entered to the Command Interface and it is

awaiting the Erase start. When the erase timeout

period is finished, DQ3 returns to ‘1’, in the range

of 80µs to 120µs.

Table 16. Polling and Toggle Bits

Mode

DQ7

0

DQ6

DQ2

1

Program

Erase

Toggle

Toggle Bit (DQ6). When Programming or Eras-

ing operations are in progress, successive at-

tempts to read DQ6 will output complementary

data. DQ6 will toggle following toggling of either

N/A

Erase Suspend Read

(in Erase Suspend

block)

1

Toggle

GF, or EF when GF is at V . The operation is com-

IL

pleted when two successive reads yield the same

output data. The next read will output the bit last

programmed or a '1' after erasing. The toggle bit

DQ6 is valid only during P/E.C. operations, that is

after the fourth WF pulse for programming or after

the sixth WF pulse for Erase. DQ6 will be set to '1'

if a Read operation is attempted on an Erase Sus-

Erase Suspend Read

(outside Erase Suspend

block)

DQ7

DQ6

DQ2

1

Erase Suspend Program

Toggle

16/46

M36DR432A, M36DR432B

(1)

Table 17. Status Register Bits

DQ

Name

Logic Level

Definition

Note

Erase Complete or erase block

in Erase Suspend.

'1'

'0'

Indicates the P/E.C. status, check

during Program or Erase, and on

completion before checking bits DQ5

for Program or Erase Success.

Erase On-going

Data

Polling

7

Program Complete or data of

non erase block during Erase

Suspend.

DQ

(2)

DQ

'-1-0-1-0-1-0-1-'

DQ

Program On-going

Erase or Program On-going

Program Complete

Successive reads output

complementary data on DQ6 while

Programming or Erase operations are

on-going. DQ6 remains at constant

level when P/E.C. operations are

completed or Erase Suspend is

acknowledged.

6

Toggle Bit

Erase Complete or Erase

Suspend on currently addressed

block

'-1-1-1-1-1-1-1-'

'1'

'0'

Program or Erase Error

This bit is set to '1' in the case of

Programming or Erase failure.

5

4

Error Bit

Program or Erase On-going

Reserved

P/E.C. Erase operation has started.

Only possible command entry is Erase

Suspend (ES)

'1'

'0'

Erase Timeout Period Expired

Erase Timeout Period On-going

Erase Time

Bit

3

An additional block to be erased in

parallel can be entered to the P/E.C:

Erase Suspend read in the

Erase Suspended Block.

Erase Error due to the currently

addressed block (when DQ5 =

'1').

'-1-0-1-0-1-0-1-'

Indicates the erase status and allows

to identify the erased block.

2

Toggle Bit

Program on-going or Erase

Complete.

1

Erase Suspend read on non

Erase Suspend block.

DQ

1

0

Reserved

Note: 1. Logic level '1' is High, '0' is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

2. In case of double word program DQ7 refers to the last word input.

17/46

M36DR432A, M36DR432B

POWER CONSUMPTION

Power Down

Power Up

The memory provides Reset/Power Down control

input RPF. The Power Down function can be acti-

vated only if the relevant Configuration Register bit

is set to '1'. In this case, when the RPF signal is

The memory Command Interface is reset on Pow-

er Up to Read Array. Either EF or WF must be tied

to V during Power Up to allow maximum security

IH

and the possibility to write a command on the first

rising edge of WF.

pulled at V the supply current drops to typically

SS

I

(see Table 24), the memory is deselected and

CC2

Supply Rails

Normal precautions must be taken for supply volt-

age decoupling; each device in a system should

the outputs are in high impedance.If RPF is pulled

to V during a Program or Erase operation, this

operation is aborted in t

content is no longer valid (see Reset/Power Down

input description).

SS

and the memory

PLQ7V

have the V

rails decoupled with a 0.1µF capac-

CCF

itor close to the V

and V pins. The PCB trace

CCF

SS

widths should be sufficient to carry the required

program and erase currents.

V

CCF

18/46

M36DR432A, M36DR432B

COMMON FLASH INTERFACE (CFI)

The Common Flash Interface (CFI) specification is

a JEDEC approved, standardised data structure

that can be read from the Flash memory device.

CFI allows a system software to query the flash

device to determine various electrical and timing

parameters, density information and functions

supported by the device. CFI allows the system to

easily interface to the Flash memory, to learn

about its features and parameters, enabling the

software to configure itself when necessary.

The CFI data structure gives information on the

device, such as the sectorization, the command

set and some electrical specifications. Tables 18,

19, 20, and 21 show the addresses used to re-

trieve each data. The CFI data structure contains

also a security area; in this section, a 64 bit unique

security number is written, starting at address 81h.

This area can be accessed only in read mode and

there are no ways of changing the code after it has

been written by ST. Write a read instruction to re-

turn to Read mode. Refer to the CFI Query instruc-

tion to understand how the M36DR432 enters the

CFI Query mode.

Tables 18, 19, 20, and 21 show the address used

to retrieve each data.

Table 18. Query Structure Overview

Offset

00h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

10h

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Additional information specific to the Alternate

Algorithm (optional)

Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections

detailed in Tables 19, 20 and 21. Query data are always presented on the lowest order data outputs.

Table 19. CFI Query Identification String

Offset

Data

Description

00h

0020h

Manufacturer Code

Device Code

Reserved

00A0h - top

00A1h - bottom

01h

02h-0Fh

10h

reserved

0051h

Query Unique ASCII String "QRY"

11h

0052h

12h

0059h

13h

0002h

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code

defining a specific algorithm

14h

0000h

15h

offset = P = 0040h

0000h

Address for Primary Algorithm extended Query table

16h

17h

0000h

Alternate Vendor Command Set and Control Interface ID Code second vendor

- specified algorithm supported (note: 0000h means none exists)

18h

0000h

19h

value = A = 0000h

0000h

Address for Alternate Algorithm extended Query table

note: 0000h means none exists

1Ah

Note: 1. Query data are always presented on the lowest - order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

19/46

M36DR432A, M36DR432B

Table 20. CFI Query System Interface Information

Offset

Data

Description

V

CCF

V

CCF

V

PPF

Logic Supply Minimum Program/Erase or Write voltage

1Bh

0017h

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 millivolts

Logic Supply Maximum Program/Erase or Write voltage

1Ch

1Dh

0022h

0000h

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 millivolts

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

Note: This value must be 0000h if no V pin is present

PP

V

[Programming] Supply Maximum Program/Erase voltage

PPF

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

1Eh

00C0h

Note: This value must be 0000h if no V pin is present

PP

n

Typical timeout per single byte/word program (multi-byte program count = 1), 2 µs

(if supported; 0000h = not supported)

1Fh

20h

21h

22h

23h

24h

25h

26h

0004h

0000h

000Ah

0000h

0004h

0000h

0004h

0000h

n

Typical timeout for maximum-size multi-byte program or page write, 2 µs

(if supported; 0000h = not supported)

n

Typical timeout per individual block erase, 2 ms

(if supported; 0000h = not supported)

n

Typical timeout for full chip erase, 2 ms

(if supported; 0000h = not supported)

n

Maximum timeout for byte/word program, 2 times typical (offset 1Fh)

(0000h = not supported)

n

Maximum timeout for multi-byte program or page write, 2 times typical (offset 20h)

(0000h = not supported)

n

Maximum timeout per individual block erase, 2 times typical (offset 21h)

(0000h = not supported)

n

Maximum timeout for chip erase, 2 times typical (offset 22h)

(0000h = not supported)

20/46

M36DR432A, M36DR432B

Table 21. Device Geometry Definition

Offset Word

Data

Description

Mode

n

27h

28h

29h

2Ah

2Bh

2Ch

0016h

0001h

0000h

0002h

Device Size = 2 in number of bytes

Flash Device Interface Code description: Asynchronous x16

n

Maximum number of bytes in multi-byte program or page = 2

Number of Erase Block Regions within device

bit 7 to 0 = x = number of Erase Block Regions

Note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk."

2. x specifies the number of regions within the device containing one or more con-

tiguous Erase Blocks of the same size. For example, a 128KB device (1Mb)

having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is considered

to have 5 Erase Block Regions. Even though two regions both contain 16KB

blocks, the fact that they are not contiguous means they are separate Erase

Block Regions.

3. By definition, symmetrically block devices have only one blocking region.

M36DR432A M36DR432A Erase Block Region Information

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

003Eh

0000h

0001h

0007h

0000h

0020h

0000h

bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes in

size. The value z = 0 is used for 128 byte block size.

e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K

bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase

Block Region:

e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number]

y = 0 means no blocking (# blocks = y+1 = "1 block")

Note: y = 0 value must be used with number of block regions of one as indicated

by (x) = 0

M36DR432B M36DR432B

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

0007h

0000h

0020h

0000h

003Eh

0000h

0001h

21/46

M36DR432A, M36DR432B

SRAM COMPONENT

Device Operations

The following operations can be performed using

the appropriate bus cycles: Read Array, Write Ar-

ray, Output Disable, Power Down (see Table 3).

occurring edge. The Write cycle can be terminated

by the rising edge of E1S, the rising edge of WS or

the falling edge of E2S, whichever occurs first.

If the Output is enabled (E1S=V , E2S=V and

IL

IH

GS=V ), then WS will return the outputs to high

IL

Read. Read operations are used to output the

contents of the SRAM Array. The SRAM is in Read

impedance within t

of its falling edge. Care

WLQZ

must be taken to avoid bus contention in this type

of operation. Data input must be valid for t

mode whenever Write Enable (WS) is at V with

IH

DVWH

Output Enable (GS) at V , and both Chip Enables

IL

before the rising edge of Write Enable, or for

(E1S and E2S) and UBS, LBS combinations are

asserted.

Valid data will be available at the output pins within

t

before the rising edge of E1S or for t

DVE1H

DVE2L

before the falling edge of E2S, whichever occurs

first, and remain valid for t , t or t

WHDX E1HAX

E2LAX

t

after the last stable address, providing GS is

AVQV

(see Table 32, Figure 19, 21, 23).

Low, E1S is Low and E2S is High. If Chip Enable

or Output Enable access times are not met, data

access will be measured from the limiting parame-

Standby/Power-Down. The SRAM chip has a

Chip Enable power-down feature which invokes

an automatic standby mode (see Table 31, Figure

18) whenever either Chip Enable is de-asserted

ter (t

, t

, or t

) rather than the ad-

E1LQV E2HQV

GLQV

dress. Data out may be indeterminate at t

,

E1LQX

(E1S=V or E2S=V ).

IH

IL

t

and t

, but data lines will always be val-

GLQX

E2HQX

id at t

(see Table 31, Figures 16 and 17).

Data Retention

AVQV

Write. Write operations are used to write data in

the SRAM. The SRAM is in Write mode whenever

the WS and E1S pins are at V , with E2S at V .

Either the Chip Enable inputs (E1S and E2S) or

the Write Enable input (WS) must be de-asserted

during address transitions for subsequent write cy-

cles. Write begins with the concurrence of both

The SRAM data retention performances as V

CCS

go down to V are described in Table 33 and Fig-

DR

ure 23, 24. In E1S controlled data retention mode,

minimum standby current mode is entered when

IL

IH

E1S ≥ V

E2S ≥ V

– 0.2V

and

E2S ≤ 0.2V

or

CCS

– 0.2V. In E2S controlled data reten-

tion mode, minimum standby current mode is en-

tered when E2S ≤ 0.2V.

Output Disable. The data outputs are high im-

pedance when the Output Enable (GS) is at V

Chip Enables being active with WS at V . A Write

IL

begins at the latest transition among E1S going to

V , E2S going to V and WS going to V . There-

IL

IH

IL

IH

fore, address setup time is referenced to Write En-

able and both Chip Enables as t , t and

with Write Enable (WS) at V .

IH

AVWL AVE1L

t

respectively, and is determined by the latter

AVE2H

22/46

M36DR432A, M36DR432B

Table 22. AC Measurement Conditions

Figure 6. AC Measurement Load Circuit

Input Rise and Fall Times

≤ 4ns

VDD

V

DD

0 to V

Input Pulse Voltages

DD

V

/2

Input and Output Timing Ref. Voltages

DD

25kΩ

Figure 5. AC Measurement Waveform

DEVICE

UNDER

TEST

V

DD

25kΩ

0.1µF

C

L

= 50pF

V

/2

DD

0V

AI90206

AI90207

C

includes JIG capacitance

L

Note: V means V

= V

DDS

DD

DDF

(1)

Table 23. Device Capacitance

(T = 25 °C, f = 1 MHz)

A

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

10

Unit

pF

C

IN

V

= 0V

IN

C

V

OUT

12

pF

OUT

Note: 1. Sampled only, not 100% tested.

23/46

M36DR432A, M36DR432B

Table 24. DC Characteristics

(T = –40 to 85°C; V

= V

= 1.65V to 2.2V)

A

DDF

DDS

Symbol

Parameter

Device

Test Condition

Min

Typ

Max

Unit

Input Leakage

Current

Flash &

SRAM

I

0V ≤ V ≤ V

±2

µA

LI

IN

DD

Output Leakage

Current

Flash &

SRAM

I

0V ≤ V

≤ V

DD

±10

50

µA

LO

OUT

EF = V

± 0.2V

DDF

Flash

SRAM

Flash

15

20

2

V

= V max

DD

DDF

V

Standby

DD

I

DDS

E1S ≥ V

– 0.2V, E2S ≤ V

– 0.2V,

DDS

Current

V

≥ V

– 0.2V

50

10

µA

IN

DDS

or V ≤ V

– 0.2V, f=0

± 0.2V

SSF

IN

DDS

Supply Current

(Reset)

RPF = V

DDD

I

= 0 mA, E1S = V , E2S = WS = V

,

IO

IL

IH

V

= V or V , V

= V max,

mA

IN

IL

IH

DDS

DD

cycle time = 1µs

I

Supply Current

SRAM

DD

= 0 mA, E1S = V , E2S = WS = V

IO

IL

V

IN

= V or V , V

= V max,

25

mA

IL

IH

DDS

DD

min cycle time

Supply Current

(Read)

I

EF = V , GF = V , f = 5 MHz

Flash

10

20

10

20

40

20

50

mA

µA

DDR

IL

IH

Supply Current

(Program)

I

Program in progress

DDW

Supply Current

(Dual Bank)

Program/Erase in progress in one bank

Read in the other bank

I

DDWD

Supply Current

(Erase)

I

Erase in progress

DDE

Supply Current

(Erase Suspend)

(1)

Erase Suspend in progress

I

DDES

Supply Current

(Program

(1)

Program Suspend in progress

Flash

50

µA

I

DDWS

Suspend)

V

≤ V

DDS

0.2

100

0.2

5

µA

PPF

Program Current

(Standby)

I

Flash

PPS

V

= 12V ± 0.6V

400

5

PPF

V

PPF

≤ V

DDS

Program Current

(Read)

I

PPR

V

= 12V ± 0.6V

100

400

PPF

= 12V ± 0.6V

Program Current

(Program)

PPF

I

Flash

5

10

mA

PPW

Program in progress

V

= 12V ± 0.6V

Program Current

(Erase)

PPF

I

mA

V

PPE

Program in progress

Flash &

SRAM

V

Input Low Voltage

–0.5

1.4

0.4

IL

Input High

Voltage

Flash &

SRAM

V

+0.3

V

IH

DD

V

= V

= V min

DDS DD

= 100µA

Output Low

Voltage

Flash &

SRAM

DDF

V

0.2

V

OL

I

OL

= V

= V min

DD

Output High

Voltage

Flash &

SRAM

DDF

DDS

V

DD

–0.1

V

OH

I

= –100µA

OH

24/46

M36DR432A, M36DR432B

Symbol

Parameter

Device

Test Condition

Min

Typ

Max

Unit

Program Voltage

(Program or

V

PPL

Flash

1.65

3.6

V

Erase operations)

Program Voltage

(Program or

Erase operations)

V

Flash

11.4

12.6

1

V

PPH

Program Voltage

(Program and

V

PPLK

Erase lock-out)

V

Supply

DDF

Voltage (Program

and Erase lock-

out)

V

LKO

Flash

2

V

Note: 1. I

DDES

and I

DDWS

are specified with device deselected. If device is read while in erase suspend, current draw is sum of I

DDES

and I

If the device is read while in program suspend, current draw is the sum of I

DDWS

and I .

DDR

DDR.

Table 25. Flash Read AC Characteristics

(TA = –40 to 85°C; V

= 1.65V to 2.2V)

DDF

Flash

Symbol

Alt

Parameter

Test Condition

100

Max

120

Unit

Min

Max

Address Valid to Next Address

Valid

t

EF = V , GF = V

100

120

ns

AVAV

RC

IL

Address Valid to Output Valid

(Random)

t

EF = V , GF = V

100

35

120

45

AVQV

ACC

IL

Address Valid to Output Valid

(Page)

t

EF = V , GF = V

AVQV1

PAGE

IL

Address Transition to Output

Transition

t

EF = V , GF = V

0

AXQX

OH

IL

Chip Enable High to Output

Transition

t

GF = V

EHQX

OH

IL

(1)

t

GF = V

Chip Enable High to Output Hi-Z

Chip Enable Low to Output Valid

25

35

ns

t

HZ

IL

EHQZ

(2)

t

GF = V

100

120

t

CE

IL

ELQV

Chip Enable Low to Output

Transition

(1)

t

GF = V

0

ns

t

LZ

IL

ELQX

Output Enable High to Output

Transition

t

EF = V

GHQX

OH

IL

Output Enable High to Output

Hi-Z

(1)

t

DF

EF = V

25

35

t

IL

GHQZ

Output Enable Low to Output

Valid

(2)

(1)

t

EF = V

t

OE

IL

GLQV

GLQX

Output Enable Low to Output

Transition

t

EF = V

0

OLZ

IL

Note: 1. Sampled only, not 100% tested.

2. GF may be delayed by up to t

- t

after the falling edge of EF without increasing t

ELQV

ELQV GLQV

25/46

M36DR432A, M36DR432B

Figure 7. Flash Read AC Waveforms

26/46

M36DR432A, M36DR432B

Figure 8. Flash Page Read AC Waveforms

27/46

M36DR432A, M36DR432B

Table 26. Flash Write AC Characteristics, Write Enable Controlled

(T = –40 to 85 °C; V

A

= 1.65V to 2.2V

DDF

Flash

Symbol

Alt

Parameter

100

120

Unit

Min

100

0

Max

Min

Max

t

WC

Address Valid to Next Address Valid

Address Valid to Write Enable Low

120

0

ns

µs

ns

AVAV

t

AVWL

AS

DS

CS

t

Input Valid to Write Enable High

50

0

50

0

DVWH

t

Chip Enable Low to Write Enable Low

Output Enable High to Write Enable Low

RPF Low to Reset Complete During Program/Erase

ELWL

t

0

GHWL

t

15

PLQ7V

t

V

CCF

High to Chip Enable Low

50

0

50

0

VDHEL

VCS

t

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Output Enable Low

Write Enable High to Write Enable Low

Write Enable Low to Address Transition

Write Enable Low to Write Enable High

WHDX

DH

CH

t

0

WHEH

t

30

50

30

50

WHGL

OEH

t

WHWL

WPH

t

AH

WLAX

t

WLWH

WP

Figure 9. Flash Write AC Waveforms, WF Controlled

tAVAV

A0-A20

VALID

tWLAX

tAVWL

tWHEH

EF

tELWL

tWHGL

GF

tGHWL

tWLWH

WF

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ15

V

DDF

tVDHEL

AI90210

Note: 1. Address are latched on the falling edge of WF, Data is latched on the rising edge of WF.

28/46

M36DR432A, M36DR432B

Table 27. Flash Write AC Characteristics, Chip Enable Controlled

(T = –40 to 85 °C; V = 1.65V to 2.2V)

A

DDF

Flash

Symbol

Alt

Parameter

100

120

Unit

Min

100

0

Max

Min

120

0

Max

t

WC

Address Valid to Next Address Valid

Address Valid to Chip Enable Low

ns

µs

ns

AVAV

t

AVEL

AS

t

Input Valid to Chip Enable High

50

0

50

0

DVEH

DS

t

Chip Enable High to Input Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

Chip Enable High to Write Enable High

Chip Enable Low to Address Transition

Chip Enable Low to Chip Enable High

Output Enable High Chip Enable Low

RPF Low to Reset Complete During Program/Erase

EHDX

DH

t

30

0

30

0

EHEL

CPH

t

EHGL

OEH

t

EHWH

WH

t

AH

50

0

50

0

ELAX

t

ELEH

CP

t

GHEL

t

15

PLQ7V

t

V

CCF

High to Write Enable Low

50

0

50

0

VDHWL

VCS

t

WS

Write Enable Low to Chip Enable Low

WLEL

Figure 10. Flash Write AC Waveforms, EF Controlled

tAVAV

A0-A20

VALID

tELAX

tAVEL

tEHWH

WF

tWLEL

tEHGL

GF

tGHEL

tELEH

EF

tEHEL

tEHDX

tDVEH

VALID

DQ0-DQ15

V

DDF

tVDHWL

AI90211

Note: Address are latched on the falling edge of EF, Data is latched on the rising edge of EF.

29/46

M36DR432A, M36DR432B

Table 28. Flash Read and Write AC Characteristics, RPF Related

(T = –40 to 85°C; V

A

= 1.65V to 2.2V)

DDF

Flash

Symbol

Alt

Parameter

Test Condition

100

120

Unit

Min

Max

Min

Max

RPF High to Data Valid (Read

Mode)

t

150

50

150

ns

PHQ7V1

RPF High to Data Valid

(Power Down enabled)

t

50

µs

ns

µs

PHQ7V2

t

RPF Pulse Width

100

PLPH

RP

RPF Low to Reset Complete

During Program/Erase

t

15

PLQ7V

Figure 11. Flash Read and Write AC Waveforms, RPF Related

READ

PROGRAM / ERASE

WF

DQ7

VALID

RPF

tPLPH

tPHQ7V1,2

tPLQ7V

AI90212

30/46

M36DR432A, M36DR432B

Table 29. Flash Program, Erase Times and Program, Erase Endurance Cycles

(T = –40 to 85°C; V

A

= 1.65V to 2.2V, V

= V

unless otherwise specified)

DDF

PPF

DDF

Typical after

100k W/E Cycles

(1)

Parameter

Min

Typ

Unit

Max

Parameter Block (4 KWord) Erase (Preprogrammed)

Main Block (32 KWord) Erase (Preprogrammed)

Bank Erase (Preprogrammed, Bank A)

2.5

10

0.15

1

0.4

3

s

2

6

Bank Erase (Preprogrammed, Bank B)

10

20

30

25

(2)

Chip Program

(2)

10

s

Chip Program (DPG, V = 12V)

PP

Word Program

200

10

µs

Program/Erase Cycles (per Block)

100,000

cycles

Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or

erase should perform significantly better.

2. Excludes the time needed to execute the sequence for program instruction.

(1)

Table 30. Flash Data Polling and Toggle Bits AC Characteristics

(T = –40 to 85 °C; V

A

= 1.65V to 2.2V)

DDF

Flash

Symbol

Parameter

Unit

Min

10

1

Max

200

10

Chip Enable High to DQ7 Valid (Program, EF Controlled)

Chip Enable High to DQ7 Valid (Block Erase, EF Controlled)

Chip Enable High to Output Valid (Program)

µs

s

t

EHQ7V

10

1

200

10

µs

s

t

EHQV

Chip Enable High to Output Valid (Block Erase)

Q7 Valid to Output Valid (Data Polling)

t

0

ns

µs

Q7VQV

Write Enable High to DQ7 Valid (Program, WF Controlled)

10

1

200

t

WHQ7V

Write Enable High to DQ7 Valid (Block Erase, WF

Controlled)

10

s

Write Enable High to Output Valid (Program)

Write Enable High to Output Valid (Block Erase)

10

1

200

10

µs

s

t

WHQV

Note: 1. All other timings are defined in Read AC Characteristics table.

31/46

M36DR432A, M36DR432B

Figure 12. Flash Data Polling DQ7 AC Waveforms

32/46

M36DR432A, M36DR432B

Figure 13. Flash Data Toggle DQ6, DQ2 AC Waveforms

33/46

M36DR432A, M36DR432B

Figure 14. Flash Data Polling Flowchart

Figure 15. Flash Data Toggle Flowchart

START

READ

DQ5 & DQ6

READ DQ5 & DQ7

at VALID ADDRESS

DQ6

NO

=

DQ7

=

DATA

YES

TOGGLES

NO

YES

NO

DQ5

= 1

DQ5

= 1

YES

READ DQ7

READ DQ6

DQ7

=

DATA

YES

DQ6

=

NO

TOGGLES

NO

YES

FAIL

PASS

FAIL

PASS

AI90215

AI90216

34/46

M36DR432A, M36DR432B

Table 31. SRAM Read AC Characteristics

(T = –40 to 85°C; V = 1.65V to 2.2V)

A

DDS

SRAM

Unit

Symbol

Alt

Parameter

Min

Max

t

Read Cycle Time

100

ns

AVAV

RC

t

Address Valid to Output Valid

100

AVQV

AA

t

Address Transition to Output Transition

UBS, LBS Disable to Hi-Z Output

UBS, LBS Access Time

15

AXQX

OH

t

BHZ

25

BHQZ

t

100

BLQV

BA

t

UBS, LBS Enable to Low-Z Output

Chip Enable 1 High to Output Hi-Z

Chip Enable 1 Low to Output Valid

Chip Enable 1 Low to Output Transition

Chip Enable 2 High to Output Valid

Chip Enable 2 High to Output Transition

Chip Enable 2 Low to Output Hi-Z

Output Enable High to Output Hi-Z

Output Enable Low to Output Valid

Output Enable Low to Output Transition

5

0

BLQX

BLZ

t

30

E1HQZ

HZ1

t

100

E1LQV

CO1

t

10

E1LQX

LZ1

t

100

E2HQV

CO2

t

10

0

E2HQX

LZ2

HZ2

OHZ

t

25

30

35

E2LQZ

t

0

GHQZ

t

GLQV

OE

t

OLZ

5

0

GLQX

Chip Enable 1 High or Chip Enable 2 Low to Power

Down

(1)

100

ns

t

PD

(1)

Chip Enable 1 Low or Chip Enable 2 High to Power Up

PU

Note: 1. Sampled only. Not 100% tested.

Figure 16. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V

IL

tAVAV

A0-A17

VALID

tAVQV

tAXQX

DQ0-DQ15

DATA VALID

AI90217

Note: E1S = Low, E2S = High, GS = Low, WS = High.

35/46

M36DR432A, M36DR432B

Figure 17. SRAM Read AC Waveforms, E1S, E2S or GS Controlled

tAVAV

A0-A17

E1S

VALID

tAVQV

tE1LQV

tAXQX

tE1HQZ

tE1LQX

tE2HQV

tE2LQZ

tBHQZ

E2S

tE2HQX

tBLQV

UBS, LBS

tBLQX

tGLQV

tGHQZ

GS

tGLQX

DQ0-DQ15

DATA VALID

AI90218

Note: Write Enable (WS) = High.

Figure 18. SRAM Standby AC Waveforms

E1S

E2S

tPU

tPD

I

DD

50%

AI90219

36/46

M36DR432A, M36DR432B

Table 32. SRAM Write AC Characteristics

(T = –40 to 85°C; V = 1.65V to 2.2V)

A

DDS

SRAM

Unit

Symbol

Alt

Parameter

Min

Max

t

WC

Write Cycle Time

100

ns

AVAV

(1)

t

Address Valid to Chip Enable 1 Low

Address Valid to Chip Enable 2 High

Address Valid to Write Enable High

Address Valid to Write Enable Low

0

t

AVE1L

AS

(1)

t

AVE2H

AS

t

80

0

AVWH

AW

(1)

t

AVWL

AS

t

UBS, LBS Valid to End of Write

Input Valid to Chip Enable 1 High

Input Valid to Chip Enable 2 Low

Input Valid to Write Enable High

Chip Enable 1 High to Address Transition

80

40

0

ns

t

BLWH

BW

t

DVE1H

DW

t

DVE2L

DW

t

DVWH

(2)

(3)

(2)

t

E1HAX

WR

t

,

E1LWH

Chip Select to End of Write

80

0

ns

t

CW

E2HWH

t

Chip Enable 2 Low to Address Transition

Output Enable Higt to Output Hi-Z

ns

t

E2LAX

WR

t

25

35

GHQZ

WHAX

WHDX

GHZ

(2)

t

Write Enable High to Address Transition

0

t

WR

t

Write Enable High to Input Transition

Write Enable High to Output Transition

Write Enable Low to Output Hi-Z

0

5

ns

DH

t

WHQX

OW

t

WLQZ

WHZ

(4)

t

Write Enable Pulse Width

70

ns

WLWH

t

WP

Note: 1. t is measured from the address valid to the beginning of write.

AS

2. t

3. t

is measured from the end or write to the address change. t

is measured from E1S going low end of write.

applied in case a write ends as E1S or WS going high.

WR

CW

4. A Write occurs during the overlap (t ) of low E1S and low WS. A write begins when E1S goes low and WS goes low with asserting

WP

UBS or LBS for single byte operation or simultaneously asserting UBS and LBS for double byte operation. A write ends at the ear-

liest transition when E1S goes high and WS goes high. The t

is measured from the beginning of write to the end of write.

WP

37/46

M36DR432A, M36DR432B

Figure 19. SRAM Write AC Waveforms, WS Controlled with GS Low

tAVAV

A0-A17

VALID

tAVWH

tE1LWH

tAVE1L

tWHAX

E1S

E2S

tAVE2H

tE2HWH

tBLWH

UBS, LBS

WS

tAVWL

tWLWH

tWLQZ

tWHQX

tWHDX

tDVWH

INPUT VALID

DQ0-DQ15

AI90220

Note: Output Enable (GS) = Low.

Figure 20. SRAM Write AC Waveforms, WS Controlled with GS High

tAVAV

A0-A17

VALID

tAVWH

tE1LWH

tAVE1L

tWHAX

E1S

E2S

tAVE2H

tE2HWH

tBLWH

UBS, LBS

tAVWL

tWLWH

WS

GS

tWHQX

tWHDX

tGHQZ

tDVWH

INPUT VALID

DQ0-DQ15

AI90221

38/46

M36DR432A, M36DR432B

Figure 21. SRAM Write Cycle Waveform, UBS and LBS Controlled

tAVAV

A0-A17

E1S

VALID

tE1LWH

tE1HAX

tAVWH

E2S

tE2HWH

tBLWH

tAVWL

UBS, LBS

tWLWH

WS

tDVWH

DATA VALID

tWHDX

DQ0-DQ15

AI90222

Figure 22. SRAM Write AC Waveforms, E1S Controlled

tAVAV

A0-A17

E1S

VALID

tE1LWH

tAVE1L

tE1HAX

E2S

tBLWH

UBS, LBS

tAVWL

WS

tDVE1H

INPUT VALID

tWHDX

DQ0-DQ15

AI90223

Note: Output Enable (GS) = High.

39/46

M36DR432A, M36DR432B

(1, 2)

Table 33. SRAM Low V

Data Retention Characteristics

CCS

(T = –40 to 85°C; V

A

= 1.65V to 2.2V)

DDS

Symbol

Parameter

Test Condition

Min

Max

10

Unit

V

= 1.2V, E1S ≥ V

– 0.2V,

DDS

I

Supply Current (Data Retention)

µA

DDDR

E2S ≥ V

– 0.2V or E2S ≤ 0.2V, f = 0

– 0.2V, E2S ≤ 0.2V, f = 0

DDS

V

E1S ≥ V

Supply Voltage (Data Retention)

Chip Disable to Power Down

Operation Recovery Time

1

0

2.2

V

DR

t

– 0.2V, E2S ≤ 0.2V, f = 0

CCS

ns

CDR

t

R

RC

Note: 1. All other Inputs V ≤ V – 0.2V or V ≤ 0.2V.

IH

DD

IL

2. Sampled only. Not 100% tested.

Figure 23. SRAM Low V

Data Retention AC Waveforms, E1S Controlled

DDS

tCDR

DATA RETENTION MODE

tR

V

DDS

1.65 V

1.2 V

V

DR

E1S ≥ V

– 0.2V

DDS

E1S

V

SSS

AI90224

Figure 24. SRAM Low V

Data Retention AC Waveforms, E2S Controlled

DDS

DATA RETENTION MODE

V

DDS

1.65 V

E2S

tCDR

tR

V

DR

E2S ≤ 0.2V

0.4 V

V

SSS

AI90225

40/46

M36DR432A, M36DR432B

Table 34. Ordering Information Scheme

Example:

M36DR432A

100 ZA

6

T

Device Type

M36 = MMP (Flash + SRAM)

Architecture

D = Dual Bank, Page Mode

Operating Voltage

R = V

= V

=1.65V to 2.2V

DDF

DDS

SRAM Chip Size & Organization

4 = 4 Mbit (256K x 16 bit)

Device Function

32A = 32 Mbit (x16), Dual Bank: 1/8-7/8 partitioning, Top Boot

32B = 32 Mbit (x16), Dual Bank: 1/8-7/8 partitioning, Bottom Boot

Speed

100 = 100ns

120 = 120ns

Package

ZA = LFBGA66: 0.8mm pitch

Temperature Range

6 = –40 to 85°C

Option

T = Tape & Reel packing

C = Cypress’s SRAM

Devices are shipped from the factory with the memory content bits erased to ’1’.

Table 35. Daisy Chain Ordering Scheme

Example:

M36DR432

-ZA T

Device Type

M36DR432

Daisy Chain

-ZA = LFBGA66: 0.8mm pitch

Option

T = Tape & Reel Packing

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the STMicroelectronics Sales Office nearest to you.

41/46

M36DR432A, M36DR432B

Table 36. Revision History

Date

Version

-01

Revision Details

24-May-2001

19-Nov-2001

First Issue

LFBGA66 mechanical data updated (Table 37)

-02

42/46

M36DR432A, M36DR432B

Table 37. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.400

0.0551

0.250

0.0098

1.100

0.0433

0.400

12.000

5.600

8.800

0.350

0.450

0.0157

0.4724

0.2205

0.3465

0.0138

0.0177

D

–

D1

D2

ddd

E

–

0.100

0.0039

8.000

5.600

0.800

1.600

1.200

0.400

–

0.3150

0.2205

0.0315

0.0630

0.0472

0.0157

–

E1

e

FD

FE

SD

SE

Figure 25. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Bottom View Package Outline

D

D2

D1

SE

b

E

E1

BALL "A1"

e

ddd

FE

FD

SD

e

A

A2

A1

BGA-Z12

Note: Drawing is not to scale.

43/46

M36DR432A, M36DR432B

Figure 26. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package)

#3

#4

#1

#2

1

2

3

4

5

6

7

8

A

B

C

D

E

F

G

H

AI90251

44/46

M36DR432A, M36DR432B

Figure 27. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through

package)

START

POINT

END

POINT

#3

#4

#1

#2

1

2

3

4

5

6

7

8

A

B

C

D

E

F

G

H

AI90252

45/46

M36DR432A, M36DR432B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

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46/46


型号：	M36DR432B100ZA6T
厂家：	ST
描述：	32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product 32兆位的2Mb X16 ，双行，页闪存和4兆位256K x16的SRAM ，多重内存产品闪存内存集成电路静态存储器
文件：	总46页 (文件大小：329K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M36DR432B100ZA6T [STMICROELECTRONICS]

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