M34S32WBN1T [STMICROELECTRONICS]
32K Serial I2C Bus EEPROM With User-Defined Read-Only Block and 32-Byte OTP Page; 32K串行I2C总线的EEPROM，带有用户自定义只读座和32字节的OTP页
| 型号： | M34S32WBN1T |
| 厂家： | 
ST |
| 描述： | 32K Serial I2C Bus EEPROM With User-Defined Read-Only Block and 32-Byte OTP Page |
| 文件： | 总18页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
M34S32
32K Serial I C Bus EEPROM
2
With User-Defined Read-Only Block and 32-Byte OTP Page
PRELIMINARY DATA
2
■
■
TWO WIRE I C SERIAL INTERFACE,
SUPPORTS 400kHz PROTOCOL
Figure 1. Delivery Forms
2
COMPATIBLE WITH I C EXTENDED
ADDRESSING
■
■
■
■
■
■
■
■
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE
HARDWARE WRITE CONTROL
USER-DEFINED READ-ONLY BLOCK
32 BYTES OTP PAGE
8
8
1
1
BYTE and PAGE WRITE (up to 32 BYTES)
S08 (MN)
150 mil Width
PSDIP8 (BN)
BYTE, RANDOM and SEQUENTIAL READ
MODES
0.25 mm Frame
■
■
■
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD and LATCH-UP
PERFORMANCES
Figure 2. Logic Diagram
DESCRIPTION
The M34S32 is a 32K bit electrically erasable pro-
grammable memory (EEPROM), organized as
4096 x 8 bits.
V
CC
Table 1. Signal Names
SDA
SCL
WC
Serial Data Address Input/Output
Serial Clock
SDA
SCL
WC
M34S32
Write Control
WCR
Write Control of Control Register
Supply Voltage
WCR
V
CC
V
Ground
SS
V
SS
AI02468
June 1998
1/18
This is a Preliminary Data. Details are subject to change without notice.
M34S32
Figure 3. DIP Pin Connections
Figure 4. SO Pin Connections
M34S32
M34S32
NC
NC
1
2
3
4
8
V
NC
NC
1
2
3
4
8
V
CC
WC
CC
7
6
WC
7
6
WCR
SCL
SDA
WCR
SCL
SDA
V
5
V
5
SS
SS
AI02448
AI02449
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
–40 to 125
–65 to 150
215
Unit
°C
T
Ambient Operating Temperature
Storage Temperature
A
T
°C
STG
Lead Temperature, Soldering
(SO8 package)
40 sec
10 sec
°C
T
LEAD
(PSDIP8
package)
260
°C
V
V
Input or Output Voltages
Supply Voltage
–0.6 to 6.5
–0.3 to 6.5
V
V
IO
CC
(Human Body model)
Electrostatic Discharge Voltage
Electrostatic Discharge Voltage
4000
500
V
V
1. MIL-STD-883C, 3015.7 (100 pF,
1500 Ω)
V
ESD
(Machine model)
2. EIAJ IC-121 (Condition C)
(200 pF, 0 Ω)
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.
2/18
M34S32
DESCRIPTION (cont’d)
When writing data to the memory it responds to
the 8 bits received by asserting an acknowledge
bit during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the
data bytes in the same way.
Data transfers are terminated with a STOP condi-
tion.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On Re-
set (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active: all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold val-
ue, all operations are disabled and the device will
not respond to any command. A stable VCC must
be applied before applying any logic signal.
2
The memory is compatible with the I C extended
addressing standard, two wire serial interface
which uses a bi-directional data bus and serial
clock. The memory carries a built-in 4 bit, unique
device identification code (1010) corresponding to
2
the I C bus definition. The memory behaves as
2
slave devices in the I C protocol with all memory
operations synchronized by the serial clock. Read
and write operations are initiated by a START con-
dition generated by the bus master. The START
condition is followed by the Device Select Byte.
This is a stream of 4 bits (the identification code
1010), then 3 bits of memory block access input,
plus one read/write bit. The byte is finally terminat-
ed by an acknowledge bit.
The M34S32 contains three memory blocks: the
OTP page, the EEPROM block and the ROM
block. The OTP (One Time Programmable) page
is a page of 32 bytes, written once by the user. The
OTP page is not located within the 32 Kbits EEP-
ROM area. Once written, the OTP page cannot be
modified by further write instructions. The ROM
block resides inside the 32 Kbit EEPROM area.
The size of the ROM block is defined (by the user)
with the help of the Control Register.
SIGNAL DESCRIPTION
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to
VCC to act as a pull up (see Figure 3)
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memo-
ry. It is an open drain output that may be wire-
OR’ed with other open drain or open collector sig-
nals on the bus. A pull-up resistor must be con-
The OTP page is accessed with the Device Select
Byte 1010001x, the EEPROM and ROM blocks
are accessed with the Device Select Byte
1010000x. The control register is accessed with
the Device Select Byte 1010100x (see Table 3).
nected from the SDA bus line to V
3).
(see Figure
CC
Table 3. Device Select Byte
Device Code
Memory Block Access
RW
b0
Device Select Bit
b7
1
b6
0
b5
1
b4
0
b3
0
b2
0
b1
0
EEPROM and ROM access
OTP Page access
RW
RW
RW
1
0
1
0
0
0
1
Control Register access
1
0
1
0
1
0
0
Table 4. Operating Modes
Mode
Data
Bytes
RW bit
Initial Sequence
Current Address Read
1
0
1
1
0
0
1
START, Device Select, RW = 1
START, Device Select, RW = 0, Address
reSTART, Device Select, RW = 1
As CURRENT or RANDOM Mode
START, Device Select, RW = 0
START, Device Select, RW = 0
Random Address Read
1
Sequential Read
Byte Write
≥ 1
1
Page Write
≤ 32
3/18
M34S32
Write Control (WC). The Write Control feature
WC is useful to protect the contents of the whole
EEPROM area from any erroneous erase/write cy-
cle. It also protects the OTP page against the first
write attempt. The Write Control signal polarity can
be selected with the WCpol bit of the Control Reg-
ister (see Table 13). When pin WC is unconnect-
ed, the WC input is internally read as VIL (see
Table 5).
When WC and WCpol are activating the Write Pro-
tection, Device Select and Address bytes are ac-
knowledged; Data bytes are not acknowledged
(see Figure 11).
Write Control (WCR). In order to prevent spurious
writes to the Control Register, the user can also
make the Control Register Read Only (Write is in-
hibited). This is achieved by use of the WCR pin
and the CRWD bit (see Table 14) :
– - if CRWD bit = 0, the Control register can be
modified regardless of the state of the WCR pin.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the memory continu-
ously monitors the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition. STOP is identified by a low to
high transition of the SDA line while the clock SCL
is stable in the high state. A STOP condition termi-
nates communication between the memory and
the bus master. A STOP condition at the end of a
Read command forces the stand-by state. A
STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successful data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During
the 9th clock pulse the receiver pulls the SDA bus
low to acknowledge the receipt of the 8 bits of da-
ta.
Data Input. During data input the memory sam-
ples the SDA bus signal on the rising edge of the
clock SCL. For correct device operation the SDA
signal must be stable during the clock low to high
transition and the data must change ONLY when
the SCL line is low.
– - if CRWD bit = 1, the Control register can be
modified if the WCR pin is high.
– - if CRWD bit = 1 and the WCR pin is low, the
Control Register is Write Protected.
DEVICE OPERATION
2
I C Bus Background
The memory supports the extended addressing
2
I C protocol. This protocol defines any device that
Device Selection. To start communication be-
tween the bus master and the slave memory, the
master must initiate a START condition. The 8 bits
sent after a START condition are made up of a De-
vice Select Byte of 4 bits that identifies the device
type, 3 memory block access bits and one bit for a
READ (RW = 1) or WRITE (RW = 0) operation.
There are two modes both for read and write.
These are summarised in Table 4 and described
hereafter. Communication between the master
and the slave is ended with a STOP condition.
sends data onto the bus as a transmitter and any
device that reads the data as a receiver. The de-
vice that controls the data transfer is known as the
master and the other as the slave. The master will
always initiate a data transfer and will provide the
serial clock for synchronisation. The memory is al-
ways a slave device in all communications.
(1)
Table 5. Input Parameters
(T = 25°C, f = 400 kHz)
A
Symbol
Parameter
Input Capacitance (SDA)
Test Condition
Min.
Max.
8
Unit
pF
C
IN
IN
C
Input Capacitance (other pins)
6
pF
Z
Z
V
V
≤ 0.3 V
WC, WCR Input Impedance
5
20
kΩ
kΩ
ns
L
IN
CC
≥ 0.7 V
IN
WC, WCR Input Impedance
500
H
CC
t
Low-pass filter input time constant (SDA and SCL)
100
LP
Note: 1. Sampled only, not 100% tested in production.
4/18
M34S32-
2
Figure 5. Maximum RL Value versus Bus Capacitance (CBUS) for an I C Bus
V
CC
20
16
R
R
L
L
12
SDA
MASTER
C
BUS
8
SCL
fc = 100kHz
4
fc = 400kHz
C
BUS
0
10
100
(pF)
1000
C
BUS
AI01665
Table 6. DC Characteristics (T = 0 to 70°C, –40 to 85°C; V = 4.5V to 5.5V, 2.5V to 5.5V)
A
CC
Symbol
Parameter
Test Condition
Min.
Max.
Unit
µA
Input Leakage Current (SCL,
SDA)
I
0 ≤ V ≤ V
±2
LI
IN
CC
I
0 ≤ V
≤ V ; SDA in Hi-Z
Output Leakage Current
Supply Current
±2
µA
LO
OUT
CC
V
= 5 V; f = 400 kHz
C
CC
2
1
mA
mA
(rise/fall time < 30 ns)
I
CC
V
= 2.5 V; f = 400 kHz
CC
C
Supply Current (W series)
(rise/fall time < 30 ns)
I
I
V
= V or V ; V = 5 V
SS CC CC
Stand-by Current
10
2
µA
µA
V
CC1
IN
IN
V
= V or V ; V = 2.5 V
Stand-by Current (W series)
Input Low Voltage (WC, WCR)
Input High Voltage (WC, WCR)
Input Low Voltage (other pins)
Input High Voltage (other pins)
Output Low Voltage
CC2
SS
CC
CC
V
V
V
V
– 0.3
0.5
IL
IH
IL
IH
V
- 0.5
V
+ 1
V
CC
CC
0.3 V
– 0.3
V
CC
0.7 V
V
+ 1
V
CC
CC
I
= 3 mA, V = 5 V
0.4
0.4
V
OL
OL
CC
V
OL
I
= 2.1 mA, V = 2.5 V
Output Low Voltage (W series)
V
CC
5/18
M34S32
Table 7. AC Measurement Conditions
Figure 6. AC Testing Input/Output Waveforms
Input Rise and
≤ 50ns
0.8V
CC
Fall Times
0.7V
CC
Input Pulse
Voltages
0.2 V to 0.8 V
0.3V
CC
CC
CC
0.2V
CC
AI00825
Input and Output
Timing Reference
Voltages
0.3 V to 0.7 V
CC
CC
Table 8. AC Characteristics (T = 0 to 70°C,
A
–40 to 85°C; V = 4.5V to 5.5V, 2.5V to 5.5V)
CC
M34S32
V
= 4.5V to
5.5V
V
= 2.5V to
5.5V
CC
CC
Symbol
Alt.
Parameter
Unit
Min.
Max.
300
Min.
Max.
300
t
t
t
Clock Rise Time
Clock Fall Time
SDA Rise Time
ns
ns
ns
CH1CH2
R
t
300
300
CL1CL2
F
(1)
t
20
20
300
300
20
20
300
300
t
t
R
DH1DH2
DL1DL2
(1)
t
SDA Fall Time
ns
F
(2)
t
Clock High to Input Transition
Clock Pulse Width High
600
600
600
0
600
600
600
0
ns
ns
t
t
t
t
t
t
t
t
SU:STA
CHDX
CHCL
DLCL
CLDX
CLCH
DXCX
CHDH
DHDL
t
HIGH
t
t
Input Low to Clock Low (START)
Clock Low to Input Transition
Clock Pulse Width Low
ns
HD:STA
µs
ns
HD:DAT
t
1300
100
600
1300
200
200
1300
100
600
1300
200
200
LOW
t
t
Input Transition to Clock Transition
Clock High to Input High (STOP)
Input High to Input Low (Bus Free)
Clock Low to Next Data Out Valid
Data Out Hold Time
ns
SU:DAT
ns
SU:STO
t
ns
BUF
(3)
t
900
900
ns
t
t
f
t
AA
CLQV
QLQx
C
t
ns
DH
f
Clock Frequency
400
10
400
10
kHz
ms
SCL
t
Write Time
W
WR
Note: 1. Sampled only, not 100% tested in production.
2. For a reSTART condition, or following a write cycle.
3. The minimum value delays the falling/rising edge of SDA away from SCL=1 in order to avoid unwanted START and/or STOP
conditions.
6/18
M34S32
EEPROM Addressing. A data byte in the memory
is addressed through 2 bytes of address informa-
tion. The Most Significant Byte is sent first and the
Least significant Byte is sent after. Bits b15 to b0
form the address of any byte of the memory. Bits
b15 to b12 are don’t care on the M34S32 series.
Write Operations
Following a START condition the master sends a
Device Select Byte with the RW bit reset to 0. The
memory acknowledges this and waits for 2 bytes
of address. These 2 address bytes (8 bits each)
provide access to any of the memory location.
Writing in the memory may be inhibited with WC
pin and WCpol bit (see Table 13 and Figure 11).
Table 9. Most Significant Byte
b15
X
b14 b13 b12 b11 b10
b9
b8
X
X
X
4. b15 to b12 are Don’t Care.
Table 10. Least Significant Byte
b7
b6
b5
b4
b3
b2
b1
b0
Figure 7. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
tDXCX
tCHDH
SDA IN
tCHDX
tCLDX
SDA
tDHDL
START
CONDITION
SDA
STOP &
BUS FREE
INPUT CHANGE
SCL
tCLQV
tCLQX
DATA VALID
SDA OUT
DATA OUTPUT
SCL
tW
SDA IN
tCHDH
tCHDX
STOP
WRITE CYCLE
START
CONDITION
CONDITION
AI00795B
7/18
M34S32
Byte Write. In the Byte Write mode the master
sends one data byte, which is acknowledged by
the memory. The master then terminates the
transfer by generating a STOP condition.
Note that for any write mode, the generation by the
master of the STOP condition starts the internal
memory program cycle. This STOP condition will
trigger an internal memory program cycle only if
the STOP condition is internally decoded right af-
ter the ACK bit; any STOP condition decoded out
of this “10th bit” time slot will not trigger the internal
programming cycle. All inputs are disabled until
the completion of this cycle and the Memory will
not respond to any request.
Page Write. The Page Write mode allows up to 32
bytes to be written in a single write cycle, provided
that they are all located in the same row of 32
bytes in the memory, that is the same Address bits
(b12 to b5). The master sends one up to 32 bytes
of data, which are each acknowledged by the
memory. After each byte is transferred, the inter-
nal byte address counter (5 Least Significant Bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition. Care
must be taken to avoid address counter “roll-over”
which could result in data being overwritten.
2
Figure 8. I C Bus Protocol
SCL
SDA
START
SDA
SDA
STOP
CONDITION
INPUT CHANGE
CONDITION
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
CONDITION
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
CONDITION
AI00792
8/18
M34S32
Write to the Control Register
B2,B1,B0. These bits control the size of the ROM
block. Their initial, default state is 0, 0, 0.
The control register is accessed using a specific
Device Select Byte (as described in Table 3, and
as shown in Table 11 and Table 12).
Table 15. Operation of the B2, B1 and B0 Bits
B2,B1,B0
0,0,0
ROM block size and location
All bits are EEPROM
Table 11. Content of the Control Register
0
b7
b6
b5
X
b4
B2
b3
b2
B0
b1
X
b0
X
CRWD WCpol
B1
0,0,1
1/64
1/32
1/16
1/8
1/4
1/2
1
ROM block=00h to 01FFh (512)
ROM block=00h to 03FFh (1K)
ROM block=00h to 07FFh (2K)
ROM block=00h to 0FFFh (4K)
ROM block=00h to 1FFFh (8K)
ROM block=00h to 3FFFh (16K)
All bits are ROM
0,1,0
Table 12. Default values
0,1,1
b7
0
b6
0
b5
X
b4
0
b3
0
b2
0
b1
X
b0
X
1,0,0
1,0,1
The meanings of the bits in Table 11 can be sum-
marised as follows:
WCpol. This bit controls the polarity of the WC in-
put (to switch pin 7 between being a WC or WC in-
put). The default (initial) state of this bit is 0.
1,1,0
1,1,1
In all cases, except when (B2,B1,B0)=(0,0,0), the
selected area of EEPROM becomes read only
(Write Protected) regardless of the status of the
other bits and pins. However, the Control Register
itself remains alterable in accordance with the sta-
tus of WC, WCpol, WCR and CRWD.
Table 13. Operation of the WCpol Bit
pin 7 = high
pin 7 = low
Write instructions
are allowed in the
EEPROM area,
and the OTP
Whole EEPROM
WCpol = 0 and OTP page are
write protected
Write to the OTP Page
The OTP page is accessed by addressing the de-
vice using the specific, Device Select Byte (as de-
scribed in Table 3).
page can be
written once
Write instructions
are allowed in the
EEPROM area,
and the OTP
page can be
written once
The correct sequence for this instruction can be
sketched out as follows:
Start
Whole EEPROM
and OTP page are
write protected
WCpol = 1
OTP Page Select(= 1010 0010)
Ack
Address (MSB) (= xxxx 0000)
CRWD. This is the Control Register Write Disable
bit. When it is 0, pin 3 is a Don’t Care input, and the
control register is always writable. This is the de-
fault (initial) condition of this bit.
Ack
Address (LSB) (= 0000 0000)
Ack
Data
Ack
(= byte to be written)
Table 14. Operation of the CRWD Bit
pin 3 = high
pin 3 = low
........
Data
Ack
(= byte to be written)
CRWD = 0
CRWD = 1
Control register is writable
Control register is
write protected
(read only)
Control register is
writable
Stop
If one bit of the OTP Page Select differs from the
above values, the OTP Page Select will NOT be
acknowledged and the WRITE instruction will be
ignored.
9/18
M34S32
If one bit of the Address bytes (excluding the three
most significant bits which are Don’t Care) differs
from the above values, the Address will be ac-
knowledged, data will not be acknowledged and
the WRITE instruction will be ignored.
The Page Write instruction must start with the first
byte that is located in the OTP page (address 0h),
otherwise the instruction will be ignored.
The first Write to the OTP page (whether it be a 1-
byte write, a 32-byte page write, or some size in
between) will disable any further write in the OTP
page.
Let us suppose that byte N of the OTP page has
just been addressed (for example because of a
Write in the OTP page or a Random read in the
OTP page). If the next instruction uses the Current
Read Mode of the device, the first byte read in
EEPROM will be in page 0, at address N+1 (or
page 1, byte 0 if the last OTP byte addressed was
at location 31).
Example of a correct sequence, leading to a 3-
byte write in the OTP page:
Start
1010 0010
Ack
(OTP page select code)
(upper address, MSB)
(lower address, LSB)
1111 0000
Ack
0000 0000
Ack
0100 1101
Ack
(write 3 bytes of data)
(in the OTP page)
1100 1010
Ack
0101 0011
Ack
Stop
Figure 9. Write Cycle Polling using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by M34Sxx
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send
Byte Address
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI02418
10/18
M34S32
Example of an incorrect sequence, disabling the
Write in the OTP page:
Start
Minimizing System Delay by Polling On ACK.
During the internal Write cycle, the memory disa-
bles itself from the bus in order to copy the data
from the internal latches to the memory cells. The
1010 0010
Ack
(OTP page select code)
(MSB address)
maximum value of the Write time (t ) is given in
W
the AC Characteristics table, this timing value may
be reduced by an ACK polling sequence issued by
the master.
xxxx 0000
Ack
The sequence is:
0000 0100
Ack
(incorrect LSB address)
(acknowledged, but...)
(the attempts at)
– Initial condition: a Write is in progress (see Fig-
ure 7).
– Step 1: the Master issues a START condition fol-
lowed by a Device Select Byte. (1st byte of the
new instruction)
0100 1101
(no ack)
1100 1010
(no ack)
0101 0011
(no ack)
Stop
(writing data to the)
(OTP page are)
– Step 2: if the memory is internally writing, no
ACK will be returned. The Master goes back to
Step1. If the memory has terminated the internal
writing, it will issue an ACK.
The memory is ready to receive the second part of
the instruction (the first byte of this instruction was
already sent during Step1).
(not acknowledged)
Figure 10. Write Modes Sequence with WC = 0
and WCpol = 0
WC
ACK
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
R/W
WC
ACK
ACK
ACK
ACK
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
ACK
ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01106B
Note: 1. The device has the same behavior when WC = 1 and
WCpol = 1.
11/18
M34S32
Figure 11. Write Modes Sequence with WC = 1
and WCpol = 0
WC
ACK
ACK
ACK
NO ACK
DATA IN
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC
ACK
ACK
ACK
NO ACK
DATA IN 1 DATA IN 2
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC (cont'd)
NO ACK
NO ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01120B
Note: 1. The device has the same behavior when WC = 0 and
WCpol = 1.
Let us suppose, again, that byte N of the OTP
page has just been addressed (for example be-
cause of a Write in the OTP page or a Random
read in the OTP page). If the next instruction uses
the Current Address Read Mode of the device, the
first byte read in EEPROM will be in page 0, at ad-
dress N+1 (or page 1, byte 0 if the last OTP byte
addressed was at location 31).
Random Address Read. A dummy write is per-
formed to load the address into the address coun-
ter, see Figure 10. This is followed by another
START condition from the master and the byte ad-
dress repeated with the RW bit set to 1. The mem-
ory acknowledges this and outputs the byte
addressed. The master does NOT acknowledge
the byte output, but terminates the transfer with a
STOP condition.
Read Operations
On delivery, the memory content is set at all “1”s
(or FFh).
Current Address Read. The memory has an in-
ternal address counter. Each time a byte is read,
this counter is incremented. For the Current Ad-
dress Read mode, following a START condition,
the master sends a Device Select Byte with the
RW bit set to 1. The memory acknowledges this
and outputs the byte addressed by the internal ad-
dress counter. This counter is then incremented.
The master does NOT acknowledge the byte out-
put, but terminates the transfer with a STOP con-
dition.
A Current Address Read in the OTP page is per-
formed by sending the appropriate Device Select
Byte, as described in Table 3.
Specific features of the Random Address read
in the OTP page. This instruction must consist of
the two sequences shown on page 14 (Sequence
A followed by Sequence B).
12/18
M34S32
Figure 12. Read Mode Sequences
ACK
NO ACK
DATA OUT
CURRENT
ADDRESS
READ
DEV SEL
R/W
ACK
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
DATA OUT N
R/W
ACK
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01105C
Note: 1. The seven most significant bits of the DEV SEL code of
a Random Read (1st byte and 4th byte) must be identi-
cal.
13/18
M34S32
Sequence A:
APPLICATION HINTS ON HOW TO USE THE
CONTROL REGISTER TOGETHER WITH THE /
WCR PIN
The application board can be designed in such a
Start
OTP Page Select(= 1010 0010)
Ack
way that WCR pin is connected to V (directly or
SS
through a pull-down resistor). It should be noted
that the WCR pin features an internal pull-down re-
sistor allowing this input to be left unconnected.
With such a P.C.B. (Printed Circuit Board), the de-
vice can be initialised according to following set-up
sequence :
Address MSB
Ack
(= xxxx 0000)
(= 000x xxxx)
Address LSB
Ack
Sequence B:
Start
1. Write the data that is to be Write protected:
– Write data in the area starting from address
00h up to the desired address.
OTP Page Select(= 1010 0011)
Ack
2. Write in the Control Register (single byte write
using the following bits):
Data
Ack
– Set B2, B1 and B0 values according to the
ROM block size (as defined in Table 15)
........
Data
– Set WCpol according to the application
needs.
(no Ack)
Stop
– Set CRWD bit to 1
If one, or more bits of the Sequence A differ from
the above values, the bytes that follow it will be ac-
knowledged (or not) according to the same rules
as for the WRITE IN OTP, and the RANDOM AD-
DRESS READ IN OTP will be ignored.
Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se-
quence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-
put, but MUST generate a STOP condition.
The output data is from consecutive byte ad-
dresses, with the internal byte address counter au-
tomatically incremented after each byte output. Af-
ter a count of the last memory address, the
address counter will “roll-over” and the memory
will continue to output data.
A Sequential Read in the OTP page is performed
by sending the appropriate Device Select Byte, as
described in Table 3. If a sequential read reaches
the last location in the OTP page (address 1Fh),
subsequent Sequential Reads will wrap round to
the start, to address 00h.
Once the CRWD bit is set to 1, the control register
becomes Write Protected. The only way to write
again to the Control Register is to set the WCR pin
high. This is possible by applying V to WCR if it
CC
was previously floating or connected to V
through an external pull-down resistor. If WCR is
SS
shorted to V , the device needs to be de-sol-
SS
dered from the PCB.
OTHER NOTES
The WCR pin has an internal pull-down resistor.
Connecting this pin to GND does not affect the
power consumption, thus giving the M34S32 its
lowest power consumption when it is in Protected
mode.
The OTP page may be programmed before or af-
ter the hardware protected mode has been set (by
setting the CRWD bit). This allows the application
MCU to program the OTP page either on the as-
sembly line or during the operating life of the appli-
cation.
The WC pin (but not the WCR pin) may be driven
dynamically by the MCU to increase the immunity
to data corruption of the unprotected EEPROM ar-
ea. This pin may alternatively be pulled to V or
CC
Acknowledge in Read Mode. In all read modes
the memory waits for an acknowledge during the
9th bit time. If the master does not pull the SDA
line low during this time, the memory terminates
the data transfer and switches to a stand-by state.
GND (depending on which is appropriate, accord-
ing to the setting of the WCpol bit).
14/18
M34S32
ORDERING INFORMATION SCHEME
For further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to
you.
Devices are shipped from the factory with the
memory content set at all “1”s (FFh).
In general, the fields of the product number are
made up as follows:
For a list of available options, refer to the current
Memory Shortform Catalogue.
Example:
M 34 S 32 - W MN 1 T
AI02469
Option
Capacity
Supply Voltage
Package
Temp. Range
o
T: Tape & Reel
Packing
32: 32 Kb (4Kx8)
blank: 4.5 to 5.5 V
W: 2.5 to 5.5 V
BN: PSDIP8
0.25 mm frame
MN: SO8
1: 0 to 70
6: -40 to 85
5: -20 to 85
C
o
o
C
C
150 mil body width
(see note 1)
Note: 1. Temperature range 1 is available on request only.
15/18
M34S32
Table 16. PSDIP8 - 8 pin Plastic Skinny DIP,
0.25mm lead frame
mm
inches
Min.
Symb.
Typ.
Min.
3.90
0.49
3.30
0.36
1.15
0.20
9.20
–
Max.
5.90
–
Typ.
Max.
0.232
–
A
A1
A2
B
0.154
0.019
0.130
0.014
0.045
0.008
0.362
–
5.30
0.56
1.65
0.36
9.90
–
0.209
0.022
0.065
0.014
0.390
–
B1
C
D
E
7.62
2.54
0.300
0.100
E1
e1
eA
eB
L
6.00
–
6.70
–
0.236
–
0.264
–
7.80
–
0.307
–
10.00
3.80
0.394
0.150
3.00
8
0.118
8
N
Figure 13. PSDIP8
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Note: 1. Note: Drawing is not to scale.
16/18
M34S32
Table 17. SO8 - 8 lead Plastic Small Outline,
150 mils body width
mm
inches
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Symb.
Typ.
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
Figure 14. SO8a
h x 45˚
C
A
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Note: 1. Note: Drawing is not to scale.
17/18
M34S32
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
© 1998 STMicroelectronics - All Rights Reserved
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
STMicroelectronics GROUP OF COMPANIES
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18/18
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