M29W641DU90ZA6F [STMICROELECTRONICS]
64 Mbit 4Mb x16, Uniform Block 3V Supply Flash Memory; 64兆位4Mb的X16 ,统一座3V电源快闪记忆体型号: | M29W641DU90ZA6F |
厂家: | ST |
描述: | 64 Mbit 4Mb x16, Uniform Block 3V Supply Flash Memory |
文件: | 总42页 (文件大小:625K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M29W641DH, M29W641DL
M29W641DU
64 Mbit (4Mb x16, Uniform Block)
3V Supply Flash Memory
PRODUCT PREVIEW
FEATURES SUMMARY
■ SUPPLY VOLTAGE
Figure 1. Packages
– V = 2.7V to 3.6V Core Power Supply
CC
– V
= 1.8V to 3.6V for Input/Output
CCQ
– V =12 V for Fast Program (optional)
PP
■ ACCESS TIME: 70, 90, 100 and 120ns
■ PROGRAMMING TIME
– 10 µs typical
– Double Word Program option
■ 128 UNIFORM, 32-KWord MEMORY BLOCKS
■ PROGRAM/ERASE CONTROLLER
– Embedded Program and Erase algorithms
■ ERASE SUSPEND and RESUME MODES
TSOP48 (N)
12 x 20mm
– Read and Program another Block during
Erase Suspend
■ UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
■ WRITE PROTECT OPTIONS
FBGA
– M29W641DH: WP Pin for Write Protection of
Highest Address Block
– M29W641DL: WP Pin for Write Protection of
Lowest Address Block
TFBGA63 (ZA)
7 x 11mm
– M29W641DU: No Write Protection
■ TEMPORARY BLOCK UNPROTECTION
MODE
■ COMMON FLASH INTERFACE
■ EXTENDED MEMORY BLOCK
– Extra block used as security block or to store
additional information
■ LOW POWER CONSUMPTION
– Standby and Automatic Standby
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code M29W641D: 22C7h
April 2003
1/42
This is preliminary information on a new product now in development. Details are subject to change without notice.
M29W641DH, M29W641DL, M29W641DU
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TFGBA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
V
V
V
(V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PP
PP
Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC
Supply Voltage (1.8V to 3.6V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CCQ
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SS
Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Unlock Bypass Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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M29W641DH, M29W641DL, M29W641DU
Enter Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Exit Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 14
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Accelerated Program Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 25
Table 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 25
Figure 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Bottom view package outline 26
Table 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Package Mechanical Data . . 26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
APPENDIX A. BLOCK ADDRESSES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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M29W641DH, M29W641DL, M29W641DU
APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 18. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 21. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 23. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
APPENDIX C. EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 24. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
APPENDIX D. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 25. Programmer Technique Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 16. Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 17. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 18. In-System Equipment Group Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 19. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 26. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 41
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M29W641DH, M29W641DL, M29W641DU
Figure 2. Logic Diagram
SUMMARY DESCRIPTION
The M29W641D is a 64 Mbit (4Mb x16) non-vola-
tile memory that can be read, erased and repro-
grammed. These operations can be performed
using a single, low voltage, 2.7V to 3.6V V sup-
CC
V
V
V
PP
CC
CCQ
ply for the circuitry and a 1.8V to 3.6V V
supply
CCQ
for the Input/Output pins. An optional 12 V V
PP
power supply is provided to speed up customer
programming.
22
16
On power-up the memory defaults to its Read
mode where it can be read in the same way as a
ROM or EPROM.
The highest address block of the M29W641DH or
the lowest address block of the M29W641DL can
be protected from accidental programming or era-
A0-A21
DQ0-DQ15
W
E
M29W641D
G
sure using the WP pin (if WP = V ). The
IL
M29W641DU does not feature the WP pin.
RB
RP
WP
Each block can be erased independently so it is
possible to preserve valid data while old data is
erased. The blocks can be protected to prevent
accidental Program or Erase commands from
modifying the memory. Program and Erase com-
mands are written to the Command Interface of
the memory. An on-chip Program/Erase Controller
simplifies the process of programming or erasing
the memory by taking care of all of the special op-
erations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions identi-
fied. The command set required to control the
memory is consistent with JEDEC standards.
V
SS
AI06697b
Table 1. Signal Names
A0-A21
Address Inputs
The M29W641D has an extra block, the Extended
Block, (of 32 KWords) that can be accessed using
a dedicated command. The Extended Block can
be protected and so is useful for storing security
information. However the protection is not revers-
ible, once protected the protection cannot be un-
done.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
DQ0-DQ7
Data Inputs/Outputs
Data Inputs/Outputs
DQ8-
DQ15
E
Chip Enable
Output Enable
Write Enable
G
W
Reset/Block Temporary Unprotect
(M29W641DH and M29W641DL only)
The memory is offered in a 48-pin TSOP package
(M29W641DL and M29W641DH) or in a 63-ball TF-
BGA package (M29W641DU). All devices are deliv-
ered with all the bits erased (set to 1).
RP
Ready/Busy Output (M29W641DU
only)
RB
Write Protect
WP
V
CC
Supply Voltage
V
CCQ
Supply Voltage for Input/Output
Supply Voltage for Fast Program
(optional)
V
V
PP
Ground
SS
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M29W641DH, M29W641DL, M29W641DU
Figure 3. TSOP Connections
A15
A14
A13
A12
A11
A10
A9
1
48
A16
V
V
CCQ
SS
DQ15
DQ7
DQ14
DQ6
A8
DQ13
DQ5
A21
A20
W
DQ12
DQ4
RP
12
13
37
36
V
CC
M29W641D
V
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
PP
WP
A19
A18
A17
A7
A6
A5
A4
A3
V
E
SS
A2
A1
24
25
A0
AI06698
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M29W641DH, M29W641DL, M29W641DU
Figure 4. TFGBA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
B
(1)
(1)
(1)
(1)
(1)
(1)
NC
NC
NC
NC
(1)
NC
NC
NC
RB
W
RP
A21
A3
A4
A7
A17
A6
A9
A8
A13
A12
A14
A15
A16
C
D
V
PP
E
F
A2
A1
A0
E
A18
A10
A5
A20
A19
A11
DQ2
DQ5
G
H
J
DQ0
DQ8
DQ9
DQ1
DQ7
DQ14
DQ13
DQ6
V
DQ10
DQ11
DQ3
DQ12
CCQ
G
V
DQ15
CC
K
L
V
DQ4
V
SS
SS
(1)
(1)
(1)
(1)
(1)
NC
NC
NC
NC
(1)
(1)
(1)
M
NC
NC
NC
NC
AI06879
Note: 1. Balls are shorted together via the substrate but not connected to the die.
7/42
M29W641DH, M29W641DL, M29W641DU
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
comes high-impedance. See Table 13 and Figure
12, Reset/Block Temporary Unprotect AC Charac-
teristics.
Address Inputs (A0-A21). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Note that if Write Protect (WP) is at V , then one
IL
of the two outermost blocks will remain protected
even if RP is at V .
ID
Data Inputs/Outputs (DQ8-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V , for at least
IL
t
. After Reset/Block Temporary Unprotect
PLPX
goes High, V , the memory will be ready for Bus
IH
Read and Bus Write operations after t
or
PHEL
t
, whichever occurs last. See Table 13 and
RHEL
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
Figure 12, Reset/Block Temporary Unprotect AC
Characteristics, for more details.
Holding RP at V will temporarily unprotect the
ID
High, V , all other pins are ignored.
IH
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
The transition from V to V must be slower than
IH ID
t
.
PHPHH
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Write Protect (WP). The Write Protect pin is
available in the M29W641DH and M29W641DL
only. It provides a hardware method of protecting
the highest address block for the M29W641DH
and the lowest address block for the
M29W641DL. The Write Protect pin must not be
left floating or unconnected.
V
(V ). When the V
pin is raised to V
PP PPH
PP
PP
the memory automatically enters the Unlock By-
pass mode. When the pin is returned to V or V
IH
IL
normal operation resumes. During Unlock Bypass
Program operations the memory draws I from
PP
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
V
than t
to V
VHVPP
and from V
, see Figure 13.
to V must be slower
IH
PP
PP IH
When Write Protect is Low, V , the memory pro-
IL
Never raise the pin to V from any mode except
PP
tects either the highest or lowest address block;
Program and Erase operations in this block are ig-
nored while Write Protect is Low.
Read mode, otherwise the memory may be left in
an indeterminate state.
V
Supply Voltage (2.7V to 3.6V). V
pro-
CC
CC
When Write Protect is High, V , the memory re-
IH
vides the power supply for all operations (Read,
Program and Erase).
The Command Interface is disabled when the V
verts to the previous protection status for this
block. Program and Erase operations can now
modify the data in this block unless the block is
protected using Block Protection.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
CC
Supply Voltage is less than the Lockout Voltage,
. This prevents Bus Write operations from ac-
V
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
Ready/Busy is Low, V . Ready/Busy is high-im-
OL
pedance during Read mode, Auto Select mode
and Erase Suspend mode.
V
Supply Voltage (1.8V to 3.6V). V
pro-
CCQ
CCQ
vides the power supply to the I/O pins and enables
all Outputs to be powered independently of V
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
.
CC
8/42
M29W641DH, M29W641DL, M29W641DU
V
can be tied to V
or can use a separate
0.1µF ceramic capacitor close to the pin for
current surge protection (high frequency, in-
herently low inductance capacitors should be
as close as possible to the device). See Figure
8, AC Measurement Load Circuit. The PCB
trace widths should be sufficient to carry the
CCQ
CC
supply.
V
Ground. V is the reference for all voltage
SS
SS
measurements. The device features two V pins
SS
which must be both connected to the system
ground.
Note: Each device in a system should have
required V program and erase currents. See
PP
Table 9, DC Characteristics.
V
, V
and V decoupled from V with a
CCQ PP SS
CC
Table 2. Bus Operations
Address Inputs
A0-A21
Data Inputs/Outputs
DQ15-DQ0
Operation
Bus Read
E
G
W
V
V
V
IH
Cell Address
Data Output
Data Input
Hi-Z
IL
IL
IL
IH
IH
V
V
V
V
V
Bus Write
Command Address
IL
Output Disable
Standby
X
X
IH
V
IH
X
X
X
Hi-Z
A0 = V , A1 = V , A9 = V ,
Read Manufacturer
Code
IL
IL
ID
V
V
V
V
0020h
22C7h
IL
IL
IL
IL
IH
IH
Others V or V
IL
IH
A0 = V , A1 = V , A9 = V ,
IH
IL
ID
V
V
Read Device Code
Others V or V
IL
IH
98h (factory locked, WP protects
highest address block)
18h (not factory locked, WP
protects highest address
block)
A0 = V , A1 = V , A6 = V ,
Extended Memory
Block Verify Code
IH
IH
IL
V
IL
V
V
IH
IL
A9 = V , Others V or V
IH
ID
IL
88h (factory locked, WP protects
lowest block)
08h (not factory locked, WP
protects lowest block)
Note: X = V or V
.
IH
IL
9/42
M29W641DH, M29W641DL, M29W641DU
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table 2, Bus Operations, for a summary. Typically
glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not af-
fect bus operations.
be held within V ± 0.2V. For the Standby current
level see Table 9, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
CC
Current, I
, for Program or Erase operations un-
CC3
til the operation completes.
Automatic Standby. If CMOS levels (V ± 0.2V)
CC
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
. The
CC2
Inputs, applying a Low signal, V , to Chip Enable
IL
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
and Output Enable and keeping Write Enable
High, V . The Data Inputs/Outputs will output the
IH
value, see Figure 9, Read Mode AC Waveforms,
and Table 10, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
They require V to be applied to some pins.
ID
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Table 2, Bus Operations.
able must remain High, V , during the whole Bus
Block Protect and Chip Unprotect. Groups
of
IH
Write operation. See Figure 10 and Figure 11,
Write AC Waveforms, and Table 11 and Table 12,
Write AC Characteristics, for details of the timing
requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
blocks can be protected against accidental Pro-
gram or Erase. The whole chip can be unprotected
to allow the data inside the blocks to be changed.
Write Protect (WP) can be used to protect one of
the outermost blocks. When Write Protect (WP) is
at V one of the two outermost blocks is protect-
IL
High, V .
ed and remains protected regardless of the Block
Protection Status or the Reset/Block Temporary
Unprotect pin status. For the M29W641DH, it is
the highest addressed block that can be protect-
ed. For the M29W641DL, it is the lowest.
IH
Standby. When Chip Enable is High, V , the
IH
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
, Chip Enable should
Block Protect and Chip Unprotect operations are
described in Appendix D.
CC2
10/42
M29W641DH, M29W641DL, M29W641DU
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
vice is in the Read Array mode, or when the device
is in Autoselected mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is-
sued subsequent Bus Read operations read from
the Common Flash Interface Memory Area.
The Read/Reset command must be issued to re-
turn the device to the previous mode (the Read Ar-
ray mode or Autoselected mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Autoselect-
ed mode.
See Table 3 for a summary of the commands.
Read/Reset Command
The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM. It also resets the errors in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.
The Read/Reset command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. If the Read/Reset command is issued
during the timeout of a Block erase operation then
the memory will take up to 10µs to abort. During
the abort period no valid data can be read from the
memory. The Read/Reset command will not abort
an Erase operation when issued while in Erase
Suspend.
See Appendix B, Table 18 to Table 23 for details
on the information contained in the Common Flash
Interface (CFI) memory area.
Program Command
The Program command can be used to program a
value to one address in the memory array at a
time. The command requires four Bus Write oper-
ations, the final write operation latches the ad-
dress and data, and starts the Program/Erase
Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
Auto Select Command
The Auto Select command is used to read the
Manufacturer Code, the Device Code, the Block
Protection Status and the Extended Memory Block
Verify Code. Three consecutive Bus Write opera-
tions are required to issue the Auto Select com-
mand. Once the Auto Select command is issued
the memory remains in Auto Select mode until a
Read/Reset command is issued. Read CFI Query
and Read/Reset commands are accepted in Auto
Select mode, all other commands are ignored.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 4. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
In Auto Select mode the Manufacturer Code can
be read using a Bus Read operation with A0 = V
IL
and A1 = V . The other address bits may be set to
IL
either V or V . The Manufacturer Code for ST-
IL
IH
Microelectronics is 0020h.
The Device Code can be read using a Bus Read
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
operation with A0 = V and A1 = V . The other
IH
IL
address bits may be set to either V or V . The
IL
IH
Device Code for the M29W641D is 22C7h.
The Block Protection Status of each block can be
Fast Program Commands
read using a Bus Read operation with A0 = V ,
IL
There is a Fast Program command available to im-
prove the programming throughput, by writing sev-
eral adjacent words or bytes in parallel: the Double
Word Program command.
Double Word Program Command. The Double
Word Program command is used to write a page
of two adjacent words in parallel. The two words
must differ only for the address A0.
A1 = V , and A12-A21 specifying the address of
IH
the block. The other address bits may be set to ei-
ther V or V . If the addressed block is protected
IL
IH
then 01h is output on Data Inputs/Outputs DQ0-
DQ7, otherwise 00h is output.
Read CFI Query Command
The Read CFI Query Command is used to read
data from the Common Flash Interface (CFI)
Memory Area. This command is valid when the de-
Three bus write cycles are necessary to issue the
Double Word Program command.
11/42
M29W641DH, M29W641DL, M29W641DU
■ The first bus cycle sets up the Double Word
dress and data, and starts the Program/Erase
Controller.
Program Command.
■ The second bus cycle latches the Address and
A Program operation initiated by issuing the Un-
lock Bypass Program command is identical to a
Program operation initiated by issuing the Pro-
gram command. It cannot be aborted and a Bus
Read operation will output the Status Register.
See the Program Command paragraph for further
details.
the Data of the first word to be written.
■ The third bus cycle latches the Address and the
Data of the second word to be written and starts
the Program/Erase Controller.
Only one bank can be programmed at any one
time. The other bank must be in Read mode or
Erase Suspend.
Unlock Bypass Reset Command
The Unlock Bypass Reset command can be used
to return to Read/Reset mode from Unlock Bypass
Mode. Two Bus Write operations are required to
issue the Unlock Bypass Reset command. Read/
Reset command does not exit from Unlock Bypass
Mode.
Programming should not be attempted when V
PP
is not at V
.
PPH
After programming has started, Bus Read opera-
tions in the Bank being programmed output the
Status Register content, while Bus Read opera-
tions to the other Bank output the contents of the
memory array.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg-
ister. A Read/Reset command must be issued to
reset the error condition and return to Read mode.
Note that the Fast Program commands cannot
change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Typical Program times are given in Table 4, Pro-
gram, Erase Times and Program, Erase Endur-
ance Cycles.
Chip Erase Command
The Chip Erase command can be used to erase
the entire chip. Six Bus Write operations are re-
quired to issue the Chip Erase Command and start
the Program/Erase Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap-
pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands, including the Erase Suspend com-
mand. It is not possible to issue any command to
abort the operation. Typical chip erase times are
given in Table 4. All Bus Read operations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the sec-
tion on the Status Register for more details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
Unlock Bypass Command
The Unlock Bypass command is used in conjunc-
tion with the Unlock Bypass Program command to
program the memory faster than with the standard
program commands. When the cycle time to the
device is long (as with some EPROM program-
mers) considerable time saving can be made by
using these commands. Three Bus Write opera-
tions are required to issue the Unlock Bypass
command.
Once the Unlock Bypass command has been is-
sued the memory enters Unlock Bypass mode.
When in this mode the memory can be read as if
in Read mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command
The Block Erase command can be used to erase
a list of one or more blocks. Six Bus Write opera-
tions are required to select the first block in the list.
Each additional block in the list can be selected by
repeating the sixth Bus Write operation using the
address of the additional block. The Block Erase
operation starts the Program/Erase Controller
about 50µs after the last Bus Write operation.
Once the Program/Erase Controller starts it is not
possible to select any more blocks. Each addition-
al block must therefore be selected within 50µs of
When V
is applied to the V pin the memory
PP
PPH
automatically enters the Unlock Bypass mode and
the Unlock Bypass Program command can be is-
sued immediately.
Unlock Bypass Program Command
The Unlock Bypass Program command can be
used to program one address in the memory array
at a time. The command requires two Bus Write
operations, the final write operation latches the ad-
12/42
M29W641DH, M29W641DL, M29W641DU
the lowest address block. The 50µs timer restarts
when an additional block is selected. The Status
Register can be read after the sixth Bus Write op-
eration. See the Status Register section for details
on how to identify if the Program/Erase Controller
has started the Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un-
changed. No error condition is given when protect-
ed blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
command. Typical block erase times are given in
Table 4. All Bus Read operations during the Block
Erase operation will output the Status Register on
the Data Inputs/Outputs. See the section on the
Status Register for more details.
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error condition is given. Read-
ing from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be ac-
cepted.
Erase Resume Command
The Erase Resume command must be used to re-
start the Program/Erase Controller after an Erase
Suspend. The device must be in Read Array mode
before the Resume command will be accepted. An
erase can be suspended and resumed more than
once.
Enter Extended Block Command
The device has an extra 32 KWord block (Extend-
ed Block) that can only be accessed using the En-
ter Extended Block command. Three Bus write
cycles are required to issue the Extended Block
command. Once the command has been issued
the device enters Extended Block mode where all
Bus Read or Write operations to the Boot Block
addresses access the Extended Block. The Ex-
tended Block (with the same address as the Boot
Blocks) cannot be erased, and can be treated as
one-time programmable (OTP) memory. In Ex-
tended Block mode the Boot Blocks are not acces-
sible.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Command
The Erase Suspend Command may be used to
temporarily suspend a Block Erase operation and
return the memory to Read mode. The command
requires one Bus Write operation.
To exit from the Extended Block mode the Exit Ex-
tended Block command must be issued.
The Program/Erase Controller will suspend within
the Erase Suspend Latency time of the Erase Sus-
pend Command being issued. Once the Program/
Erase Controller has stopped the memory will be
set to Read mode and the Erase will be suspend-
ed. If the Erase Suspend command is issued dur-
ing the period when the memory is waiting for an
additional block (before the Program/Erase Con-
troller starts) then the Erase is suspended immedi-
ately and will start immediately when the Erase
Resume Command is issued. It is not possible to
select any further blocks to erase after the Erase
Resume.
The Extended Block can be protected, however
once protected the protection cannot be undone.
Exit Extended Block Command
The Exit Extended Block command is used to exit
from the Extended Block mode and return the de-
vice to Read mode. Four Bus Write operations are
required to issue the command.
Block Protect and Chip Unprotect Commands
Groups of blocks can be protected against acci-
dental Program or Erase. The whole chip can be
unprotected to allow the data inside the blocks to
be changed.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspended
Block Protect and Chip Unprotect operations are
described in Appendix D.
13/42
M29W641DH, M29W641DL, M29W641DU
Table 3. Commands
Bus Write Operations
3rd 4th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command
1st
2nd
5th
6th
1
3
3
4
3
3
X
F0
AA
AA
AA
50
Read/Reset
555
555
555
555
555
2AA
2AA
2AA
55
55
55
X
F0
90
Auto Select
555
555
PA1
555
Program
A0
PA
PD
Double Word Program
Unlock Bypass
PA0 PD0
PD1
20
AA
2AA
PA
55
Unlock Bypass
Program
2
X
A0
PD
Unlock Bypass Reset
Chip Erase
2
6
X
90
AA
AA
B0
30
X
00
55
55
555
2AA
2AA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
BA
10
30
Block Erase
6+ 555
Erase Suspend
Erase Resume
1
1
1
3
4
X
X
Read CFI Query
Enter Extended Block
Exit Extended Block
55
98
555
555
AA
AA
2AA
2AA
55
55
555
555
88
90
X
00
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
Table 4. Program, Erase Times and Program, Erase Endurance Cycles
(1, 2)
(2)
Parameter
Min
Unit
Typ
80
Max
(3)
Chip Erase
s
s
400
(4)
Block Erase (32 KWords)
0.8
6
(4)
Erase Suspend Latency Time
Program (Word)
µs
µs
µs
s
50
(3)
(3)
(3)
(3)
10
10
40
20
200
200
200
100
Double Word Program
Chip Program (Word by Word)
Chip Program (Double Word)
Program/Erase Cycles (per Block)
Data Retention
s
100,000
20
cycles
years
Note: 1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and V after 100,00 program/erase cycles.
CC
4. Maximum value measured at worst case conditions for both temperature and V
.
CC
14/42
M29W641DH, M29W641DL, M29W641DU
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Sus-
pend when an address within a block being erased
is accessed.
The bits in the Status Register are summarized in
Table 5, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
Figure 5, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 6, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
15/42
M29W641DH, M29W641DL, M29W641DU
Table 5. Status Register Bits
(1)
Operation
Address
DQ7
DQ7
DQ7
DQ7
0
DQ6
DQ5
DQ3
DQ2
RB
Program
Any Address
Any Address
Any Address
Any Address
Erasing Block
Toggle
Toggle
Toggle
Toggle
Toggle
0
0
1
0
0
–
–
–
1
0
–
–
0
0
0
0
0
Program During Erase Suspend
Program Error
–
Chip Erase
Toggle
Toggle
0
Block Erase before timeout
Block Erase
No
Toggle
Non-Erasing Block
Erasing Block
0
0
0
Toggle
Toggle
Toggle
0
0
0
0
1
1
0
0
0
Toggle
No
Toggle
Non-Erasing Block
No
Toggle
Erasing Block
1
0
–
Toggle
1
1
0
0
Erase Suspend
Erase Error
Non-Erasing Block
Good Block Address
Faulty Block Address
Data read as normal
No
Toggle
0
0
Toggle
Toggle
1
1
1
1
Toggle
Note: 1. Only the M29W641DU device is concerned.
2. Unspecified data bits should be ignored.
16/42
M29W641DH, M29W641DL, M29W641DU
Figure 6. Data Toggle Flowchart
Figure 5. Data Polling Flowchart
START
START
READ DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ
DQ5 & DQ6
DQ7
=
DATA
YES
DQ6
NO
=
NO
TOGGLE
YES
NO
DQ5
= 1
NO
DQ5
YES
= 1
YES
READ DQ7
at VALID ADDRESS
READ DQ6
TWICE
DQ7
=
DATA
YES
DQ6
=
NO
NO
FAIL
TOGGLE
YES
FAIL
PASS
PASS
AI90194
AI90195B
17/42
M29W641DH, M29W641DL, M29W641DU
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 6. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
T
Temperature Under Bias
–50
125
°C
BIAS
T
–65
150
°C
STG
Storage Temperature
(1,2)
V
–0.6
–0.6
–0.6
–0.6
4
V
V
V
V
CCQ
Input/Output Supply Voltage
Supply Voltage
V
4
CC
V
Identification Voltage
13.5
13.5
ID
(3)
Program Voltage
V
PP
Note: 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to V +2V during transition and for less than 20ns during transitions.
CC
3. V must not remain at 12V for more than a total of 80hrs.
PP
18/42
M29W641DH, M29W641DL, M29W641DU
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 7. Operating and AC Measurement Conditions
M29W641D
Parameter
70
90
100
120
Unit
Min
3.0
Max
3.6
3.6
85
Min
2.7
Max
3.6
3.6
85
Min
3.0
Max
3.6
Min
2.7
Max
3.6
V
Supply Voltage
V
V
CC
V
Supply Voltage
3.0
2.7
1.65
–40
1.95
85
1.65
–40
1.95
85
CCQ
Ambient Operating Temperature
–40
–40
°C
pF
ns
V
Load Capacitance (C )
30
30
30
30
L
Input Rise and Fall Times
Input Pulse Voltages
10
10
10
10
0 to V
0 to V
0 to V
0 to V
CCQ
CCQ
CCQ
CCQ
Input and Output Timing Ref.
Voltages
V
/2
CCQ
V
/2
CCQ
V
CCQ
/2
V
CCQ
/2
V
Figure 7. AC Measurement I/O Waveform
Figure 8. AC Measurement Load Circuit
V
V
V
V
CCQ
PP
CCQ
CC
V
CCQ
25kΩ
25kΩ
V
/2
CCQ
0V
DEVICE
UNDER
TEST
AI05557b
0.1µF
0.1µF 0.1µF
C
L
C
includes JIG capacitance
L
AI05558b
Table 8. Device Capacitance
Symbol
Parameter
Test Condition
Min
Max
6
Unit
pF
C
V
= 0V
= 0V
Input Capacitance
Output Capacitance
IN
IN
C
OUT
V
OUT
12
pF
Note: Sampled only, not 100% tested.
19/42
M29W641DH, M29W641DL, M29W641DU
Table 9. DC Characteristics
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
±1
Unit
µA
I
0V ≤ V ≤ V
LI
IN
CCQ
I
LO
0V ≤ V
≤ V
OUT CCQ
±1
µA
E = V , G = V ,
IL
IH
Supply Current (Read)
10
100
20
mA
µA
I
I
CC1
CC2
f = 6 MHz
E = V ±0.2V,
CC
Supply Current (Standby)
RP = V ±0.2V
CC
V
V
pin =
PP
mA
mA
or V
IL
IH
Supply Current (Program/
Erase)
Program/Erase
Controller active
I
CC3
V
pin =
PP
20
V
PPH
V
V
≤ V
≤ V
0.8
Input Low Voltage
–0.5
V
V
IL
CCQ
CC
V
IH
V
CCQ
0.7V
V
+ 0.3
Input High Voltage
CC
CCQ
CCQ
Voltage for V
Acceleration
Program
PP
V
V
V
= 3.0V ±10%
= 3.0V ±10%
11.5
12.5
V
PPH
CC
CC
Current for V
Acceleration
Program
PP
I
15
mA
PP
V
I
= 4.0mA, V = V
OL CC CCmin
Output Low Voltage
Output High Voltage
Identification Voltage
0.45
V
V
V
V
OL
I
I
= –2.0mA, V = V
0.85V
CCQ
OH
CC
CCmin
(1)
V
OH
V
– 0.4
= –100µA, V = V
CCQ
OH
CC
CCmin
V
11.5
1.8
12.5
2.3
ID
Program/Erase Lockout Supply
Voltage
(1)
V
V
LKO
Note: 1. Sampled only, not 100% tested.
20/42
M29W641DH, M29W641DL, M29W641DU
Figure 9. Read Mode AC Waveforms
tAVAV
VALID
A0-A21
tAVQV
tAXQX
E
tELQV
tELQX
tEHQX
tEHQZ
G
tGLQX
tGLQV
tGHQX
tGHQZ
DQ0-DQ7/
DQ8-DQ15
VALID
AI06699
Table 10. Read AC Characteristics
M29W641D
Symbol
Alt
Parameter
Test Condition
Unit
70
90
100
120
E = V ,
IL
t
t
Address Valid to Next Address Valid
Address Valid to Output Valid
Min
70
90
100
120
ns
ns
AVAV
RC
G = V
IL
E = V ,
IL
t
t
ACC
Max
70
90
100
120
AVQV
G = V
G = V
G = V
E = V
IL
IL
IL
(1)
t
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
Output Enable Low to Output Transition
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Min
Max
Min
0
0
0
100
0
0
120
0
ns
ns
ns
ns
ns
ns
t
t
LZ
ELQX
t
t
70
0
90
0
ELQV
CE
(1)
t
OLZ
IL
IL
GLQX
t
t
E = V
Max
Max
Max
30
25
25
35
30
30
35
30
30
50
30
30
GLQV
OE
(1)
(1)
t
G = V
t
HZ
IL
IL
EHQZ
t
E = V
t
DF
GHQZ
t
t
t
EHQX
Chip Enable, Output Enable or Address
Transition to Output Transition
t
Min
0
0
0
0
ns
GHQX
OH
AXQX
Note: 1. Sampled only, not 100% tested.
21/42
M29W641DH, M29W641DL, M29W641DU
Figure 10. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A21
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
VALID
tWHDX
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHEL
RB
tWHRL
AI06800b
Note: 1. RB concerns the M29W461DU only.
Table 11. Write AC Characteristics, Write Enable Controlled
M29W641D
Symbol
Alt
Parameter
Unit
70
70
0
90
90
0
100
100
0
120
120
0
t
t
WC
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
AVAV
t
t
CS
ELWL
t
t
WP
35
45
0
35
45
0
35
45
0
50
50
0
WLWH
t
t
DVWH
DS
DH
CH
t
t
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
Write Enable High to Output Enable Low
Program/Erase Valid to RB Low
WHDX
t
t
0
0
0
0
WHEH
t
t
WPH
30
0
30
0
30
0
30
0
WHWL
t
t
AVWL
AS
t
t
45
0
45
0
45
0
50
0
WLAX
AH
t
GHWL
t
t
OEH
0
0
0
0
WHGL
(1)
t
90
50
90
50
90
50
90
50
t
BUSY
WHRL
t
t
V
CC
High to Chip Enable Low
VCHEL
VCS
Note: 1. This timing concerns the M29W461DU only.
22/42
M29W641DH, M29W641DL, M29W641DU
Figure 11. Write AC Waveforms, Chip Enable Controlled
tAVAV
VALID
A0-A21
tELAX
tAVEL
tEHWH
W
G
E
tWLEL
tEHGL
tGHEL
tELEH
tEHEL
tDVEH
VALID
tEHDX
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHWL
RB
tEHRL
AI06801b
Note: 1. RB concerns the M29W461DU only.
Table 12. Write AC Characteristics, Chip Enable Controlled
M29W641D
Symbol
Alt
Parameter
Unit
70
70
0
90
90
0
100
100
0
120
120
0
t
t
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
WC
t
t
WLEL
WS
t
t
45
45
0
45
45
0
45
45
0
50
50
0
ELEH
CP
DS
DH
t
t
DVEH
t
t
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
Chip Enable High to Output Enable Low
Program/Erase Valid to RB Low
EHDX
t
t
WH
0
0
0
0
EHWH
t
t
30
0
30
0
30
0
30
0
EHEL
CPH
t
t
AVEL
AS
t
t
45
0
45
0
45
0
50
0
ELAX
AH
t
GHEL
t
t
0
0
0
0
EHGL
OEH
(1)
t
90
50
90
50
90
50
90
50
t
BUSY
EHRL
t
t
V
CC
High to Write Enable Low
Min
µs
VCHWL
VCS
Note: 1. This timing concerns the M29W461DU only.
23/42
M29W641DH, M29W641DL, M29W641DU
Figure 12. Reset/Block Temporary Unprotect AC Waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPHPHH
tPLPX
RP
tPLYH
AI06802b
Note: 1. RB concerns the M29W461DU only.
Table 13. Reset/Block Temporary Unprotect AC Characteristics
M29W641D
Symbol
Alt
Parameter
Unit
70
90
100
120
(1)
t
PHWL
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
t
t
Min
Min
50
50
50
50
ns
PHEL
RH
(1)
t
PHGL
(1, 2)
t
RHWL
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
(1, 2)
(1, 2)
t
0
0
0
0
ns
t
RB
RHEL
t
RHGL
t
t
READY
RP Low to Read Mode
Max
Min
Min
50
50
50
50
µs
ns
ns
PLYH
t
t
RP Pulse Width
500
500
500
500
500
500
500
500
PLPX
RP
(1)
(1)
t
RP Rise Time to V
t
VIDR
ID
PHPHH
V
PP
Rise and Fall Time
Min
250
250
250
250
ns
t
VHVPP
Note: 1. Sampled only, not 100% tested.
2. These timings concern the M29W461DU only.
Figure 13. Accelerated Program Timing Waveforms
V
PP
V
Pin
PP
V
or V
IH
IL
tVHVPP
tVHVPP
AI06806
24/42
M29W641DH, M29W641DL, M29W641DU
PACKAGE MECHANICAL
Figure 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Note: Drawing is not to scale.
Table 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
0.270
0.210
0.100
20.200
18.500
–
Typ
Max
0.0472
0.0059
0.0413
0.0106
0.0083
0.0039
0.7953
0.7283
–
A
A1
A2
B
0.100
1.000
0.050
0.950
0.170
0.100
0.0039
0.0394
0.0020
0.0374
0.0067
0.0039
C
CP
D
19.800
18.300
–
0.7795
0.7205
–
D1
e
0.500
0.0197
E
11.900
0.500
0
12.100
0.700
5
0.4685
0.0197
0
0.4764
0.0276
5
L
alfa
N
48
48
25/42
M29W641DH, M29W641DL, M29W641DU
Figure 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Bottom view package outline
D
D1
SD
FD
e
ddd
SE
E
E1
BALL "A1"
FE
e
b
A
A2
A1
BGA-Z33
Note: Drawing is not to scale.
Table 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.250
0.0098
0.900
0.0354
0.350
0.450
0.0138
0.0177
D
7.000
5.600
–
6.900
7.100
0.2756
0.2205
–
0.2717
0.2795
D1
ddd
E
–
–
–
–
–
0.100
–
0.0039
11.000
8.800
0.800
0.700
1.100
0.400
0.400
10.900
11.100
0.4331
0.3465
0.0315
0.0276
0.0433
0.0157
0.0157
0.4291
0.4370
E1
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FD
FE
SD
SE
26/42
M29W641DH, M29W641DL, M29W641DU
PART NUMBERING
Table 16. Ordering Information Scheme
Example:
M29W641DL
70
N
1
T
Device Type
M29
Operating Voltage
W = V = 2.7 to 3.6V
CC
Device Function
641DH = 64 Mbit (x16), Uniform Block, Write Protection on highest
address Block
641DL = 64 Mbit (x16), Uniform Block, Write Protection on Lowest
Address Block
641DU = 64 Mbit (x16), Uniform Block, No Write Protection
Speed
70 = 70ns
90 = 90ns
10 = 100ns
12 = 120ns
Package
N = TSOP48: 12 x 20 mm (M29W641DH and M29W641DL only)
ZA = TFBGA63: 7 x 11mm, 0.80mm pitch (M29W641DU only)
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing
Note: This product is also available with the Extended Block factory locked. For further details and ordering
information contact your nearest ST sales office.
Devices are shipped from the factory with the memory content bits erased to 1. For a list of available op-
tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact your
nearest ST Sales Office.
27/42
M29W641DH, M29W641DL, M29W641DU
APPENDIX A. BLOCK ADDRESSES
Table 17. Block Addresses
Block
0
KWords
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Protection Block Group
Address Range
(1)
000000h–007FFFh
1
008000h–00FFFFh
010000h–017FFFh
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
0D0000h–0D7FFFh
0D8000h–0DFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
0F8000h–0FFFFFh
Protection Group
2
3
4
5
Protection Group
Protection Group
Protection Group
Protection Group
Protection Group
Protection Group
Protection Group
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
28/42
M29W641DH, M29W641DL, M29W641DU
Block
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
KWords
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Protection Block Group
Address Range
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
Protection Group
Protection Group
Protection Group
Protection Group
Protection Group
Protection Group
Protection Group
Protection Group
Protection Group
29/42
M29W641DH, M29W641DL, M29W641DU
Block
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
KWords
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Protection Block Group
Address Range
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–287FFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2F7FFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
Protection Group
Protection Group
Protection Group
Protection Group
Protection Group
Protection Group
Protection Group
Protection Group
Protection Group
30/42
M29W641DH, M29W641DL, M29W641DU
Block
104
105
106
107
108
109
110
111
KWords
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Protection Block Group
Address Range
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
Protection Group
Protection Group
Protection Group
Protection Group
Protection Group
Protection Group
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
32
3F8000h–3FFFFFh
Note: 1. Used as the Extended Block Addresses in Extended Block mode.
31/42
M29W641DH, M29W641DL, M29W641DU
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem-
ory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
When the CFI Query Command is issued the de-
vice enters CFI Query mode and the data structure
is read from the memory. Table 18 to Table 23
show the addresses used to retrieve the data.
The CFI data structure also contains a security
area where a 64 bit unique security number is writ-
ten (see Table 23, Security Code Area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security num-
ber after it has been written by ST.
Table 18. Query Structure Overview
Address
10h
Sub-section Name
CFI Query Identification String
System Interface Information
Device Geometry Definition
Description
Command set ID and algorithm data offset
Device timing & voltage information
Flash device layout
1Bh
27h
Primary Algorithm-specific Extended
Query table
Additional information specific to the Primary
Algorithm (optional)
40h
61h
Security Code Area
64 bit unique device number
Note: Query data are always presented on the lowest order data outputs.
Table 19. CFI Query Identification String
Address
10h
Data
Description
Value
“Q”
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
11h
Query Unique ASCII String "QRY"
"R"
12h
"Y"
13h
Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm
AMD
Compatible
14h
15h
Address for Primary Algorithm extended Query table (see Table 22)
P = 40h
NA
16h
17h
Alternate Vendor Command Set and Control Interface ID Code second
vendor - specified algorithm supported
18h
19h
Address for Alternate Algorithm extended Query table
NA
1Ah
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
32/42
M29W641DH, M29W641DL, M29W641DU
Table 20. CFI Query System Interface Information
Address
Data
Description
Value
V
V
V
V
Logic Supply Minimum Program/Erase voltage
CC
1Bh
0027h
2.7V
bit 7 to 4
bit 3 to 0
BCD value in volts
BCD value in 100 mV
Logic Supply Maximum Program/Erase voltage
CC
1Ch
1Dh
1Eh
0036h
00B5h
00C5h
3.6V
11.5V
12.5V
bit 7 to 4
bit 3 to 0
BCD value in volts
BCD value in 100 mV
[Programming] Supply Minimum Program/Erase voltage
PP
bit 7 to 4
bit 3 to 0
HEX value in volts
BCD value in 100 mV
[Programming] Supply Maximum Program/Erase voltage
PP
bit 7 to 4
bit 3 to 0
HEX value in volts
BCD value in 100 mV
n
1Fh
20h
21h
22h
23h
24h
25h
26h
0004h
0000h
000Ah
0000h
0004h
0000h
0003h
0000h
16µs
NA
Typical timeout per single word program = 2 µs
n
Typical timeout for minimum size write buffer program = 2 µs
n
1s
Typical timeout per individual block erase = 2 ms
n
NA
Typical timeout for full chip erase = 2 ms
n
256 µs
NA
Maximum timeout for word program = 2 times typical
n
Maximum timeout for write buffer program = 2 times typical
n
8 s
Maximum timeout per individual block erase = 2 times typical
n
NA
Maximum timeout for chip erase = 2 times typical
Table 21. Device Geometry Definition
Address
Data
Description
Value
n
27h
0017h
8 MByte
Device Size = 2 in number of bytes
28h
29h
0001h
0000h
x16
Async.
Flash Device Interface Code description
2Ah
2Bh
0000h
0000h
n
NA
1
Maximum number of bytes in multi-byte program or page = 2
Number of Erase Block Regions. It specifies the number of
2Ch
0001h
regions containing contiguous Erase Blocks of the same size.
2Dh
2Eh
007Fh
0000h
Region 1 Information
Number of identical size erase block = 007Fh+1
128
2Fh
30h
0000h
0001h
Region 1 Information
Block size in Region 1 = 0100h * 256 byte
64 KByte
33/42
M29W641DH, M29W641DL, M29W641DU
Table 22. Primary Algorithm-Specific Extended Query Table
Address
40h
Data
Description
Value
"P"
"R"
"I"
0050h
0052h
0049h
0031h
0030h
0000h
41h
Primary Algorithm extended Query table unique ASCII string “PRI”
42h
43h
Major version number, ASCII
Minor version number, ASCII
"1"
44h
"0"
45h
Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Yes
Silicon Revision Number (bits 7 to 2)
46h
47h
48h
49h
0002h
0004h
0001h
0004h
Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write
2
4
Block Protection
00 = not supported, x = number of blocks per protection group
Temporary Block Unprotect
00 = not supported, 01 = supported
Yes
4
Block Protect /Unprotect
04 = M29W400B
4Ah
4Bh
4Ch
4Dh
0000h
0000h
0000h
00B5h
Simultaneous Operations, 00 = not supported
No
No
Burst Mode, 00 = not supported, 01 = supported
Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word
No
V
PP
Supply Minimum Program/Erase voltage
11.5V
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
4Eh
00C5h
V
PP
Supply Maximum Program/Erase voltage
12.5V
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
Table 23. Security Code Area
Address
61h
Data
XXXX
XXXX
XXXX
XXXX
Description
62h
64 bit: unique device number
63h
64h
34/42
M29W641DH, M29W641DL, M29W641DU
Factory Locked Extended Block
In devices where the Extended Block is factory
locked, the Security Identification Number is writ-
ten to the Extended Block address space (see Ta-
ble 24, Extended Block Address and Data) in the
factory. The DQ7 bit is set to ‘1’ and the Extended
Block cannot be unprotected.
APPENDIX C. EXTENDED MEMORY BLOCK
The M29W641D has an extra block, the Extended
Block, that can be accessed using a dedicated
command.
This Extended Block is 32 KWords. It is used as a
security block (to provide a permanent security
identification number) or to store additional infor-
mation.
The Extended Block is either Factory Locked or
Customer Lockable, its status is indicated by bit
DQ7. This bit is permanently set to either ‘1’ or ‘0’
at the factory and cannot be changed. When set to
‘1’, it indicates that the device is factory locked and
the Extended Block is protected. When set to ‘0’, it
indicates that the device is customer lockable and
the Extended Block is unprotected. Bit DQ7 being
permanently locked to either ‘1’ or ‘0’ is another
security feature which ensures that a customer
lockable device cannot be used instead of a facto-
ry locked one.
Bit DQ7 is the most significant bit in the Extended
Block Verify Code and a specific procedure must
be followed to read it. See “Extended Memory
Block Verify Code” in Table 2, Bus Operations, for
details of how to read bit DQ7.
Customer Lockable Extended Block
A device where the Extended Block is customer
lockable is delivered with the DQ7 bit set to ‘0’ and
the Extended Block unprotected. It is up to the
customer to program and protect the Extended
Block but care must be taken because the protec-
tion of the Extended Block is not reversible.
There are two ways of protecting the Extended
Block:
■ Issue the Enter Extended Block command to
place the device in Extended Block mode, then
use the In-System Technique (refer to Appendix
D, In-System Technique and to the
corresponding flowcharts, Figures 18 and 19,
for a detailed explanation of the technique).
■ Issue the Enter Extended Block command to
place the device in Extended Block mode, then
use the Programmer Technique (refer to
The Extended Block can only be accessed when
the device is in Extended Block mode. For details
of how the Extended Block mode is entered and
exited, refer to the Enter Extended Block Com-
mand and Exit Extended Block Command para-
graphs, and to Table 3, “Commands”.
Appendix D, Programmer Technique and to the
corresponding flowcharts, Figures 16 and 17,
for a detailed explanation of the technique).
Once the Extended Block is programmed and pro-
tected, the Exit Extended Block command must be
issued to exit the Extended Block mode and return
the device to Read mode.
Table 24. Extended Block Address and Data
(1)
Data
Address
Device
x16
Factory Locked
Security Identification Number
Unavailable
Customer Lockable
000000h-000007h
M29W641D
Determined by Customer
000008h-007FFFh
Note: 1. See Table 17, Block Addresses.
35/42
M29W641DH, M29W641DL, M29W641DU
APPENDIX D. BLOCK PROTECTION
Block protection can be used to prevent any oper-
ation from modifying the data stored in the memo-
ry. Once protected, Program and Erase
operations within the protected group fail to
change the data.
specified, it is followed as closely as possible. Do
not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.
There are three techniques that can be used to
control Block Protection, these are the Program-
mer technique, the In-System technique and Tem-
porary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unpro-
tection pin, RP; this is described in the Signal De-
scriptions section.
In-System Technique
The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP. This can be achieved without violating the
maximum ratings of the components on the micro-
processor bus, therefore this technique is suitable
for use after the memory has been fitted to the sys-
tem.
Programmer Technique
The Programmer technique uses high (V ) volt-
To protect a group of blocks follow the flowchart in
Figure 18, In-System Equipment Group Protect
Flowchart. To unprotect the whole chip it is neces-
sary to protect all of the groups first, then all the
groups can be unprotected at the same time. To
unprotect the chip follow Figure 19, In-System
Equipment Chip Unprotect Flowchart.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not allow the microprocessor to service interrupts
that will upset the timing and do not abort the pro-
cedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.
ID
age levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended only for
use in Programming Equipment.
To protect a group of blocks follow the flowchart in
Figure 16, Programmer Equipment Group Protect
Flowchart. To unprotect the whole chip it is neces-
sary to protect all of the groups first, then all
groups can be unprotected at the same time. To
unprotect the chip follow Figure 17, Programmer
Equipment Chip Unprotect Flowchart. Table 25,
Programmer Technique Bus Operations, gives a
summary of each operation.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
Table 25. Programmer Technique Bus Operations
Address Inputs
A0-A21
Data Inputs/Outputs
DQ15-DQ0
Operation
E
G
W
Block (Group)
A9 = V , A12-A21 Block Address
ID
V
V
V
V
Pulse
Pulse
X
X
IL
ID
ID
IL
IL
(1)
Others = X
Protect
A9 = V , A12 = V , A15 = V
ID
IH
IH
V
ID
V
Chip Unprotect
Others = X
A0 = V , A1 = V , A6 = V , A9 = V ,
IL
IH
IL
ID
Block (Group)
Protection Verify
Pass = XX01h
Retry = XX00h
V
V
V
V
A12-A21 Block Address
Others = X
IL
IL
IL
IL
IH
IH
A0 = V , A1 = V , A6 = V , A9 = V ,
IL
IH
IH
ID
Block (Group)
Unprotection Verify
Retry = XX01h
Pass = XX00h
V
V
A12-A21 Block Address
Others = X
Note: 1. Block Protection Groups are shown in Appendix A, Tables 17.
36/42
M29W641DH, M29W641DL, M29W641DU
Figure 16. Programmer Equipment Group Protect Flowchart
START
ADDRESS = GROUP ADDRESS
W = V
IH
n = 0
G, A9 = V
E = V
,
ID
IL
Wait 4µs
W = V
IL
Wait 100µs
W = V
IH
E, G = V
,
IH
A0, A6 = V
A1 = V
,
IL
IH
E = V
IL
Wait 4µs
G = V
IL
Wait 60ns
Read DATA
DATA
=
01h
NO
YES
++n
= 25
NO
A9 = V
IH
E, G = V
IH
YES
PASS
A9 = V
E, G = V
IH
IH
AI05574
FAIL
37/42
M29W641DH, M29W641DL, M29W641DU
Figure 17. Programmer Equipment Chip Unprotect Flowchart
START
PROTECT ALL GROUPS
n = 0
CURRENT GROUP = 0
(1)
A6, A12, A15 = V
IH
E, G, A9 = V
ID
Wait 4µs
W = V
IL
Wait 10ms
W = V
IH
E, G = V
IH
ADDRESS = CURRENT GROUP ADDRESS
A0 = V , A1, A6 = V
IL
IH
E = V
IL
Wait 4µs
G = V
IL
INCREMENT
CURRENT GROUP
Wait 60ns
Read DATA
NO
YES
DATA
=
00h
LAST
GROUP
NO
NO
++n
= 1000
YES
YES
A9 = V
A9 = V
E, G = V
IH
IH
E, G = V
IH
IH
FAIL
PASS
AI05575
38/42
M29W641DH, M29W641DL, M29W641DU
Figure 18. In-System Equipment Group Protect Flowchart
START
n = 0
RP = V
ID
WRITE 60h
ADDRESS = GROUP ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
WRITE 60h
ADDRESS = GROUP ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
Wait 100µs
WRITE 40h
IL
ADDRESS = GROUP ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
Wait 4µs
READ DATA
ADDRESS = GROUP ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
DATA
NO
=
01h
YES
RP = V
++n
= 25
NO
IH
YES
RP = V
ISSUE READ/RESET
COMMAND
IH
PASS
ISSUE READ/RESET
COMMAND
FAIL
AI05576
39/42
M29W641DH, M29W641DL, M29W641DU
Figure 19. In-System Equipment Chip Unprotect Flowchart
START
PROTECT ALL GROUPS
n = 0
CURRENT GROUP = 0
RP = V
ID
WRITE 60h
ANY ADDRESS WITH
A0 = V , A1 = V , A6 = V
IL
IH
IH
IH
WRITE 60h
ANY ADDRESS WITH
A0 = V , A1 = V , A6 = V
IL
IH
Wait 10ms
WRITE 40h
ADDRESS = CURRENT GROUP ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IH
Wait 4µs
INCREMENT
CURRENT GROUP
READ DATA
ADDRESS = CURRENT GROUP ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IH
DATA
NO
YES
=
00h
++n
= 1000
NO
NO
LAST
GROUP
YES
RP = V
YES
RP = V
IH
IH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
PASS
FAIL
AI05577
40/42
M29W641DH, M29W641DL, M29W641DU
REVISION HISTORY
Table 26. Document Revision History
Date
Version
Revision Details
30-Apr-2002
-01
Document released
When in Extended Block mode, the block at the boot block address can be used as OTP.
Data Toggle Flow chart corrected. Double Word Program Time (typ) changed to 20s.
Revision numbering modified: a minor revision will be indicated by incrementing the digit
after the dot, and a major revision, by incrementing the digit before the dot (revision
version 01 equals 1.0).
05-Sep-2002
1.1
New Part Numbers added. 100ns and 120ns Speed Classes added. TFBGA63 package
added. V removed from and V
added to Table 6, Absolute Maximum Ratings. V
IO
CCQ
CCQ
added to Table 7, Operating and AC Measurement Conditions. Ready/Busy pin
(TFBGA63 package) added to the signals (concerns M29W641DU only).
Figure 7, AC Measurement I/O Waveform, and Figure 8, AC Measurement Load Circuit,
modified. Unlock Bypass Commands clarified and V description specified in SIGNAL
CCQ
DESCRIPTIONS section. Test Conditions modified for I , I , V , V , V and V
OH
LI LO IL
IH OL
parameters in Table 9, DC Characteristics, and V , V , V and V parameters
IL
IH OL
OH
corrected. t
, t
, t
, t
parameters modified for 90ns speed class in Table
WLWH DVWH WLAX WHRL
11, Write AC Characteristics, Write Enable Controlled. t
, t
, t
and t
ELEH DVEH ELAX EHRL
parameters modified for 90ns speed class in Table 12, Write AC Characteristics, Chip
8-Apr-2003
2.0
Enable Controlled. t
parameter added to Table 13, Reset/Block Temporary Unprotect
PLYH
AC Characteristics.
Data and Value modified for address 2Dh, and Data modified for address 30h in Table 21,
Device Geometry Definition. Description modified at address offset 4Eh in Table 22.
Data Retention and Erase Suspend Latency Time parameters added to Table 6, Program,
Erase Times and Program, Erase Endurance Cycles, and Typical after 100k W/E Cycles
column removed. I (Identification) current removed from Table 9, DC Characteristics.
ID
Lead-free package options E and F added to Table 16, Ordering Information Scheme.
Appendix C, EXTENDED MEMORY BLOCK, added. V pin connection to ground
SS
clarified. Auto Select Command is used to read the Extended Memory Block. Note added
to Table 16, Ordering Information Scheme.
41/42
M29W641DH, M29W641DL, M29W641DU
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2003 STMicroelectronics - All Rights Reserved
STMicroelectronics group of companies
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42/42
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M29W800AB100M6T
8 Mbit 1Mb x8 or 512Kb x16, Boot Block Low Voltage Single Supply Flash Memory
STMICROELECTR
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