M29W400DT55M1E [STMICROELECTRONICS]
4 Mbit (512Kb x8 or 256Kb x16, Boot Block) 3V Supply Flash Memory; 4兆位（ 512KB ×8或256Kb的X16 ，引导块） 3V供应闪存
| 型号： | M29W400DT55M1E |
| 厂家： | 
ST |
| 描述： | 4 Mbit (512Kb x8 or 256Kb x16, Boot Block) 3V Supply Flash Memory |
| 文件： | 总36页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M29W400DT
M29W400DB
4 Mbit (512Kb x8 or 256Kb x16, Boot Block)
3V Supply Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
■ SUPPLY VOLTAGE
Figure 1. Packages
– V = 2.7V to 3.6V for Program, Erase and
CC
Read
■ ACCESS TIME: 45, 55, 70ns
■ PROGRAMMING TIME
– 10µs per Byte/Word typical
■ 11 MEMORY BLOCKS
SO44 (M)
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 8 Main Blocks
■ PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program algorithms
■ ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
TSOP48 (N)
12 x 20mm
■ UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
FBGA
■ TEMPORARY BLOCK UNPROTECTION
MODE
■ LOW POWER CONSUMPTION
TFBGA48 (ZA)
6 x 9mm
– Standby and Automatic Standby
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29W400DT: 00EEh
– Bottom Device Code M29W400DB: 00EFh
February 2003
1/36
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M29W400DT, M29W400DB
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Input/Output or Address Input (DQ15A-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
V
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CC
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Special Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. Bus Operations, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
IL
Table 3. Bus Operations, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IH
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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M29W400DT, M29W400DB
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Block Protect and Chip Unprotect Commands.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Commands, 16-bit mode, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
IH
Table 6. Commands, 8-bit mode, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
IL
Table 4. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 14
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 15. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 16. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline . . . . . . . . 25
Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data 25
Figure 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 26
Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 26
Figure 18. TFBGA48 6x9mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline . . . 27
Table 18. TFBGA48 6x9mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data. . 27
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/36
M29W400DT, M29W400DB
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 20. Top Boot Block Addresses M29W400DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21. Bottom Boot Block Addresses M29W400DB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
APPENDIX B. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 22. Programmer Technique Bus Operations, BYTE = V or V . . . . . . . . . . . . . . . . . . . . . 30
IH
IL
Figure 19. Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 20. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 21. In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 22. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 23. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 35
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M29W400DT, M29W400DB
SUMMARY DESCRIPTION
The M29W400D is a 4 Mbit (512Kb x8 or 256Kb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.
command set required to control the memory is
consistent with JEDEC standards.
The blocks in the memory are asymmetrically ar-
ranged, see Figures 6 and 7, Block Addresses.
The first or last 64 Kbytes have been divided into
four additional blocks. The 16 Kbyte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 Kbyte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the ap-
plication may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents.
The memory is offered in SO44, TSOP48 (12 x
20mm) and TFBGA48 (0.8mm pitch) packages.
The memory is supplied with all the bits erased
(set to ’1’).
The end of a program or erase operation can be
detected and any error conditions identified. The
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A17
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
Data Inputs/Outputs
Data Input/Output or Address Input
Chip Enable
V
CC
DQ8-DQ14
DQ15A–1
18
15
A0-A17
DQ0-DQ14
E
G
Output Enable
W
E
DQ15A–1
BYTE
RB
M29W400DT
M29W400DB
W
RP
Write Enable
Reset/Block Temporary Unprotect
G
Ready/Busy Output
(not available on SO44 package)
RP
RB
BYTE
Byte/Word Organization Select
Supply Voltage
V
CC
V
SS
AI06853
V
SS
Ground
NC
Not Connected Internally
5/36
M29W400DT, M29W400DB
Figure 3. SO Connections
Figure 4. TSOP Connections
A15
A14
A13
A12
A11
A10
A9
1
48
A16
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP
NC
RB
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
BYTE
2
W
V
SS
3
A8
DQ15A–1
4
A9
DQ7
5
A10
A11
A12
A13
A14
A15
A16
BYTE
DQ14
DQ6
6
7
A8
DQ13
DQ5
8
NC
NC
W
9
DQ12
DQ4
10
11
12
13
14
15
16
17
18
19
20
21
22
M29W400DT
M29W400DB
RP
NC
NC
RB
NC
A17
A7
12
13
37
36
V
M29W400DT
M29W400DB
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V
V
SS
DQ15A–1
SS
G
DQ0
DQ8
DQ7
DQ14
DQ6
DQ1
DQ9
DQ13
DQ5
A6
DQ2
A5
DQ10
DQ3
DQ12
DQ4
A4
A3
V
E
SS
DQ11
V
CC
A2
AI06855
A1
24
25
A0
AI06854
Note: 1. NC = Not Connected
Note: 1. NC = Not Connected
6/36
M29W400DT, M29W400DB
Figure 5. TFBGA Connections (Top view through package)
1
2
3
4
5
6
A9
A8
A
B
C
D
E
F
A3
A4
A7
RB
NC
W
A13
A12
RP
A17
A2
A1
A6
A5
NC
NC
NC
NC
A10
A11
A14
A15
A0
DQ0
DQ2
DQ5
DQ7
A16
DQ12
DQ14
DQ13
DQ6
E
DQ8
DQ9
DQ1
DQ10
DQ11
DQ3
BYTE
DQ15
A–1
G
H
G
V
CC
V
DQ4
V
SS
SS
AI06856
Note: 1. NC = Not Connected
7/36
M29W400DT, M29W400DB
Figure 6. Block Addresses (x8)
M29W400DT
M29W400DB
Top Boot Block Addresses (x8)
Bottom Boot Block Addresses (x8)
7FFFFh
7FFFFh
16 KByte
64 KByte
64 KByte
7C000h
7BFFFh
70000h
6FFFFh
8 KByte
7A000h
79FFFh
60000h
Total of 7
64 KByte Blocks
8 KByte
78000h
77FFFh
32 KByte
70000h
6FFFFh
1FFFFh
64 KByte
64 KByte
32 KByte
8 KByte
8 KByte
16 KByte
60000h
10000h
0FFFFh
08000h
07FFFh
Total of 7
64 KByte Blocks
06000h
05FFFh
1FFFFh
64 KByte
10000h
0FFFFh
04000h
03FFFh
64 KByte
00000h
00000h
AI06857
Note: Also see Appendix A, Tables 20 and 21 for a full listing of the Block Addresses.
8/36
M29W400DT, M29W400DB
Figure 7. Block Addresses (x16)
M29W400DT
Top Boot Block Addresses (x16)
M29W400DB
Bottom Boot Block Addresses (x16)
3FFFFh
8 KWord
3E000h
3DFFFh
3FFFFh
32 KWord
32 KWord
38000h
37FFFh
4 KWord
3D000h
3CFFFh
30000h
Total of 7
32 KWord Blocks
4 KWord
3C000h
3BFFFh
16 KWord
38000h
37FFFh
0FFFFh
32 KWord
32 KWord
16 KWord
4 KWord
4 KWord
8 KWord
30000h
08000h
07FFFh
04000h
03FFFh
Total of 7
32 KWord Blocks
03000h
02FFFh
0FFFFh
32 KWord
08000h
07FFFh
02000h
01FFFh
32 KWord
00000h
00000h
AI06858
Note: Also see Appendix A, Tables 20 and 21 for a full listing of the Block Addresses.
9/36
M29W400DT, M29W400DB
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A17). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Outputs (DQ8-DQ14). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
goes High, V , the memory will be ready for Bus
IH
Read and Bus Write operations after t
or
PHEL
t
, whichever occurs last. See the Ready/Busy
RHEL
Output section, Table 15 and Figure 15, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V will temporarily unprotect the
ID
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V to V must be slower than
IH
ID
t
.
PHPHH
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 15 and Figure
15, Reset/Temporary Unprotect AC Characteris-
tics.
is High, V . When BYTE is Low, V , these pins
IH
IL
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
During Program or Erase operations Ready/Busy
Data Input/Output or Address Input (DQ15A-1).
is Low, V . Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
OL
When BYTE is High, V , this pin behaves as a
IH
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V , this pin behaves as an address
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the 8-bit and 16-bit Bus modes of
the memory. When Byte/Word Organization Se-
IL
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
lect is Low, V , the memory is in 8-bit mode, when
IL
it is High, V , the memory is in 16-bit mode.
IH
V
Supply Voltage. The V
Supply Voltage
CC
CC
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
High, V , all other pins are ignored.
IH
V
. This prevents Bus Write operations from ac-
LKO
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
the V
Supply Voltage pin and the V Ground
CC
SS
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
.
CC3
A Hardware Reset is achieved by holding Reset/
V
Ground. The V Ground is the reference for
SS
SS
Block Temporary Unprotect Low, V , for at least
IL
all voltage measurements.
t
. After Reset/Block Temporary Unprotect
PLPX
10/36
M29W400DT, M29W400DB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 2 and 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
ance state. To reduce the Supply Current to the
Standby Supply Current, I
, Chip Enable should
CC2
be held within V ± 0.2V. For the Standby current
CC
level see Table 11, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
, for Program or Erase operations un-
CC3
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
til the operation completes.
Automatic Standby. If CMOS levels (V ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations. Additional bus opera-
tions can be performed to read the Electronic Sig-
nature and also to apply and remove Block
Protection. These bus operations are intended for
use by programming equipment and are not usu-
ally used in applications. They require V to be
applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 2 and 3, Bus Operations.
CC
Inputs, applying a Low signal, V , to Chip Enable
IL
and Output Enable and keeping Write Enable
. The
CC2
High, V . The Data Inputs/Outputs will output the
IH
value, see Figure 12, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
ID
able must remain High, V , during the whole Bus
IH
Write operation. See Figures 13 and 14, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing require-
ments.
Block Protection and Blocks Unprotection.
Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow data to be changed.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. Block Protect and Chip Unprotect operations
are described in Appendix B.
High, V .
IH
Standby. When Chip Enable is High, V , the
IH
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
Table 2. Bus Operations, BYTE = V
IL
Data Inputs/Outputs
Address Inputs
DQ15A–1, A0-A17
Operation
E
G
W
DQ14-DQ8
Hi-Z
DQ7-DQ0
Data Output
Data Input
Hi-Z
V
IL
V
V
IH
Bus Read
Cell Address
IL
IH
IH
V
IL
V
V
V
V
Bus Write
Command Address
Hi-Z
IL
Output Disable
Standby
X
X
Hi-Z
IH
V
X
X
X
Hi-Z
Hi-Z
IH
A0 = V , A1 = V , A9 = V ,
Read Manufacturer
Code
IL
IL
ID
V
V
V
V
V
Hi-Z
Hi-Z
20h
IL
IL
IL
IL
IH
IH
Others V or V
IL
IH
A0 = V , A1 = V , A9 = V ,
EEh (M29W400DT)
EFh (M29W400DB)
IH
IL
ID
V
Read Device Code
Others V or V
IL
IH
Note: X = V or V
.
IH
IL
11/36
M29W400DT, M29W400DB
Table 3. Bus Operations, BYTE = V
IH
Address Inputs
A0-A17
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Operation
Bus Read
E
G
W
V
IL
V
V
IH
Cell Address
Data Output
Data Input
Hi-Z
IL
IH
IH
V
IL
V
V
V
V
Bus Write
Command Address
IL
Output Disable
Standby
X
X
IH
V
X
X
X
Hi-Z
IH
A0 = V , A1 = V , A9 = V ,
Read Manufacturer
Code
IL
IL
ID
V
V
V
V
V
0020h
IL
IL
IL
IL
IH
IH
Others V or V
IL
IH
A0 = V , A1 = V , A9 = V ,
00EEh (M29W400DT)
00EFh (M29W400DB)
IH
IL
ID
V
Read Device Code
Others V or V
IL
IH
Note: X = V or V
.
IH
IL
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
may be set to either V or V . The Manufacturer
IL IH
Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read
operation with A0 = V and A1 = V . The other
IH
IL
address bits may be set to either V or V . The
IL
IH
Device Code for the M29W400DT is 00EEh and
for the M29W400DB is 00EFh.
The address used for the commands changes de-
pending on whether the memory is in 16-bit or 8-
bit mode. See either Table 5, or 6, depending on
the configuration that is being used, for a summary
of the commands.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = V ,
IL
A1 = V , and A12-A17 specifying the address of
IH
the block. The other address bits may be set to ei-
ther V or V . If the addressed block is protected
IL
IH
Read/Reset Command. The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM, unless other-
wise stated. It also resets the errors in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select com-
mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until another com-
mand is issued.
then 01h is output on Data Inputs/Outputs DQ0-
DQ7, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
eration latches the address and data in the internal
state machine and starts the Program/Erase Con-
troller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 4. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V and A1 = V . The other address bits
IL
IL
12/36
M29W400DT, M29W400DB
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memo-
ry. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com-
mands. Three Bus Write operations are required
to issue the Unlock Bypass command.
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command. The Block Erase com-
mand can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register for
details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un-
changed. No error condition is given when protect-
ed blocks are ignored.
Once the Unlock Bypass command has been is-
sued the memory will only accept the Unlock By-
pass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Un-
lock Bypass Program command can be used to
program one address in memory at a time. The
command requires two Bus Write operations, the
final write operation latches the address and data
in the internal state machine and starts the Pro-
gram/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. A
protected block cannot be programmed; the oper-
ation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, which leaves the device in Unlock By-
pass Mode. See the Program command for details
on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset
command does not exit from Unlock Bypass
Mode.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
command. Typical block erase times are given in
Table 4. All Bus Read operations during the Block
Erase operation will output the Status Register on
the Data Inputs/Outputs. See the section on the
Status Register for more details.
Chip Erase Command. The Chip Erase com-
mand can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap-
pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
During the erase operation the memory will ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical chip erase
times are given in Table 4. All Bus Read opera-
13/36
M29W400DT, M29W400DB
Read mode. The command requires one Bus
Write operation.
the data remains unchanged. The Status Register
is not read and no error condition is given. Read-
ing from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select and Un-
lock Bypass commands during an Erase Suspend.
The Read/Reset command must be issued to re-
turn the device to Read Array mode before the Re-
sume command will be accepted.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.
Block Protect and Chip Unprotect Commands.
Each block can be separately protected against
accidental Program or Erase. The whole chip can
be unprotected to allow the data inside the blocks
to be changed.
The Program/Erase Controller will suspend within
the Erase Suspend Latency Time after the Erase
Suspend Command is issued (see Table 4 for nu-
merical values). Once the Program/Erase Control-
ler has stopped the memory will be set to Read
mode and the Erase will be suspended. If the
Erase Suspend command is issued during the pe-
riod when the memory is waiting for an additional
block (before the Program/Erase Controller starts)
then the Erase is suspended immediately and will
start immediately when the Erase Resume Com-
mand is issued. It is not possible to select any fur-
ther blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspended
block then the Program command is ignored and
Block Protect and Chip Unprotect operations are
described in Appendix B.
Table 4. Program, Erase Times and Program, Erase Endurance Cycles
(1,2)
(2)
Parameter
Chip Erase (All bits in the memory set to ‘0’)
Chip Erase
Min
Unit
s
Typ
2.5
Max
(3)
6
s
35
(4)
Block Erase (64 Kbytes)
0.8
10
s
6
(3)
Program (Byte or Word)
µs
s
200
(3)
Chip Program (Byte by Byte)
Chip Program (Word by Word)
5.5
2.8
18
30
15
25
(3)
(4)
s
Erase Suspend Latency Time
Program/Erase Cycles (per Block)
Data Retention
µs
100,000
20
cycles
years
Note: 1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and V after 100,00 program/erase cycles.
CC
4. Maximum value measured at worst case conditions for both temperature and V
.
CC
14/36
M29W400DT, M29W400DB
Table 5. Commands, 16-bit mode, BYTE = V
IH
Bus Write Operations
3rd 4th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command
1st
2nd
5th
6th
1
3
3
4
3
X
F0
AA
AA
AA
AA
Read/Reset
555
555
555
555
2AA
2AA
2AA
2AA
55
55
55
55
X
F0
90
A0
20
Auto Select
Program
555
555
555
PA
PD
Unlock Bypass
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
Chip Erase
2
6
X
90
AA
AA
B0
30
X
00
55
55
555
2AA
2AA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
BA
10
30
Block Erase
6+ 555
Erase Suspend
Erase Resume
1
1
X
X
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The
Command Interface only uses A-1; A0-A10 and DQ0-DQ7 to verify the commands; A11-A17, DQ8-DQ14 and DQ15 are Don't Care.
DQ15A-1 is A-1 when BYTE is V or DQ15 when BYTE is V
.
IH
IL
Table 6. Commands, 8-bit mode, BYTE = V
IL
Bus Write Operations
3rd 4th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command
1st
2nd
5th
6th
1
3
3
4
3
X
F0
AA
AA
AA
AA
Read/Reset
AAA
AAA
AAA
AAA
555
555
555
555
55
55
55
55
X
F0
90
A0
20
Auto Select
Program
AAA
AAA
AAA
PA
PD
Unlock Bypass
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
Chip Erase
2
6
X
90
AA
AA
B0
30
X
00
55
55
AAA
555
555
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
BA
10
30
Block Erase
6+ AAA
Erase Suspend
Erase Resume
1
1
X
X
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The
Command Interface only uses A-1; A0-A10 and DQ0-DQ7 to verify the commands; A11-A17, DQ8-DQ14 and DQ15 are Don't Care.
DQ15A-1 is A-1 when BYTE is V or DQ15 when BYTE is V
.
IH
IL
15/36
M29W400DT, M29W400DB
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Sus-
pend when an address within a block being erased
is accessed.
The bits in the Status Register are summarized in
Table 7, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
ror is signalled and DQ6 toggles for approximately
1µs.
Figure 9, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing, the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ‘0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.
Figure 8, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
If any attempt is made to erase a protected block,
the operation is aborted, no error is signalled and
DQ6 toggles for approximately 100µs. If any at-
tempt is made to program a protected block or a
suspended block, the operation is aborted, no er-
16/36
M29W400DT, M29W400DB
Table 7. Status Register Bits
Operation
Program
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Any Address
DQ7
Toggle
0
–
–
0
Program During Erase
Suspend
Any Address
DQ7
Toggle
0
–
–
0
Program Error
Chip Erase
Any Address
Any Address
DQ7
Toggle
Toggle
1
0
0
0
0
0
0
–
1
0
0
1
1
–
–
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
Toggle
Erasing Block
Toggle
Toggle
Block Erase before
timeout
Non-Erasing Block
Erasing Block
Toggle
No Toggle
Toggle
Toggle
Block Erase
Erase Suspend
Erase Error
Non-Erasing Block
Erasing Block
Toggle
No Toggle
Toggle
No Toggle
Non-Erasing Block
Good Block Address
Faulty Block Address
Data read as normal
0
0
Toggle
Toggle
1
1
1
No Toggle
Toggle
1
Note: Unspecified data bits should be ignored.
Figure 8. Data Polling Flowchart
Figure 9. Data Toggle Flowchart
START
START
READ DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ
DQ5 & DQ6
DQ7
=
DATA
YES
DQ6
NO
=
NO
TOGGLE
YES
NO
DQ5
= 1
NO
DQ5
YES
= 1
YES
READ DQ7
at VALID ADDRESS
READ DQ6
TWICE
DQ7
=
DATA
YES
DQ6
=
NO
NO
FAIL
TOGGLE
PASS
YES
FAIL
PASS
AI03598
AI01370C
17/36
M29W400DT, M29W400DB
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 8. Absolute Maximum Ratings
Symbol
Parameter
Min
–50
–65
Max
125
150
Unit
°C
T
Temperature Under Bias
BIAS
T
Storage Temperature
°C
STG
(1,2)
V
+0.6
–0.6
–0.6
–0.6
V
V
V
V
Input or Output Voltage
Supply Voltage
CC
IO
V
CC
4
V
Identification Voltage
13.5
ID
Note: 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to V +2V during transition and for less than 20ns during transitions.
CC
18/36
M29W400DT, M29W400DB
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 9, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 9. Operating and AC Measurement Conditions
M29W400D
Parameter
45
55
70
Unit
Min
3.0
–40
0
Max
3.6
85
Min
2.7
–40
0
Max
3.6
85
Min
2.7
–40
0
Max
3.6
85
V
Supply Voltage
V
CC
Ambient Operating Temperature (range 6)
°C
Ambient Operating Temperature (range 1)
70
70
70
Load Capacitance (C )
30
30
100
pF
ns
V
L
Input Rise and Fall Times
10
10
10
0 to V
0 to V
0 to V
CC
Input Pulse Voltages
CC
CC
V
CC
/2
V
CC
/2
V
CC
/2
Input and Output Timing Ref. Voltages
V
Figure 10. AC Measurement I/O Waveform
Figure 11. AC Measurement Load Circuit
V
V
CC
CC
V
CC
V
/2
CC
25kΩ
0V
DEVICE
UNDER
TEST
AI04498
25kΩ
0.1µF
C
L
AI04499
C
includes JIG capacitance
L
Table 10. Device Capacitance
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
6
Unit
pF
C
V
= 0V
= 0V
IN
IN
C
OUT
V
OUT
12
pF
Note: Sampled only, not 100% tested.
19/36
M29W400DT, M29W400DB
Table 11. DC Characteristics
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
±1
Unit
µA
I
0V ≤ V ≤ V
LI
IN
CC
I
0V ≤ V
≤ V
OUT CC
±1
µA
LO
E = V , G = V ,
IL
IH
I
Supply Current (Read)
10
mA
µA
mA
CC1
f = 6MHz
E = V
±0.2V,
CC
I
Supply Current (Standby)
Supply Current (Program/Erase)
100
CC2
RP = V ±0.2V
CC
Program/Erase
Controller active
(1)
20
I
CC3
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Identification Voltage
Identification Current
–0.5
0.8
V
V
IL
V
V
0.7V
V
+0.3
CC
IH
CC
I
= 1.8mA
0.45
V
OL
OH
OL
V
V
–0.4
CC
I
= –100µA
V
OH
V
ID
11.5
12.5
100
V
I
A9 = V
µA
ID
ID
Program/Erase Lockout Supply
Voltage
1.8
2.3
V
V
LKO
Note: 1. Sampled only, not 100% tested.
20/36
M29W400DT, M29W400DB
Figure 12. Read Mode AC Waveforms
tAVAV
VALID
A0-A17/
A–1
tAVQV
tAXQX
E
tELQV
tELQX
tEHQX
tEHQZ
G
tGLQX
tGLQV
tGHQX
tGHQZ
DQ0-DQ7/
DQ8-DQ15
VALID
tBHQV
BYTE
tELBL/tELBH
tBLQZ
AI02907
Table 12. Read AC Characteristics
M29W400D
55
Symbol
Alt
Parameter
Test Condition
Unit
45
70
E = V ,
IL
t
t
Address Valid to Next Address Valid
Address Valid to Output Valid
Min
45
55
55
70
ns
ns
AVAV
RC
G = V
IL
E = V ,
IL
t
t
ACC
Max
45
70
AVQV
G = V
G = V
G = V
E = V
E = V
G = V
E = V
IL
IL
IL
IL
IL
IL
(1)
t
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
Output Enable Low to Output Transition
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Min
Max
Min
0
0
0
ns
ns
ns
ns
ns
t
LZ
ELQX
t
t
45
0
55
0
70
0
ELQV
CE
(1)
t
t
OLZ
GLQX
t
t
OE
Max
Max
30
20
30
25
35
30
GLQV
(1)
t
t
HZ
DF
EHQZ
(1)
t
Output Enable High to Output Hi-Z
Max
Min
20
0
25
0
30
0
ns
ns
t
IL
GHQZ
t
t
t
EHQX
Chip Enable, Output Enable or Address
Transition to Output Transition
t
GHQX
OH
AXQX
t
t
ELBL
ELFL
Chip Enable to BYTE Low or High
Max
5
5
5
ns
t
t
ELBH
ELFH
t
t
BYTE Low to Output Hi-Z
BYTE High to Output Valid
Max
Max
25
30
25
30
30
40
ns
ns
BLQZ
FLQZ
t
t
FHQV
BHQV
Note: 1. Sampled only, not 100% tested.
21/36
M29W400DT, M29W400DB
Figure 13. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A17/
VALID
A–1
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHEL
RB
tWHRL
AI01869C
Table 13. Write AC Characteristics, Write Enable Controlled
M29W400D
Symbol
Alt
Parameter
Unit
45
45
0
55
55
0
70
70
0
t
t
WC
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
CS
ELWL
t
t
WP
40
25
0
45
30
0
45
45
0
WLWH
t
t
DVWH
DS
DH
CH
t
t
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
Write Enable High to Output Enable Low
Program/Erase Valid to RB Low
WHDX
t
t
0
0
0
WHEH
t
t
WPH
30
0
30
0
30
0
WHWL
t
t
AVWL
AS
t
t
40
0
45
0
45
0
WLAX
AH
t
GHWL
t
t
OEH
0
0
0
WHGL
(1)
t
30
50
30
50
35
50
t
BUSY
WHRL
t
t
V
CC
High to Chip Enable Low
Min
µs
VCHEL
VCS
Note: 1. Sampled only, not 100% tested.
22/36
M29W400DT, M29W400DB
Figure 14. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A17/
VALID
A–1
tELAX
tAVEL
tEHWH
tEHGL
W
tWLEL
G
tGHEL
tELEH
E
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHWL
RB
tEHRL
AI01870C
Table 14. Write AC Characteristics, Chip Enable Controlled
M29W400D
Unit
Symbol
Alt
Parameter
45
45
0
55
55
0
70
70
0
t
t
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
WC
t
t
WLEL
WS
t
t
40
25
0
45
30
0
45
45
0
ELEH
CP
DS
DH
t
t
DVEH
t
t
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
Chip Enable High to Output Enable Low
Program/Erase Valid to RB Low
EHDX
t
t
WH
0
0
0
EHWH
t
t
30
0
30
0
30
0
EHEL
CPH
t
t
AVEL
AS
t
t
40
0
45
0
45
0
ELAX
AH
t
GHEL
t
t
0
0
0
EHGL
OEH
(1)
t
30
50
30
50
35
50
t
BUSY
EHRL
t
t
V
CC
High to Write Enable Low
Min
µs
VCHWL
VCS
Note: 1. Sampled only, not 100% tested.
23/36
M29W400DT, M29W400DB
Figure 15. Reset/Block Temporary Unprotect AC Waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPHPHH
tPLPX
RP
tPLYH
AI02931
Table 15. Reset/Block Temporary Unprotect AC Characteristics
M29W400D
Symbol
Alt
Parameter
Unit
45
55
70
(1)
t
PHWL
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
t
t
Min
Min
50
50
50
0
ns
PHEL
RH
(1)
t
PHGL
(1)
(1)
(1)
t
t
RHWL
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
t
0
0
ns
t
RB
RHEL
RHGL
t
t
RP Pulse Width
Min
Max
Min
500
10
500
10
500
10
ns
µs
ns
PLPX
(1)
RP
t
RP Low to Read Mode
t
READY
PLYH
(1)
t
RP Rise Time to V
500
500
500
t
VIDR
ID
PHPHH
Note: 1. Sampled only, not 100% tested.
24/36
M29W400DT, M29W400DB
PACKAGE MECHANICAL
Figure 16. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
A2
A
C
b
e
CP
D
N
E
EH
1
A1
α
L
SO-d
Note: Drawing is not to scale.
Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
2.80
0.1102
0.10
2.20
0.35
0.10
0.0039
0.0866
0.0138
0.0039
2.30
0.40
0.15
2.40
0.50
0.20
0.08
28.40
13.50
16.25
–
0.0906
0.0157
0.0059
0.0945
0.0197
0.0079
0.0030
1.1181
0.5315
0.6398
–
C
CP
D
28.20
13.30
16.00
1.27
28.00
13.20
15.75
–
1.1102
0.5236
0.6299
0.0500
0.0315
1.1024
0.5197
0.6201
–
E
EH
e
L
0.80
a
8
8
N
44
44
25/36
M29W400DT, M29W400DB
Figure 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Note: Drawing is not to scale.
Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
0.270
0.210
0.100
20.200
18.500
–
Typ
Max
0.0472
0.0059
0.0413
0.0106
0.0083
0.0039
0.7953
0.7283
–
A
A1
A2
B
0.100
1.000
0.050
0.950
0.170
0.100
0.0039
0.0394
0.0020
0.0374
0.0067
0.0039
C
CP
D
19.800
18.300
–
0.7795
0.7205
–
D1
e
0.500
0.0197
E
11.900
0.500
0
12.100
0.700
5
0.4685
0.0197
0
0.4764
0.0276
5
L
alfa
N
48
48
26/36
M29W400DT, M29W400DB
Figure 18. TFBGA48 6x9mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
BALL "A1"
E
E1
ddd
e
e
b
A
A2
A1
BGA-Z00
Note: Drawing is not to scale.
Table 18. TFBGA48 6x9mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.200
0.0079
1.000
0.0394
0.400
6.000
4.000
0.350
5.900
–
0.450
0.0157
0.2362
0.1575
0.0138
0.2323
–
0.0177
D
6.100
0.2402
D1
ddd
E
–
–
0.100
0.0039
9.000
0.800
5.600
1.000
1.700
0.400
0.400
8.900
9.100
0.3543
0.0315
0.2205
0.0394
0.0669
0.0157
0.0157
0.3504
0.3583
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
E1
FD
FE
SD
SE
27/36
M29W400DT, M29W400DB
PART NUMBERING
Table 19. Ordering Information Scheme
Example:
M29W400DB
55
N
6
T
Device Type
M29
Operating Voltage
W = V = 2.7 to 3.6V
CC
Device Function
400D = 4 Mbit (512Kx8 or 256Kx16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
45 = 45ns
55 = 55ns
70 = 70ns
Package
M = SO44
N = TSOP48: 12 x 20mm
ZA = TFBGA48: 6 x 9mm
Temperature Range
6 = –40 to 85 °C
1 = 0 to 70 °C
Option
T = Tape & Reel Packing
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
28/36
M29W400DT, M29W400DB
APPENDIX A. BLOCK ADDRESS TABLE
Table 20. Top Boot Block Addresses
M29W400DT
Table 21. Bottom Boot Block Addresses
M29W400DB
Size
(Kbytes)
Address Range
(x8)
Address Range
(x16)
Size
(Kbytes)
Address Range
(x8)
Address Range
(x16)
#
#
10
9
8
7
6
5
4
3
2
1
0
16
8
7C000h-7FFFFh
7A000h-7BFFFh
78000h-79FFFh
70000h-77FFFh
60000h-6FFFFh
50000h-5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
00000h-0FFFFh
3E000h-3FFFFh
3D000h-3DFFFh
3C000h-3CFFFh
38000h-3BFFFh
30000h-37FFFh
28000h-2FFFFh
20000h-27FFFh
18000h-1FFFFh
10000h-17FFFh
08000h-0FFFFh
00000h-07FFFh
10
9
8
7
6
5
4
3
2
1
0
64
64
64
64
64
64
64
32
8
70000h-7FFFFh
60000h-6FFFFh
50000h-5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
08000h-0FFFFh
06000h-07FFFh
04000h-05FFFh
00000h-03FFFh
38000h-3FFFFh
30000h-37FFFh
28000h-2FFFFh
20000h-27FFFh
18000h-1FFFFh
10000h-17FFFh
08000h-0FFFFh
04000h-07FFFh
03000h-03FFFh
02000h-02FFFh
00000h-01FFFh
8
32
64
64
64
64
64
64
64
8
16
29/36
M29W400DT, M29W400DB
APPENDIX B. BLOCK PROTECTION
Block protection can be used to prevent any oper-
ation from modifying the data stored in the Flash.
Each Block can be protected individually. Once
protected, Program and Erase operations on the
block fail to change the data.
There are three techniques that can be used to
control Block Protection, these are the Program-
mer technique, the In-System technique and Tem-
porary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unpro-
tection pin, RP; this is described in the Signal De-
scriptions section.
Unlike the Command Interface of the Program/
Erase Controller, the techniques for protecting and
unprotecting blocks change between different
Flash memory suppliers. For example, the tech-
niques for AMD parts will not work on STMicro-
electronics parts. Care should be taken when
changing drivers for one part to work on another.
Technique Bus Operations, gives a summary of
each operation.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.
In-System Technique
The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP. This can be achieved without violating the
maximum ratings of the components on the micro-
processor bus, therefore this technique is suitable
for use after the Flash has been fitted to the sys-
tem.
To protect a block follow the flowchart in Figure 21,
In-System Block Protect Flowchart. To unprotect
the whole chip it is necessary to protect all of the
blocks first, then all the blocks can be unprotected
at the same time. To unprotect the chip follow Fig-
ure 22, In-System Chip Unprotect Flowchart.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not allow the microprocessor to service interrupts
that will upset the timing and do not abort the pro-
cedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.
Programmer Technique
The Programmer technique uses high (V ) volt-
ID
age levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended only for
use in Programming Equipment.
To protect a block follow the flowchart in Figure 19,
Programmer Equipment Block Protect Flowchart.
To unprotect the whole chip it is necessary to pro-
tect all of the blocks first, then all blocks can be un-
protected at the same time. To unprotect the chip
follow Figure 20, Programmer Equipment Chip
Unprotect Flowchart. Table 22, Programmer
Table 22. Programmer Technique Bus Operations, BYTE = V or V
IH
IL
Address Inputs
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Operation
E
G
W
A0-A17
A9 = V , A12-A17 Block Address
ID
V
V
V
V
Pulse
Pulse
Block Protect
X
X
IL
ID
ID
IL
IL
Others = X
A9 = V , A12 = V , A15 = V
ID
IH
IH
V
ID
V
Chip Unprotect
Others = X
A0 = V , A1 = V , A6 = V , A9 = V ,
IL
IH
IL
ID
Block Protection
Verify
Pass = XX01h
Retry = XX00h
V
V
V
V
A12-A17 Block Address
Others = X
IL
IL
IL
IL
IH
IH
A0 = V , A1 = V , A6 = V , A9 = V ,
IL
IH
IH
ID
Block Unprotection
Verify
Retry = XX01h
Pass = XX00h
V
V
A12-A17 Block Address
Others = X
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M29W400DT, M29W400DB
Figure 19. Programmer Equipment Block Protect Flowchart
START
ADDRESS = BLOCK ADDRESS
W = V
IH
n = 0
G, A9 = V
E = V
,
ID
IL
Wait 4µs
W = V
IL
Wait 100µs
W = V
IH
E, G = V
,
IH
A0, A6 = V
A1 = V
,
IL
IH
E = V
IL
Wait 4µs
G = V
IL
Wait 60ns
Read DATA
DATA
=
01h
NO
YES
++n
= 25
NO
A9 = V
IH
E, G = V
IH
YES
PASS
A9 = V
E, G = V
IH
IH
AI03469
FAIL
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M29W400DT, M29W400DB
Figure 20. Programmer Equipment Chip Unprotect Flowchart
START
PROTECT ALL BLOCKS
n = 0
CURRENT BLOCK = 0
(1)
A6, A12, A15 = V
IH
E, G, A9 = V
ID
Wait 4µs
W = V
IL
Wait 10ms
W = V
IH
E, G = V
IH
ADDRESS = CURRENT BLOCK ADDRESS
A0 = V , A1, A6 = V
IL
IH
E = V
IL
Wait 4µs
G = V
IL
INCREMENT
CURRENT BLOCK
Wait 60ns
Read DATA
NO
YES
DATA
=
00h
LAST
BLOCK
NO
NO
++n
= 1000
YES
YES
A9 = V
A9 = V
E, G = V
IH
IH
E, G = V
IH
IH
FAIL
PASS
AI03470
32/36
M29W400DT, M29W400DB
Figure 21. In-System Equipment Block Protect Flowchart
START
n = 0
RP = V
ID
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
Wait 100µs
WRITE 40h
IL
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
Wait 4µs
READ DATA
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
DATA
NO
=
01h
YES
RP = V
++n
= 25
NO
IH
YES
RP = V
ISSUE READ/RESET
COMMAND
IH
PASS
ISSUE READ/RESET
COMMAND
FAIL
AI03471
33/36
M29W400DT, M29W400DB
Figure 22. In-System Equipment Chip Unprotect Flowchart
START
PROTECT ALL BLOCKS
n = 0
CURRENT BLOCK = 0
RP = V
ID
WRITE 60h
ANY ADDRESS WITH
A0 = V , A1 = V , A6 = V
IL
IH
IH
IH
WRITE 60h
ANY ADDRESS WITH
A0 = V , A1 = V , A6 = V
IL
IH
Wait 10ms
WRITE 40h
ADDRESS = CURRENT BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IH
Wait 4µs
INCREMENT
CURRENT BLOCK
READ DATA
ADDRESS = CURRENT BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IH
DATA
NO
YES
=
00h
++n
= 1000
NO
NO
LAST
BLOCK
YES
RP = V
YES
RP = V
IH
IH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
PASS
FAIL
AI03472
34/36
M29W400DT, M29W400DB
REVISION HISTORY
Table 23. Document Revision History
Date
Version
Revision Details
26-Jul-2002
-01
First Issue
Revision numbering modified: a minor revision will be indicated by incrementing the digit
after the dot, and a major revision, by incrementing the digit before the dot (revision
version 01 equals 1.0). Revision History moved to end of document.
Typical after 100k W/E Cycles column removed from Table 4, Program, Erase Times and
Program, Erase Endurance Cycles, Data Retention and Erase Suspend Latency Time
parameters added. Common Flash Interface removed from datasheet.
19-Feb-2003
2.0
Lead-free package options E and F added to Table 19, Ordering Information Scheme.
Document promoted from Product Preview to Preliminary Data status.
35/36
M29W400DT, M29W400DB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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