M29F100BB90N1_技术文档

M29F100T

M29F100B

1 Mbit (128Kb x8 or 64Kb x16, Boot Block)

Single Supply Flash Memory

NOT FOR NEW DESIGN

M29F100T and M29F100B are replaced

respectivelyby the M29F100BT and

M29F100BB.

5V ± 10% SUPPLY VOLTAGE for PROGRAM,

ERASE and READ OPERATIONS

44

FAST ACCESS TIME:70ns

FAST PROGRAMMING TIME

– 10µs by Byte / 16µs by Word typical

PROGRAM/ERASE CONTROLLER (P/E.C.)

– Program Byte-by-Byte or Word-by-Word

– Status Register bits and Ready/BusyOutput

MEMORY BLOCKS

1

TSOP48 (N)

12 x 20 mm

SO44 (M)

– Boot Block (Top or Bottom location)

– Parameterand Main blocks

BLOCK, MULTI-BLOCK and CHIP ERASE

MULTI-BLOCK PROTECTION/TEMPORARY

UNPROTECTION MODES

ERASE SUSPEND and RESUME MODES

Figure 1. LogicDiagram

– Read and Program another Block during

Erase Suspend

LOW POWER CONSUMPTION

– Stand-byand Automatic Stand-by

100,000PROGRAM/ERASE CYCLES per

BLOCK

V

CC

20 YEARSDATA RETENTION

– Defectivity below 1ppm/year

ELECTRONIC SIGNATURE

16

15

A0-A15

DQ0-DQ14

– ManufacturerCode:0020h

– Device Code, M29F100T:00D0h

– Device Code, M29F100B: 00D1h

W

E

DQ15A–1

BYTE

RB

M29F100T

M29F100B

G

DESCRIPTION

RP

TheM29F100is a non-volatilememory thatmaybe

erased electrically at the block or chip level and

programmedin-system on a Byte-by-Byteor Word-

by-Word basis using only a single 5V V_CCsupply.

For Program and Erase operations the necessary

high voltages are generated internally. The device

can alsobe programmedin standardprogrammers.

V

SS

AI01974

The array matrix organisation allows each block to

be erased and reprogrammed without affecting

other blocks.Blocks can be protected against pro-

graming and erase on programming equipment,

July 2000

1/30

Tihs is information on a productstill in production but not recommendedfor new design.

M29F100T, M29F100B

Figure 2A. TSOP Pin Connections

Figure 2B. TSOP Reverse Pin Connections

NC

1

48

A15

A14

A13

A12

A11

A10

A9

A15

A14

A13

A12

A11

A10

A9

1

48

NC

BYTE

V

SS

DQ15A–1

SS

DQ15A–1

DQ7

DQ14

DQ6

DQ14

DQ6

A8

DQ13

DQ5

DQ13

DQ5

A8

NC

W

NC

W

DQ12

DQ4

DQ12

DQ4

M29F100T

M29F100B

(Reverse)

M29F100T

M29F100B

(Normal)

V

12

13

37

36

RP

NC

RB

NC

A7

RP

NC

RB

NC

A7

12

13

37

36

V

CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

A6

A5

A4

V

A3

V

E

SS

E

A2

A1

24

25

A0

24

25

A1

AI01975

AI01976

Warning: NC = Not Connected.

Figure 2C. SO Pin Connections

Table 1. Signal Names

A0-A15

DQ0-DQ7

DQ8-DQ14

DQ15A–1

E

Address Inputs

NC

RB

NC

A7

A6

A5

A4

A3

A2

A1

A0

E

1

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

RP

Data Input/Outputs, Command Inputs

Data Input/Outputs

2

W

3

A8

4

A9

5

A10

A11

A12

A13

A14

A15

NC

Data Input/Output or Address Input

Chip Enable

6

7

8

9

G

Output Enable

10

11

12

13

14

15

16

17

18

19

20

21

22

M29F100T

M29F100B

W

Write Enable

BYTE

V

RP

Reset / Block Temporary Unprotect

Ready/Busy Output

Byte/Word Organisation

Supply Voltage

SS

G

SS

DQ15A–1

RB

DQ0

DQ8

DQ7

DQ14

DQ6

BYTE

V_CC

DQ1

DQ9

DQ13

DQ5

DQ2

DQ10

DQ3

DQ12

DQ4

V_SS

Ground

DQ11

V

CC

AI01977

Warning: NC = Not Connected.

2/30

M29F100T, M29F100B

Table 2. Absolute Maximum Ratings ⁽¹⁾

Symbol

T_A

Parameter

Value

Unit

°C

Ambient Operating Temperature ⁽³⁾

Temperature Under Bias

Storage Temperature

–40 to 125

–50 to 125

–65 to 150

–0.6 to 7

T_BIAS

T_STG

°C

C

°

(2)

V_IO

Input or Output Voltages

Supply Voltage

V

V_CC

–0.6 to 7

(2)

V_{(A9, E, G, RP)}

A9, E, G, RP Voltage

–0.6 to 13.5

Notes: 1. Except for the rating”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to AbsoluteMaximum

Rating conditions for extended periods may affect device reliability.Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

2. Minimum Voltagemay undershoot to –2V during transition and for less than 20ns.

3. Depends on range.

DESCRIPTION (Cont’d)

DQ2 provide Toggle signals to indicate the state of

the P/E.C operations. A Ready/Busy RB output

indicates the completion of the internal algorithms.

and temporarily unprotected to make changes in

the application. Each block can be programmed

and erased over 100,000 cycles.

Memory Blocks

The devices feature asymmetrically blocked archi-

tecture providing system memory integration.Both

M29F100T and M29F100B devices have an array

of 5 blocks, one Boot Block of 16 KBytes or 8

KWords, two Parameter Blocks of 8 KBytes or 4

KWords, one Main Block of 32 KBytes or 16

KWords and one Main Blocks of 64 KBytes or 32

KWords.The M29F100T has the Boot Block at the

top of the memory address space and the

M29F100B locates the Boot Block starting at the

bottom.The memory maps are showed in Figure 3.

Each block can be erased separately, any combi-

nation of blocks can be specified for multi-block

erase or the entire chip may be erased.The Erase

operations are managed automatically by the

P/E.C. The block erase operation can be sus-

pended in order to read from or program to any

block not being ersased, and then resumed.

InstructionsforRead/Reset,AutoSelectforreading

the Electronic Signatureor BlockProtectionstatus,

Programming, Block and Chip Erase, Erase Sus-

pend and Resume are written to the device in

cyclesof commandsto a CommandInterfaceusing

standard microprocessor write timings.

The device is offered in TSOP48 (12 x 20mm) and

SO44 packages.Both normal and reverse pinouts

are availablefor the TSOP48package.

Organisation

The M29F100 is organised as 128Kb x8 or 64Kb

x16 bitsselectablebytheBYTEsignal.WhenBYTE

is Low the Byte-wide x8 organisation is selected

and the address lines are DQ15A–1 and A0-A15.

The Data Input/Output signal DQ15A–1 acts as

address line A–1 which selects the lower or upper

Byte of the memory word for output on DQ0-DQ7,

DQ8-DQ14 remain at High impedance. When

BYTE is High the memory uses the address inputs

A0-A15 and the Data Input/Outputs DQ0-DQ15.

Memory control is provided by Chip Enable E,

Output Enable G and Write Enable W inputs.

Block protection provides additional data security.

Each block can be separately protected or unpro-

tected against Program or Erase on programming

equipment.All previously protected blocks can be

temporarily unprotected in the application.

Bus Operations

A Reset/BlockTemporary Unprotection RPtri-level

input provides a hardware reset when pulled Low,

and whenheld High(at V_ID) temporarily unprotects

blocks previously protected allowing them to be

programed and erased.Erase and Programopera-

tions are controlled by an internal Program/Erase

Controller (P/E.C.).Status Register data output on

DQ7 provides a Data Polling signal, and DQ6 and

The following operations can be performed using

the appropriate bus cycles:Read (Array, Electronic

Signature, Block Protection Status), Write com-

mand, Output Disable, Standby, Reset, Block Pro-

tection, Unprotection, Protection Verify,

UnprotectionVerifyandBlockTemporaryUnprotec-

tion. See Tables 4 and 5.

3/30

M29F100T, M29F100B

Figure 3. Memory Map and Block Address Table (x8)

M29F100T

1FFFFh

M29F100B

1FFFFh

16K BOOT BLOCK

64K MAIN BLOCK

1C000h

1BFFFh

10000h

0FFFFh

8K PARAMETER BLOCK

32K MAIN BLOCK

1A000h

19FFFh

08000h

07FFFh

8K PARAMETER BLOCK

16K BOOT BLOCK

06000h

05FFFh

18000h

17FFFh

32K MAIN BLOCK

10000h

0FFFFh

04000h

03FFFh

64K MAIN BLOCK

00000h

AI01978

Table 3A. M29F100T Block Address Table

Address Range (x8)

00000h-0FFFFh

10000h-17FFFh

18000h-19FFFh

1A000h-1BFFFh

1C000h-1FFFFh

Address Range (x16)

0000h-7FFFh

A15

0

A14

X

A13

X

A12

X

8000h-BFFFh

1

0

X

C000h-CFFFh

D000h-DFFFh

E000h-FFFFh

1

0

1

0

1

X

Table 3B. M29F100BBlock Address Table

Address Range (x8)

00000h-03FFFh

04000h-05FFFh

06000h-07FFFh

08000h-0FFFFh

10000h-1FFFFh

Address Range (x16)

0000h-1FFFh

A15

0

A14

0

A13

0

A12

X

2000h-2FFFh

0

1

0

3000h-3FFFh

0

1

4000h-7FFFh

0

1

X

8000h-FFFFh

1

X

4/30

M29F100T, M29F100B

Command Interface

When A9 is raised to V_ID, either a Read Electronic

SignatureManufactureror DeviceCode,BlockPro-

tection Status or a Write Block Protection or Block

Unprotection is enabled depending on the combi-

nation of levels on A0, A1, A6, A12 and A15.

Instructions, made up of commands written in cy-

cles, can be given to the Program/Erase Controller

through a Command Interface (C.I.). For added

data protection, program or erase execution starts

after 4 or 6 cycles.The first, second,fourth and fifth

cycles are used to input Coded cycles to the C.I.

This Coded sequence is the same for all Pro-

gram/EraseControllerinstructions.The’Command’

itself and its confirmation, when applicable, are

given on the third, fourth or sixthcycles. Any incor-

rect command or any improper command se-

quence will reset the device to Read Array mode.

Data Input/Outputs (DQ0-DQ7). These In-

puts/Outputsare used in the Byte-wideand Word-

wide organisations. The input is data to be

programmedin the memory arrayor a commandto

be written to the C.I. Both are latched on the rising

edge of Chip Enable E or Write Enable W. The

outputisdata fromtheMemoryArray,theElectronic

SignatureManufactureror Devicecodes, the Block

ProtectionStatusor theStatusregisterData Polling

bit DQ7,the ToggleBits DQ6 and DQ2,the Error bit

DQ5 or the Erase Timer bit DQ3.Outputs are valid

when Chip Enable E and Output Enable G are

active.The outputis high impedancewhen the chip

is deselectedor the outputsare disabledand when

RP is at a Low level.

Data Input/Outputs (DQ8-DQ14 and DQ15A–1).

These Inputs/Outputs are additionally used in the

Word-wide organisation.WhenBYTE is High DQ8-

DQ14 and DQ15A–1 act as the MSB of the Data

Input or Output, functioning as described for DQ0-

DQ7 above, and DQ8-DQ15 are ’don’t care’ for

command inputs or status outputs.When BYTE is

Low, DQ8-DQ14 are high impedance,DQ15A–1 is

the Address A–1 input.

Instructions

Seven instructions are defined to perform Read

Array,Auto Select (to read the ElectronicSignature

or BlockProtection Status), Program, Block Erase,

Chip Erase, Erase Suspend and Erase Resume.

Theinternal P/E.C.automaticallyhandlesall timing

and verification of the Program and Erase opera-

tions. The Status Register Data Polling, Toggle,

Error bits and the RB output may be read at any

time, during programming or erase, to monitor the

progress of the operation.

Instructionsare composed of up to six cycles. The

first two cycles input a Coded sequence to the

Command Interfacewhich is commonto allinstruc-

tions (see Table 8). The third cycle inputs the in-

struction set-up command. Subsequent cycles

output the addresseddata, Electronic Signatureor

Block Protection Status for Read operations. In

order to give additionaldata protection,theinstruc-

tions for Program and Block or Chip Erase require

further commandinputs.Fora Programinstruction,

the fourth command cycle inputs the address and

data to be programmed. For an Erase instruction

(Block or Chip), the fourth and fifth cycles input a

further Coded sequence before the Erase confirm

command on the sixth cycle. Erasure of a memory

blockmay besuspended,in orderto readdata from

another block or to program data in another block,

and then resumed.

Chip Enable (E). The Chip Enable input activates

the memory control logic, input buffers, decoders

and senseamplifiers.E High deselectsthememory

and reduces thepower consumptionto the standby

level. E can also be used to control writing to the

command register and to the memory array, while

W remains at a low level.The Chip Enablemust be

forced to V_IDduring the Block Unprotection opera-

tion.

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read

operation. When G is High the outputs are High

impedance. G must be forced to V_IDlevel during

Block Protection and Unprotection operations.

When power is first applied or if V_CCfalls below

V

_LKO, thecommandinterfaceisresetto ReadArray.

WriteEnable (W). This input controlswriting to the

CommandRegisterand Addressand Datalatches.

Byte/Word Organization Select (BYTE). The

BYTE input selects the outputconfiguration for the

device: Byte-wide (x8) mode or Word-wide (x16)

mode. When BYTE is Low, the Byte-wide mode is

selected and the data is read and programmed on

DQ0-DQ7. In this mode, DQ8-DQ14 are at high

impedance and DQ15A–1 is the LSB address.

When BYTE is High, the Word-wide mode is se-

lected and the data is read and programmed on

DQ0-DQ15.

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs (A0-A15). The address inputs for

the memory arrayare latched duringa write opera-

tion on the falling edge of Chip Enable E or Write

Enable W. In Word-wide organisation the address

lines are A0-A15, in Byte-wide organisation

DQ15A–1 acts as an additional LSB address line.

5/30

M29F100T, M29F100B

Ready/Busy Output (RB). Ready/Busy is an

open-drainoutputandgives theinternalstateof the

P/E.C.of the device.When RB is Low,the device is

Busy with a Program or Erase operation and it will

not acceptany additionalprogram or erase instruc-

tions except the Erase Suspend instruction. When

RB is High, the device is ready for any Read,

Program or Erase operation. The RB will also be

High when the memory is put in Erase Suspend or

Standbymodes.

Output Disable. The data outputs are high imped-

ance when the OutputEnable G is High with Write

Enable W High.

Standby. The memory is in standby when Chip

Enable E is High and the P/E.C. is idle. The power

consumption is reduced to the standby level and

the outputsare highimpedance,independentof the

Output Enable G or Write EnableW inputs.

Automatic Standby. After 150ns of bus inactivity

and when CMOS levels are driving the addresses,

the chip automatically enters a pseudo-standby

mode where consumptionis reduced to theCMOS

standbyvalue, while outputs still drive the bus.

Reset/Block Temporary Unprotect Input (RP).

The RP Input provides hardware reset and pro-

tected block(s) temporary unprotection functions.

Reset of the memory is acheived by pulling RP to

V_ILforat least500ns.Whenthe resetpulseis given,

if the memory is in Read or Standbymodes, it will

be available for new operations in 50ns after the

rising edge of RP.If the memory is in Erase,Erase

SuspendorProgrammodestheresetwilltake10µs

during which the RB signal will be held at V_IL. The

end of the memory reset will be indicated by the

rising edge of RB. A hardware reset during an

Erase or Program operation will corrupt the data

being programmedor the sector(s) being erased.

Electronic Signature. Two codes identifying the

manufacturer and the device can be read from the

memory.The manufacturer’scodeforSTMicroelec-

tronics is 20h, the device code is D0h for the

M29F100T (Top Boot) and D1h for the M29F100B

(Bottom Boot). These codes allow programming

equipment or applications to automatically match

their interface to the characteristics of the

M29F100. The Electronic Signature is output by a

Read operation when the voltage applied to A9 is

at V_IDand address input A1 is Low.The manufac-

turer code is output when the Address input A0 is

Low and the device code when this input is High.

Other Address inputs are ignored. The codes are

output on DQ0-DQ7.

Temporary block unprotection is made by holding

RP at V_ID. In this condition previously protected

blocks can be programmed or erased. The transi-

tion of RP from V_IHto V_IDmust slower than 500ns.

When RP is returned from V_IDto V_IHall blocks

temporarily unprotected will be again protected.

The Electronic Signaturecan also be read, without

raising A9 to V_ID, by giving the memory the Instruc-

tion AS. If the Byte-wide configuration is selected

the codesare outputon DQ0-DQ7withDQ8-DQ14

at High impedance;if the Word-wide configuration

is selectedthe codes are outputon DQ0-DQ7 with

DQ8-DQ15 at 00h.

V_CCSupply Voltage. The power supply for all op-

erations (Read, Program and Erase).

V_SSGround. V_SSis the reference for all voltage

measurements.

Block Protection. Each block can be separately

protected against Program or Erase on program-

ming equipment. Block protection provides addi-

tional data security, as it disables all program or

eraseoperations.This modeis activatedwhenboth

A9 and G are raised to V_IDand an address in the

block is applied on A12-A15.The Block Protection

algorithm is shown in Figure 14.Block protectionis

initiated on the edge of W falling to V_IL. Then after

a delay of 100µs, the edge of W rising to V_IHends

the protection operations.Block protectionverify is

achievedby bringing G, E, A0 and A6to V_ILandA1

to V_IH, whileW is at V_IHandA9 at V_ID. Under these

conditions, reading the data output will yield 01h if

the block defined by the inputs on A12-A15 is

protected.Any attempt to program or erase a pro-

tected block will be ignored by the device.

DEVICE OPERATIONS

See Tables4, 5 and 6.

Read. Readoperationsare usedto outputthe con-

tentsof theMemory Array,the ElectronicSignature,

the Status Register or the Block Protection Status.

Both Chip Enable E and Output EnableG must be

low in order to read the output of the memory.

Write. Write operationsare usedto give Instruction

Commands to the memory or to latch input data to

be programmed.A writeoperationis initiatedwhen

Chip Enable E is Low and Write Enable W is Low

with Output EnableG High. Addresses are latched

on the falling edge of W or E whichever occurslast.

CommandsandInputData arelatchedon therising

edge of W or E whicheveroccurs first.

6/30

M29F100T, M29F100B

Table 4. User Bus Operations ⁽¹⁾

DQ15

A–1

DQ8-

DQ14

Operation

Read Word

Read Byte

Write Word

Write Byte

E

G

W

RP

V_IH

BYTE

V_IH

A0

A1

A6

A9

A12 A15

DQ0-DQ7

Data

Output

Data

Output

Data

Output

V_IL

V_IH

V_IL

Address

Input

Data

Output

V_IL

Hi-Z

Data

Input

V_IH

A12 A15 Data Input Data Input

Address

Data

Input

V_IL

A12 A15

Hi-Z

Input

Hi-Z

Output Disable

Standby

V_IL

V_IH

X

V_IH

X

V_IH

X

V_IH

V_IL

X

Hi-Z

Reset

X

Block

V_IL

V_ID

V_IDV_ILPulse V_IH

X

V_ID

X

Protection^(2,4)

Blocks

V_IH

Unprotection⁽⁴⁾

Block

Protect

Status ⁽³⁾

Protection

V_IL

X

V_IL

X

V_IH

X

V_IH

V_ID

X

V_IL

X

V_IH

X

V_IL

V_IH

X

V_ID

X

A12 A15

X

Verify^(2,4)

Block

Protect

Status ⁽³⁾

Unprotection

Verify^(2,4)

Block

Temporary

Unprotection

X

Notes: 1. X = V_ILor V_IH

2. Block Address must be given on A12-A15 bits.

3. See Table 6.

4. Operation performed on programming equipment.

Table 5. Read Electronic Signature (following AS instruction or with A9 = V_ID)

Other

Addresses

DQ15

A–1

DQ8 -

DQ14

DQ0 -

DQ7

Org.

Code

Device

E

G

W

BYTE

A0

A1

Manufact.

Code

V_IL

V_IH

V_IL

Don’t Care

0

00h

20h

Word-

wide

M29F100T

V_IL

V_IH

V_IL

Don’t Care

0

00h

D0h

D1h

Device

Code

M29F100B V_IL

V_IL

Manufact.

Code

Don’t

Care

V_IL

V_IH

V_IL

V_IH

V_IL

Don’t Care

Hi-Z

20h

D0h

D1h

Byte-

wide

Don’t

Care

M29F100T

V_IL

Device

Code

Don’t

Care

M29F100B V_IL

Table 6. Read Block Protection with AS Instruction

Other

Code

E

G

W

A0

A1

A12 - A15

DQ0 - DQ7

Addresses

Don’t Care

Protected Block

V_IL

V_IH

V_IL

V_IH

Block Address

01h

00h

Unprotected Block

7/30

M29F100T, M29F100B

Block Temporary Unprotection. Any previously

protected block can be temporarily unprotected in

order to changestored data.The temporary unpro-

tection mode is activated by bringing RP to V_ID.

During the temporary unprotection mode the pre-

viously protected blocks are unprotected.A block

can be selected and data can be modified by exe-

cuting theErase or Programinstructionwiththe RP

signal held at V_ID. When RP is returned to V_IH, all

thepreviouslyprotectedblocksareagain protected.

Any read attempt during Program or Erase com-

mand execution will automaticallyoutput these five

Status Register bits.The P/E.C.automatically sets

bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits

(DQ0, DQ1 and DQ4) are reserved for future use

and should be masked.See Tables 9 and 10.

Data Polling Bit (DQ7). When Programming op-

erations are in progress, this bit outputs the com-

plement of the bit being programmed on DQ7.

During Erase operation, it outputs a ’0’. After com-

pletion of the operation, DQ7 will output the bit last

programmed or a ’1’ after erasing. Data Polling is

validand onlyeffectiveduringP/E.C.operation,that

is after the fourth W pulse for programming or after

thesixth W pulse for erase.It must be performed at

the address being programmed or at an address

within the block being erased. If all the blocks se-

lected for erasure are protected, DQ7 will be set to

’0’for about 100µs, and then return to the previous

addressed memory data value. See Figure 11 for

the Data Polling flowchart and Figure 10 for the

Data Polling waveforms. DQ7 will also flag the

Erase Suspend mode by switching from ’0’ to ’1’ at

the start of the Erase Suspend. In order to monitor

DQ7in the EraseSuspend mode an addresswithin

a blockbeing erased must be provided.Fora Read

Operationin EraseSuspendmode,DQ7will output

’1’if the read is attemptedon a blockbeing erased

andthedata valueonotherblocks.DuringProgram

operation in Erase Suspend Mode, DQ7 will have

the same behaviour as in the normal program

execution outside of the suspend mode.

Block Unprotection. All protected blocks can be

unprotected on programming equipment to allow

updating of bit contents. All blocks must first be

protected before the unprotection operation.Block

unprotectionis activated when A9, G and E are at

V_IDand A12, A15 at V_IH. The Block Unprotection

algorithm is shown in Figure 15. Unprotection is

initiatedby theedge of W fallingto V_IL.After a delay

of10ms,theunprotectionoperationwillend.Unpro-

tection verify is achieved by bringing G and E to V_IL

while A0 is at V_IL, A6 and A1 are at V_IHand A9

remains at V_ID. In these conditions, reading the

outputdata will yield 00h if the block defined by the

inputsA12-A15 has been succesfully unprotected.

Eachblock mustbe separatelyverifiedby giving its

address in order to ensure that it has been unpro-

tected.

INSTRUCTIONS AND COMMANDS

TheCommandInterfacelatchescommandswritten

to the memory. Instructions are made up from one

ormorecommandsto performReadMemoryArray,

Read ElectronicSignature,Read Block Protection,

Program,Block Erase,Chip Erase,Erase Suspend

and Erase Resume. Commands are made of ad-

dressanddatasequences.The instructionsrequire

from1 to 6 cycles, the firstor first threeof which are

always write operations used to initiate the instruc-

tion.Theyare followedby eitherfurther write cycles

to confirm the first command or execute the com-

mand immediately.Command sequencingmust be

followed exactly. Any invalid combination of com-

mands will reset the device to Read Array. The

increased number of cycles has been chosen to

assure maximum data security. Instructions are

initialised by two initial Coded cycles which unlock

the Command Interface.In addition, for Erase, in-

struction confirmationis again precededby the two

Coded cycles.

Table 7. Commands

Hex Code

00h

Command

Invalid/Reserved

10h

Chip Erase Confirm

Reserved

20h

30h

Block Erase Resume/Confirm

Set-up Erase

80h

Read Electronic Signature/

Block Protection Status

90h

A0h

B0h

F0h

Program

Status Register Bits

Erase Suspend

Read Array/Reset

P/E.C.status is indicated during execution by Data

Polling on DQ7, detection of Toggle on DQ6 and

DQ2, or Error on DQ5 and Erase Timer DQ3 bits.

8/30

M29F100T, M29F100B

Table 8. Instructions ⁽¹⁾

Mne.

Instr.

Cyc.

1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.

Addr. ^(3,7)

Data

X

1+

Read Memory Array until a new write cycle is initiated.

F0h

Read/Reset

Memory Array

RD ^(2,4)

Byte

AAAAh

5555h

AAh

5555h

2AAAh

55h

AAAAh

5555h

F0h

Addr. ^(3,7)

Read Memory Array until a new write cycle

is initiated.

3+

Word

Data

Byte

AAAAh

5555h

AAh

5555h

2AAAh

55h

AAAAh

5555h

90h

Addr. ^(3,7)

Read Electronic Signature or Block

Protection Status until a new write cycle is

initiated. See Note 5 and 6.

AS ⁽⁴⁾

Auto Select

Program

Word

Data

Byte

AAAAh

5555h

2AAAh

AAAAh

5555h

Program

Address

Addr. ^(3,7)

Read Data Polling or Toggle Bit

until Program completes.

PG

4

Word

Program

Data

AAh

55h

A0h

Byte

AAAAh

5555h

AAh

AAAAh

5555h

AAh

X

5555h

2AAAh

55h

AAAAh

5555h

80h

AAAAh

5555h

AAh

5555h

2AAAh

55h

Block

Additional

Addr. ^(3,7)

Address Block ⁽⁸⁾

BE

CE

Block Erase

Chip Erase

6

Word

Data

30h

AAAAh

5555h

10h

30h

Byte

5555h

2AAAh

55h

AAAAh

5555h

80h

AAAAh

5555h

AAh

5555h

2AAAh

55h

Addr. ^(3,7)

Note 9

Word

Data

Addr. ^(3,7)

Erase

Suspend

Read until Toggle stops, then read all the data needed from any

Block(s) not being erased then Resume Erase.

ES ⁽¹⁰⁾

1

Data

B0h

Addr. ^(3,7)

Data

X

Erase

Resume

Read Data Pollingor Toggle Bits until Erase completes or Erase is

suspended another time

ER

30h

Notes: 1. Commands not interpreted in this table will default to read array mode.

2. A wait of t_PLYHis necessary after a Read/Reset command if the memory was in an Erase or Program mode

before starting any new operation (see Table14 and Figure 9).

3. X = Don’t Care.

4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after

the command cycles.

5. Signature Address bits A0, A1 at V_ILwill outputManufacturer code (20h). Address bits A0 at V_IHand A1 at V_ILwill output

Device code.

6. Block Protection Address: A0 at V_IL, A1 at V_IHand A12-A15 within the Block will output the Block Protection status.

7. For Coded cycles address inputs A15 is don’t care.

8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry,

timeout status can be verified through DQ3 value (see Erase Timer Bit DQ3 description).

When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.

9. Read Data Polling,Toggle bits or RB until Erase completes.

10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.

9/30

M29F100T, M29F100B

Table 9. Status Register Bits

DQ

Name

Logic Level

Definition

Note

Erase Complete or erase

block in Erase Suspend

’1’

’0’

Indicates the P/E.C.status, check during

Program or Erase, and on completion

before checking bits DQ5 for Program or

Erase Success.

Erase On-going

Data

Polling

7

Program Complete or data

of non erase block during

Erase Suspend

DQ

Program On-going

’-1-0-1-0-1-0-1-’ Erase or Program On-going

Successive reads output complementary

data on DQ6 while Programming or Erase

operations are on-going. DQ6 remains at

constant level when P/E.C. operations are

completed or Erase Suspend is

DQ

Program Complete

6

Toggle Bit

Erase Complete or Erase

’-1-1-1-1-1-1-1-’ Suspend on currently

acknowledged.

addressed block

’1’

’0’

Program or Erase Error

This bit is set to ’1’ in the case of

Programming or Erase failure.

5

4

Error Bit

Program or Erase On-going

Reserved

P/E.C. Erase operation has started. Only

possible command entry is Erase

Suspend (ES).

’1’

’0’

Erase Timeout Period Expired

Erase

Time Bit

3

Erase Timeout Period

On-going

An additional block to be erased in parallel

can be entered to the P/E.C.

Chip Erase, Erase or Erase

Suspend on the currently

addressed block.

Erase Error due to the

currently addressed block

(when DQ5 = ’1’).

’-1-0-1-0-1-0-1-’

Indicates the erase status and allows to

identify the erased block

2

Toggle Bit

Program on-going, Erase

on-going on another block or

Erase Complete

1

Erase Suspend read on

non Erase Suspend block

DQ

1

0

Reserved

Notes: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

Toggle Bit (DQ6). When Programming or Erasing

operationsare in progress, successive attemptsto

read DQ6will outputcomplementarydata.DQ6 will

toggle following toggling of either G, or E when G

is low. The operation is completed when two suc-

cessive reads yield the same outputdata. The next

read willoutputthe bitlast programmedor a ’1’after

erasing. The toggle bit DQ6 is valid only during

P/E.C. operations, that is after the fourth W pulse

for programming or after the sixth W pulse for

Erase. If the blocks selected for erasure are pro-

tected, DQ6 will toggle for about 100µs and then

return backto Read.DQ6 will be set to ’1’if a Read

operationis attemptedon an EraseSuspend block.

When erase is suspended DQ6 will toggle during

programming operations in a block different to the

block in Erase Suspend.Either E or G toggling will

cause DQ6 to toggle.See Figure 12 for Toggle Bit

flowchart and Figure 13 for Toggle Bit waveforms.

10/30

M29F100T, M29F100B

Table 10. Polling and Toggle Bits

During the second cycle the Coded cycles consist

of writing the data 55h at address 5555h in the

Byte-wide configuration and at address 2AAAh in

the Word-wide configuration.In the Byte-wide con-

figurationthe address lines A–1 to A14 are valid, in

Word-wide A0 to A14 are valid, other addresslines

are ’don’t care’. The Coded cycles happen on first

and second cycles of the command write or on the

fourth and fifth cycles.

Mode

DQ7

0

DQ6

DQ2

Program

Erase

Toggle

1

Toggle Note 1

Erase Suspend Read

(in Erase Suspend

block)

1

Toggle

Instructions

See Table 8.

Erase Suspend Read

(outside Erase Suspend

block)

DQ7

DQ6

DQ2

N/A

Read/Reset (RD) Instruction. The Read/Reset

instruction consists of one write cycle giving the

commandF0h. It can be optionallyprecededby the

two Coded cycles.Subsequentread operationswill

read the memory array addressed and output the

data read. A wait state of 10µs is necessary after

Read/Reset prior to any valid read if the memory

was in an Erase mode when the RD instruction is

given.

Auto Select (AS) Instruction. This instruction

uses the two Coded cycles followed by one write

cycle giving the command 90h to address AAAAh

in the Byte-wide configurationor address5555h in

the Word-wide configuration for command set-up.

A subsequent read will output the manufacturer

code and the device code or the block protection

status depending on the levels of A0 and A1. The

manufacturer code, 20h, is output when the ad-

dresses lines A0 and A1 are Low, the devicecode,

D0h for Top Boot, D1h for Bottom Boot is output

when A0 is High with A1 Low.

Erase Suspend Program

Toggle

Note: 1. Toggle if the address is within a block being erased.

’1’ if the address is within a block not being erased.

Toggle Bit (DQ2). This toggle bit, together with

DQ6, can be used to determine the device status

during the Erase operations.It can also be used to

identify the block being erased. During Erase or

Erase Suspend a read from a block being erased

will cause DQ2 to toggle. A read from a block not

being erasedwill set DQ2 to ’1’during erase and to

DQ2 during Erase Suspend. During Chip Erase a

read operation will cause DQ2 to toggle as all

blocksare being erased.DQ2 willbe setto’1’during

program operation and when erase is complete.

After erase completion and if the error bit DQ5 is

set to ’1’, DQ2 will toggle if the faulty block is

addressed.

Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.

when thereis a failureof programming,blockerase,

or chip erase that results in invalid data in the

memory block.In case of an error in block erase or

program, the block in which the error occured or to

which the programmed data belongs,must be dis-

carded. The DQ5 failure condition will also appear

if a user tries to program a ’1’ to a location that is

previouslyprogrammedto ’0’.OtherBlocksmaystill

be used. The error bit resets after a Read/Reset

(RD) instruction.In case of success of Program or

Erase, the error bit will be set to ’0’.

The AS instruction also allows access to the block

protectionstatus.Aftergivingthe AS instruction,A0

is settoV_ILwithA1at V_IH, whileA12-A15define the

address of the block to be verified. A read in these

conditionswill output a 01h if the block is protected

and a 00h if the blockis not protected.

Program (PG) Instruction. This instruction uses

four write cycles. Both for Byte-wide configuration

and for Word-wide configuration. The Program

command A0h is written to address AAAAh in the

Byte-wide configuration or to address 5555h in the

Word-wide configurationon thethird cycleafter two

Coded cycles. A fourth write operation latches the

Addresson the falling edge of W or E and the Data

tobe writtenon therisingedgeandstartsthe P/E.C.

Read operations output the Status Register bits

after the programming has started. Memory pro-

gramming is made only by writing ’0’in placeof ’1’.

Status bits DQ6 and DQ7 determine if program-

ming is on-goingand DQ5 allowsverification ofany

possible error. Programming at an address not in

blocks being erased is also possible during erase

suspend. In this case, DQ2 will toggle at the ad-

dress being programmed.

Erase Timer Bit (DQ3). This bit is set to ’0’ by the

P/E.C. when the last block Erase command has

been entered to the Command Interface and it is

awaiting the Erase start. When the erase timeout

periodis finished,after80µs to 120µs, DQ3 returns

to ’1’.

Coded Cycles

The two Coded cycles unlock the Command Inter-

face. They are followed by an input command or a

confirmation command. The Coded cycles consist

of writing the data AAh at address AAAAh in the

Byte-wide configuration and at address 5555h in

the Word-wide configuration during the first cycle.

11/30

M29F100T, M29F100B

Table 11. AC Measurement Conditions

High Speed

Standard

Input Rise and Fall Times

Input Pulse Voltages

≤ 10ns

0 to 3V

1.5V

≤ 10ns

0.45V to 2.4V

0.8V and 2V

Input and Output Timing Ref. Voltages

Figure 4. AC Testing Input Output Waveform

Figure 5. AC Testing Load Circuit

1.3V

High Speed

1N914

3V

1.5V

3.3kΩ

0V

DEVICE

UNDER

TEST

OUT

Standard

C

L

2.4V

2.0V

0.8V

0.45V

C

= 30pF for High Speed

= 100pF for Standard

includes JIG capacitance

L

AI01275B

AI01276B

Table 12. Capacitance⁽¹⁾(T_A= 25 °C, f = 1 MHz )

Symbol

C_IN

Parameter

Input Capacitance

Output Capacitance

Test Condition

V_IN= 0V

Min

Max

6

Unit

pF

C_OUT

V_OUT= 0V

12

pF

Note: 1. Sampled only, not 100% tested.

Block Erase (BE) Instruction. This instruction

uses a minimum of six write cycles. The Erase

Set-up command 80h is written to address AAAAh

in the Byte-wide configuration or address 5555h in

the Word-wideconfigurationon third cycle after the

two Coded cycles. The Block Erase Confirm com-

mand 30h issimilarlywritten on thesixthcycleafter

another two Coded cycles. During the input of the

second commandan addresswithin the blockto be

erased is given and latched into the memory.Addi-

tional block Erase Confirm commands and block

addresses can be written subsequently to erase

other blocks in parallel, without further Coded cy-

cles. The erase will start after the erase timeout

period(see EraseTimer BitDQ3 description).Thus,

additional Erase Confirm commands for other

blocks must be given within this delay.The input of

a new Erase Confirm command will restart the

timeout period. The status of the internal timer can

be monitored through the level of DQ3, if DQ3 is ’0’

the Block Erase Command has been givenandthe

timeout is running, if DQ3 is ’1’, the timeout has

expiredand the P/E.C.is erasing the Block(s).If the

second command given is not an erase confirm or

if the Coded cycles are wrong, the instruction

aborts, and the device is reset to Read Array. It is

not necessary to programthe blockwith00h as the

P/E.C.willdo thisautomaticallybefore to erasing to

FFh. Read operations after the sixth rising edge of

W or E output the statusregister status bits.

12/30

M29F100T, M29F100B

Table 13. DC Characteristics

(T_A= 0 to 70°C, –40 to 85°C or –40 to 125°C;V_CC= 5V ± 10%)

Symbol

I_LI

Parameter

Test Condition

0V

Min

Max

Unit

Input Leakage Current

V

IN

V

CC

1

A

≤

±

µ

I_LO

Output Leakage Current

0V

V

OUT

V

≤

CC

≤

I_CC1

I_CC2

I_CC3

Supply Current (Read) TTL Byte

Supply Current (Read) TTL Word

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

E = V_IL, G = V_IH, f = 6MHz

E = V_IH

20

1

mA

100

E = V_CC0.2V

A

µ

±

Byte program, Block or

Chip Erase in progress

(1)

I_CC4

Supply Current (Program or Erase)

20

mA

V_IL

V_IH

V_OL

Input Low Voltage

–0.5

2

0.8

V_CC+ 0.5

0.45

V

Input High Voltage

Output Low Voltage

I_OL= 5.8mA

Output High Voltage TTL

Output High Voltage CMOS

A9 Voltage (Electronic Signature)

A9 Current (Electronic Signature)

I_OH= –2.5mA

2.4

V_CC–0.4V

11.0

V_OH

I_OH= –100 A

µ

V_ID

I_ID

12.0

100

A9 = V_ID

A

µ

Supply Voltage(Erase and

Program lock-out)

V_LKO

3.2

4.2

V

Note: 1. Sampled only, not 100% tested.

During the executionof the eraseby the P/E.C.,the

memory accepts only the Erase Suspend ES and

Read/Reset RD instructions. Data Polling bit DQ7

returns ’0’ while the erasure is in progress and ’1’

when it has completed. The Toggle bit DQ2 and

DQ6 toggle during the erase operation.They stop

when erase is completed. After completion the

StatusRegisterbit DQ5returns ’1’ifthere has been

an erase failure. In such a situation, the Toggle bit

DQ2 can be used to determine which block is not

correctly erased. In the case of erase failure, a

Read/ResetRD instructionis necessary inorder to

reset the P/E.C.

configurationon the third cycleafter the twoCoded

cycles. The Chip Erase Confirm command 10h is

similarlywritten on thesixth cycle afteranother two

Coded cycles.If the second command given is not

an erase confirm or if theCoded cycles are wrong,

the instruction aborts and the device is reset to

Read Array.It is notnecessaryto programthearray

with00h firstas the P/E.C.will automaticallydo this

before erasing it to FFh. Read operations after the

sixth rising edge of W or E output the Status Reg-

ister bits. During the execution of the erase by the

P/E.C., Data Polling bit DQ7 returns ’0’, then ’1’ on

completion.The Toggle bits DQ2 and DQ6 toggle

during erase operation and stop when erase is

completed.After completion the Status Registerbit

DQ5 returns ’1’ if there has been an Erase Failure.

Chip Erase(CE) Instruction.Thisinstructionuses

six write cycles. The Erase Set-up command 80h

is written to address AAAAh in the Byte-wide con-

figuration or the address 5555h in the Word-wide

13/30

M29F100T, M29F100B

Table 14. Read AC Characteristics

(T_A= 0 to 70°C, –40 to 85°C or –40 to 125°C)

M29F100T / M29F100B

-90

-70

-120

Symbol

Alt

Parameter

Test Condition

Unit

V_CC= 5V 5% V = 5V 10% V = 5V 10%

±

CC

High Speed

Interface

Standard

Interface

Standard

Interface

Min

Max

Min

Max

Min

Max

Address Valid to Next

Address Valid

t_AVAV

t_RC

t_ACC

t_LZ

E = V_IL, G = V_IL

G = V_IL

70

90

120

ns

µs

Address Valid to

Output Valid

t_AVQV

70

90

35

20

10

120

Chip Enable Low to

Output Transition

(1)

t_ELQX

0

Chip Enable Low to

Output Valid

(2)

t_ELQV

t_CE

t_OLZ

t_OE

t_OH

t_HZ

G = V_IL

70

30

20

10

120

50

30

10

Output Enable Low

to Output Transition

(1)

t_GLQX

E = V_IL

0

Output Enable Low

to Output Valid

(2)

t_GLQV

E = V_IL

Chip Enable High to

Output Transition

t_EHQX

G = V_IL

0

Chip Enable High to

Output Hi-Z

(1)

t_EHQZ

G = V_IL

Output Enable High

to Output Transition

t_GHQX

t_OH

t_DF

E = V_IL

0

Output Enable High

to Output Hi-Z

(1)

t_GHQZ

E = V_IL

Address Transition to

Output Transition

t_AXQX

t_OH

E = V_IL, G = V_IL

0

t_RRBRP Low to Read

t_READYMode

(1,3)

t_PLYH

RP High to Chip

t_RH

t_PHEL

t_PLPX

50

ns

Enable Low

t_RPRP Pulse Width

500

Chip Enable to BYTE

t_ELBL

t_ELBH

t_ELFL

Switching Low or

5

ns

t_ELFH

High

BYTE Switching Low

t_FLQZto Output

High Z

t_BLQZ

30

40

BYTE Switching

t_FHQVHigh to Output

Valid

t_BHQV

Notes: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t_ELQV- t_GLQVafter the falling edge of E without increasing t_ELQV

3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.

.

14/30

M29F100T, M29F100B

Figure 6. Read Mode AC Waveforms

15/30

M29F100T, M29F100B

Table 15. Write AC Characteristics,Write Enable Controlled

(T_A= 0 to 70°C, –40 to 85°C or –40 to 125°C)

M29F100T / M29F100B

-90

-70

-120

Symbol

Alt

Parameter

Unit

V

_CC= 5V ± 5% V_CC= 5V ± 10% V_CC= 5V ± 10%

High Speed

Interface

Standard

Interface

Standard

Interface

Min

Max

Min

Max

Min

Max

t_AVAV

t_WCAddress Valid to Next Address Valid

70

0

90

0

120

0

ns

Chip Enable Low to Write Enable

t_ELWL

t_CS

Low

Write Enable Low to Write Enable

t_WLWH

t_DVWH

t_WHDX

t_WP

35

30

0

45

0

50

0

ns

High

t_DSInput Valid to Write Enable High

Write Enable High to Input

Transition

t_DH

Write Enable High to Chip Enable

High

t_WHEH

t_CH

0

ns

Write Enable High to Write Enable

t_WHWL

t_AVWL

t_WLAX

t_WPH

Low

20

0

20

0

20

0

ns

t_ASAddress Valid to Write Enable Low

Write Enable Low to Address

Transition

t_AH

45

50

Output Enable High to Write

Enable Low

t_GHWL

t_VCHEL

t_WHGL

0

50

0

50

0

50

0

ns

t_VCSV_CCHigh to Chip Enable Low

s

µ

Write Enable High to Output

Enable Low

t_OEH

ns

(1,2)

t_PHPHH

t_VIDRRP Rise Time to V_ID

500

ns

t_PLPX

t_RPRP Pulse Width

(1)

t_WHRL

t_BUSYProgram Erase Valid to RB Delay

t_RSPRP High to Write Enable Low

30

35

50

(1)

t_PHWL

4

s

µ

Notes: 1. Sample only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

EraseSuspend(ES)Instruction.TheBlockErase

operation may be suspended by this instruction

which consistsof writing the commandB0h without

any specific address. No Coded cycles are re-

quired.It permitsreadingof data fromanotherblock

and programming in another block while an erase

operationis inprogress.Erasesuspendis accepted

only during the Block Erase instruction execution.

Writing this command during Erase timeout will, in

addition to suspending the erase, terminate the

timeout. The Toggle bit DQ6 stops toggling when

the P/E.C. is suspended. The Toggle bits will stop

toggling between 0.1µs and 15µs after the Erase

Suspend (ES) command has been written. The

device will then automatically be set to Read Mem-

ory Arraymode.Whenerase is suspended,a Read

from blocks being erased will output DQ2 toggling

and DQ6 at ’1’. A Read from a block not being

16/30

M29F100T, M29F100B

Figure 7. WriteAC Waveforms,W Controlled

tAVAV

VALID

A0-A15/

A–1

tWLAX

tAVWL

tWHEH

E

tELWL

tWHGL

G

tGHWL

tWLWH

W

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHEL

RB

tWHRL

AI01980B

Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.

erased returns valid data. During suspension the

memory will respond onlyto the EraseResume ER

and the Program PG instructions. A Program op-

erationcan beinitiatedduringerasesuspendinone

of the blocks not being erased. It will result in both

DQ2 and DQ6 toggling when the data is being

programmed. A Read/Reset command will defini-

tively abort erasure and result in invalid data in the

blocks being erased.

POWER SUPPLY

Power Up

The memory Command Interfaceis reset on power

up to Read Array. Either E or W must be tied to V_IH

during Power Up to allow maximum security and

the possibilityto writea commandon the firstrising

edgeofE andW.Anywritecycleinitiationis blocked

when Vcc is belowV_LKO

.

Supply Rails

Erase Resume(ER) Instruction. If an EraseSus-

pend instruction was previously executed, the

erase operation may be resumed by giving the

command 30h, at any address, and without any

Coded cycles.

Normal precautions must be taken for supply volt-

age decoupling; each device in a system should

havethe V_CCrail decoupled with a 0.1µF capacitor

closetothe V_CCandV_SSpins.ThePCBtracewidths

should be sufficient to carry the V_CCprogram and

erase currents required.

17/30

M29F100T, M29F100B

Table 16. Write AC Characteristics,Chip Enable Controlled

(T_A= 0 to 70°C, –40 to 85°C or –40 to 125°C)

M29F100T / M29F100B

-90

-70

-120

Symbol

Alt

Parameter

Unit

V

_CC= 5V ± 5% V_CC= 5V ± 10% V_CC= 5V ± 10%

High Speed

Interface

Standard

Interface

Standard

Interface

Min

Max

Min

Max

Min

Max

Address Valid to Next Address

Valid

t_AVAV

t_WC

t_WS

70

0

90

0

120

0

ns

Write Enable Low to Chip

Enable Low

t_WLEL

Chip Enable Low to Chip Enable

High

t_ELEH

t_DVEH

t_EHDX

t_CP

t_DS

t_DH

35

30

0

45

0

50

0

ns

Input Valid to Chip Enable High

Chip Enable High to Input

Transition

Chip Enable High to Write

Enable High

t_EHWH

t_EHEL

t_AVEL

t_ELAX

t_WH

t_CPH

t_AS

0

20

0

20

0

ns

Chip Enable High to Chip

Enable Low

20

0

Address Valid to Chip Enable

Low

Chip Enable Low to Address

Transition

t_AH

45

50

Output Enable High Chip

Enable Low

t_GHEL

t_VCHWL

t_EHGL

0

50

0

50

0

50

0

t_VCS

t_OEH

V_CCHigh to Write Enable Low

s

µ

Chip Enable High to Output

Enable Low

ns

(1,2)

t_PHPHH

t_VIDR

t_RP

RP Rise TIme to V_ID

RP Pulse Width

500

ns

t_PLPX

Program Erase Valid to RB

Delay

(1)

t_EHRL

t_PHWL

t_BUSY

30

35

50

ns

t_RSP

RP High to Write Enable Low

4

µs

Notes: 1. Sample only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

18/30

M29F100T, M29F100B

Figure 8. WriteAC Waveforms,E Controlled

tAVAV

VALID

A0-A15/

A–1

tELAX

tAVEL

tEHWH

W

tWLEL

tEHGL

G

tGHEL

tELEH

E

tEHEL

tEHDX

tDVEH

VALID

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHWL

RB

tEHRL

AI01981B

Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.

Figure 9. Read and Write AC Characteristics,RP Related

E

tPHEL

W

tPHWL

RB

tPLPX

RP

tPHPHH

tPLYH

AI02091

19/30

M29F100T, M29F100B

Table 17. Data Polling and Toggle Bit AC Characteristics ⁽¹⁾

(T_A= 0 to 70°C, –40 to 85°C or –40 to 125°C)

M29F100T / M29F100B

-70

-90

-120

Symbol

Parameter

Unit

V

_CC= 5V ± 5%

V_CC= 5V ± 10%

High Speed

Interface

Standard

Interface

Standard

Interface

Min

Max

Min

Max

Min

Max

Write Enable High to DQ7 Valid

(Program, W Controlled)

10

2400

30

10

2400

10

2400

µs

t_WHQ7V

Write Enable High to DQ7 Valid

(Chip Erase, W Controlled)

1.0

10

1.0

10

30

2400

30

1.0

10

30

2400

30

sec

Chip Enable High to DQ7 Valid

(Program, E Controlled)

2400

30

s

µ

t_EHQ7V

Chip Enable High to DQ7 Valid

(Chip Erase, E Controlled)

1.0

sec

ns

Q7 Valid to Output Valid (Data

Polling)

t_Q7VQV

30

35

50

Write Enable High to Output Valid

(Program)

10

1.0

10

2400

30

10

1.0

10

2400

30

10

1.0

10

2400

30

s

µ

t_WHQV

Write Enable High to Output Valid

(Chip Erase)

sec

µs

Chip Enable High to Output Valid

(Program)

2400

30

2400

30

2400

30

t_EHQV

Chip Enable High to Output Valid

(Chip Erase)

1.0

sec

Note: 1. All other timings are defined in Read AC Characteristics table.

20/30

M29F100T, M29F100B

Figure 10. Data Polling DQ7 AC Waveforms

21/30

M29F100T, M29F100B

Figure 11. Data Polling Flowchart

Figure 12. Data Toggle Flowchart

START

READ

DQ2, DQ5 & DQ6

READ DQ5 & DQ7

at VALID ADDRESS

NO

DQ2, DQ6

=

DQ7

=

DATA

YES

TOGGLE

NO

YES

NO

DQ5

= 1

DQ5

= 1

YES

READ DQ2, DQ6

READ DQ7

DQ7

=

DATA

YES

NO

DQ2, DQ6

=

TOGGLE

NO

YES

FAIL

PASS

AI01369

AI01873

Table 18. Program,Erase Times and Program,Erase Endurance Cycles

(T_A= 0 to 70°C;V_CC= 5V ± 10% or 5V ± 5%)

M29F100T / M29F100B

Parameter

Unit

Typical after

100k W/E Cycles

Min

Typ

Chip Erase (Preprogrammed)

Chip Erase

0.4

1.5

0.6

0.5

0.9

1.0

1.4

11

0.6

1.7

sec

µs

Boot Block Erase

Parameter Block Erase

Main Block (32Kb) Erase

Main Block (64Kb) Erase

Chip Program (Byte)

Byte Program

1.4

11

20

Word Program

20

s

µ

Program/Erase Cycles (per Block)

100,000

cycles

22/30

M29F100T, M29F100B

Figure 13. DataToggle DQ6,DQ2 AC Waveforms

23/30

M29F100T, M29F100B

Figure 14. BlockProtection Flowchart

START

BLOCK ADDRESS

on A12-A15

W = V

IH

Set-up

n = 0

G, A9 = V

E = V

,

ID

IL

Wait 4µs

W = V

IL

Protect

Verify

Wait 100µs

W = V

IH

E, G = V

IH

VERIFY BLOCK PROTECTION

A0, A6 = V ; A1 = V ; A9 = V

ID

IL

IH

A12-A15 IDENTIFY BLOCK

E = V

IL

Wait 4µs

G = V

IL

Wait 60ns

VERIFY BLOCK

PROTECT STATUS

NO

DATA

=

01h

YES

A9 = V

IH

++n

NO

= 25

PASS

YES

A9 = V

IH

FAIL

AI01984C

24/30

M29F100T, M29F100B

Figure 15. All Blocks Unprotecting Flowchart

START

PROTECT

ALL BLOCKS

n = 0

Set-up

W = V

IH

E, G, A9 = V

ID

A12, A15 = V

IH

Wait 4µs

W = V

IL

Wait 10ms

Unprotect

Verify

W = V

IH

E, G = V

IH

E, A0 = V ; A1, A6 = V ; A9 = V

ID

IL

IH

A12-A15 IDENTIFY BLOCK

Wait 4µs

G = V

IL

Wait 60ns

VERIFY BLOCK

PROTECT STATUS

NO

DATA

=

00h

YES

NO

++n

= 1000

LAST

BLK.

NO

YES

A9 = V

IH

FAIL

PASS

AI01985D

25/30

M29F100T, M29F100B

ORDERING INFORMATION SCHEME

Example:

M29F100T

-70

X

N

1

TR

OperatingVoltage

Option

F

5V

R

Reverse

Pinout

TR Tape & Reel

Packing

Array Matrix

Top Boot

Speed

-70 70ns

Power Supplies

blank

Package

Temp. Range

T

B

N

TSOP48

12 x 20mm

1

6

3

V_CC10%

0 to 70 C

°

±

Bottom Boot

-90 90ns

X

V_CC5%

–40 to 85 C

°

±

M

SO44

-120 120ns

–40 to 125 C

°

M29F100T and M29F100B are replaced respectively by the new version M29F100BT and

M29F100BB.

Devices are shipped from the factory with the memory content erased (to FFh).

For a list of availableoptions (Speed, Package,etc...)or forfurther informationon any aspect of this device,

please contact the STMicroelectronics Sales Office nearest to you.

26/30

M29F100T, M29F100B

TSOP48 Normal Pinout - 48 lead Plastic Thin Small Outline, 12 x 20mm

mm

Min

inches

Min

Symb

Typ

Max

1.20

0.15

1.05

0.27

0.21

20.20

18.50

12.10

-

Typ

Max

0.047

0.006

0.041

0.011

0.008

0.795

0.728

0.476

-

A

A1

A2

B

0.05

0.95

0.17

0.10

19.80

18.30

11.90

-

0.002

0.037

0.007

0.004

0.780

0.720

0.469

-

C

D

D1

E

e

0.50

0.020

L

0.50

0°

0.70

5°

0.020

0°

0.028

5°

α

N

48

CP

0.10

0.004

A2

1

N

e

E

B

N/2

D1

A

CP

D

DIE

C

TSOP-a

A1

α

L

Drawing is not to scale.

27/30

M29F100T, M29F100B

TSOP48 Reverse Pinout - 48 lead Plastic Thin Small Outline, 12 x 20mm

mm

Min

inches

Min

Symb

Typ

Max

1.20

0.15

1.05

0.27

0.21

20.20

18.50

12.10

–

Typ

Max

0.047

0.006

0.041

0.011

0.008

0.795

0.728

0.476

–

A

A1

A2

B

0.05

0.95

0.17

0.10

19.80

18.30

11.90

–

0.002

0.037

0.007

0.004

0.780

0.720

0.469

–

C

D

D1

E

e

0.50

0.020

L

0.50

0°

0.70

5°

0.020

0°

0.028

5°

α

N

48

CP

0.10

0.004

A2

1

N

e

E

B

N/2

D1

A

CP

D

DIE

C

TSOP-b

A1

α

L

Drawing is not to scale.

28/30

M29F100T, M29F100B

SO44 - 44 lead Plastic Small Outline, 525 mils body width

mm

Min

2.42

0.22

2.25

inches

Min

Symb

Typ

Max

2.62

0.23

2.35

0.50

0.25

28.30

13.40

Typ

Max

0.103

0.010

0.093

0.020

0.010

1.114

0.528

A

A1

A2

B

0.095

0.009

0.089

C

0.10

28.10

13.20

0.004

1.106

0.520

D

E

e

1.27

0.050

H

15.90

44

16.10

0.626

44

0.634

L

0.80

0.031

α

3°

N

CP

0.10

0.004

A2

A

C

B

CP

e

D

N

1

E

H

A1

α

L

SO-b

Drawing is not to scale.

29/30

M29F100T, M29F100B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of

use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patentrights of STMicroelectronics. Specifications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

30/30


型号：	M29F100BB90N1
厂家：	ST
描述：	64KX16 FLASH 5V PROM, 70ns, PDSO48, 12 X 20 MM, PLASTIC, TSOP-48 可编程只读存储器光电二极管内存集成电路
文件：	总30页 (文件大小：209K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M29F100BB90N1 [STMICROELECTRONICS]

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