M29F100-T90XN1R [STMICROELECTRONICS]
1 Mbit 128Kb x8 or 64Kb x16, Boot Block Single Supply Flash Memory; 1兆位128KB ×8或64Kb的X16 ，引导块单电源闪存
| 型号： | M29F100-T90XN1R |
| 厂家： | 
ST |
| 描述： | 1 Mbit 128Kb x8 or 64Kb x16, Boot Block Single Supply Flash Memory |
| 文件： | 总30页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M29F100T
M29F100B
1 Mbit (128Kb x8 or 64Kb x16, Boot Block)
Single Supply Flash Memory
5V ± 10% SUPPLYVOLTAGEfor PROGRAM,
ERASE and READ OPERATIONS
FASTACCESS TIME: 70ns
FAST PROGRAMMING TIME
– 10 s by Byte / 16 s by Word typical
µ
µ
44
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte or Word-by-Word
– Status Register bits and Ready/Busy Output
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameterand Main blocks
1
TSOP48 (N)
12 x 20 mm
SO44 (M)
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI-BLOCKPROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
Figure 1. Logic Diagram
LOW POWER CONSUMPTION
– Stand-byand AutomaticStand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARSDATARETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
V
CC
16
15
– ManufacturerCode: 0020h
– Device Code, M29F100T: 00D0h
– Device Code, M29F100B: 00D1h
A0-A15
DQ0-DQ14
W
E
DQ15A–1
BYTE
RB
M29F100T
M29F100B
DESCRIPTION
The M29F100 is a non-volatile memory that may
be erased electrically at the block or chiplevel and
programmedin-systemona Byte-by-Byteor Word-
by-Word basis using only a single 5V VCC supply.
For Program and Erase operations the necessary
high voltages are generatedinternally. The device
can also be programmed in standard program-
mers.
G
RP
V
The array matrix organisationallows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protectedagainst pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in
the application. Each block can be programmed
and erased over 100,000 cycles.
SS
AI01974
July 1998
1/30
M29F100T, M29F100B
Figure 2A. TSOP Pin Connections
Figure 2B. TSOP Reverse Pin Connections
A15
A14
A13
A12
A11
A10
A9
1
48
NC
NC
1
48
A15
A14
A13
A12
A11
A10
A9
BYTE
BYTE
V
SS
V
SS
DQ15A–1
DQ15A–1
DQ7
DQ7
DQ14
DQ6
DQ14
DQ6
DQ13
DQ5
A8
A8
DQ13
DQ5
NC
NC
W
NC
NC
W
DQ12
DQ4
DQ12
DQ4
M29F100T
M29F100B
(Normal)
M29F100T
M29F100B
(Reverse)
V
12
13
37
36
RP
NC
NC
RB
NC
NC
A7
RP
NC
NC
RB
NC
NC
A7
12
13
37
36
V
CC
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
A6
A6
A5
A5
A4
A4
A3
V
V
SS
A3
SS
E
A2
A2
E
A0
24
25
A1
A1
24
25
A0
AI01975
AI01976
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Figure 2C. SO Pin Connections
Table 1. Signal Names
A0-A15
DQ0-DQ7
DQ8-DQ14
DQ15A–1
E
Address Inputs
NC
RB
NC
A7
A6
A5
A4
A3
A2
A1
A0
E
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP
Data Input/Outputs, Command Inputs
Data Input/Outputs
2
W
3
A8
4
A9
5
A10
A11
A12
A13
A14
A15
NC
Data Input/Output or Address Input
Chip Enable
6
7
8
9
G
Output Enable
10
11
12
13
14
15
16
17
18
19
20
21
22
M29F100T
M29F100B
W
Write Enable
BYTE
V
V
RP
Reset / Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organisation
Supply Voltage
SS
G
SS
DQ15A–1
DQ0
DQ8
DQ7
RB
DQ14
DQ6
BYTE
VCC
DQ1
DQ9
DQ13
DQ5
DQ2
DQ10
DQ3
DQ12
DQ4
VSS
Ground
DQ11
V
CC
AI01977
Warning: NC = Not Connected.
2/30
M29F100T, M29F100B
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
Unit
Ambient Operating Temperature (3)
Temperature Under Bias
Storage Temperature
–40 to 125
–50 to 125
–65 to 150
–0.6 to 7
C
°
TBIAS
TSTG
C
°
C
°
(2)
VIO
Input or Output Voltages
Supply Voltage
V
VCC
–0.6 to 7
V
V
(2)
V(A9, E, G, RP)
A9, E, G, RP Voltage
–0.6 to 13.5
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”AbsoluteMaximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltagemay undershoot to –2V during transitionand for less than 20ns.
3. Depends on range.
DESCRIPTION (Cont’d)
the P/E.C operations. A Ready/Busy RB output
indicates the completionof the internal algorithms.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature or Block Protection
status,Programming, Blockand ChipErase, Erase
Suspend and Resume are written to the device in
cyclesof commandstoa CommandInterfaceusing
standardmicroprocessor write timings.
Memory Blocks
The devices feature asymmetrically blockedarchi-
tectureprovidingsystem memory integration.Both
M29F100T and M29F100B devices have an array
of 5 blocks, one Boot Block of 16 KBytes or 8
KWords, two Parameter Blocks of 8 KBytes or 4
KWords, one Main Block of 32 KBytes or 16
KWords and one Main Blocks of 64 KBytes or 32
KWords. The M29F100Thas the Boot Blockat the
top of the memory address space and the
M29F100B locates the Boot Block starting at the
bottom. The memory maps are showed in Figure
3. Each block can be erased separately,any com-
bination of blocks can be specified for multi-block
erase or the entire chip may be erased. The Erase
operations are managed automatically by the
P/E.C. The block erase operation can be sus-
pended in order to read from or program to any
block not being ersased, and then resumed.
The device is offeredin TSOP48(12 x 20mm) and
SO44 packages.Both normal and reversepinouts
are available for the TSOP48package.
Organisation
The M29F100 is organised as 128Kb x8 or 64Kb
x16 bits selectable by the BYTE signal. When
BYTE is Low the Byte-wide x8 organisation is
selected and the address lines are DQ15A–1 and
A0-A15. The Data Input/Output signal DQ15A–1
actsas addressline A–1which selectsthe loweror
upper Byte of the memory word for output on
DQ0-DQ7, DQ8-DQ14 remain at High impedance.
When BYTEis Highthe memory uses the address
inputs A0-A15 and the Data Input/Outputs DQ0-
DQ15. Memory control is provided by Chip Enable
E, Output Enable G and Write Enable W inputs.
Block protection provides additional data security.
Each block can be separately protected or unpro-
tected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotectedin the application.
AReset/BlockTemporaryUnprotection RPtri-level
input provides a hardware reset when pulled Low,
andwhen heldHigh(atVID)temporarily unprotects
blocks previously protected allowing them to be
programedand erased.Erase andProgramopera-
tions are controlled by an internal Program/Erase
Controller(P/E.C.). StatusRegisterdata output on
DQ7 provides a Data Polling signal, and DQ6 and
DQ2 provide Toggle signals to indicatethe state of
Bus Operations
The following operations can be performed using
theappropriatebus cycles:Read(Array, Electronic
Signature, Block Protection Status), Write com-
mand, Output Disable, Standby,Reset, Block Pro-
tection, Unprotection, Protection Verify,
Unprotection Verify and Block Temporary Unpro-
tection. See Tables4 and 5.
3/30
M29F100T, M29F100B
Figure 3. Memory Map and Block Address Table (x8)
M29F100T
1FFFFh
M29F100B
1FFFFh
16K BOOT BLOCK
64K MAIN BLOCK
1C000h
1BFFFh
10000h
0FFFFh
8K PARAMETER BLOCK
32K MAIN BLOCK
1A000h
19FFFh
08000h
07FFFh
8K PARAMETER BLOCK
8K PARAMETER BLOCK
8K PARAMETER BLOCK
16K BOOT BLOCK
06000h
05FFFh
18000h
17FFFh
32K MAIN BLOCK
10000h
0FFFFh
04000h
03FFFh
64K MAIN BLOCK
00000h
00000h
AI01978
Table 3A. M29F100T Block Address Table
Address Range (x8)
00000h-0FFFFh
10000h-17FFFh
18000h-19FFFh
1A000h-1BFFFh
1C000h-1FFFFh
Address Range (x16)
0000h-7FFFh
A15
0
A14
X
A13
X
A12
X
8000h-BFFFh
1
0
X
X
C000h-CFFFh
D000h-DFFFh
E000h-FFFFh
1
1
0
0
1
1
0
1
1
1
1
X
Table 3B. M29F100B Block Address Table
Address Range (x8)
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
Address Range (x16)
0000h-1FFFh
A15
0
A14
0
A13
0
A12
X
2000h-2FFFh
0
0
1
0
3000h-3FFFh
0
0
1
1
4000h-7FFFh
0
1
X
X
8000h-FFFFh
1
X
X
X
4/30
M29F100T, M29F100B
Command Interface
When A9 is raised to V , either a Read Electronic
ID
Signature Manufacturer or Device Code, Block
Protection Status or a Write Block Protection or
Block Unprotection is enabled depending on the
combinationof levelson A0, A1,A6, A12 and A15.
Instructions, made up of commands written in cy-
cles, can be givento theProgram/EraseController
through a Command Interface (C.I.). For added
data protection, program or erase executionstarts
after4 or 6 cycles. Thefirst, second,fourthand fifth
cycles are used to input Coded cycles to the C.I.
This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The ’Com-
mand’ itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se-
quencewill reset the device to Read Array mode.
Data Input/Outputs (DQ0-DQ7). These In-
puts/Outputsare used in the Byte-wide and Word-
wide organisations. The input is data to be
programmed in the memory array or a command
to be written to the C.I. Both are latched on the
rising edge of Chip Enable E or Write Enable W.
The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputsaredisabledand whenRPis at aLowlevel.
Data Input/Outputs (DQ8-DQ14 and DQ15A–1).
These Inputs/Outputsare additionally used in the
Word-wideorganisation.WhenBYTEis HighDQ8-
DQ14 and DQ15A–1 act as the MSB of the Data
Input or Output, functioningas described for DQ0-
DQ7 above, and DQ8-DQ15 are ’don’t care’ for
command inputs or statusoutputs. When BYTEis
Low,DQ8-DQ14 are highimpedance, DQ15A–1is
the Address A–1 input.
Instructions
Seven instructions are defined to perform Read
Array,Auto Select(to readthe ElectronicSignature
or Block ProtectionStatus), Program, BlockErase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all tim-
ing and verification of the Program and Erase
operations.The Status Register Data Polling, Tog-
gle, Error bits and the RB output may be read at
any time, duringprogramming or erase, to monitor
the progress of the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
CommandInterfacewhich iscommontoall instruc-
tions (see Table 8). The third cycle inputs the
instruction set-up command. Subsequent cycles
outputthe addressed data, Electronic Signatureor
Block Protection Status for Read operations. In
orderto giveadditionaldata protection,the instruc-
tions for Programand Block or Chip Erase require
furthercommandinputs. ForaPrograminstruction,
the fourth command cycle inputs the address and
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Coded sequence before the Erase confirm
command on the sixth cycle. Erasure of a memory
blockmaybe suspended,in orderto readdatafrom
anotherblock or to programdata in another block,
and then resumed.
Chip Enable (E). The Chip Enable input activates
the memory control logic, input buffers, decoders
andsenseamplifiers.E Highdeselectsthememory
andreducesthe powerconsumptiontothestandby
level. E can also be used to control writing to the
command register and to the memory array, while
Wremainsat a low level. TheChip Enablemust be
forced to VID duringthe Block Unprotection opera-
tion.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to VID level during
Block Protection and Unprotection operations.
When power is first applied or if VCC falls below
VLKO, the command interface is reset to Read
Array.
WriteEnable (W). This inputcontrols writing to the
CommandRegisterand Addressand Datalatches.
Byte/Word Organization Select (BYTE). The
BYTE input selects the outputconfigurationfor the
device: Byte-wide (x8) mode or Word-wide (x16)
mode. When BYTEis Low, the Byte-wide mode is
selectedand the data is read and programmed on
DQ0-DQ7. In this mode, DQ8-DQ14 are at high
impedance and DQ15A–1 is the LSB address.
When BYTE is High, the Word-wide mode is se-
lected and the data is read and programmed on
DQ0-DQ15.
SIGNAL DESCRIPTIONS
See Figure 1 and Table1.
Address Inputs (A0-A15). The address inputs for
the memory array are latchedduring a write opera-
tion on the falling edge of Chip Enable E or Write
Enable W. In Word-wide organisation the address
lines are A0-A15, in Byte-wide organisation
DQ15A–1 acts as an additional LSB address line.
5/30
M29F100T, M29F100B
Ready/Busy Output (RB). Ready/Busy is an
open-drainoutputandgivestheinternalstateof the
P/E.C. of the device. When RB is Low, the device
is Busy with a Program or Erase operation and it
will not accept any additional program or erase
instructionsexcept the Erase Suspendinstruction.
WhenRB is High,the deviceis readyfor any Read,
Program or Erase operation. The RB will also be
High when the memory is put in Erase Suspendor
Standbymodes.
Output Disable. The data outputsare high imped-
ance when the Output Enable G is High with Write
Enable W High.
Standby. The memory is in standby when Chip
EnableE is High and the P/E.C. is idle. Thepower
consumption is reduced to the standby level and
the outputs are high impedance, independent of
the Output Enable G or WriteEnable W inputs.
Automatic Standby. After 150ns of bus inactivity
and when CMOS levels are driving the addresses,
the chip automatically enters a pseudo-standby
mode whereconsumptionis reducedto the CMOS
standby value, while outputs still drive the bus.
Reset/Block Temporary Unprotect Input (RP).
The RP Input provides hardware reset and pro-
tected block(s) temporary unprotection functions.
Reset of the memory is acheived by pulling RP to
VIL for at least 500ns. When the reset pulse is
given, if the memoryis in Read or Standbymodes,
it will be availablefor new operationsin 50ns after
the rising edge of RP. If the memory is in Erase,
Erase Suspend or Program modes the reset will
Electronic Signature. Two codes identifying the
manufacturer and the devicecan be readfrom the
memory. The manufacturer’s code for STMi-
croelectronicsis20h, the devicecodeis D0hfor the
M29F100T(Top Boot) and D1h for the M29F100B
(Bottom Boot). These codes allow programming
equipment or applications to automatically match
their interface to the characteristics of the
M29F100. The Electronic Signature is output by a
Read operation when the voltage applied to A9 is
at VID and address input A1 is Low. The manufac-
turer code is output when the Address input A0 is
Low and the device code when this input is High.
Other Address inputs are ignored. The codes are
output on DQ0-DQ7.
take 10 s during which the RB signal will be held
µ
atVIL. Theendof thememoryresetwill beindicated
by the rising edge of RB. A hardware reset during
an Eraseor Programoperationwillcorruptthe data
being programmed or the sector(s)being erased.
Temporary block unprotection is made by holding
RP at VID. In this condition previously protected
blocks can be programmed or erased. The transi-
tion of RP from VIH to VID must slowerthan 500ns.
When RP is returned from VID to VIH all blocks
temporarily unprotectedwill be again protected.
VCC Supply Voltage. The power supply for all
operations(Read, Program and Erase).
VSS Ground. VSS is the reference for all voltage
measurements.
TheElectronic Signaturecan alsobe read, without
raisingA9 to VID, bygiving the memory the Instruc-
tion AS. If the Byte-wide configuration is selected
thecodesareoutput onDQ0-DQ7with DQ8-DQ14
at High impedance; if the Word-wide configuration
is selected the codes are output on DQ0-DQ7 with
DQ8-DQ15 at 00h.
Block Protection. Each block can be separately
protected against Program or Erase on program-
ming equipment. Block protection provides addi-
tional data security, as it disables all program or
eraseoperations.Thismodeis activatedwhenboth
A9 and G are raised to VID and an address in the
block is appliedon A12-A15.The Block Protection
algorithmis shown in Figure14. Blockprotectionis
initiated on the edge of W falling to VIL. Then after
a delay of 100µs, the edge of W rising to VIH ends
the protectionoperations.Block protectionverifyis
achievedby bringingG, E, A0and A6 to VIL andA1
to VIH, while W is at VIH and A9 atVID. Underthese
conditions, reading the data output will yield 01h if
the block defined by the inputs on A12-A15 is
protected. Any attempt to programor erase a pro-
tected block will be ignored by the device.
DEVICE OPERATIONS
See Tables 4, 5 and 6.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register or the BlockProtection
Status. Both Chip Enable E and Output Enable G
must be low in order to read the output of the
memory.
Write. Writeoperationsare usedto giveInstruction
Commands to the memory or to latch input data to
be programmed.Awrite operationis initiatedwhen
Chip Enable E is Low and Write Enable W is Low
withOutput Enable G High. Addressesare latched
on the fallingedge of W or E whicheveroccurs last.
CommandsandInputDataarelatchedontherising
edge of W or E whichever occurs first.
6/30
M29F100T, M29F100B
Table 4. User Bus Operations (1)
DQ15
A–1
DQ8-
DQ14
Operation
Read Word
Read Byte
Write Word
Write Byte
E
G
W
RP
VIH
VIH
VIH
VIH
BYTE
VIH
A0
A0
A0
A0
A0
A1
A1
A1
A1
A1
A6
A6
A6
A6
A6
A9
A9
A9
A9
A9
A12 A15
A12 A15
A12 A15
DQ0-DQ7
Data
Output
Data
Output
Data
Output
VIL
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIL
VIL
Address
Input
Data
Output
VIL
Hi-Z
Data
Input
VIH
A12 A15 Data Input Data Input
Address
Data
Input
VIL
A12 A15
Hi-Z
Input
Hi-Z
Hi-Z
Hi-Z
Output Disable
Standby
VIL
VIH
X
VIH
X
VIH
X
VIH
VIH
VIL
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Reset
X
X
Block
VIL
VID
VID VIL Pulse VIH
VID VIL Pulse VIH
X
X
X
X
X
X
X
X
VID
VID
X
X
X
X
X
X
X
X
Protection(2,4)
Blocks
VIH
VIH
Unprotection(4)
Block
Block
Protect
Status (3)
Protection
VIL
VIL
X
VIL
VIL
X
VIH
VIH
X
VIH
VIH
VID
X
X
X
VIL
VIL
X
VIH
VIH
X
VIL
VIH
X
VID
VID
X
A12 A15
A12 A15
X
X
X
X
X
X
Verify(2,4)
Block
Block
Protect
Status (3)
Unprotection
Verify(2,4)
Block
Temporary
X
X
X
Unprotection
Notes: 1. X = VIL or VIH
2. Block Address must be given on A12-A15 bits.
3. See Table 6.
4. Operation performed on programming equipment.
Table 5. Read Electronic Signature (following AS instruction or with A9 = VID)
Other
Addresses A–1
DQ15
DQ8 -
DQ14
DQ0 -
DQ7
Org.
Code
Device
E
G
W
BYTE
A0
A1
Manufact.
Code
VIL
VIL
VIH
VIH
VIL
VIL
Don’t Care
0
00h
20h
Word-
wide
M29F100T VIL
M29F100B VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIL
Don’t Care
Don’t Care
0
0
00h
00h
D0h
D1h
Device
Code
Manufact.
Code
Don’t
Care
VIL
M29F100T VIL
M29F100B VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIL
Don’t Care
Don’t Care
Don’t Care
Hi-Z
Hi-Z
Hi-Z
20h
D0h
D1h
Byte-
wide
Don’t
Care
Device
Code
Don’t
Care
Table 6. Read Block Protection with AS Instruction
Other
Code
E
G
W
A0
A1
A12 - A15
DQ0 - DQ7
Addresses
Don’t Care
Don’t Care
Protected Block
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH
Block Address
Block Address
01h
00h
Unprotected Block
7/30
M29F100T, M29F100B
Block Temporary Unprotection. Any previously
protected block can be temporarily unprotected in
orderto changestoreddata. Thetemporaryunpro-
tection mode is activated by bringing RP to VID.
During the temporary unprotection mode the pre-
viously protected blocks are unprotected. A block
can be selected and data can be modified by
executingthe Eraseor Programinstructionwith the
RP signal held at VID. When RP is returnedto VIH,
all the previously protected blocks are again pro-
tected.
Any read attempt during Program or Erase com-
mand executionwill automaticallyoutput thesefive
StatusRegisterbits. The P/E.C.automatically sets
bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits
(DQ0, DQ1 and DQ4) are reserved for future use
and should be masked. See Tables 9 and 10.
Data Polling Bit (DQ7). When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com-
pletionof the operation,DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourth W pulse for programmingor
after the sixth W pulse for erase. It must be per-
formed at the address being programmed or at an
address within the block being erased. If all the
blocks selectedfor erasureare protected,DQ7 will
be set to ’0’for about 100µs, and then return to the
previous addressed memory data value. See Fig-
ure 11for the Data Polling flowchart and Figure 10
for the Data Polling waveforms. DQ7 will also flag
the Erase Suspend mode by switching from ’0’ to
’1’ at the start of the Erase Suspend. In order to
monitor DQ7 in the Erase Suspend mode an ad-
dress within a block being erased must be pro-
vided. For a Read Operation in Erase Suspend
mode, DQ7 will output ’1’ if the read is attempted
on ablockbeing erasedandthe datavalueon other
blocks. During Program operation in Erase Sus-
pend Mode, DQ7 will have the same behaviour as
in the normal program execution outside of the
suspend mode.
Block Unprotection. All protected blocks can be
unprotected on programming equipment to allow
updating of bit contents. All blocks must first be
protectedbefore the unprotectionoperation.Block
unprotectionis activated when A9, G and E are at
VID and A12, A15 at VIH. The Block Unprotection
algorithm is shown in Figure 15. Unprotection is
initiatedby theedgeofWfallingto V .Aftera delay
IL
of 10ms, the unprotection operation will end. Un-
protectionverify is achievedby bringingG and E to
VIL while A0 is at VIL, A6 and A1 are at VIH andA9
remains at VID. In these conditions, reading the
outputdata willyield 00h if theblock definedby the
inputs A12-A15has been succesfullyunprotected.
Eachblock mustbe separatelyverified bygivingits
address in order to ensure that it has beenunpro-
tected.
INSTRUCTIONS AND COMMANDS
The Command Interface latches commands writ-
ten to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read ElectronicSignature,Read Block Pro-
tection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
made of address and data sequences. The in-
structionsrequirefrom 1 to6 cycles,the first or first
three of which are alwayswrite operationsused to
initiate the instruction. They are followed by either
further write cycles toconfirm the first command or
executethe command immediately. Commandse-
quencing must be followed exactly. Any invalid
combination of commands will reset the device to
Read Array. The increased number of cycles has
been chosen to assure maximum data security.
Instructions are initialised by two initial Coded cy-
cleswhich unlock the CommandInterface.In addi-
tion, for Erase, instruction confirmation is again
preceded by the two Coded cycles.
Table 7. Commands
Hex Code
00h
Command
Invalid/Reserved
10h
Chip Erase Confirm
Reserved
20h
30h
Block Erase Resume/Confirm
Set-up Erase
80h
Read Electronic Signature/
Block Protection Status
90h
A0h
B0h
F0h
Program
Status Register Bits
Erase Suspend
Read Array/Reset
P/E.C. statusis indicatedduring executionbyData
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
8/30
M29F100T, M29F100B
Table 8. Instructions (1)
Mne.
Instr.
Cyc.
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.
Addr. (3,7)
Data
X
1+
Read Memory Array until a new writecycle is initiated.
F0h
Read/Reset
MemoryArray
RD (2,4)
Byte
AAAAh
5555h
AAh
5555h
2AAAh
55h
AAAAh
5555h
F0h
Addr. (3,7)
Read Memory Array untila new write cycle
is initiated.
3+
3+
Word
Data
Byte
AAAAh
5555h
AAh
5555h
2AAAh
55h
AAAAh
5555h
90h
Addr. (3,7)
Read Electronic Signature or Block
Protection Status until a new write cycle is
initiated. See Note 5 and 6.
AS (4)
Auto Select
Program
Word
Data
Byte
AAAAh
5555h
5555h
2AAAh
AAAAh
5555h
Program
Address
Addr. (3,7)
Read Data Polling or Toggle Bit
until Program completes.
PG
4
Word
Program
Data
Data
AAh
55h
A0h
Byte
AAAAh
5555h
AAh
AAAAh
5555h
AAh
X
5555h
2AAAh
55h
AAAAh
5555h
80h
AAAAh
5555h
AAh
5555h
2AAAh
55h
Block
Additional
Addr. (3,7)
Address Block (8)
BE
CE
Block Erase
Chip Erase
6
6
Word
Data
30h
AAAAh
5555h
10h
30h
Byte
5555h
2AAAh
55h
AAAAh
5555h
80h
AAAAh
5555h
AAh
5555h
2AAAh
55h
Addr. (3,7)
Note 9
Word
Data
Addr. (3,7)
Data
Erase
Suspend
Read until Toggle stops, then read all the data needed from any
Block(s) not being erased then Resume Erase.
ES (10)
1
1
B0h
Addr. (3,7)
Data
X
Erase
Resume
Read Data Polling or ToggleBits until Erase completes or Erase is
suspended another time
ER
30h
Notes: 1. Commands not interpreted in this table will default to read array mode.
2. Await of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode
before starting any new operation (see Table 14 and Figure 9).
3. X = Don’t Care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after
the command cycles.
5. Signature Address bits A0,A1 at VIL willoutput Manufacturer code (20h). Address bits A0 at VIH and A1 at VIL will output
Device code.
6. Block Protection Address: A0 at VIL, A1 at VIH and A12-A15 within the Block will output the Block Protection status.
7. For Coded cycles address inputs A15 is don’t care.
8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry,
timeout status can be verified through DQ3 value (see Erase Timer Bit DQ3 description).
When full command is entered, read Data Polling or Togglebit until Erase is completed or suspended.
9. Read Data Polling, Toggle bits or RB until Erase completes.
10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
9/30
M29F100T, M29F100B
Table 9. Status Register Bits
DQ
Name
Logic Level
Definition
Note
Erase Complete or erase
block in Erase Suspend
’1’
’0’
Indicates the P/E.C. status, check during
Program or Erase, and on completion
before checking bits DQ5 for Program or
Erase Success.
Erase On-going
Data
Polling
7
Program Complete or data
of non erase block during
Erase Suspend
DQ
DQ
Program On-going
’-1-0-1-0-1-0-1-’ Erase or Program On-going
Successive reads output complementary
data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed or Erase Suspend is
DQ
Program Complete
6
Toggle Bit
Erase Complete or Erase
’-1-1-1-1-1-1-1-’ Suspend on currently
addressed block
acknowledged.
’1’
’0’
Program or Erase Error
This bit is set to ’1’ in the case of
Programming or Erase failure.
5
4
Error Bit
Program or Erase On-going
Reserved
P/E.C. Erase operation has started. Only
possible command entry is Erase Suspend
(ES).
’1’
’0’
Erase Timeout Period Expired
Erase
Time Bit
3
Erase Timeout Period
On-going
An additional block to be erased in parallel
can be entered to the P/E.C.
Chip Erase, Erase or Erase
Suspend on the currently
addressed block.
Erase Error due to the
currently addressed block
(when DQ5 = ’1’).
’-1-0-1-0-1-0-1-’
Indicates the erase status and allows to
identify the erased block
2
Toggle Bit
Program on-going, Erase
on-going on another block or
Erase Complete
1
Erase Suspend read on
non Erase Suspend block
DQ
1
0
Reserved
Reserved
Notes: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
Toggle Bit (DQ6). WhenProgramming or Erasing
operationsare in progress,successiveattemptsto
readDQ6willoutputcomplementarydata. DQ6will
toggle following toggling of either G, or E when G
is low. The operationis completed when two suc-
cessivereads yieldthe same output data.Thenext
readwill outputthe bitlastprogrammedora ’1’after
erasing. The toggle bit DQ6 is valid only during
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the blocks selected for erasure are pro-
tected, DQ6 will toggle for about 100 s and then
µ
returnback toRead. DQ6will be setto ’1’if a Read
operationis attemptedon an EraseSuspendblock.
When erase is suspended DQ6 will toggle during
programming operations in a blockdifferent to the
block in Erase Suspend.Either E or G toggling will
cause DQ6 to toggle. See Figure 12 for Toggle Bit
flowchart and Figure 13 for ToggleBit waveforms.
10/30
M29F100T, M29F100B
Table 10. Polling and Toggle Bits
During the second cycle the Coded cycles consist
of writing the data 55h at address 5555h in the
Byte-wide configuration and at address 2AAAh in
theWord-wideconfiguration.In the Byte-widecon-
figurationthe addresslines A–1 to A14are valid,in
Word-wideA0 to A14 arevalid, other addresslines
are ’don’t care’. The Coded cycles happen on first
and second cycles of the command write or on the
fourth and fifth cycles.
Mode
DQ7
DQ7
0
DQ6
DQ2
Program
Erase
Toggle
1
Toggle Note 1
Erase Suspend Read
(in Erase Suspend
block)
1
1
Toggle
Instructions
See Table 8.
Erase Suspend Read
(outside Erase Suspend
block)
DQ7
DQ7
DQ6
DQ2
N/A
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
commandF0h. It can be optionallyprecededby the
twoCodedcycles.Subsequentreadoperationswill
read the memory array addressed and output the
data read. A wait state of 10µs is necessary after
Read/Reset prior to any valid read if the memory
was in an Erase mode when the RD instruction is
given.
Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address AAAAh
in the Byte-wide configurationor address5555hin
the Word-wide configuration for command set-up.
A subsequent read will output the manufacturer
code and the device code or the block protection
status depending on the levels of A0 and A1. The
manufacturer code, 20h, is output when the ad-
dresseslines A0 and A1 are Low,the device code,
D0h for Top Boot, D1h for Bottom Boot is output
when A0 is High with A1 Low.
Erase Suspend Program
Toggle
Note: 1. Toggle if the address is within a block being erased.
’1’ if the address is within a block not being erased.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
duringthe Erase operations.It can also be usedto
identify the block being erased. During Erase or
Erase Suspend a read from a block being erased
will cause DQ2 to toggle. A read from a block not
being erased will set DQ2 to ’1’ during erase and
to DQ2 during Erase Suspend. During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being erased. DQ2 will be set to ’1’
during program operationand when erase is com-
plete. After erase completion and if the error bit
DQ5 is set to ’1’, DQ2 will toggle if the faulty block
is addressed.
Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that results in invalid data in
thememoryblock.In caseof anerrorin blockerase
or program,the block in whichthe error occured or
to which the programmed data belongs, must be
discarded. The DQ5 failure condition will also ap-
pear if a usertries to programa ’1’ toa locationthat
is previously programmedto ’0’. OtherBlocksmay
stillbe used.Theerrorbit resetsaftera Read/Reset
(RD) instruction. In case of success of Program or
Erase, the error bit will be set to ’0’ .
The AS instruction also allows access to the block
protectionstatus.After givingtheASinstruction,A0
is set to VIL with A1 at VIH, while A12-A15 define
the address of the block to be verified. A read in
these conditions will output a 01h if the block is
protectedand a 00h if the block is not protected.
Program (PG) Instruction. This instruction uses
four write cycles. Both for Byte-wide configuration
and for Word-wide configuration. The Program
command A0h is written to address AAAAh in the
Byte-wideconfigurationor to address 5555h in the
Word-wideconfigurationonthe thirdcycle aftertwo
Coded cycles. A fourth write operation latches the
Addresson the falling edge of W or E and the Data
to be written on the rising edge and starts the
P/E.C.Read operationsoutput the StatusRegister
bits after the programming has started. Memory
programming is made only by writing ’0’ in place of
’1’.StatusbitsDQ6 and DQ7determineif program-
mingis on-goingand DQ5allowsverificationof any
possible error. Programming at an address not in
blocks being erased is also possible during erase
suspend. In this case, DQ2 will toggle at the ad-
dress being programmed.
Erase Timer Bit (DQ3). This bit is set to ’0’ by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
periodis finished,after 80µs to120µs, DQ3returns
to ’1’.
Coded Cycles
The two Coded cycles unlock the Command Inter-
face. They are followed by an input command or a
confirmation command. The Coded cycles consist
of writing the data AAh at address AAAAh in the
Byte-wide configuration and at address 5555h in
the Word-wide configuration during the first cycle.
11/30
M29F100T, M29F100B
Table 11. AC MeasurementConditions
High Speed
10ns
Standard
10ns
Input Rise and Fall Times
≤
≤
Input Pulse Voltages
0 to 3V
1.5V
0.45V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 4. AC Testing Input Output Waveform
Figure 5. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.45V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01275B
AI01276B
Table 12. Capacitance(1) (T = 25 C, f = 1 MHz )
°
A
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
6
Unit
pF
COUT
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to addressAAAAh
in the Byte-wideconfiguration or address5555h in
theWord-wideconfigurationon thirdcycleafter the
two Coded cycles. The Block Erase Confirm com-
mand30h is similarlywritten onthe sixthcycleafter
another two Coded cycles. During the input of the
secondcommandan addresswithinthe blockto be
erasedis given and latchedinto the memory.Addi-
tional block Erase Confirm commands and block
addresses can be written subsequently to erase
other blocks in parallel, without further Coded cy-
cles. The erase will start after the erase timeout
period (see Erase Timer Bit DQ3 description).
Thus, additional Erase Confirm commands for
other blocks must be given within this delay. The
input of a new Erase Confirm commandwill restart
the timeout period. The status of the internal timer
can be monitoredthrough the level of DQ3,if DQ3
is ’0’ the Block Erase Command has been given
andthe timeoutis running,if DQ3is ’1’, the timeout
has expired and the P/E.C. is erasingthe Block(s).
If the second command given is not an erase
confirm or if the Coded cycles are wrong, the
instruction aborts, and the device is reset to Read
Array. It is not necessary toprogram the block with
00h as the P/E.C. will do this automaticallybefore
to erasing to FFh. Read operations after the sixth
rising edge of W or E output the status register
status bits.
12/30
M29F100T, M29F100B
Table 13. DC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 10%)
Symbol
ILI
Parameter
Test Condition
0V ≤ VIN ≤ VCC
Min
Max
±1
±1
20
Unit
µA
Input Leakage Current
ILO
Output Leakage Current
0V ≤ VOUT ≤ VCC
µA
ICC1
ICC1
ICC2
ICC3
Supply Current (Read) TTL Byte
Supply Current (Read) TTL Word
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
E = VIL, G = VIH, f = 6MHz
E = VIL, G = VIH, f = 6MHz
E = VIH
mA
mA
mA
20
1
E = VCC 0.2V
100
A
µ
±
Byte program, Block or
Chip Erase in progress
(1)
ICC4
Supply Current (Program or Erase)
20
mA
VIL
VIH
VOL
Input Low Voltage
–0.5
2
0.8
VCC + 0.5
0.45
V
V
V
V
V
V
Input High Voltage
Output Low Voltage
IOL = 5.8mA
Output High Voltage TTL
Output High Voltage CMOS
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
IOH = –2.5mA
2.4
VCC –0.4V
11.0
VOH
IOH = –100 A
µ
VID
IID
12.0
100
A9 = VID
A
µ
Supply Voltage(Erase and
Program lock-out)
VLKO
3.2
4.2
V
Note: 1. Sampled only, not 100% tested.
Duringthe executionof theeraseby theP/E.C.,the
memory accepts onlythe Erase Suspend ES and
Read/Reset RD instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The Toggle bit DQ2 and
DQ6 toggle during the erase operation. They stop
when erase is completed. After completion the
StatusRegisterbit DQ5returns’1’ iftherehas been
an erase failure. In such a situation, the Toggle bit
DQ2 can be used to determine which block is not
correctly erased. In the case of erase failure, a
Read/ResetRDinstruction is necessaryin orderto
reset the P/E.C.
configurationon the thirdcycleafter the two Coded
cycles. The Chip Erase Confirm command 10h is
similarly writtenon thesixth cycleafter anothertwo
Coded cycles. If the secondcommand given is not
an erase confirm or if the Codedcyclesare wrong,
the instruction aborts and the device is reset to
ReadArray.It is notnecessaryto programthearray
with00h firstas theP/E.C.will automaticallydo this
before erasing it to FFh. Read operationsafter the
sixth rising edge of W or E output the Status
Registerbits. Duringthe executionof the erase by
theP/E.C.,Data Polling bitDQ7 returns’0’, then’1’
on completion. The Toggle bits DQ2 and DQ6
toggleduring eraseoperationand stopwhen erase
is completed. After completion the StatusRegister
bit DQ5 returns ’1’ if there has been an Erase
Failure.
ChipErase(CE)Instruction.Thisinstructionuses
six write cycles. The Erase Set-up command 80h
is written to address AAAAh in the Byte-wide con-
figuration or the address 5555h in the Word-wide
13/30
M29F100T, M29F100B
Table 14. Read AC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F100T / M29F100B
-90
-70
-120
Symbol
Alt
Parameter
Test Condition
Unit
VCC = 5V ± 5% VCC = 5V ± 10% VCC = 5V ± 10%
High Speed
Interface
Standard
Interface
Standard
Interface
Min
Max
Min
Max
Min
Max
Address Valid to
tAVAV
tRC
tACC
tLZ
E = VIL, G = VIL
E = VIL, G = VIL
G = VIL
70
90
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Next Address Valid
Address Valid to
Output Valid
tAVQV
70
90
90
35
20
20
10
120
Chip Enable Low to
Output Transition
(1)
tELQX
0
0
0
0
0
0
0
Chip Enable Low to
Output Valid
(2)
tELQV
tCE
tOLZ
tOE
tOH
tHZ
G = VIL
70
30
20
20
10
120
50
30
30
10
Output Enable Low
to Output Transition
(1)
tGLQX
E = VIL
0
0
Output Enable Low
to Output Valid
(2)
tGLQV
E = VIL
Chip Enable High to
Output Transition
tEHQX
G = VIL
0
0
Chip Enable High to
Output Hi-Z
(1)
tEHQZ
G = VIL
Output Enable High
to Output Transition
tGHQX
tOH
tDF
E = VIL
0
0
Output Enable High
to Output Hi-Z
(1)
tGHQZ
E = VIL
Address Transition to
Output Transition
tAXQX
tOH
E = VIL, G = VIL
0
0
tRRB RP Low to Read
tREADY Mode
(1,3)
tPLYH
s
µ
RP High to Chip
tRH
tPHEL
tPLPX
50
50
50
ns
ns
Enable Low
tRP RP Pulse Width
500
500
500
Chip Enable to BYTE
tELBL
tELBH
tELFL
Switching Low or
5
5
5
ns
ns
ns
tELFH
High
BYTE Switching Low
tFLQZ to Output
High Z
tBLQZ
30
30
40
40
40
40
BYTE Switching
High to Output
Valid
tBHQV
tFHQV
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV afterthe falling edge of E without increasing tELQV
3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.
.
14/30
M29F100T, M29F100B
Figure 6. Read Mode AC Waveforms
15/30
M29F100T, M29F100B
Table 15. Write AC Characteristics,Write Enable Controlled
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F100T / M29F100B
-90
-70
-120
Symbol
Alt
Parameter
Unit
VCC = 5V 5% VCC = 5V 10% V = 5V 10%
±
±
±
CC
High Speed
Interface
Standard
Interface
Standard
Interface
Min
Max
Min
Max
Min
Max
tAVAV
tWC Address Validto Next Address Valid
70
90
0
120
0
ns
ns
Chip Enable Low to Write Enable
tELWL
tCS
0
Low
Write Enable Low to Write Enable
tWLWH
tDVWH
tWHDX
tWP
35
30
0
45
45
0
50
50
0
ns
ns
ns
High
tDS Input Valid to Write Enable High
Write Enable High to Input
Transition
tDH
Write Enable High to Chip Enable
High
tWHEH
tCH
0
0
0
ns
Write Enable High to Write Enable
tWHWL
tAVWL
tWLAX
tWPH
Low
20
0
20
0
20
0
ns
ns
ns
tAS Address Valid to Write Enable Low
Write Enable Low to Address
Transition
tAH
45
45
50
Output Enable High to Write
Enable Low
tGHWL
tVCHEL
tWHGL
0
50
0
0
50
0
0
50
0
ns
tVCS VCC High to Chip Enable Low
s
µ
Write Enable High to Output
Enable Low
tOEH
ns
(1,2)
tPHPHH
tPLPX
tVIDR RP Rise Timeto VID
500
500
500
500
500
500
ns
ns
ns
µs
tRP RP Pulse Width
(1)
tWHRL
tPHWL
tBUSY Program Erase Valid to RB Delay
tRSP RP High to Write Enable Low
30
35
50
(1)
4
4
4
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotectionoperation.
Erase Suspend (ES) Instruction. The Block
Eraseoperationmay be suspendedbythis instruc-
tion which consists of writing the command B0h
without any specific address. No Codedcycles are
required. It permits reading of data from another
block and programming in another block while an
erase operation is in progress. Erase suspend is
accepted only during the Block Erase instruction
execution. Writing this command during Erase
timeout will, in addition to suspending the erase,
terminate the timeout. The Toggle bit DQ6 stops
togglingwhen theP/E.C.is suspended.TheToggle
bitswill stoptogglingbetween0.1µs and 15µs after
the Erase Suspend (ES) command has been writ-
ten. The device will then automatically be set to
Read Memory Array mode. When erase is sus-
pended, a Read from blocks being erased will
output DQ2 toggling and DQ6 at ’1’. A Read from
16/30
M29F100T, M29F100B
Figure 7. Write AC Waveforms, W Controlled
tAVAV
VALID
A0-A15/
A–1
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHEL
RB
tWHRL
AI01980B
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
a blocknot being erasedreturnsvalid data. During
suspension the memory will respond only to the
Erase Resume ER and the Program PG instruc-
tions. A Program operation can be initiated during
erase suspend in one of the blocks not being
erased. It will result in both DQ2 and DQ6 toggling
whenthedatais beingprogrammed.ARead/Reset
command will definitively abort erasure and result
in invalid data in the blocks being erased.
POWER SUPPLY
Power Up
ThememoryCommandInterfaceis reset onpower
up to Read Array. Either E or W must be tied to VIH
during Power Up to allow maximum security and
thepossibility to writea commandon the first rising
edge of E and W. Any write cycle initiation is
blocked when Vcc is below VLKO
.
EraseResume(ER)Instruction. Ifan EraseSus-
pend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at any address, and without any
Coded cycles.
Supply Rails
Normal precautionsmust be taken for supply volt-
age decoupling; each device in a system should
havethe VCC rail decoupledwith a 0.1µF capacitor
close to the VCC and VSS pins. The PCB trace
widths should be sufficient to carry the VCC pro-
gram and erase currents required.
17/30
M29F100T, M29F100B
Table 16. Write AC Characteristics,Chip Enable Controlled
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F100T / M29F100B
-90
-70
-120
Symbol
Alt
Parameter
Unit
VCC = 5V 5% VCC = 5V 10% V = 5V 10%
±
±
±
CC
High Speed
Interface
Standard
Interface
Standard
Interface
Min
Max
Min
Max
Min
Max
Address Valid to Next Address
Valid
tAVAV
tWC
tWS
70
90
0
120
0
ns
ns
Write Enable Low to Chip
Enable Low
tWLEL
0
Chip Enable Low to Chip Enable
High
tELEH
tDVEH
tEHDX
tCP
tDS
tDH
35
30
0
45
45
0
50
50
0
ns
ns
ns
Input Valid to Chip Enable High
Chip Enable High to Input
Transition
Chip Enable High to Write
Enable High
tEHWH
tEHEL
tAVEL
tELAX
tWH
tCPH
tAS
0
20
0
0
20
0
0
20
0
ns
ns
ns
ns
Chip Enable High to Chip
Enable Low
Address Valid to Chip Enable
Low
Chip Enable Low to Address
Transition
tAH
45
45
50
Output Enable High Chip
Enable Low
tGHEL
tVCHWL
tEHGL
0
50
0
0
50
0
0
50
0
ns
µs
ns
tVCS
tOEH
VCC High to Write Enable Low
Chip Enable High to Output
Enable Low
(1,2)
tPHPHH
tVIDR
tRP
RP Rise TIme to VID
RP Pulse Width
500
500
500
500
500
500
ns
ns
tPLPX
Program Erase Valid to RB
Delay
(1)
tEHRL
tBUSY
tRSP
30
35
50
ns
(1)
tPHWL
RP High to Write Enable Low
4
4
4
s
µ
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotectionoperation.
18/30
M29F100T, M29F100B
Figure 8. Write AC Waveforms, E Controlled
tAVAV
VALID
A0-A15/
A–1
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHWL
RB
tEHRL
AI01981B
Note: Address are latched on the fallingedge of E, Data is latchedon the rising edge of E.
Figure 9. Read and Write AC Characteristics, RP Related
E
tPHEL
W
tPHWL
RB
tPLPX
RP
tPHPHH
tPLYH
AI02091
19/30
M29F100T, M29F100B
Table 17. Data Polling and Toggle Bit AC Characteristics(1)
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F100T / M29F100B
-90
-70
-120
Symbol
Parameter
Unit
VCC = 5V 5%
VCC = 5V 10%
VCC = 5V 10%
±
±
±
High Speed
Interface
Standard
Interface
Standard
Interface
Min
Max
Min
Max
Min
Max
Write Enable High to DQ7 Valid
(Program, W Controlled)
10
2400
10
2400
10
2400
s
µ
tWHQ7V
Write Enable High to DQ7 Valid
(Chip Erase, W Controlled)
1.0
10
30
2400
30
1.0
10
30
2400
30
1.0
10
30
2400
30
sec
µs
Chip Enable High to DQ7 Valid
(Program, E Controlled)
tEHQ7V
Chip Enable High to DQ7 Valid
(Chip Erase, E Controlled)
1.0
1.0
1.0
sec
ns
Q7 Validto Output Valid (Data
Polling)
tQ7VQV
30
35
50
Write Enable High to Output Valid
(Program)
10
1.0
10
2400
30
10
1.0
10
2400
30
10
1.0
10
2400
30
s
µ
tWHQV
Write Enable High to Output Valid
(Chip Erase)
sec
µs
Chip Enable High to Output Valid
(Program)
2400
30
2400
30
2400
30
tEHQV
Chip Enable High to Output Valid
(Chip Erase)
1.0
1.0
1.0
sec
Note: 1. All other timings are defined in Read AC Characteristics table.
20/30
M29F100T, M29F100B
Figure 10. DataPolling DQ7 AC Waveforms
21/30
M29F100T, M29F100B
Figure 11. DataPolling Flowchart
Figure 12. Data Toggle Flowchart
START
START
READ
DQ2, DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
NO
DQ2, DQ6
=
DQ7
=
DATA
YES
TOGGLE
NO
YES
NO
NO
DQ5
= 1
DQ5
= 1
YES
YES
READ DQ2, DQ6
READ DQ7
DQ7
=
DATA
YES
NO
DQ2, DQ6
=
TOGGLE
NO
YES
FAIL
FAIL
PASS
PASS
AI01369
AI01873
Table 18. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C; VCC = 5V ± 10% or 5V ± 5%)
M29F100T / M29F100B
Parameter
Unit
Typical after
100k W/E Cycles
Min
Typ
Chip Erase (Preprogrammed)
Chip Erase
0.4
1.5
0.6
0.5
0.9
1.0
1.4
11
0.6
1.7
sec
sec
sec
sec
sec
sec
sec
Boot Block Erase
Parameter Block Erase
Main Block (32Kb) Erase
Main Block (64Kb) Erase
Chip Program (Byte)
Byte Program
1.4
11
20
s
s
µ
µ
Word Program
20
Program/Erase Cycles (per Block)
100,000
cycles
22/30
M29F100T, M29F100B
Figure 13. DataToggle DQ6, DQ2 AC Waveforms
23/30
M29F100T, M29F100B
Figure 14. Block Protection Flowchart
START
BLOCK ADDRESS
on A12-A15
W = V
IH
Set-up
n = 0
G, A9 = V
E = V
,
ID
IL
Wait 4µs
W = V
IL
Protect
Verify
Wait 100µs
W = V
IH
E, G = V
IH
VERIFY BLOCK PROTECTION
A0, A6 = V ; A1 = V ; A9 = V
ID
IL
IH
A12-A15 IDENTIFY BLOCK
E = V
IL
Wait 4µs
G = V
IL
Wait 60ns
VERIFY BLOCK
PROTECT STATUS
NO
DATA
=
01h
YES
A9 = V
IH
++n
NO
= 25
PASS
YES
A9 = V
IH
FAIL
AI01984C
24/30
M29F100T, M29F100B
Figure 15. All Blocks Unprotecting Flowchart
START
PROTECT
ALL BLOCKS
n = 0
Set-up
W = V
IH
E, G, A9 = V
ID
A12, A15 = V
IH
Wait 4µs
W = V
IL
Wait 10ms
Unprotect
Verify
W = V
IH
E, G = V
IH
E, A0 = V ; A1, A6 = V ; A9 = V
ID
IL
IH
A12-A15 IDENTIFY BLOCK
NEXT
BLOCK
Wait 4µs
G = V
IL
Wait 60ns
VERIFY BLOCK
PROTECT STATUS
NO
YES
DATA
=
00h
NO
++n
= 1000
LAST
BLK.
NO
YES
YES
A9 = V
IH
A9 = V
IH
FAIL
PASS
AI01985D
25/30
M29F100T, M29F100B
ORDERING INFORMATION SCHEME
Example:
M29F100T
-70
X
N
1
TR
Operating Voltage
Option
F
5V
R
Reverse
Pinout
TR Tape & Reel
Packing
Array Matrix
Top Boot
Speed
-70 70ns
Power Supplies
blank VCC 10%
Package
Temp. Range
T
B
N
TSOP48
12 x 20mm
1
6
3
0 to 70 C
°
±
Bottom Boot
-90 90ns
X
VCC 5%
–40 to 85 C
°
±
M
SO44
-120 120ns
–40 to 125 C
°
Devices are shipped from the factory with the memory content erased (to FFh).
Fora list ofavailableoptions(Speed, Package,etc...)or for furtherinformationon anyaspect of thisdevice,
please contact the STMicroelectronics Sales Office nearest to you.
26/30
M29F100T, M29F100B
TSOP48 Normal Pinout - 48 lead Plastic Thin Small Outline, 12 x 20mm
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
12.10
-
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.795
0.728
0.476
-
A
A1
A2
B
0.05
0.95
0.17
0.10
19.80
18.30
11.90
-
0.002
0.037
0.007
0.004
0.780
0.720
0.469
-
C
D
D1
E
e
0.50
0.020
L
0.50
0.70
0.020
0.028
0
°
5
°
0
°
5
°
α
N
48
48
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale.
27/30
M29F100T, M29F100B
TSOP48 Reverse Pinout - 48 lead Plastic Thin Small Outline, 12 x 20mm
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
12.10
–
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.795
0.728
0.476
–
A
A1
A2
B
0.05
0.95
0.17
0.10
19.80
18.30
11.90
–
0.002
0.037
0.007
0.004
0.780
0.720
0.469
–
C
D
D1
E
e
0.50
0.020
L
0.50
0.70
0.020
0.028
0
°
5
°
0
°
5
°
α
N
48
48
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-b
A1
α
L
Drawing is not to scale.
28/30
M29F100T, M29F100B
SO44 - 44 lead Plastic Small Outline, 525 mils body width
mm
Min
2.42
0.22
2.25
inches
Min
Symb
Typ
Max
2.62
0.23
2.35
0.50
0.25
28.30
13.40
Typ
Max
0.103
0.010
0.093
0.020
0.010
1.114
0.528
A
A1
A2
B
0.095
0.009
0.089
C
0.10
28.10
13.20
0.004
1.106
0.520
D
E
e
1.27
0.80
0.050
0.031
H
15.90
44
16.10
0.626
44
0.634
L
3
°
3
α
°
N
CP
0.10
0.004
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Drawing is not to scale.
29/30
M29F100T, M29F100B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implicationor otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1998 STMicroelectronics - All Rights Reserved
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30/30
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