M28W640FCB90ZB6T [STMICROELECTRONICS]
4MX16 FLASH 3V PROM, 90ns, PBGA48, 6.39 X 10.50 MM, 0.75 PITCH, TFBGA-48;
| 型号： | M28W640FCB90ZB6T |
| 厂家： | 
ST |
| 描述： | 4MX16 FLASH 3V PROM, 90ns, PBGA48, 6.39 X 10.50 MM, 0.75 PITCH, TFBGA-48 闪存 存储 内存集成电路 |
| 文件： | 总77页 (文件大小：531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M28W640FCT
M28W640FCB
64 Mbit (4Mbx16, Boot Block)
3V Supply Flash memory
Feature summary
■ Supply voltage
– V = 2.7V to 3.6V Core Power Supply
DD
FBGA
– V
= 1.65V to 3.6V for Input/Output
DDQ
– V = 12V for fast Program (optional)
PP
■ Access times: 70, 85, 90,100ns
TFBGA48 (ZB)
6.39 x 10.5mm
■ Programming time:
– 10µs typical
– Double Word Programming Option
– Quadruple Word Programming Option
■ Common Flash Interface
■ Memory blocks
– Parameter Blocks (Top or Bottom location)
– Main Blocks
TSOP48 (N)
12 x 20mm
■ Block locking
– All blocks locked at Power Up
– Any combination of blocks can be locked
– WP for Block Lock-Down
■ Packages
– ECOPACK® compliant
■ Security
– 128 bit user Programmable OTP cells
– 64 bit unique device identifier
■ Automatic standby mode
■ Program and Erase Suspend
■ 100,000 program/erase cycles per block
■ Electronic signature
– Manufacturer code: 20h
– Top device code, M28W640FCT: 8848h
– Bottom device code, M28W640FCB: 8849h
October 2006
Rev 3
1/77
www.st.com
1
Contents
M28W640FCT, M28W640FCB
Contents
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
Address inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Input/Output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
V
DDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PP Program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
V
2.11 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
3.2
3.3
3.4
3.5
3.6
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/77
M28W640FCT, M28W640FCB
Contents
4.9
Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.10 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.11 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.12 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.13 Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.14 Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.15 Block Lock-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
5.2
5.3
5.4
5.5
Reading a Block’s Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Lock-Down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Locking Operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . 28
6
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Program/Erase Controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Erase Suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Program status (bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
VPP status (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Program Suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Block Protection status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Reserved (bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8
9
10
Appendix A Block address tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3/77
Contents
M28W640FCT, M28W640FCB
Appendix C Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Appendix D Command Interface and Program/Erase Controller State . . . . . . . 72
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4/77
M28W640FCT, M28W640FCB
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Read Electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Block Lock signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Program, Erase Times and Program/Erase endurance cycles. . . . . . . . . . . . . . . . . . . . . . 26
Block Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Protection status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Write AC characteristics, Write enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Write AC characteristics, Chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Power-Up and Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data. . . . 44
TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, package mechanical data . . . . . 45
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Daisy Chain ordering scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Top Boot Block Addresses, M28W640FCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Bottom Boot Block Addresses, M28W640FCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Primary Algorithm-specific Extended Query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Write State machine Current/Next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Write State machine Current/Next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
5/77
List of figures
M28W640FCT, M28W640FCB
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Write AC waveforms, Write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 10. Write AC waveforms, Chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 11. Power-Up and Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline . . . . . . . . . . . 44
Figure 13. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, bottom view package outline . . . 45
Figure 14. TFBGA48 daisy chain - package connections (top view through package) . . . . . . . . . . . . 46
Figure 15. TFBGA48 daisy chain - PCB connections proposal (top view through package). . . . . . . . 47
Figure 16. Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 17. Double Word Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 18. Quadruple Word Program flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 19. Program Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 20. Erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 21. Erase Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 22. Locking Operations flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 23. Protection Register Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 71
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M28W640FCT, M28W640FCB
Summary description
1
Summary description
The M28W640FCT and M28W640FCB are 64 Mbit (4 Mbit x 16) non-volatile Flash
memories that can be erased electrically at block level and programmed in-system on a
Word-by-Word basis using a 2.7V to 3.6V V supply for the circuitry and a 1.65V to 3.6V
DD
V
supply for the Input/Output pins. An optional 12V V power supply is provided to
DDQ
PP
speed up customer programming.
The devices feature an asymmetrical blocked architecture. They have an array of 135
blocks: 8 Parameter Blocks of 4 KWord and 127 Main Blocks of 32 KWord. The
M28W640FCT has the Parameter Blocks at the top of the memory address space while the
M28W640FCB locates the Parameter Blocks starting from the bottom. The memory maps
are shown in Figure 4: Block addresses.
The M28W640FCT and M28W640FCB feature an instant, individual block locking scheme
that allows any block to be locked or unlocked with no latency, enabling instant code and
data protection. All blocks have three levels of protection. They can be locked and locked-
down individually preventing any accidental programming or erasure. There is an additional
hardware protection against program and erase. When V ≤V
all blocks are protected
PP
PPLK
against program or erase. All blocks are locked at Power Up.
Each block can be erased separately. Erase can be suspended in order to perform either
read or program in any other block and then resumed. Program can be suspended to read
data in any other block and then resumed. Each block can be programmed and erased over
100,000 cycles.
The device includes a 192 bit Protection Register to increase the protection of a system
design. The Protection Register is divided into a 64 bit segment and a 128 bit segment. The
64 bit segment contains a unique device number written by ST, while the second one is one-
time-programmable by the user. The user programmable segment can be permanently
protected. Figure 5, shows the Protection Register Memory Map.
Program and Erase commands are written to the Command Interface of the memory. An on-
chip Program/Erase Controller takes care of the timings necessary for program and erase
operations. The end of a program or erase operation can be detected and any error
conditions identified. The command set required to control the memory is consistent with
JEDEC standards.
The memory is offered in TSOP48 (12 × 20mm) and TFBGA48 (6.39 × 10.5mm, 0.75mm
pitch) packages and is supplied with all the bits erased (set to ’1’).
In order to meet environmental requirements, ST offers the M28W640FCT and
M28W640FCB in ECOPACK® packages. These packages have a Lead-free second level
interconnect. The category of second Level Interconnect is marked on the package and on
the inner box label, in compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
7/77
Summary description
Figure 1.
M28W640FCT, M28W640FCB
Logic diagram
V
V
V
DD DDQ PP
22
16
A0-A21
DQ0-DQ15
W
E
M28W640FCT
M28W640FCB
G
RP
WP
V
SS
AI09903
Table 1.
Signal names
Address Inputs
A0-A21
DQ0-DQ15
E
Data Input/Output
Chip Enable
G
Output Enable
Write Enable
W
RP
Reset
WP
Write Protect
VDD
VDDQ
VPP
VSS
NC
Core Power supply
Power supply for Input/Output
Optional supply voltage for Fast Program & Erase
Ground
Not Connected Internally
8/77
M28W640FCT, M28W640FCB
Summary description
Figure 2.
TSOP connections
A15
A14
A13
A12
A11
A10
A9
1
48
A16
V
V
DDQ
SS
DQ15
DQ7
DQ14
DQ6
A8
DQ13
DQ5
A21
A20
W
DQ12
DQ4
RP
12
13
37
36
V
M28W640FCT
M28W640FCB
DD
V
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
PP
WP
A19
A18
A17
A7
A6
A5
A4
A3
V
E
SSQ
A2
A1
24
25
A0
AI09904b
9/77
Summary description
Figure 3.
M28W640FCT, M28W640FCB
TFBGA connections (top view through package)
1
2
3
4
5
6
7
8
WP
A18
A20
DQ2
DQ3
A19
A17
A
B
C
D
E
F
A13
A14
A15
A16
A11
A10
A8
W
V
A7
A5
A4
A2
A1
A0
PP
RP
A12
A9
A21
A6
A3
DQ11
DQ12
DQ4
DQ14
DQ15
DQ7
DQ5
DQ6
DQ13
DQ8
DQ9
DQ10
E
V
DQ0
DQ1
V
DDQ
SSQ
V
V
SS
DD
G
AI04380b
10/77
M28W640FCT, M28W640FCB
Summary description
Figure 4.
Block addresses
M28W640FCT
Top Boot Block Addresses
M28W640FCB
Bottom Boot Block Addresses
3FFFFF
3FF000
3FFFFF
4 KWords
32 KWords
32 KWords
3F8000
3F7FFF
Total of 8
4 KWord Blocks
3F0000
Total of 127
32 KWord Blocks
3F8FFF
4 KWords
3F8000
3F7FFF
32 KWords
3F0000
00FFFF
32 KWords
4 KWords
008000
007FFF
Total of 127
007000
32 KWord Blocks
Total of 8
00FFFF
4 KWord Blocks
32 KWords
32 KWords
008000
007FFF
000FFF
000000
4 KWords
000000
AI09905
1. Also see Appendix A, Tables 24 and 25 for a full listing of the Block Addresses.
Figure 5.
Protection Register memory map
PROTECTION REGISTER
8Ch
User Programmable OTP
85h
84h
Unique device number
81h
Protection Register Lock
1
0
80h
AI05520b
11/77
Signal descriptions
M28W640FCT, M28W640FCB
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-A21)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the internal state machine.
2.2
2.3
Data Input/Output (DQ0-DQ15)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
or inputs a command or the data to be programmed during a Write Bus operation.
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at V and Reset is at V the device is in active
IL
IH
mode. When Chip Enable is at V the memory is deselected, the outputs are high
IH
impedance and the power consumption is reduced to the stand-by level.
2.4
2.5
Output Enable (G)
The Output Enable controls data outputs during the Bus Read operation of the memory.
Write Enable (W)
The Write Enable controls the Bus Write operation of the memory’s Command Interface.
The data and address inputs are latched on the rising edge of Chip Enable, E, or Write
Enable, W, whichever occurs first.
2.6
Write Protect (WP)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is at V , the Lock-Down is enabled and the protection status of the block
IL
cannot be changed. When Write Protect is at V , the Lock-Down is disabled and the block
IH
can be locked or unlocked. (refer to Table 7: Read Protection Register and Lock Register).
12/77
M28W640FCT, M28W640FCB
Signal descriptions
2.7
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at V , the
IL
memory is in reset mode: the outputs are high impedance and the current consumption is
minimized. After Reset all blocks are in the Locked state. When Reset is at V , the device is
IH
in normal operation. Exiting reset mode the device enters read array mode, but a negative
transition of Chip Enable or a change of the address is required to ensure valid data outputs.
2.8
VDD supply voltage
V
provides the power supply to the internal core of the memory device. It is the main
DD
power supply for all operations (Read, Program and Erase).
2.9
VDDQ supply voltage
V
provides the power supply to the I/O pins and enables all Outputs to be powered
DDQ
independently from V . V
can be tied to V or can use a separate supply.
DD DDQ
DD
2.10
VPP Program supply voltage
V
is both a control input and a power supply pin. The two functions are selected by the
PP
voltage range applied to the pin. The Supply Voltage V and the Program Supply Voltage
DD
V
can be applied in any order.
PP
If V is kept in a low voltage range (0V to 3.6V) V is seen as a control input. In this case
PP
PP
a voltage lower than V
gives an absolute protection against program or erase, while
PPLK
V
> V
enables these functions (see Table 15: DC characteristics, for the relevant
PP
PP1
values). V is only sampled at the beginning of a program or erase; a change in its value
PP
after the operation has started does not have any effect on Program or Erase, however for
Double or Quadruple Word Program the results are uncertain.
If V is in the range 11.4V to 12.6V it acts as a power supply pin. In this condition V must
PP
PP
be stable until the Program/Erase algorithm is completed (see Table 17 and Table 18).
2.11
VSS Ground
V
is the reference for all voltage measurements.
SS
Note: Each device in a system should have V , V
and V decoupled with a 0.1µF
PP
DD DDQ
capacitor close to the pin. See Figure 7: AC measurement load circuit. The PCB track
widths should be sufficient to carry the required V program and erase currents.
PP
13/77
Bus operations
M28W640FCT, M28W640FCB
3
Bus operations
There are six standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby, Automatic Standby and Reset. See Table 2: Bus operations,
for a summary.
Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the
memory and do not affect bus operations.
3.1
Read
Read Bus operations are used to output the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common Flash Interface. Both Chip Enable and
Output Enable must be at V in order to perform a read operation. The Chip Enable input
IL
should be used to enable the device. Output Enable should be used to gate data onto the
output. The data read depends on the previous command written to the memory (see
Command Interface section). See Figure 8: Read AC waveforms, and Table 16: Read AC
characteristics, for details of when the output becomes valid.
Read mode is the default state of the device when exiting Reset or after power-up.
3.2
Write
Bus Write operations write Commands to the memory or latch Input Data to be
programmed. A write operation is initiated when Chip Enable and Write Enable are at V
IL
with Output Enable at V . Commands, Input Data and Addresses are latched on the rising
IH
edge of Write Enable or Chip Enable, whichever occurs first.
See Figure 9 and Figure 10, Write AC Waveforms, and Table 17 and Table 18, Write AC
Characteristics, for details of the timing requirements.
3.3
3.4
Output Disable
The data outputs are high impedance when the Output Enable is at V .
IH
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in stand-by when Chip Enable is at V and the device is in
IH
read mode. The power consumption is reduced to the stand-by level and the outputs are set
to high impedance, independently from the Output Enable or Write Enable inputs. If Chip
Enable switches to V during a program or erase operation, the device enters Standby
IH
mode when finished.
14/77
M28W640FCT, M28W640FCB
Bus operations
3.5
Automatic Standby
Automatic Standby provides a low power consumption state during Read mode. Following a
read operation, the device enters Automatic Standby after 150ns of bus inactivity even if
Chip Enable is Low, V , and the supply current is reduced to I
. The data Inputs/Outputs
IL
DD1
will still output data if a bus Read operation is in progress.
3.6
Reset
During Reset mode when Output Enable is Low, V , the memory is deselected and the
IL
outputs are high impedance. The memory is in Reset mode when Reset is at V . The power
IL
consumption is reduced to the Standby level, independently from the Chip Enable, Output
Enable or Write Enable inputs. If Reset is pulled to V during a Program or Erase, this
SS
operation is aborted and the memory content is no longer valid.
(1)
Table 2.
Bus operations
Operation
E
G
W
RP
WP
VPP
DQ0-DQ15
Bus Read
Bus Write
Output Disable
Standby
VIL
VIL
VIL
VIH
X
VIL
VIH
VIH
X
VIH
VIL
VIH
X
VIH
VIH
VIH
VIH
VIL
X
X
X
X
X
Don't Care
VDD or VPPH
Don't Care
Don't Care
Don't Care
Data Output
Data Input
Hi-Z
Hi-Z
Reset
X
X
Hi-Z
1. X = VIL or VIH, VPPH = 12V ± 5%
15/77
Command interface
M28W640FCT, M28W640FCB
4
Command interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. An internal
Program/Erase Controller handles all timings and verifies the correct execution of the
Program and Erase commands. The Program/Erase Controller provides a Status Register
whose output may be read at any time during, to monitor the progress of the operation, or
the Program/Erase states. See Table 3: Command codes, for a summary of the commands
and see Appendix D, Table 32: Write State machine Current/Next, for a summary of the
Command Interface.
The Command Interface is reset to Read mode when power is first applied, when exiting
from Reset or whenever V is lower than V
. Command sequences must be followed
DD
LKO
exactly. Any invalid combination of commands will reset the device to Read mode. Refer to
Table 4: Commands, in conjunction with the text descriptions below.
4.1
4.2
Read Memory Array command
The Read command returns the memory to its Read mode. One Bus Write cycle is required
to issue the Read Memory Array command and return the memory to Read mode.
Subsequent read operations will read the addressed location and output the data. When a
device Reset occurs, the memory defaults to Read mode.
Read Status Register command
The Status Register indicates when a program or erase operation is complete and the
success or failure of the operation itself. Issue a Read Status Register command to read the
Status Register’s contents. Subsequent Bus Read operations read the Status Register at
any address, until another command is issued. See Table 11: Status Register bits, for details
on the definitions of the bits.
The Read Status Register command may be issued at any time, even during a
Program/Erase operation. Any Read attempt during a Program/Erase operation will
automatically output the content of the Status Register.
4.3
Read electronic signature command
The Read Electronic Signature command reads the Manufacturer and Device Codes and
the Block Locking Status, or the Protection Register.
The Read Electronic Signature command consists of one write cycle, a subsequent read will
output the Manufacturer Code, the Device Code, the Block Lock and Lock-Down Status, or
the Protection and Lock Register. See Tables 5, 6 and 7 for the valid address.
16/77
M28W640FCT, M28W640FCB
Command interface
Table 3.
Command codes
Hex Code
Command
01h
10h
20h
2Fh
30h
40h
50h
56h
60h
70h
90h
98h
B0h
C0h
D0h
FFh
Block Lock confirm
Program
Erase
Block Lock-Down confirm
Double Word Program
Program
Clear Status Register
Quadruple Word Program
Block Lock, Block Unlock, Block Lock-Down
Read Status Register
Read Electronic Signature
Read CFI Query
Program/Erase Suspend
Protection Register Program
Program/Erase Resume, Block Unlock confirm
Read Memory Array
4.4
Read CFI Query command
The Read Query Command is used to read data from the Common Flash Interface (CFI)
Memory Area, allowing programming equipment or applications to automatically match their
interface to the characteristics of the device. One Bus Write cycle is required to issue the
Read Query Command. Once the command is issued subsequent Bus Read operations
read from the Common Flash Interface Memory Area. See Appendix B: Common Flash
Interface (CFI), Tables 26, 27, 28, 29, 30 and 31 for details on the information contained in
the Common Flash Interface memory area.
17/77
Command interface
M28W640FCT, M28W640FCB
4.5
Block Erase command
The Block Erase command can be used to erase a block. It sets all the bits within the
selected block to ’1’. All previous data in the block is lost. If the block is protected then the
Erase operation will abort, the data in the block will not be changed and the Status Register
will output the error.
Two Bus Write cycles are required to issue the command.
■
■
The first bus cycle sets up the Erase command.
The second latches the block address in the internal state machine and starts the
Program/Erase Controller.
If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are
set and the command aborts.
Erase aborts if Reset turns to V . As data integrity cannot be guaranteed when the Erase
IL
operation is aborted, the block must be erased again.
During Erase operations the memory will accept the Read Status Register command and
the Program/Erase Suspend command, all other commands will be ignored. Typical Erase
times are given in Table 8: Program, Erase Times and Program/Erase endurance cycles.
See Appendix C, Figure 20: Erase flowchart and pseudo code, for a suggested flowchart for
using the Erase command.
4.6
Program command
The memory array can be programmed word-by-word. Two bus write cycles are required to
issue the Program Command.
■
■
The first bus cycle sets up the Program command.
The second latches the Address and the Data to be written and starts the
Program/Erase Controller.
During Program operations the memory will accept the Read Status Register command and
the Program/Erase Suspend command. Typical Program times are given in Table 8:
Program, Erase Times and Program/Erase endurance cycles.
Programming aborts if Reset goes to V . As data integrity cannot be guaranteed when the
IL
program operation is aborted, the block containing the memory location must be erased and
reprogrammed.
See Appendix C, Figure 16: Program flowchart and pseudo code, for the flowchart for using
the Program command.
18/77
M28W640FCT, M28W640FCB
Command interface
4.7
Double Word Program command
This feature is offered to improve the programming throughput, writing a page of two
adjacent words in parallel.The two words must differ only for the address A0. Programming
should not be attempted when V is not at V
.
PPH
PP
Three bus write cycles are necessary to issue the Double Word Program command.
■
■
■
The first bus cycle sets up the Double Word Program Command.
The second bus cycle latches the Address and the Data of the first word to be written.
The third bus cycle latches the Address and the Data of the second word to be written
and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
Programming aborts if Reset goes to V . As data integrity cannot be guaranteed when the
IL
program operation is aborted, the block containing the memory location must be erased and
reprogrammed.
See Appendix C, Figure 17: Double Word Program flowchart and pseudo code for the
flowchart for using the Double Word Program command.
4.8
Quadruple Word Program command
This feature is offered to improve the programming throughput, writing a page of four
adjacent words in parallel.The four words must differ only for the addresses A0 and A1.
Programming should not be attempted when V is not at V
.
PP
PPH
Five bus write cycles are necessary to issue the Quadruple Word Program command.
■
■
■
■
■
The first bus cycle sets up the Quadruple Word Program Command.
The second bus cycle latches the Address and the Data of the first word to be written.
The third bus cycle latches the Address and the Data of the second word to be written.
The fourth bus cycle latches the Address and the Data of the third word to be written.
The fifth bus cycle latches the Address and the Data of the fourth word to be written
and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
Programming aborts if Reset goes to V . As data integrity cannot be guaranteed when the
IL
program operation is aborted, the block containing the memory location must be erased and
reprogrammed.
See Appendix C, Figure 18: Quadruple Word Program flowchart and pseudo code, for the
flowchart for using the Quadruple Word Program command.
4.9
Clear Status Register command
The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status
Register to ‘0’. One bus write cycle is required to issue the Clear Status Register command.
The bits in the Status Register do not automatically return to ‘0’ when a new Program or
Erase command is issued. The error bits in the Status Register should be cleared before
attempting a new Program or Erase command.
19/77
Command interface
M28W640FCT, M28W640FCB
4.10
Program/Erase Suspend command
The Program/Erase Suspend command is used to pause a Program or Erase operation.
One bus write cycle is required to issue the Program/Erase command and pause the
Program/Erase controller.
During Program/Erase Suspend the Command Interface will accept the Program/Erase
Resume, Read Array, Read Status Register, Read Electronic Signature and Read CFI
Query commands. Additionally, if the suspend operation was Erase then the Program,
Double Word Program, Quadruple Word Program, Block Lock, Block Lock-Down or
Protection Program commands will also be accepted. The block being erased may be
protected by issuing the Block Protect, Block Lock or Protection Program commands. When
the Program/Erase Resume command is issued the operation will complete. Only the blocks
not being erased may be read or programmed correctly.
During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by
taking Chip Enable to V . Program/Erase is aborted if Reset turns to V .
IH
IL
See Appendix C, Figure 19: Program Suspend & Resume flowchart and pseudo code, and
Figure 21: Erase Suspend & Resume flowchart and pseudo code, for flowcharts for using
the Program/Erase Suspend command.
4.11
4.12
Program/Erase Resume command
The Program/Erase Resume command can be used to restart the Program/Erase Controller
after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to
issue the command. Once the command is issued subsequent Bus Read operations read
the Status Register.
See Appendix C, Figure 19: Program Suspend & Resume flowchart and pseudo code, and
Figure 21: Erase Suspend & Resume flowchart and pseudo code, for flowcharts for using
the Program/Erase Resume command.
Protection Register Program command
The Protection Register Program command is used to Program the 128 bit user One-Time-
Programmable (OTP) segment of the Protection Register. The segment is programmed 16
bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program
the bits to ‘0’.
Two write cycles are required to issue the Protection Register Program command.
■
■
The first bus cycle sets up the Protection Register Program command.
The second latches the Address and the Data to be written to the Protection Register
and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
The segment can be protected by programming bit 1 of the Protection Lock Register (see
Figure 5: Protection Register memory map). Attempting to program a previously protected
Protection Register will result in a Status Register error. The protection of the Protection
Register is not reversible.
The Protection Register Program cannot be suspended.
20/77
M28W640FCT, M28W640FCB
Command interface
4.13
Block Lock command
The Block Lock command is used to lock a block and prevent Program or Erase operations
from changing the data in it. All blocks are locked at power-up or reset.
Two Bus Write cycles are required to issue the Block Lock command.
■
■
The first bus cycle sets up the Block Lock command.
The second Bus Write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature
command. Table 10 shows the protection status after issuing a Block Lock command.
The Block Lock bits are volatile, once set they remain set until a hardware reset or power-
down/power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block
Locking, for a detailed explanation.
21/77
Command interface
M28W640FCT, M28W640FCB
4.14
Block Unlock command
The Block Unlock command is used to unlock a block, allowing the block to be programmed
or erased. Two Bus Write cycles are required to issue the Block Unlock command.
■
■
The first bus cycle sets up the Block Unlock command.
The second Bus Write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature
command. Table 10 shows the protection status after issuing a Block Unlock command.
Refer to the section, Block Locking, for a detailed explanation.
4.15
Block Lock-Down command
A locked block cannot be Programmed or Erased, or have its protection status changed
when WP is low, V . When WP is high, V the Lock-Down function is disabled and the
IL
IH,
locked blocks can be individually unlocked by the Block Unlock command.
Two Bus Write cycles are required to issue the Block Lock-Down command.
■
■
The first bus cycle sets up the Block Lock command.
The second Bus Write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature
command. Locked-Down blocks revert to the locked (and not locked-down) state when the
device is reset on power-down. Table 10 shows the protection status after issuing a Block
Lock-Down command. Refer to the section, Block Locking, for a detailed explanation.
22/77
M28W640FCT, M28W640FCB
Command interface
(1)
Table 4.
Commands
Bus Write operations
3rd Cycle
Commands
1st Cycle
2nd Cycle
4th Cycle
5th Cycle
Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data
Read Memory
Array
1+ Write
1+ Write
X
X
FFh Read RA
70h Read
RD
Read Status
Register
X
SRD
Read
Electronic
Signature
1+ Write
1+ Write
X
90h Read SA(2) IDh
98h Read QA QD
Read CFI
Query
X
X
X
Erase
2
2
Write
Write
20h Write BA D0h
40h or
Program
Write PA
PD
10h
Double Word
Program(3)
3
5
Write
Write
X
X
30h Write PA1 PD1 Write PA2 PD2
Quadruple
Word
56h Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4
Program(4)
Clear Status
Register
1
1
1
Write
Write
Write
X
X
X
50h
B0h
D0h
Program/Erase
Suspend
Program/Erase
Resume
Block Lock
2
2
Write
Write
X
X
60h Write BA 01h
60h Write BA D0h
Block Unlock
Block Lock-
Down
2
2
Write
Write
X
X
60h Write BA 2Fh
C0h Write PRA PRD
Protection
Register
Program
1. X = Don't Care,RA=Read Address,RD=Read Data, SRD=Status Register Data, ID=Identifier (Manufacture and Device
Code), QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data,
PRA=Protection Register Address, PRD=Protection Register Data.
2. The signature addresses are listed in Tables 5, 6 and 7.
3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0.
4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
23/77
Command interface
M28W640FCT, M28W640FCB
DQ8-
(1)
Table 5.
Code
Read Electronic signature
Device
E
G
W
A0 A1 A2-A7 A8-A21 DQ0-DQ7
DQ15
Manufacture
Code
VIL VIL VIH VIL VIL
VIL VIL VIH VIH VIL
VIL VIL VIH VIH VIL
0
0
0
Don't Care
Don't Care
Don't Care
20h
48h
49h
00h
M28W640
FCT
88h
88h
Device Code
M28W640
FCB
1. RP = VIH
.
Table 6.
Read Block Lock signature
DQ2-
DQ15
Block Status
E
G
W
A0 A1 A2-A7 A8-A11
A12-A21 DQ0 DQ1
Don't
Care
Block
Address
Locked Block VIL VIL VIH VIL VIH
0
0
0
1
0
0
0
1
00h
00h
00h
Unlocked
Don't
Care
Block
Address
VIL VIL VIH VIL VIH
Block
Locked-
Don't
Care
Block
Address
VIL VIL VIH VIL VIH
Down Block
X (1)
1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Block Locking section.
24/77
M28W640FCT, M28W640FCB
Command interface
Table 7.
Word
Read Protection Register and Lock Register
DQ3-
DQ7
DQ8-
DQ15
E
G
W
A0-A7 A8-A21
DQ0
DQ1
DQ2
Don't
Care
OTP Prot.
data
Lock
VIL VIL VIH 80h
VIL VIL VIH 81h
VIL VIL VIH 82h
VIL VIL VIH 83h
VIL VIL VIH 84h
VIL VIL VIH 85h
VIL VIL VIH 86h
VIL VIL VIH 87h
VIL VIL VIH 88h
VIL VIL VIH 89h
VIL VIL VIH 8Ah
VIL VIL VIH 8Bh
VIL VIL VIH 8Ch
0
0
00h
00h
Unique
ID 0
Don't
Care
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data ID data ID data
ID data ID data ID data
ID data ID data ID data
ID data ID data ID data
Unique
ID 1
Don't
Care
Unique
ID 2
Don't
Care
Unique
ID 3
Don't
Care
Don't
Care
OTP
data
OTP
data
OTP 0
OTP 1
OTP 2
OTP 3
OTP 4
OTP 5
OTP 6
OTP 7
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
Don't
Care
OTP
data
OTP
data
Don't
Care
OTP
data
OTP
data
Don't
Care
OTP
data
OTP
data
Don't
Care
OTP
data
OTP
data
Don't
Care
OTP
data
OTP
data
Don't
Care
OTP
data
OTP
data
Don't
Care
OTP
data
OTP
data
25/77
Command interface
Table 8.
M28W640FCT, M28W640FCB
Program, Erase Times and Program/Erase endurance cycles
M28W640FCT, M28W640FCB
Parameter
Test Conditions
Unit
Min
Typ
Max
Word Program
VPP = VDD
10
200
200
200
5
µs
µs
µs
s
Double Word Program
VPP = 12V ±5%
VPP = 12V ±5%
10
Quadruple Word Program
10
V
V
V
V
PP = 12V ±5%
0.16/0.08 (1)
Main Block Program
Parameter Block Program
Main Block Erase
VPP = VDD
0.32
5
s
PP = 12V ±5%
0.02/0.01 (1)
4
s
VPP = VDD
0.04
1
4
s
PP = 12V ±5%
VPP = VDD
10
10
10
10
s
1
s
PP = 12V ±5%
VPP = VDD
0.4
0.4
s
Parameter Block Erase
s
Program/Erase Cycles
(per Block)
100,000
cycles
1. Typical time to program a Main or Parameter Block using the Double Word Program and the Quadruple
Word Program commands respectively.
26/77
M28W640FCT, M28W640FCB
Block locking
5
Block locking
The M28W640FCT and M28W640FCB feature an instant, individual block locking scheme
that allows any block to be locked or unlocked with no latency. This locking scheme has
three levels of protection.
■
■
Lock/Unlock - this first level allows software-only control of block locking.
Lock-Down - this second level requires hardware interaction before locking can be
changed.
■
V
≤V
- the third level offers a complete hardware protection against program and
PPLK
PP
erase on all blocks.
The protection status of each block can be set to Locked, Unlocked, and Lock-Down.
Table 10, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C,
Figure 22, shows a flowchart for the locking operations.
5.1
Reading a Block’s Lock status
The lock status of every block can be read in the Read Electronic Signature mode of the
device. To enter this mode write 90h to the device. Subsequent reads at the address
specified in Table 6, will output the protection status of that block. The lock status is
represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the
Lock command and cleared by the Unlock command. It is also automatically set when
entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down
command. It cannot be cleared by software, only by a hardware reset or power-down.
The following sections explain the operation of the locking system.
5.2
5.3
Locked state
The default status of all blocks on power-up or after a hardware reset is Locked (states
(0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any
program or erase operations attempted on a locked block will return an error in the Status
Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the
appropriate software commands. An Unlocked block can be Locked by issuing the Lock
command.
Unlocked state
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware reset or when the device is powered-
down. The status of an unlocked block can be changed to Locked or Locked-Down using the
appropriate software commands. A locked block can be unlocked by issuing the Unlock
command.
27/77
Block locking
M28W640FCT, M28W640FCB
5.4
Lock-Down state
Blocks that are Locked-Down (state (0,1,x))are protected from program and erase
operations (as for Locked blocks) but their protection status cannot be changed using
software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the
Lock-Down command. Locked-Down blocks revert to the Locked state when the device is
reset or powered-down.
The Lock-Down function is dependent on the WP input pin. When WP=0 (V ), the blocks in
IL
the Lock-Down state (0,1,x) are protected from program, erase and protection status
changes. When WP=1 (V ) the Lock-Down function is disabled (1,1,1) and Locked-Down
IH
blocks can be individually unlocked to the (1,1,0) state by issuing the software command,
where they can be erased and programmed. These blocks can then be relocked (1,1,1) and
unlocked (1,1,0) as desired while WP remains high. When WP is low , blocks that were
previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes
made while WP was high. Device reset or power-down resets all blocks , including those in
Lock-Down, to the Locked state.
5.5
Locking Operations during Erase Suspend
Changes to block lock status can be performed during an erase suspend by using the
standard locking command sequences to unlock, lock or lock-down a block. This is useful in
the case when another block needs to be updated while an erase operation is in progress.
To change block locking during an erase operation, first write the Erase Suspend command,
then check the status register until it indicates that the erase operation has been
suspended. Next write the desired Lock command sequence to a block and the lock status
will be changed. After completing any desired lock, read, or program operations, resume the
erase operation with the Erase Resume command.
If a block is locked or locked-down during an erase suspend of the same block, the locking
status bits will be changed immediately, but when the erase is resumed, the erase operation
will complete.
Locking operations cannot be performed during a program suspend. Refer to Appendix D,
Command Interface and Program/Erase Controller State, for detailed information on which
commands are valid during erase suspend.
Table 9.
Block Lock status
Item
Address
Data
Block Lock Configuration
Block is Unlocked
LOCK
DQ0=0
DQ0=1
DQ1=1
xx002
Block is Locked
Block is Locked-Down
28/77
M28W640FCT, M28W640FCB
Block locking
Table 10. Protection status
Current Protection Status(1)
(WP, DQ1, DQ0)
Next Protection Status(1)
(WP, DQ1, DQ0)
After Block
Lock
Command
After Block
Unlock
Command
After Block
Lock-Down
Command
Program/Erase
Current State
After WP
transition
Allowed
1,0,0
1,0,1(2)
1,1,0
yes
no
1,0,1
1,0,1
1,1,1
1,1,1
0,0,1
0,0,1
0,1,1
1,0,0
1,0,0
1,1,0
1,1,0
0,0,0
0,0,0
0,1,1
1,1,1
1,1,1
1,1,1
1,1,1
0,1,1
0,1,1
0,1,1
0,0,0
0,0,1
yes
no
0,1,1
1,1,1
0,1,1
0,0,0
yes
no
1,0,0
0,0,1(2)
1,0,1
0,1,1
no
1,1,1 or 1,1,0 (3)
1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for
a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL.
2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
29/77
Status Register
M28W640FCT, M28W640FCB
6
Status Register
The Status Register provides information on the current or previous Program or Erase
operation. The various bits convey information and errors on the operation. To read the
Status register the Read Status Register command can be issued, refer to Read Status
Register Command section. To output the contents, the Status Register is latched on the
falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable
or Output Enable returns to V . Either Chip Enable or Output Enable must be toggled to
IH
update the latched data.
Bus Read operations from any address always read the Status Register during Program and
Erase operations.
The bits in the Status Register are summarized in Table 11: Status Register bits. Refer to
Table 11 in conjunction with the following text descriptions.
6.1
Program/Erase Controller status (bit 7)
The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is
active or inactive. When the Program/Erase Controller Status bit is Low (set to ‘0’), the
Program/Erase Controller is active; when the bit is High (set to ‘1’), the Program/Erase
Controller is inactive, and the device is ready to process a new command.
The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend
command is issued until the Program/Erase Controller pauses. After the Program/Erase
Controller pauses the bit is High .
During Program, Erase, operations the Program/Erase Controller Status bit can be polled to
find the end of the operation. Other bits in the Status Register should not be tested until the
Program/Erase Controller completes the operation and the bit is High.
After the Program/Erase Controller completes its operation the Erase Status, Program
Status, V Status and Block Lock Status bits should be tested for errors.
PP
6.2
Erase Suspend status (bit 6)
The Erase Suspend Status bit indicates that an Erase operation has been suspended or is
going to be suspended. When the Erase Suspend Status bit is High (set to ‘1’), a
Program/Erase Suspend command has been issued and the memory is waiting for a
Program/Erase Resume command.
The Erase Suspend Status should only be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Controller inactive). Bit 7 is set within 30µs of
the Program/Erase Suspend command being issued therefore the memory may still
complete the operation rather than entering the Suspend mode.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns
Low.
30/77
M28W640FCT, M28W640FCB
Status Register
6.3
6.4
6.5
Erase status (bit 5)
The Erase Status bit can be used to identify if the memory has failed to verify that the block
has erased correctly. When the Erase Status bit is High (set to ‘1’), the Program/Erase
Controller has applied the maximum number of pulses to the block and still failed to verify
that the block has erased correctly. The Erase Status bit should be read once the
Program/Erase Controller Status bit is High (Program/Erase Controller inactive).
Once set High, the Erase Status bit can only be reset Low by a Clear Status Register
command or a hardware reset. If set High it should be reset before a new Program or Erase
command is issued, otherwise the new command will appear to fail.
Program status (bit 4)
The Program Status bit is used to identify a Program failure. When the Program Status bit is
High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses
to the byte and still failed to verify that it has programmed correctly. The Program Status bit
should be read once the Program/Erase Controller Status bit is High (Program/Erase
Controller inactive).
Once set High, the Program Status bit can only be reset Low by a Clear Status Register
command or a hardware reset. If set High it should be reset before a new command is
issued, otherwise the new command will appear to fail.
VPP status (bit 3)
The V Status bit can be used to identify an invalid voltage on the V pin during Program
PP
PP
and Erase operations. The V pin is only sampled at the beginning of a Program or Erase
PP
operation. Indeterminate results can occur if V becomes invalid during an operation.
PP
When the V Status bit is Low (set to ‘0’), the voltage on the V pin was sampled at a valid
PP
PP
voltage; when the V Status bit is High (set to ‘1’), the V pin has a voltage that is below
PP
PP
the V Lockout Voltage, V
, the memory is protected and Program and Erase
PP
PPLK
operations cannot be performed.
Once set High, the V Status bit can only be reset Low by a Clear Status Register
PP
command or a hardware reset. If set High it should be reset before a new Program or Erase
command is issued, otherwise the new command will appear to fail.
6.6
Program Suspend status (bit 2)
The Program Suspend Status bit indicates that a Program operation has been suspended.
When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend
command has been issued and the memory is waiting for a Program/Erase Resume
command. The Program Suspend Status should only be considered valid when the
Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 2 is set
within 5µs of the Program/Erase Suspend command being issued therefore the memory
may still complete the operation rather than entering the Suspend mode.
When a Program/Erase Resume command is issued the Program Suspend Status bit
returns Low.
31/77
Status Register
M28W640FCT, M28W640FCB
6.7
Block Protection status (bit 1)
The Block Protection Status bit can be used to identify if a Program or Erase operation has
tried to modify the contents of a locked block.
When the Block Protection Status bit is High (set to ‘1’), a Program or Erase operation has
been attempted on a locked block.
Once set High, the Block Protection Status bit can only be reset Low by a Clear Status
Register command or a hardware reset. If set High it should be reset before a new
command is issued, otherwise the new command will appear to fail.
6.8
Reserved (bit 0)
Bit 0 of the Status Register is reserved. Its value must be masked.
Note:
Refer to Appendix C: Flowcharts and pseudo codes, for using the Status Register.
(1)
Table 11. Status Register bits
Bit
Name
Logic Level
Definition
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
Ready
7
P/E.C. Status
Busy
Suspended
6
5
4
3
2
Erase Suspend Status
Erase Status
In progress or Completed
Erase Error
Erase Success
Program Error
Program Status
Program Success
VPP Invalid, Abort
VPP Status
VPP OK
Suspended
Program Suspend Status
In Progress or Completed
Program/Erase on protected Block,
Abort
'1'
'0'
1
0
Block Protection Status
Reserved
No operation to protected blocks
1. Logic level '1' is High, '0' is Low.
32/77
M28W640FCT, M28W640FCB
Maximum rating
7
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 12. Absolute maximum ratings
Value
Symbol
Parameter
Unit
Min
Max
TA
Ambient Operating Temperature (1)
Temperature Under Bias
Storage Temperature
– 40
– 40
– 55
– 0.6
– 0.6
– 0.6
85
125
°C
°C
°C
V
TBIAS
TSTG
VIO
155
Input or Output voltage
VDDQ+0.6
4.1
V
DD, VDDQ Supply voltage
V
VPP Program voltage
13
V
1. Depends on range.
33/77
DC and AC parameters
M28W640FCT, M28W640FCB
8
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 13: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the measurement conditions when relying on the
quoted parameters.
Table 13. Operating and AC measurement conditions
M28W640FCT, M28W640FCB
Parameter
70
85
90
10
Units
Min
Max
Min
Max
Min
Max
Min
Max
VDD supply voltage
2.7
3.6
2.7
3.6
2.7
3.6
2.7
3.6
V
V
VDDQ supply voltage
2.7
3.6
85
2.7
3.6
85
2.7
3.6
85
1.65
–40
3.6
85
(VDDQ ≤VDD
)
Ambient Operating
Temperature
–40
–40
–40
°C
Load capacitance (CL)
Input Rise and Fall Times
Input pulse voltages
50
50
50
50
pF
ns
V
5
5
5
5
0 to VDDQ
VDDQ/2
0 to VDDQ
VDDQ/2
0 to VDDQ
VDDQ/2
0 to VDDQ
VDDQ/2
Input and Output Timing
Ref. voltages
V
Figure 6.
AC measurement I/O waveform
V
DDQ
V
/2
DDQ
0V
AI00610
34/77
M28W640FCT, M28W640FCB
DC and AC parameters
Figure 7.
AC measurement load circuit
V
DDQ
V
DDQ
V
DD
25kΩ
DEVICE
UNDER
TEST
C
L
25kΩ
0.1µF
0.1µF
C
includes JIG capacitance
AI00609C
L
(1)
Table 14. Capacitance
Symbol
Parameter
Input capacitance
Output capacitance
Test Condition
Min
Max
Unit
CIN
VIN = 0V
6
pF
pF
COUT
VOUT = 0V
12
1. Sampled only, not 100% tested.
35/77
DC and AC parameters
M28W640FCT, M28W640FCB
Table 15. DC characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
ILI
Input Leakage Current
Output Leakage Current
0V≤VIN ≤VDDQ
0V≤VOUT ≤VDDQ
±1
µA
µA
ILO
±10
E = VSS, G = VIH,
f = 5MHz
IDD
Supply Current (Read)
9
18
mA
Supply Current (Stand-by or
Automatic Stand-by)
E = VDDQ ± 0.2V,
RP = VDDQ ± 0.2V
IDD1
IDD2
15
15
5
50
50
10
µA
µA
Supply Current (Reset)
RP = VSS ± 0.2V
Program in progress
mA
VPP = 12V ± 5%
IDD3
Supply Current (Program)
Program in progress
10
5
20
20
mA
mA
mA
µA
VPP = VDD
Erase in progress
VPP = 12V ± 5%
IDD4
Supply Current (Erase)
Erase in progress
VPP = VDD
10
15
20
Supply Current
(Program/Erase Suspend)
E = VDDQ ± 0.2V,
Erase suspended
IDD5
IPP
IPP1
IPP2
50
Program Current
(Read or Stand-by)
VPP > VDD
400
µA
Program Current
(Read or Stand-by)
VPP ≤VDD
1
1
1
5
5
µA
µA
Program Current (Reset)
RP = VSS ± 0.2V
Program in progress
VPP = 12V ± 5%
10
mA
IPP3
Program Current (Program)
Program in progress
VPP = VDD
1
3
1
5
10
5
µA
mA
µA
Erase in progress
VPP = 12V ± 5%
IPP4
Program Current (Erase)
Erase in progress
VPP = VDD
–0.5
–0.5
0.4
V
V
V
V
VIL
VIH
Input Low voltage
Input High voltage
V
DDQ ≥ 2.7V
DDQ ≥ 2.7V
0.8
V
DDQ –0.4
VDDQ +0.4
VDDQ +0.4
V
0.7 VDDQ
IOL = 100µA,
VOL
Output Low voltage
Output High voltage
VDD = VDD min,
VDDQ = VDDQ min
0.1
V
V
I
OH = –100µA,
VDD = VDD min,
DDQ = VDDQ min
VOH
VDDQ –0.1
V
36/77
M28W640FCT, M28W640FCB
DC and AC parameters
Table 15. DC characteristics (continued)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
Program voltage (Program or
Erase operations)
VPP1
1.65
3.6
V
Program voltage (Program or
Erase operations)
VPPH
VPPLK
VLKO
11.4
12.6
1
V
V
V
Program voltage (Program
and Erase lock-out)
VDD supply voltage (Program
and Erase lock-out)
2
37/77
DC and AC parameters
Figure 8.
M28W640FCT, M28W640FCB
Read AC waveforms
tAVAV
VALID
A0-A21
E
tAVQV
tAXQX
tELQV
tELQX
tEHQX
tEHQZ
G
tGLQV
tGHQX
tGHQZ
tGLQX
DQ0-
DQ15
VALID
OUTPUTS
ENABLED
ADDR. VALID
CHIP ENABLE
DATA VALID
STANDBY
AI04387
Table 16. Read AC characteristics
M28W640FCT, M28W640FCB
Symbol Alt
Parameter
Unit
70
85
90
10
Address Valid to Next Address
Valid
tAVAV
tRC
Min
Max
Min
70
70
0
85
85
0
90
90
0
100
100
0
ns
ns
ns
tAVQV tACC Address Valid to Output Valid
Address Transition to Output
Transition
(1)
tAXQX
tEHQX
tOH
Chip Enable High to Output
Transition
(1)
tOH
Min
0
0
0
0
ns
(1)
(2)
tEHQZ
tELQV
tHZ Chip Enable High to Output Hi-Z
tCE Chip Enable Low to Output Valid
Max
Max
20
70
20
85
25
90
25
ns
ns
100
Chip Enable Low to Output
Transition
(1)
tELQX
tLZ
Min
Min
0
0
0
0
ns
tG(H1Q) X
Output Enable High to Output
Transition
tOH
0
0
0
0
ns
ns
ns
(1)
tGHQZ
tDF Output Enable High to Output Hi-Z Max
Output Enable Low to Output
20
20
20
20
25
30
25
35
(2)
(1)
tGLQV
tOE
Max
Valid
Output Enable Low to Output
Transition
tGLQX
tOLZ
Min
0
0
0
0
ns
1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV
38/77
M28W640FCT, M28W640FCB
DC and AC parameters
Figure 9.
Write AC waveforms, Write enable controlled
39/77
DC and AC parameters
M28W640FCT, M28W640FCB
Table 17. Write AC characteristics, Write enable controlled
M28W640FCT,
M28W640FCB
Symbol
Alt
Parameter
Unit
70
85
90
10
tAVAV
tAVWH
tDVWH
tWC Write Cycle Time
Min
70
45
45
85
45
45
90
50
50
100
50
ns
ns
ns
tAS Address Valid to Write Enable High Min
tDS Data Valid to Write Enable High
Min
Min
Min
Min
Min
50
Chip Enable Low to Write Enable
Low
tELWL
tELQV
tCS
0
70
0
0
85
0
0
90
0
0
100
0
ns
ns
ns
Chip Enable Low to Output Valid
Output Valid to VPP Low
(1)
tQVVPL
(2)
tQVWPL
Output Valid to Write Protect Low
tVPS VPP High to Write Enable High
0
0
0
0
ns
ns
(1)
tVPHWH
Min 200
200
200
200
Write Enable High to Address
Transition
tWHAX
tWHDX
tWHEH
tWHEL
tAH
Min
Min
Min
Min
Min
Min
Min
Min
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
Write Enable High to Data
Transition
tDH
0
0
0
0
Write Enable High to Chip Enable
High
tCH
0
0
0
0
Write Enable High to Chip Enable
Low
25
20
25
45
45
25
20
25
45
45
30
30
30
50
50
30
30
30
50
50
Write Enable High to Output
Enable Low
tWHGL
tWHWL
tWLWH
tWPHWH
tWP Write Enable High to Write Enable
Low
H
Write Enable Low to Write Enable
High
tWP
Write Protect High to Write Enable
High
1. Sampled only, not 100% tested.
2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
40/77
M28W640FCT, M28W640FCB
DC and AC parameters
Figure 10. Write AC waveforms, Chip enable controlled
41/77
DC and AC parameters
M28W640FCT, M28W640FCB
Table 18. Write AC characteristics, Chip enable controlled
M28W640FCT, M28W640FCB
Symbol
Alt
Parameter
Unit
70
85
90
10
tAVAV
tAVEH
tDVEH
tEHAX
tWC Write Cycle Time
Min
Min
Min
Min
70
85
90
100
ns
ns
ns
ns
Address Valid to Chip Enable
High
tAS
45
45
0
45
45
0
50
50
0
50
50
0
tDS Data Valid to Chip Enable High
Chip Enable High to Address
Transition
tAH
Chip Enable High to Data
Transition
tEHDX
tEHEL
tEHGL
tEHWH
tDH
Min
Min
Min
Min
Min
0
25
25
0
0
25
25
0
0
30
30
0
0
30
30
0
ns
ns
ns
ns
Chip Enable High to Chip Enable
tCPH
Low
Chip Enable High to Output
Enable Low
Chip Enable High to Write Enable
High
tWH
Chip Enable Low to Chip Enable
High
tELEH
tELQV
tCP
45
70
0
45
85
0
50
90
0
50
100
0
ns
ns
ns
Chip Enable Low to Output Valid Min
tQVVPL
Output Valid to VPP Low
Min
(1)(2)
tQVWPL
Data Valid to Write Protect Low
Min
Min
0
0
0
0
ns
ns
(1)
tVPHEH
tVPS VPP High to Chip Enable High
200
200
200
200
Write Enable Low to Chip Enable
Low
tWLEL
tCS
Min
Min
0
0
0
0
ns
ns
Write Protect High to Chip
Enable High
tWPHEH
45
45
50
50
1. Sampled only, not 100% tested.
2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
42/77
M28W640FCT, M28W640FCB
DC and AC parameters
Figure 11. Power-Up and Reset AC waveforms
W, E, G
tPHWL
tPHEL
tPHGL
tPHWL
tPHEL
tPHGL
RP
tVDHPH
tPLPH
VDD, VDDQ
Power-Up
Reset
AI03537b
Table 19. Power-Up and Reset AC characteristics
M28W640FCT,
M28W640FCB
Symbol
Parameter
Test Condition
Unit
70
85
90
10
During
Program
and Erase
tPHWL
tPHEL
tPHGL
Reset High to Write Enable Low,
Chip Enable Low, Output Enable
Low
Min
Min
50
30
50
50
30
50
30
µs
ns
others
30
(1)(2)
tPLPH
Reset Low to Reset High
Min 100
Min 50
100
100 100 ns
Supply Voltages High to Reset
High
(3)
tVDHPH
50
50
50
µs
1. The device Reset is possible but not guaranteed if tPLPH < 100ns
2. Sampled only, not 100% tested.
3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.
43/77
Package mechanical
M28W640FCT, M28W640FCB
9
Package mechanical
Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline
1
48
e
D1
B
L1
24
25
A2
A
E1
E
A1
α
L
DIE
C
CP
TSOP-G
1. Drawing is not to scale.
Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package
mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
B
1.200
0.150
1.050
0.270
0.210
0.100
12.100
20.200
18.500
–
0.0472
0.0059
0.0413
0.0106
0.0083
0.0039
0.4764
0.7953
0.7283
–
0.100
1.000
0.220
0.050
0.950
0.170
0.100
0.0039
0.0394
0.0087
0.0020
0.0374
0.0067
0.0039
C
CP
D1
E
12.000
20.000
18.400
0.500
0.600
0.800
3°
11.900
19.800
18.300
–
0.4724
0.7874
0.7244
0.0197
0.0236
0.0315
3°
0.4685
0.7795
0.7205
–
E1
e
L
0.500
0.700
0.0197
0.0276
L1
α
0°
5°
0°
5°
44/77
M28W640FCT, M28W640FCB
Package mechanical
Figure 13. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, bottom view
package outline
D
D1
FD
FE
SD
SE
E
E1
e
BALL "A1"
ddd
e
b
A2
A
A1
BGA-Z34
1. Drawing is not to scale.
Table 21. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, package
mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.260
0.0102
1.000
0.0394
0.400
6.390
5.250
0.350
6.290
–
0.450
0.0157
0.2516
0.2067
0.0138
0.2476
–
0.0177
D
6.490
0.2555
D1
ddd
E
–
–
0.100
0.0039
10.500
3.750
0.750
0.570
3.375
0.375
0.375
10.400
10.600
0.4134
0.1476
0.0295
0.0224
0.1329
0.0148
0.0148
0.4094
0.4173
E1
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FD
FE
SD
SE
45/77
Package mechanical
M28W640FCT, M28W640FCB
Figure 14. TFBGA48 daisy chain - package connections (top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
AI04390
46/77
M28W640FCT, M28W640FCB
Package mechanical
Figure 15. TFBGA48 daisy chain - PCB connections proposal (top view through
package)
1
2
3
4
5
6
7
8
START
POINT
A
B
C
D
E
F
END
POINT
AI04391
47/77
Part numbering
M28W640FCT, M28W640FCB
10
Part numbering
Table 22. Ordering information scheme
Example:
M28W640FCT 90
N
6
E
Device type
M28
Operating voltage
W = VDD = 2.7V to 3.6V; VDDQ = 1.65V to 3.6V
Device function
640FC = 64 Mbit (4 Mb x16), Boot Block
Array matrix
T = Top Boot
B = Bottom Boot
Speed
70 = 70ns
85 = 85ns
90 = 90ns
10 = 100ns
Package
N = TSOP48: 12 x 20 mm
ZB = TFBGA48: 6.39 x 10.5mm, 0.75 mm pitch
Temperature range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
E = ECOPACK® Package, Standard Packing
F = ECOPACK® Package, Tape & Reel Packing
48/77
M28W640FCT, M28W640FCB
Part numbering
Table 23. Daisy Chain ordering scheme
Example:
M28W640FC
-ZB T
Device type
M28W640FC
Daisy chain
-ZB = TFBGA48: 6.39 x 10.5mm, 0.75 mm pitch
Option
E = ECOPACK® Package, Standard Packing
F = ECOPACK® Package, Tape & Reel Packing, 24mm
1. Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available
options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the
ST Sales Office nearest to you.
49/77
Block address tables
M28W640FCT, M28W640FCB
Appendix A Block address tables
Table 24. Top Boot Block Addresses, M28W640FCT
#
Size (KWord)
Address range
0
4
3FF000-3FFFFF
3FE000-3FEFFF
3FD000-3FDFFF
3FC000-3FCFFF
3FB000-3FBFFF
3FA000-3FAFFF
3F9000-3F9FFF
3F8000-3F8FFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
50/77
M28W640FCT, M28W640FCB
Block address tables
Table 24. Top Boot Block Addresses, M28W640FCT (continued)
#
Size (KWord)
Address range
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
330000-337FFF
328000-32FFFF
320000-327FFF
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
2B8000-2BFFFF
2B0000-2B7FFF
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
51/77
Block address tables
M28W640FCT, M28W640FCB
Table 24. Top Boot Block Addresses, M28W640FCT (continued)
#
Size (KWord)
Address range
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
218000-21FFFF
210000-217FFF
208000-20FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
52/77
M28W640FCT, M28W640FCB
Block address tables
Table 24. Top Boot Block Addresses, M28W640FCT (continued)
#
Size (KWord)
Address range
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
53/77
Block address tables
M28W640FCT, M28W640FCB
Table 25. Bottom Boot Block Addresses, M28W640FCB
#
Size (KWord)
Address Range
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
3F8000-3FFFFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
54/77
M28W640FCT, M28W640FCB
Block address tables
Table 25. Bottom Boot Block Addresses, M28W640FCB (continued)
#
Size (KWord)
Address Range
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
2B8000-2BFFFF
2B0000-2B7FFF
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-20FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
55/77
Block address tables
M28W640FCT, M28W640FCB
Table 25. Bottom Boot Block Addresses, M28W640FCB (continued)
#
Size (KWord)
Address Range
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
56/77
M28W640FCT, M28W640FCB
Block address tables
Table 25. Bottom Boot Block Addresses, M28W640FCB (continued)
#
Size (KWord)
Address Range
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
007000-007FFF
006000-006FFF
005000-005FFF
004000-004FFF
003000-003FFF
002000-002FFF
001000-001FFF
000000-000FFF
8
7
6
4
5
4
4
4
3
4
2
4
1
4
0
4
57/77
Common Flash Interface (CFI)
M28W640FCT, M28W640FCB
Appendix B Common Flash Interface (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the CFI Query Command (RCFI) is issued the device enters CFI Query mode and the
data structure is read from the memory. Tables 26, 27, 28, 29, 30 and 31 show the
addresses used to retrieve the data.
The CFI data structure also contains a security area where a 64 bit unique security number
is written (see Table 31: Security code area). This area can be accessed only in Read mode
by the final user. It is impossible to change the security number after it has been written by
ST. Issue a Read command to return to Read mode.
(1)
Table 26. Query Structure Overview
Offset
Sub-section Name
Description
00h
10h
1Bh
27h
Reserved
Reserved for algorithm-specific information
Command set ID and algorithm data offset
Device timing & voltage information
Flash device layout
CFI Query Identification String
System Interface Information
Device Geometry Definition
Primary Algorithm-specific Extended Query Additional information specific to the
P
A
table
Primary Algorithm (optional)
Alternate Algorithm-specific Extended
Query table
Additional information specific to the
Alternate Algorithm (optional)
1. Query data are always presented on the lowest order data outputs.
58/77
M28W640FCT, M28W640FCB
Common Flash Interface (CFI)
(1)
Table 27. CFI Query Identification String
Offset
Data
Description
Value
00h
0020h Manufacturer code
ST
8848h
Top
01h
Device code
8849h
Bottom
02h-0Fh reserved Reserved
10h
11h
12h
13h
0051h
"Q"
"R"
0052h Query Unique ASCII String "QRY"
0059h
0003h
"Y"
Intel
compatibl
e
Primary Algorithm Command Set and Control Interface ID code 16
bit ID code defining a specific algorithm
14h
0000h
15h
16h
17h
0035h
0000h
Address for Primary Algorithm extended Query table (see Table 29) P = 35h
0000h Alternate Vendor Command Set and Control Interface ID code
second vendor - specified algorithm supported (0000h means none
0000h
exists)
NA
NA
18h
19h
1Ah
0000h
0000h
Address for Alternate Algorithm extended Query table
(0000h means none exists)
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
59/77
Common Flash Interface (CFI)
M28W640FCT, M28W640FCB
Value
Table 28. CFI Query System Interface Information
Offset
Data
Description
VDD Logic Supply Minimum Program/Erase or Write voltage
1Bh
0027h bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
2.7V
3.6V
VDD Logic Supply Maximum Program/Erase or Write voltage
1Ch
1Dh
1Eh
0036h bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
VPP [Programming] Supply Minimum Program/Erase voltage
00B4h bit 7 to 4HEX value in volts
11.4V
12.6V
bit 3 to 0BCD value in 100 mV
VPP [Programming] Supply Maximum Program/Erase voltage
00C6h bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
1Fh
20h
21h
22h
23h
0004h Typical time-out per single word program = 2n µs
0004h Typical time-out for Double/Quadruple Word Program = 2n µs
000Ah Typical time-out per individual block erase = 2n ms
0000h Typical time-out for full chip erase = 2n ms
16µs
16µs
1s
NA
0005h Maximum time-out for Word program = 2n times typical
512µs
Maximum time-out for Double/Quadruple Word Program = 2n times
24h
0005h
typical
512µs
25h
26h
0003h Maximum time-out per individual block erase = 2n times typical
0000h Maximum time-out for chip erase = 2n times typical
8s
NA
60/77
M28W640FCT, M28W640FCB
Common Flash Interface (CFI)
Table 29.
Device Geometry Definition
Data
Offset
Word
Mode
Description
Value
27h
0017h Device size = 2n in number of bytes
8 Mbyte
28h
29h
0001h
x16
Flash Device Interface code description
0000h
Async.
2Ah
2Bh
0003h
Maximum number of bytes in multi-byte program or page = 2n
8
2
0000h
Number of Erase Block Regions within the device.
2Ch
0002h
It specifies the number of regions within the device containing
contiguous Erase Blocks of the same size.
2Dh
2Eh
007Eh Region 1 Information
127
64 Kbyte
8
0000h Number of identical-size erase block = 007Eh+1
2Fh
30h
0000h Region 1 Information
0001h Block size in Region 1 = 0100h * 256 byte
31h
32h
0007h Region 2 Information
0000h Number of identical-size erase block = 0007h+1
33h
34h
0020h Region 2 Information
8 Kbyte
8
0000h Block size in Region 2 = 0020h * 256 byte
2Dh
2Eh
0007h Region 1 Information
0000h Number of identical-size erase block = 0007h+1
2Fh
30h
0020h Region 1 Information
8 Kbyte
127
0000h Block size in Region 1 = 0020h * 256 byte
31h
32h
007Eh Region 2 Information
0000h Number of identical-size erase block = 007Eh=1
33h
34h
0000h Region 2 Information
64 Kbyte
0001h Block size in Region 2 = 0100h * 256 byte
61/77
Common Flash Interface (CFI)
M28W640FCT, M28W640FCB
Table 30. Primary Algorithm-specific Extended Query table
Offset
Data
Description
Value
P = 35h (1)
(P+0)h = 35h 0050h
(P+1)h = 36h 0052h
(P+2)h = 37h 0049h
"P"
Primary Algorithm extended Query table unique ASCII string
“PRI”
"R"
"I"
(P+3)h = 38h 0031h Major version number, ASCII
(P+4)h = 39h 0030h Minor version number, ASCII
"1"
"0"
(P+5)h = 3Ah 0066h
(P+6)h = 3Bh 0000h
(P+7)h = 3Ch 0000h
Extended Query table contents for Primary Algorithm. Address
(P+5)h contains less significant byte.
bit 0Chip Erase supported(1 = Yes, 0 = No)
bit 1Suspend Erase supported(1 = Yes, 0 = No)
bit 2Suspend Program supported(1 = Yes, 0 = No)
bit 3Legacy Lock/Unlock supported(1 = Yes, 0 = No)
bit 4Queued Erase supported(1 = Yes, 0 = No)
bit 5Instant individual block locking supported(1 = Yes, 0 = No)
bit 6Protection bits supported(1 = Yes, 0 = No)
bit 7Page mode read supported(1 = Yes, 0 = No)
bit 8Synchronous read supported(1 = Yes, 0 = No)
bit 31 to 9Reserved; undefined bits are ‘0’
No
Yes
Yes
No
No
(P+8)h = 3Dh 0000h
Yes
Yes
No
No
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query are always
supported during Erase or Program operation
(P+9)h = 3Eh 0001h
bit 0Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1Reserved; undefined bits are ‘0’
Yes
(P+A)h = 3Fh 0003h Block Lock Status
Defines which bits in the Block Status Register section of the
Query are implemented.
Address (P+A)h contains less significant byte
bit 0Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0
= No)
(P+B)h = 40h 0000h
Yes
Yes
bit 1Block Lock Status Register Lock-Down bit active (1 = Yes, 0
= No)
bit 15 to 2Reserved for future use; undefined bits are ‘0’
VDD Logic Supply Optimum Program/Erase voltage (highest
performance)
(P+C)h = 41h 0030h
3V
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
VPP Supply Optimum Program/Erase voltage
(P+D)h = 42h 00C0h bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
12V
01
Number of Protection register fields in JEDEC ID space.
"00h," indicates that 256 protection bytes are available
(P+E)h = 43h 0001h
62/77
M28W640FCT, M28W640FCB
Common Flash Interface (CFI)
Table 30. Primary Algorithm-specific Extended Query table (continued)
Offset
Data
Description
Value
P = 35h (1)
(P+F)h = 44h 0080h Protection Field 1: Protection Description
80h
00h
This field describes user-available One Time Programmable
(P+10)h =
45h
0000h
0003h
(OTP) Protection register bytes. Some are pre-programmed with
device unique serial numbers. Others are user programmable.
bits 0–15 point to the Protection register Lock byte, the section’s
first byte.
(P+11)h =
46h
8 byte
The following bytes are factory pre-programmed and user-
programmable.
bit 0 to 7 Lock/bytes JEDEC-plane physical low address
bit 8 to 15Lock/bytes JEDEC-plane physical high address
bit 16 to 23 "n" such that 2n = factory pre-programmed bytes
bit 24 to 31 "n" such that 2n = user programmable bytes
(P+12)h =
47h
0004h
16 byte
(P+13)h =
48h
Reserved
1. See Table 27, offset 15 for P pointer definition
Table 31. Security code area
Offset
Data
Description
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
00XX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
Protection Register Lock
64 bits: unique device number
128 bits: User Programmable OTP
63/77
Flowcharts and pseudo codes
M28W640FCT, M28W640FCB
Appendix C Flowcharts and pseudo codes
Figure 16. Program flowchart and pseudo code
Start
program_command (addressToProgram, dataToProgram) {:
Write 40h or 10h
writeToFlash (any_address, 0x40) ;
/*or writeToFlash (any_address, 0x10) ; */
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
NO
V
Invalid
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
PP
b3 = 0
YES
Error (1, 2)
NO
NO
Program
Error (1, 2)
if (status_register.b4==1) /*program error */
error_handler ( ) ;
b4 = 0
YES
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI03538b
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation
or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
64/77
M28W640FCT, M28W640FCB
Flowcharts and pseudo codes
Figure 17. Double Word Program flowchart and pseudo code
Start
Write 30h
double_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2)
{
writeToFlash (any_address, 0x30) ;
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
Write Address 1
& Data 1 (3)
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
/*Memory enters read status state after
the Program command*/
Write Address 2
& Data 2 (3)
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
Read Status
Register
NO
NO
NO
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
V
Invalid
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
PP
b3 = 0
YES
Error (1, 2)
if (status_register.b4==1) /*program error */
error_handler ( ) ;
Program
b4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI03539b
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation
or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
65/77
Flowcharts and pseudo codes
M28W640FCT, M28W640FCB
Figure 18. Quadruple Word Program flowchart and pseudo code
Start
quadruple_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2,
addressToProgram3, dataToProgram3,
addressToProgram4, dataToProgram4)
{
Write 56h
Write Address 1
& Data 1 (3)
writeToFlash (any_address, 0x56) ;
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
Write Address 2
& Data 2 (3)
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
writeToFlash (addressToProgram3, dataToProgram3) ;
/*see note (3) */
Write Address 3
& Data 3 (3)
writeToFlash (addressToProgram4, dataToProgram4) ;
/*see note (3) */
Write Address 4
& Data 4 (3)
/*Memory enters read status state after
the Program command*/
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
Read Status
Register
NO
NO
NO
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
V
Invalid
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
PP
b3 = 0
YES
Error (1, 2)
if (status_register.b4==1) /*program error */
error_handler ( ) ;
Program
b4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI06233
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation
or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
66/77
M28W640FCT, M28W640FCB
Flowcharts and pseudo codes
Figure 19. Program Suspend & Resume flowchart and pseudo code
Start
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
Write 70h
writeToFlash (any_address, 0x70) ;
/* read status register to check if
program has already completed */
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
Read Status
Register
NO
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
b2 = 1
YES
Program Complete
if (status_register.b2==0) /*program completed */
{ writeToFlash (any_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
}
Read data from
another address
else
{ writeToFlash (any_address, 0xFF) ;
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
Write D0h
Write FFh
Read Data
}
}
Program Continues
AI03540b
67/77
Flowcharts and pseudo codes
M28W640FCT, M28W640FCB
Figure 20. Erase flowchart and pseudo code
Start
erase_command ( blockToErase ) {
writeToFlash (any_address, 0x20) ;
Write 20h
writeToFlash (blockToErase, 0xD0) ;
/* only A12-A20 are significannt */
/* Memory enters read status state after
the Erase Command */
Write Block
Address & D0h
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
NO
b7 = 1
} while (status_register.b7== 0) ;
YES
NO
YES
NO
NO
V
Invalid
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
PP
Error (1)
b3 = 0
YES
if ( (status_register.b4==1) && (status_register.b5==1) )
/* command sequence error */
Command
Sequence Error (1)
b4, b5 = 1
NO
error_handler ( ) ;
if ( (status_register.b5==1) )
/* erase error */
b5 = 0
YES
Erase Error (1)
error_handler ( ) ;
Erase to Protected
Block Error (1)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI03541b
1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
68/77
M28W640FCT, M28W640FCB
Flowcharts and pseudo codes
Figure 21. Erase Suspend & Resume flowchart and pseudo code
Start
erase_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
Write 70h
writeToFlash (any_address, 0x70) ;
/* read status register to check if
erase has already completed */
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
NO
NO
} while (status_register.b7== 0) ;
b7 = 1
YES
if (status_register.b6==0) /*erase completed */
{ writeToFlash (any_address, 0xFF) ;
b6 = 1
YES
Erase Complete
read_data ( ) ;
/*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
Read data from
another block
or
Program/Protection Program
or
Block Protect/Unprotect/Lock
}
else
{ writeToFlash (any_address, 0xFF) ;
read_program_data ( );
Write D0h
Write FFh
Read Data
/*read or program data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume erase*/
}
}
Erase Continues
AI03542b
69/77
Flowcharts and pseudo codes
M28W640FCT, M28W640FCB
Figure 22. Locking Operations flowchart and pseudo code
Start
locking_operation_command (address, lock_operation) {
writeToFlash (any_address, 0x60) ; /*configuration setup*/
Write 60h
if (lock_operation==LOCK) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (lock_operation==UNLOCK) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
Write
01h, D0h or 2Fh
else if (lock_operation==LOCK-DOWN) /*to lock the block*/
writeToFlash (address, 0x2F) ;
writeToFlash (any_address, 0x90) ;
Write 90h
Read Block
Lock States
if (readFlash (address) ! = locking_state_expected)
error_handler () ;
NO
Locking
change
/*Check the locking state (see Read Block Signature table )*/
confirmed?
YES
writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/
Write FFh
}
End
AI04364
70/77
M28W640FCT, M28W640FCB
Flowcharts and pseudo codes
Figure 23. Protection Register Program flowchart and pseudo code
Start
protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (any_address, 0xC0) ;
Write C0h
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
NO
V
Invalid
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
PP
b3 = 0
YES
Error (1, 2)
NO
NO
Program
Error (1, 2)
if (status_register.b4==1) /*program error */
error_handler ( ) ;
b4 = 0
YES
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI04381
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation
or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
71/77
Command Interface and Program/Erase Controller State
M28W640FCT, M28W640FCB
Appendix D Command Interface and Program/Erase
Controller State
.
(1)
Table 32. Write State machine Current/Next
Command Input (and Next State)
SR
Current
State
Data When
Read
Read Program Erase
Erase
Prog/Ers Prog/Ers Read Clear
bit
7
Array
(FFh)
Setup
Setup
(20h)
Confirm Suspend Resume Status Status
(10/40h)
(D0h)
(B0h)
(D0h)
(70h)
(50h)
Read
Array
Ers.
Setup
Read
Sts.
Read
Array
Read Array “1”
Array
Prog.Setup
Read Array
Read
“1”
Read
Array
Program
Setup
Erase
Setup
Read
Status Array
Read
Status
Read Array
Read Array
Read Array
Status
Program
Setup
Read
“1”
Electronic Read
Signature Array
Erase
Setup
Read Read
Elect.Sg.
Status Array
Read Read
Program
Setup
Read CFI
“1”
Read
CFI
Erase
Setup
Query
Array
Status Array
Lock
(complete)
Lock Cmd
Error
Lock
(complete)
Lock Command
Error
Lock Setup “1”
Status
Status
Lock Command Error
Program
Setup
Lock Cmd
“1”
Read
Array
Erase
Setup
Read
Read
Read Array
Read Array
Error
Status Array
Program
Setup
Lock
“1”
Read
Array
Erase
Setup
Read Read
Status Array
Status
Status
Status
Status
Status
Status
(complete)
Prot. Prog.
“1”
Protection Register Program
Setup
Prot. Prog.
“0”
Protection Register Program continue
(continue)
Program
Setup
Prot. Prog.
“1”
Read
Array
Erase
Read
Read
Read Array
Setup
(complete)
Status Array
Prog.
“1”
Program
Setup
Program
“0”
Prog. Sus
Read Sts
Program (continue)
Program (continue)
(continue)
Prog.
Prog.
Sus
(continue) Read
Sts
Prog.
Prog. Sus
Read
Array
Prog. Sus
“1”
Sus Program Suspend to Program
Read
Array
Program
Sus
Read
Array
Status
Status
Read Array
(continue)
Prog.
Prog.
Sus
(continue) Read
Sts
Prog.
Sus
Read
Array
Prog. Sus
Read
Array
Prog. Sus
“1”
Sus Program Suspend to Program
Read
Array
Program
Array
Read Array
Read Array
(continue)
Prog.
Prog.
Sus
(continue) Read
Sts
Prog.
Sus
Read
Array
Prog. Sus
Read
Elect.Sg.
Prog. Sus
Read
Array
Electronic
Sus Program Suspend to Program
Signature Read
Array
Program
“1”
Read Array
(continue)
72/77
M28W640FCT, M28W640FCB
Command Interface and Program/Erase Controller State
(1)
Table 32. Write State machine Current/Next (continued)
Command Input (and Next State)
SR
bit
7
Current
State
Data When
Read
Read Program Erase
Erase
Prog/Ers Prog/Ers Read Clear
Array
(FFh)
Setup
(10/40h)
Setup
(20h)
Confirm Suspend Resume Status Status
(D0h)
(B0h)
(D0h)
(70h)
(50h)
Prog.
Prog.
Sus
(continue) Read
Sts
Prog.
Sus
Read
Array
Prog. Sus
Read
Array
Prog. Sus
Read CFI
Sus Program Suspend to Program
Read
Array
Program
“1”
CFI
Read Array
(continue)
Program
(complete)
Read
Array
Program
Setup
Erase
Setup
Read
Status Array
Read
“1”
“1”
“1”
“0”
Status
Status
Status
Status
Read Array
Erase
Erase
Setup
Erase
Erase
EraseCommand
Error
Erase Command Error
(continue) CmdError (continue)
Erase
Cmd.Error
Read
Array
Program
Setup
Erase
Setup
Read
Status Array
Read
Read Array
Erase
(continue)
Erase Sus
Read Sts
Erase (continue)
Erase (continue)
Erase
Sus
Read
Array
Erase
Sus
Read
Array
Erase Erase
Erase Sus
Read
Program
Erase
Erase
Erase Sus
Read Sts
Sus
Read
Sts
Sus
Read
Array
“1”
“1”
“1”
Status
Setup
(continue)
(continue)
Array
Erase
Sus
Read
Array
Erase
Sus
Read
Array
Erase Erase
Erase Sus
Read
Program
Setup
Erase
Erase
Erase Sus
Read Array
Sus
Read
Sts
Sus
Read
Array
Array
(continue)
(continue)
Array
Erase
Sus
Signature Read
Array
Erase
Sus
Read
Array
Erase Erase
Erase Sus
Read
Elect.Sg.
Erase Sus
Read
Program
Setup
Erase
Erase
Electronic
Sus
Read
Sts
Sus
Read
Array
(continue)
(continue)
Array
Erase
Sus
Read
Array
Erase
Sus
Read
Array
Erase Erase
Erase Sus
Read
Program
Setup
Erase
Erase
Erase Sus
Read CFI
Sus
Read
Sts
Sus
Read
Array
“1”
“1”
CFI
(continue)
(continue)
Array
Erase
(complete)
Read
Status
Program
Setup
Erase
Setup
Read
Status Array
Read
Read Array
Array
1. Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.
73/77
Command Interface and Program/Erase Controller State
M28W640FCT, M28W640FCB
.
(1)
Table 33. Write State machine Current/Next
Command Input (and Next State)
Prot.
Lock
Down
Confirm
(2Fh)
Current
State
Read
Elect.Sg.
Read CFI
Query
Lock
Setup
Unlock
Confirm
Lock
Confirm
(01h)
Prog.
Setup
(C0h)
(90h)
(98h)
(60h)
(D0h)
Read
Elect.Sg.
Read CFI
Query
Prot. Prog.
Setup
Read Array
Lock Setup
Lock Setup
Lock Setup
Lock Setup
Read Array
Read Array
Read Array
Read
Status
Read
Elect.Sg.
Read CFI
Query
Prot. Prog.
Setup
Read
Elect.Sg.
Read
Elect.Sg.
Read CFI
Query
Prot. Prog.
Setup
Read CFI
Query
Read
Elect.Sg.
Read CFI
Query
Prot. Prog.
Setup
Read Array
Lock (complete)
Read Array
Lock Setup
Lock Command Error
Lock Cmd
Error
Read
Elect.Sg.
Read CFI
Lock Setup
Query
Prot. Prog.
Setup
Lock
Read
Read CFI
Lock Setup
Query
Prot. Prog.
Setup
Read Array
(complete) Elect.Sg.
Prot. Prog.
Setup
Protection Register Program
Prot. Prog.
(continue)
Protection Register Program (continue)
Prot. Prog.
(complete) Elect.Sg.
Read
Read CFI
Query
Prot. Prog.
Lock Setup
Read Array
Setup
Prog.
Setup
Program
Program
(continue)
Program (continue)
Prog.
Suspend
Prog.
Suspend
Read
Prog.
Suspend
Read CFI
Query
Program
Program Suspend Read Array
Program Suspend Read Array
Program Suspend Read Array
Program Suspend Read Array
Read
Status
(continue)
Elect.Sg.
Prog.
Suspend
Read
Prog.
Suspend
Read CFI
Query
Prog.
Suspend
Program
(continue)
Read Array
Elect.Sg.
Prog.
Suspend
Prog.
Suspend
Read
Prog.
Suspend
Read CFI
Query
Program
Read
Elect.Sg.
(continue)
Elect.Sg.
Prog.
Suspend
Read
Prog.
Suspend
Read CFI
Query
Prog.
Suspend
Program
(continue)
Read CFI
Elect.Sg.
74/77
M28W640FCT, M28W640FCB
Command Interface and Program/Erase Controller State
(1)
Table 33. Write State machine Current/Next (continued)
Command Input (and Next State)
Prot.
Lock
Down
Confirm
(2Fh)
Current
State
Read
Elect.Sg.
Read CFI
Query
Lock
Setup
Unlock
Confirm
Lock
Confirm
(01h)
Prog.
Setup
(C0h)
(90h)
(98h)
(60h)
(D0h)
Program
(complete) Elect.Sg.
Read
Read
CFIQuery
Prot. Prog.
Setup
Lock Setup
Read Array
Read Array
Erase
Setup
Erase
(continue)
Erase Command Error
Erase
Cmd.Error Elect.Sg.
Read
Read CFI
Query
Prot. Prog.
Lock Setup
Setup
Erase
(continue)
Erase (continue)
Erase
Suspend
Erase
Suspend
Erase
Suspend
Read
Erase
(continue)
Lock Setup
Lock Setup
Lock Setup
Erase Suspend Read Array
Erase Suspend Read Array
Erase Suspend Read Array
Erase Suspend Read Array
Read
Ststus
Read CFI
Query
Elect.Sg.
Erase
Suspend
Read
Erase
Suspend
Read CFI
Query
Erase
Suspend
Read Array
Erase
(continue)
Elect.Sg.
Erase
Suspend
Read
Erase
Suspend
Read
Erase
Suspend
Read CFI
Query
Erase
(continue)
Elect.Sg.
Elect.Sg.
Erase
Suspend
Read CFI
Query
Erase
Suspend
Read
Erase
Suspend
Read CFI
Query
Erase
(continue)
Lock Setup
Lock Setup
Elect.Sg.
Erase
(complete) Elect.Sg.
Read
Read CFI
Query
Prot. Prog.
Setup
Read Array
1. Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.
75/77
Revision history
M28W640FCT, M28W640FCB
Revision history
Table 34. Document revision history
Date
Version
Revision details
24-May-2004
0.1
First Issue
Figure 2: TSOP connections and Figure 3: TFBGA connections (top
view through package) updated.
23-Aug-2004
08-Apr-2005
0.2
1.0
Datasheet maturity changed to PRELIMINARY DATA.
TSOP48 Package Mechanical Data updated in Table 20: TSOP48 - 48
lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data.
Document status promoted from Preliminary Data to full Datasheet.
tGLQV value changed for 100ns speed class (codified as 10 in part
numbering scheme) in Table 16: Read AC characteristics.
21-Aug-2006
23-Oct-2006
2
3
Blank and T options removed from below Option in Table 22 and
Table 23.
Packages are ECOPACK® compliant.
The 0.13µm technology was removed from the device options of
Table 22: Ordering information scheme.
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M28W640FCT, M28W640FCB
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相关型号：
M28W640FCT10ZB1T
4MX16 FLASH 3V PROM, 100ns, PBGA48, 6.39 X 10.50 MM, 0.75 PITCH, TFBGA-48
STMICROELECTR
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