M28010-15WBA6 [STMICROELECTRONICS]
128KX8 EEPROM 3V, 150ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32;
| 型号： | M28010-15WBA6 |
| 厂家： | 
ST |
| 描述： | 128KX8 EEPROM 3V, 150ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总23页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M28010
1 Mbit (128K x 8) Parallel EEPROM
With Software Data Protection
PRELIMINARY DATA
■ Fast Access Time: 100 ns
■ Single Supply Voltage:
– 4.5 V to 5.5 V for M28010
– 2.7 V to 3.6 V for M28010-W
– 1.8 V to 2.4 V for M28010-R
■ Low Power Consumption
32
■ Fast BYTE and PAGE WRITE (up to 128 Bytes)
■ Enhanced Write Detection and Monitoring:
– Data Polling
1
PDIP32 (BA)
– Toggle Bit
– Page Load Timer Status
■ JEDEC Approved Bytewide Pin-Out
■ Software Data Protection
■ Hardware Data Protection
TSOP32 (NA)
8 x 20 mm
■ Software Chip Erase
PLCC32 (KA)
■ 100000 Erase/Write Cycles (minimum)
■ Data Retention (minimum): 10 Years
DESCRIPTION
The M28010 devices consist of 128Kx8 bits of low
power, parallel EEPROM, fabricated with
STMicroelectronics’ proprietary double polysilicon
CMOS technology. The devices offer fast access
time, with low power dissipation, and require a
single voltage supply (5V, 3V or 2V, depending on
the option chosen).
Figure 1. Logic Diagram
V
CC
17
8
A0-A16
DQ0-DQ7
Table 1. Signal Names
A0-A16
Address Input
Data Input / Output
Write Enable
W
M28010
DQ0-DQ7
E
W
E
G
Chip Enable
G
Output Enable
Supply Voltage
V
SS
V
CC
AI02221
V
Ground
SS
February 2000
1/23
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M28010
Figure 2C. TSOP Connections
Figure 2A. DIP Connections
A11
A9
1
32
G
DU
A16
A15
A12
A7
1
2
3
4
5
6
7
8
9
32
31
V
CC
W
A10
E
A8
30 DU
29 A14
28 A13
27 A8
26 A9
25 A11
A13
A14
DU
W
DQ7
DQ6
DQ5
DQ4
DQ3
A6
A5
V
CC
DU
8
9
25
24
A4
M28010
M28010
V
A3
24
23 A10
22
G
SS
A16
A15
A12
A7
DQ2
DQ1
DQ0
A0
A2 10
A1 11
E
A0 12
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
DQ0 13
DQ1 14
DQ2 15
A6
A1
A5
A2
A4
16
17
A3
V
16
SS
AI02222
AI02224
Note: 1. DU = Do Not Use
Note: 1. DU = Do Not Use
Figure 2B. PLCC Connections
data retention. The organization of the data in a 4
byte (32-bit) “word” format leads to significant
savings in power consumption. Once a byte has
been read, subsequent byte read cycles from the
same “word” (with addresses differing only in the
two least significant bits) are fetched from the
previously loaded Read Buffer, not from the
memory array. As a result, the power consumption
for these subsequent read cycles is much lower
than the power consumption for the first cycle. By
careful design of the memory access patterns, a
50% reduction in the power consumption is
possible.
1 32
A7
A14
A13
A8
A6
A5
A4
A9
A3
A2
9
M28010
25 A11
G
A1
A10
E
SIGNAL DESCRIPTION
A0
The external connections to the device are
summarized in Table 1, and their use in Table 3.
DQ0
DQ7
17
Addresses (A0-A16). The address inputs are
used to select one byte from the memory array
during a read or write operation.
AI02223
Data In/Out (DQ0-DQ7). The contents of the data
byte are written to, or read from, the memory array
through the Data I/O pins.
Note: 1. DU = Do Not Use
The device has been designed to offer a flexible
microcontroller interface, featuring both hardware
and software hand-shaking, with Data Polling and
Toggle Bit. The device supports a 128 byte Page
Write operation. Software Data Protection (SDP)
is also supported, using the standard JEDEC
algorithm.
Chip Enable (E). The chip enable input must be
held low to enable read and write operations.
When Chip Enable is high, power consumption is
reduced.
Output Enable (G). The Output Enable input
controls the data output buffers, and is used to
initiate read operations.
The M28010 is designed for applications requiring
as much as 100,000 write cycles and ten years of
2/23
M28010
1
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
°C
V
TA
TSTG
VCC
VIO
Ambient Operating Temperature
–40 to 85
–65 to 150
Storage Temperature
Supply Voltage
–0.3 to V
+1
CCMAX
–0.3 to V +0.6
Input or Output Voltage (except A9)
Input Voltage
V
CC
VI
–0.3 to 4.5
2000
V
2
VESD
V
Electrostatic Discharge Voltage (Human Body model)
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
Figure 3. Block Diagram
ADDRESS
LATCH
A7-A16
(Page Address)
1Mbit ARRAY
ADDRESS
LATCH
A0-A6
LATCH PAGE
Y DECODE
V
GEN
PP
SENSE PAGE & DATA LATCH
V
GEN
READ
E
PROGRAMMING
STATE
CONTROL
LOGIC
(1)
G
ECC
& MULTIPLEXER
MACHINE
W
I/O BUFFERS
DQ0-DQ7
AI02225
3/23
M28010
1
Table 3. Operating Modes
Mode
E
G
W
DQ0-DQ7
Data Out
V
V
V
IH
Read
IL
IL
IL
Write
V
V
V
V
Data In
IH
IL
Stand-by / Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
X
X
Hi-Z
IH
V
X
X
Data Out or Hi-Z
Data Out or Hi-Z
Hi-Z
IH
V
X
X
X
IL
V
X
IH
Note: 1. X = V or V
IH
.
IL
Write Enable (W). The Write Enable input controls
whether the addressed location is to be read, from
or written to.
V
threshold (V >V ), write access to the
WI CC WI
memory is allowed after a time-out t
specified in Table 4A to Table 4C.
, as
PUW
Further protection against data corruption is
offered by the E and W low pass filters: any glitch,
on the E and W inputs, with a pulse width less than
10 ns (typical) is internally filtered out to prevent
inadvertent write operations to the memory.
DEVICE OPERATION
In order to prevent data corruption and inadvertent
write operations, an internal V
inhibits the Write operations if the V
comparator
voltage is
CC
CC
lower than V (see Table 4A to Table 4C). Once
WI
the voltage applied on the V
pin goes over the
CC
1
Table 4A. Power-Up Timing for M28010 (5V range)
(T = –40 to 85 °C; V = 4.5 to 5.5 V)
A
CC
Symbol
Parameter
Min.
5
Max.
Unit
ms
ms
V
t
Time Delay to Read Operation
Time Delay to Write Operation (once VCC ≥ VWI
Write Inhibit Threshold
PUR
t
)
5
PUW
VWI
3.0
4.2
Note: 1. Sampled only, not 100% tested.
1
Table 4B. Power-Up Timing for M28010-W (3V range)
(T = –40 to 85 °C; V = 2.7 to 3.6 V)
A
CC
Symbol
Parameter
Min.
5
Max.
Unit
ms
ms
V
t
Time Delay to Read Operation
Time Delay to Write Operation (once VCC ≥ VWI
Write Inhibit Threshold
PUR
t
)
5
PUW
VWI
2.0
2.6
Note: 1. Sampled only, not 100% tested.
1
Table 4C. Power-Up Timing for M28010-R (2V range)
(T = –40 to 85 °C; V = 1.8 to 2.4 V)
A
CC
Symbol
Parameter
Min.
5
Max.
Unit
ms
ms
V
t
Time Delay to Read Operation
Time Delay to Write Operation (once VCC ≥ VWI
Write Inhibit Threshold
PUR
t
)
5
PUW
VWI
1.2
1.7
Note: 1. Sampled only, not 100% tested.
4/23
M28010
Read
shown in Figure 12 and Figure 13). The address is
latched during the falling edge of W or E (which
ever occurs later) and the data is latched on the
rising edge of W or E (which ever occurs first).
The device is accessed like a static RAM. When E
and G are low, and W is high, the contents of the
addressed location are presented on the I/O pins.
Otherwise, when either G or E is high, the I/O pins
revert to their high impedance state.
After a delay, t
, that cannot be shorter than
WLQ5H
the value specified in Table 9A to Table 9C, the
internal write cycle starts. It continues, under
internal timing control, until the write operation is
complete. The commencement of this period can
be detected by reading the Page Load Timer
Status on DQ5. The end of the internal write cycle
Write
Write operations are initiated when both W and E
are low and G is high. The device supports both
W-controlled and E-controlled write cycles (as
Figure 4. Software Data Protection Enable Algorithms (with or without Memory Write)
SDP is Disabled and Application
needs to Enable it, and Write Data
SDP is Disabled and
Application needs to Enable it
Write AAh in
Write AAh in
Address 5555h
Address 5555h
Page Write
Timing
Write 55h in
Address 2AAAh
Write 55h in
Address 2AAAh
Page Write
Timing
Write A0h in
Address 5555h
Write A0h in
Address 5555h
Write
is enabled
Time Out (t
)
WLQ5H
Write data
in any addresses
within one page
Waitfor write completion (t
SDP is set
)
Q5HQ5X
Time Out (t
)
WLQ5H
Write AAh in
Address 5555h
Waitfor write completion (t
)
Q5HQ5X
Write 55h in
Address 2AAAh
DATA has been written
and SDP is Enabled
Page Write
Timing
Write A0h in
Address 5555h
Write
is enabled
Write data
in any addresses
within one page
Time Out (t
)
WLQ5H
Waitfor write completion (t
)
Q5HQ5X
DATA has been written
and SDP is Enabled
AI02227B
5/23
M28010
Figure 5. Software Data Protection Disable Algorithms (with or without Memory Write)
SDP is Enabled and
SDP is Enabled and
Application needs to Disable it
Application needs to Write Data
Write AAh in
Write AAh in
Address 5555h
Address 5555h
Write 55h in
Write 55h in
Address 2AAAh
Address 2AAAh
Write 80h in
Write 80h in
Address 5555h
Address 5555h
Page Write
Timing
Page Write
Timing
Write AAh in
Write AAh in
Address 5555h
Address 5555h
Write 55h in
Write 55h in
Address 2AAAh
Address 2AAAh
Write 20h in
Write 20h in
Address 5555h
Address 5555h
Write data
in any addresses
within one page
Time Out (t
)
Physical
Write
Instructions
WLQ5H
Wait for writecompletion (t
)
Q5HQ5X
Time Out (t
)
WLQ5H
SDP is Disabled
Waitfor write completion (t
)
Q5HQ5X
DATA has been written
and SDP is Disabled
AI02226B
can be detected by reading the status of the Data
Polling and the Toggle Bit functions on DQ7 and
DQ6.
internally timed, and continues, uninterrupted,
until completion.
All bytes must be located on the same page
address (A16-A7 must be the same for all bytes).
Otherwise, the Page Write operation is not
executed. The Page Write Abort event is indicated
to the application via DQ1 (as described on page
8).
As with the single byte Write operation, described
above, the DQ5, DQ6 and DQ7 lines can be used
to detect the beginning and end of the internally
controlled phase of the Page Write cycle.
Page Write
The Page Write mode allows up to 128 bytes to be
written on a single page in a single go. This is
achieved through a series of successive Write
operations, no two of which are separated by more
than the t
value (as specified in Table 9A to
WLQ5H
Table 9C).
The page write can be initiated during any byte
write operation. Following the first Byte Write
instruction, the host may send another address
and data with a minimum data transfer rate of:
Software Data Protection (SDP)
The device offers a software-controlled write-
protection mechanism that allows the user to
inhibit all write operations to the device, including
chip erase. This can be useful for protecting the
1/t
.
WLQ5H
The internal write cycle can start at any instant
after t
6/23
. Once initiated, the write operation is
WLQ5H
M28010
Figure 6. Software Chip Erase Algorithm
Figure 7. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Write AAh in
Address 5555h
DP
TB
PLTS
X
X
X
PWA SDP
Write 55h in
Address 2AAAh
DP
TB
= Data Polling
= Toggle Bit
PLTS = Page Load Timer Status
Write 80h in
Address 5555h
X
= undefined
PWA
SDP
= Page Write Abort
= Software Data Protection
Page Write
Timing
AI02486B
Write AAh in
Address 5555h
Write 55h in
Address 2AAAh
Figure 8. Software Data Protection Status Read
Algorithm
Write 10h in
Address 5555h
Write AAh in
Address 5555h
Time Out (t
)
WLQ5H
Page Write
Write 55h in
Timing
Address 2AAAh
Waitfor write completion (t
)
Q5HQ5X
Write 20h in
Address 5555h
Whole Array has been Set to FFh
Read SDP
on DQ0
AI02236C
Write xxh in
Address xxxxh
memory from inadvertent write cycles that may
occur during periods of instability (uncontrolled
bus conditions when excessive noise is detected,
or when power supply levels are outside their
specified values).
Normal User Mode
By default, the device is shipped in the
“unprotected” state: the memory contents can be
freely changed by the user. Once the Software
Data Protection Mode is enabled, all write
commands are ignored, and have no effect on the
memory contents.
The device remains in this mode until a valid
Software Data Protection disable sequence is
received. The device reverts to its “unprotected”
state.
The status of the Software Data Protection
(enabled or disabled) is represented by a non-
volatile latch, and is remembered across periods
of the power being off.
The Software Data Protection Enable command
consists of the writing of three specific data bytes
to three specific memory locations (each location
being on a different page), as shown in Figure 4.
AI02237B
Similarly, to disable the Software Data Protection,
the user has to write specific data bytes into six
different locations, as shown in Figure 5. This
complex series of operations protects against the
chance of inadvertent enabling or disabling of the
Software Data Protection mechanism.
When SDP is enabled, the memory array can still
have data written to it, but the sequence is more
complex (and hence better protected from
inadvertent use). The sequence is as shown in
Figure 5. This consists of an unlock key, to enable
the write action, at the end of which the SDP
continues to be enabled. This allows the SDP to
be enabled, and data to be written, within a single
Write cycle (t ).
WC
7/23
M28010
Software Chip Erase
addressed memory byte. This indicates that the
device is again available for new Read and Write
operations.
The device can be erased (with all bytes set to
FFh) by using a six-byte software command code.
This operation can be initiated only if the user
loads, with a Page Write addressing mode, six
specific data bytes to six specific locations (as
shown in Figure 6). The complexity of the
sequence has been designed to guard against
inadvertent use of the command.
Page Load Timer Status bit (DQ5). An internal
timer is used to measure the period between
successive Write operations, up to t
WLQ5H
(defined in Table 9A to Table 9C). The DQ5 line is
held low to show when this timer is running (hence
showing that the device has received one write
operation, and is waiting for the next). The DQ5
line is held high when the counter has overflowed
(hence showing that the device is now starting the
internal write to the memory array).
Page Write Abort bit (DQ1). During a page write
operation, the A16 to A7 signals should be kept
constant. They should not change while
successive data bytes are being transferred to the
internal latches of the memory device. If a change
occurs on any of the pins, A16 to A7, during the
page write operation (that is, before the falling
edge of W or E, which ever occurs later), the
internal write cycle is not started, and the internal
circuitry is completely reset.
Status Bits
The devices provide five status bits (DQ7, DQ6,
DQ5, DQ1 and DQ0) for use during write
operations. These allow the application to use the
write time latency of the device for getting on with
other work. These signals are available on the I/O
port bits DQ7, DQ6, DQ5, DQ1 and DQ0 (but only
during the internal write cycle, t
Data Polling bit (DQ7). The internally timed write
cycle starts as soon as t (defined in Table
9A to Table 9C) has elapsed since the previous
byte was latched in to the memory. The value of
the DQ7 bit of this last byte, is used as a signal
throughout this write operation: it is inverted while
the internal write operation is underway, and is
inverted back to its original value once the
operation is complete.
).
Q5HQ5X
WLQ5H
The abort signal can be observed on the DQ1 pin,
using a normal read operation. This can be
performed at any time during the byte load cycle,
t
, or while the W input is being held high
WLQ5H
Toggle bit (DQ6). The device offers another way
for determining when the internal write cycle is
running. During the internal write cycle, DQ6
toggles from ’0’ to ’1’ and ’1’ to ’0’ (the first read
value being ’0’) on subsequent attempts to read
any byte of the memory. When the internal write
cycle is complete, the toggling is stopped, and the
values read on DQ7-DQ0 are those of the
between two load cycles. The default value of DQ1
is initially set to ’0’ and changes to ’1’ if the internal
circuitry has detected a change on any of the
address pins A16 to A7. This PWA bit can be
checked regardless of whether Software Data
Protection is enabled or disabled.
Table 5A. Read Mode DC Characteristics for M28010 (5V range)
(T = –40 to 85 °C; V = 4.5 to 5.5 V)
A
CC
Symbol
Parameter
Test Condition
Min.
Max.
5
Unit
µA
µA
mA
mA
mA
µA
V
0 V ≤ V ≤ V
ILI
Input Leakage Current
Output Leakage Current
IN
CC
ILO
0 V ≤ V
≤ V
5
OUT
CC
E = V , G = V , f = 0.1 MHz
2
IL
IL
1
E = V , G = V , f = 5 MHz
Supply Current (CMOS inputs)
22
40
50
0.8
ICC
IL
IL
E = V , G = V , f = 10 MHz
IL
IL
1
Supply Current (Stand-by) CMOS
Input Low Voltage
E > V – 0.3 V
CC
ICC1
VIL
VIH
VOL
VOH
–0.3
2
V
+ 0.3
Input High Voltage
V
CC
I
= 2.1 mA
Output Low Voltage
0.4
V
OL
I
= –400 µA
Output High Voltage
2.4
V
OH
Note: 1. All inputs and outputs open circuit.
8/23
M28010
Table 5B. Read Mode DC Characteristics for M28010-W (3V range)
(T = –40 to 85 °C; V = 2.7 to 3.6 V)
A
CC
Symbol
Parameter
Test Condition
Min.
Max.
Unit
µA
0 V ≤ V ≤ V
ILI
Input Leakage Current
Output Leakage Current
5
5
IN
CC
0 V ≤ V
≤ V
CC
ILO
µA
OUT
E = V , G = V , f = 0.1 MHz
2
mA
mA
mA
IL
IL
1
E = V , G = V , f = 5 MHz
Supply Current (CMOS inputs)
15
26
IL
IL
ICC
E = V , G = V , f = 10 MHz
IL
IL
1
E > V – 0.3 V
Supply Current (Stand-by) CMOS
Input Low Voltage
30
µA
V
ICC1
CC
VIL
VIH
VOL
VOH
–0.3
2
0.6
V
+ 0.3
Input High Voltage
V
CC
I
= 1.6 mA
Output Low Voltage
0.45
V
OL
I
= –100 µA
Output High Voltage
2.4
V
OH
Note: 1. All inputs and outputs open circuit.
Table 5C. Read Mode DC Characteristics for M28010-R (2V range)
(T = –40 to 85 °C; V = 1.8 to 2.4 V)
A
CC
Symbol
Parameter
Test Condition
Min.
Max.
Unit
µA
0 V ≤ V ≤ V
ILI
Input Leakage Current
Output Leakage Current
5
5
IN
CC
ILO
0 V ≤ V ≤ V
OUT CC
µA
E = V , G = V , f = 0.1 MHz, V = 2.4 V
2
mA
mA
IL
IL
CC
1
Supply Current (CMOS inputs)
ICC
E = V , G = V , f = 5 MHz, V = 2.4 V
12
IL
IL
CC
1
E > V – 0.3 V
Supply Current (Stand-by) CMOS
Input Low Voltage
30
µA
V
ICC1
CC
VIL
VIH
VOL
VOH
–0.3
0.2
V
–0.3
CC
V
+0.3
CC
Input High Voltage
V
I
= 0.4 mA
Output Low Voltage
0.15
V
OL
I
= –100 µA
V
–0.15
CC
Output High Voltage
V
OH
Note: 1. All inputs and outputs open circuit.
Software Data Protection bit (DQ0). Reading the
SDP bit (DQ0) allows the user to determine
whether the Software Data Protection mode has
been enabled (SDP=1) or disabled (SDP=0). The
SDP bit (DQ0) can be read by using a dedicated
algorithm (as shown in Figure 8), or can be
combined with the reading of the DP bit (DQ7), TB
bit (DQ6) and PLTS bit (DQ5).
9/23
M28010
1
Table 6. Input and Output Parameters (T = 25 °C, f = 1 MHz)
A
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0 V
Min.
Max.
6
Unit
pF
COUT
VOUT = 0 V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 7. AC Measurement Conditions
Figure 10. AC Testing Equivalent Load Circuit
Input Rise and Fall Times
≤ 5 ns
0 V to V
Input Pulse Voltages
CC
V
/2
CC
Input and Output Timing Ref. Voltages
I
OL
DEVICE
UNDER
TEST
Figure 9. AC Testing Input Output Waveforms
OUT
I
OH
V
CC
C
= 30pF
L
V
/2
CC
0V
AI02228
C
includes JIG capacitance
L
AI02578
Table 8A. Read Mode AC Characteristics for M28010 (5V range)
(T = –40 to 85 °C; V = 4.5 to 5.5 V)
A
CC
M28010
Test
Condit
ion
Symbol
Alt.
Parameter
–10
–12
Unit
Min
Max
Min
Max
E = V ,
IL
t
t
ACC
Address Valid to Output Valid
100
120
ns
AVQV
G = V
G = V
E = V
IL
t
t
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
100
40
120
45
ns
ns
ns
ELQV
CE
IL
t
t
GLQV
OE
IL
1
t
G = V
0
0
40
0
0
45
t
DF
IL
IL
EHQZ
1
t
E = V
Output Enable High to Output Hi-Z
40
45
ns
ns
t
DF
GHQZ
E = V ,
Address Transition to Output
Transition
IL
t
t
0
0
AXQX
OH
G = V
IL
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
10/23
M28010
Table 8B. Read Mode AC Characteristics for M28010-W (3V range)
(T = –40 to 85 °C; V = 2.7 to 3.6 V)
A
CC
M28010-W
–12
Test
Condit
ion
Symbol
Alt.
Parameter
–10
–15
Max
Unit
Min
Max
Min
Max
Min
E = V ,
G = V
IL
t
t
ACC
Address Valid to Output Valid
100
120
150
ns
AVQV
IL
IL
IL
t
t
G = V
Chip Enable Low to Output Valid
100
70
120
80
150
100
ns
ns
ELQV
CE
t
t
Output Enable Low to Output Valid E = V
GLQV
OE
1
t
t
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
G = V
0
0
50
50
0
0
60
60
0
0
70
70
ns
ns
t
DF
DF
IL
EHQZ
GHQZ
1
E = V
t
IL
E = V ,
Address Transition to Output
Transition
IL
t
t
0
0
0
ns
AXQX
OH
G = V
IL
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Table 8C. Read Mode AC Characteristics for M28010-R (2V range)
(T = –40 to 85 °C; V = 1.8 to 2.4 V)
A
CC
M28010-R
Test
Condit
ion
Symbol
Alt.
Parameter
–20
–25
Unit
Min
Max
Min
Max
E = V ,
G = V
IL
t
t
ACC
Address Valid to Output Valid
200
250
ns
AVQV
IL
IL
IL
t
t
G = V
Chip Enable Low to Output Valid
200
80
250
90
ns
ns
ELQV
CE
t
t
Output Enable Low to Output Valid E = V
GLQV
OE
1
t
t
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
G = V
0
0
50
50
0
0
60
60
ns
ns
t
DF
DF
IL
EHQZ
GHQZ
1
E = V
t
IL
E = V ,
Address Transition to Output
Transition
IL
t
t
0
0
ns
AXQX
OH
G = V
IL
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
11/23
M28010
Figure 11. Read Mode AC Waveforms (with Write Enable, W, high)
A0-A16
E
VALID
tAVQV
tAXQX
tGLQV
tEHQZ
tGHQZ
G
tELQV
Hi-Z
DQ0-DQ7
DATA OUT
AI02229
Note: 1. Write Enable (W) = V
IH
Table 9A. Write Mode AC Characteristics for M28010 (5V range)
(T = –40 to 85 °C; V = 4.5 to 5.5 V)
A
CC
M28010
Max
Symbol
Alt.
Parameter
Test Condition
E = V , G = V
IH
Unit
Min
0
t
t
t
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Write Enable Low
Output Enable High to Write Enable Low
Output Enable High to Chip Enable Low
Write Enable Low to Chip Enable Low
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Chip Enable Low to Chip Enable High
Write Enable High to Chip Enable High
Write Enable High to Output Enable Low
Chip Enable High to Write Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Time-out after the last byte write
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ms
ns
ns
AVWL
AS
AS
IL
t
G = V , W= V
IH IL
0
AVEL
ELWL
t
t
t
G = V
E = V
0
CES
IH
IL
t
0
GHWL
OES
t
t
W = V
IL
0
GHEL
OES
WES
t
t
G = V
IH
0
WLEL
t
t
70
70
100
0
WLAX
AH
t
t
ELAX
ELEH
WHEH
AH
t
t
WP
t
t
CEH
OEH
t
t
0
WHGL
EHWH
WHDX
t
t
t
0
WEH
t
0
DH
t
t
0
EHDX
DH
t
t
WPH
50
100
150
WHWL
t
t
WLWH
WP
t
t
BLC
WLQ5H
Byte Write Cycle time
5
t
t
WC
Q5HQ5X
Page Write Cycle time (up to 128 bytes)
Data Valid before Write Enable High
Data Valid before Chip Enable High
10
t
t
50
50
DVWH
DS
DS
t
t
DVEH
12/23
M28010
Table 9B. Write Mode AC Characteristics for M28010-W (3V range)
(T = –40 to 85 °C; V = 2.7 to 3.6 V)
A
CC
M28010-W
Min Max
Symbol
Alt.
Parameter
Test Condition
Unit
t
t
E = V , G = V
IH
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Write Enable Low
Output Enable High to Write Enable Low
Output Enable High to Chip Enable Low
Write Enable Low to Chip Enable Low
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Chip Enable Low to Chip Enable High
Write Enable High to Chip Enable High
Write Enable High to Output Enable Low
Chip Enable High to Write Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Time-out after the last byte write
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ms
ns
ns
AVWL
AS
IL
t
t
G = V , W= V
AVEL
AS
IH
IL
t
t
G = V
0
ELWL
CES
IH
t
t
E = V
IL
0
GHWL
OES
t
t
W = V
IL
0
GHEL
OES
t
t
G = V
0
WLEL
WLAX
WES
IH
t
t
70
70
100
0
AH
t
t
ELAX
ELEH
WHEH
AH
t
t
WP
t
t
CEH
OEH
t
t
t
t
0
WHGL
0
EHWH
WHDX
WEH
t
t
0
DH
t
t
0
EHDX
DH
t
t
50
100
150
WHWL
WPH
t
t
WLWH
WP
t
t
BLC
WLQ5H
Byte Write Cycle time
5
t
t
WC
Q5HQ5X
Page Write Cycle time (up to 128 bytes)
Data Valid before Write Enable High
Data Valid before Chip Enable High
10
t
t
80
80
DVWH
DS
DS
t
t
DVEH
13/23
M28010
Table 9C. Write Mode AC Characteristics for M28010-R (2V range)
(T = –40 to 85 °C; V = 1.8 to 2.4 V)
A
CC
M28010-R
Symbol
Alt.
Parameter
Test Condition
Unit
Min
Max
t
t
E = V , G = V
IH
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Write Enable Low
Output Enable High to Write Enable Low
Output Enable High to Chip Enable Low
Write Enable Low to Chip Enable Low
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Chip Enable Low to Chip Enable High
Write Enable High to Chip Enable High
Write Enable High to Output Enable Low
Chip Enable High to Write Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Time-out after the last byte write
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ms
ns
ns
AVWL
AS
IL
t
t
G = V , W= V
AVEL
AS
IH
IL
t
t
G = V
0
ELWL
CES
IH
t
t
E = V
0
GHWL
OES
IL
t
t
W = V
0
GHEL
OES
WES
IL
t
t
G = V
0
WLEL
IH
t
t
120
120
120
0
WLAX
AH
t
t
t
AH
ELAX
t
ELEH
WP
t
t
WHEH
CEH
OEH
t
t
t
t
0
WHGL
0
EHWH
WHDX
WEH
t
t
0
DH
t
t
0
EHDX
DH
t
t
100
120
150
WHWL
WPH
t
t
WLWH
WP
t
t
BLC
WLQ5H
Byte Write Cycle time
5
t
t
WC
WHRH
Page Write Cycle time (up to 128 bytes)
Data Valid before Write Enable High
Data Valid before Chip Enable High
10
t
t
120
120
DVWH
DS
DS
t
t
DVEH
14/23
M28010
Figure 12. Write Mode AC Waveforms (Write Enable, W, controlled)
A0-A16
E
VALID
tAVWL
tELWL
tGHWL
tWLAX
tWHEH
tWHGL
G
tWLWH
W
tWHWL
DATA IN
tDVWH
DQ0-DQ7
tWHDX
AI02230
Figure 13. Write Mode AC Waveforms (Chip Enable, E, controlled)
A0-A16
E
VALID
tAVEL
tGHEL
tWLEL
tELAX
tELEH
G
tEHGL
W
tEHWH
DATA IN
tDVEH
DQ0-DQ7
tEHDX
AI02231
15/23
M28010
Figure 14. Page Write Mode AC Waveforms (Write Enable, W, controlled)
A0-A16
Addr 0
Addr 1
Addr 2
Addr n
E
G
tWHWL
W
tWLWH
DQ0-DQ7 (in)
DQ5 (out)
Byte 0
Byte 1
Byte 2
Byte n
tWLQ5H
tQ5HQ5X
AI02829B
Figure 15. Software Protected Write Cycle Waveforms
A0-A6
Byte Add 0 Byte Add n
5555h
2AAAh
5555h
1
A7-A16
Page Add
E
G
tWHWL
W
tWLWH
tDVWH
55h
tWHDX
DQ0-DQ7
AAh
A0h
Byte 0
Byte n
AI02233B
Note: 1. A16 to A7 must specify the same page address during each high-to-low transition of W (or E). G must be high only when W and E
are both low.
16/23
M28010
Figure 16. Data Polling Sequence Waveforms
A0-A16
Address of the last byte of the Page Write instruction
E
G
tWHGL
W
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
LAST BYTE
LOADED
INTERNAL WRITE SEQUENCE
OR
TIME BETWEEN TWO CONSECUTIVE
BYTES LOADING
READY
AFTER INTERNAL
WRITE SEQUENCE
AI02234
Figure 17. Toggle Bit Sequence Waveforms
A0-A16
Address of the last byte of the Page Write instruction
E
G
W
DQ6
(1)
LAST BYTE
LOADED
TOGGLE
INTERNAL WRITE SEQUENCE
OR
READY
AFTER INTERNAL
WRITE SEQUENCE
TIME BETWEEN TWO CONSECUTIVE
BYTES LOADING
AI02235
Note: 1. The Toggle Bit is first set to ‘0’.
17/23
M28010
Table 10. Ordering Information Scheme
Example:
M28010
–10
W
KA
6
T
Option
T
Tape & Reel Packing
Speed
100 ns
120 ns
Temperature Range
0 to 70 °C
-10
-12
1
1
6
-15
-20
-25
150 ns
200 ns
250 ns
–40 to 85 °C
Operating Voltage
Package
PDIP32
blank 4.5 V to 5.5 V
BA
KA
W
R
2.7 V to 3.6 V
1.8 V to 2.4 V
PLCC32
NA TSOP32: 8 x 20mm
Note: 1. This temperature range on request only.
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all ‘1’s (FFh).
The notation used for the device number is as
shown in Table 10. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact the ST
Sales Office nearest to you.
18/23
M28010
Table 11. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data
mm
Min.
–
inches
Min.
–
Symbol
Typ.
Max.
5.08
–
Typ.
Max.
0.200
–
A
A1
A2
B
0.38
3.56
0.38
–
0.015
0.140
0.015
–
4.06
0.51
–
0.160
0.020
–
B1
C
1.52
0.060
0.20
41.78
–
0.30
42.04
–
0.008
1.645
–
0.012
1.655
–
D
D2
E
38.10
15.24
1.500
0.600
–
–
–
–
E1
e1
eA
eB
L
13.59
–
13.84
–
0.535
–
0.545
–
2.54
0.100
0.600
15.24
–
–
–
–
15.24
3.18
1.78
0°
17.78
3.43
2.03
10°
0.600
0.125
0.070
0°
0.700
0.135
0.080
10°
S
α
N
32
32
Figure 18. PDIP32 (BA)
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
Note: 1. Drawing is not to scale.
19/23
M28010
Table 12. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
inches
Min.
0.100
0.060
–
Symbol
Typ.
Min.
2.54
1.52
–
Max.
3.56
2.41
0.38
0.53
0.81
12.57
11.56
10.92
15.11
14.10
13.46
–
Typ.
Max.
0.140
0.095
0.015
0.021
0.032
0.495
0.455
0.430
0.595
0.555
0.530
–
A
A1
A2
B
0.33
0.66
12.32
11.35
9.91
14.86
13.89
12.45
–
0.013
0.026
0.485
0.447
0.390
0.585
0.547
0.490
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.89
0.050
0.035
F
0.00
–
0.25
–
0.000
–
0.010
–
R
N
32
32
Nd
Ne
CP
7
7
9
9
0.10
0.004
Figure 19. PLCC32 (KA)
D
A1
D1
A2
1
N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Note: 1. Drawing is not to scale.
20/23
M28010
Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data
mm
inches
Symbol
Typ.
Min.
Max.
1.20
0.17
1.05
0.27
0.21
20.20
18.50
8.10
–
Typ.
Min.
Max.
0.047
0.006
0.041
0.011
0.008
0.795
0.728
0.319
–
A
A1
A2
B
0.05
0.95
0.15
0.10
19.80
18.30
7.90
–
0.002
0.037
0.006
0.004
0.780
0.720
0.311
–
C
D
D1
E
e
0.50
0.020
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
32
32
CP
0.10
0.004
Figure 20. TSOP32 (NS)
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
A1
α
L
Note: 1. Drawing is not to scale.
21/23
M28010
Table 14. Revision History
Date
Description of Revision
15-Feb-2000
28-Feb-2000
I
t
(max), in Read Mode DC Char table for 5V, changed from 30 µA to 50 µA.
CC1
(min) and t
DVWH
(min), in Write Mode AC Char table for 3V, changed from 50 ns to 80 ns
DVEH
22/23
M28010
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express writtenapproval of STMicroelectronics.
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23/23
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