M27V256-100F6TR [STMICROELECTRONICS]
256 Kbit 32Kb x 8 Low Voltage UV EPROM and OTP EPROM; 256千位32Kb的×8低电压UV EPROM和OTP EPROM
| 型号： | M27V256-100F6TR |
| 厂家： | 
ST |
| 描述： | 256 Kbit 32Kb x 8 Low Voltage UV EPROM and OTP EPROM |
| 文件： | 总15页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M27V256
256 Kbit (32Kb x 8) Low Voltage UV EPROM and OTP EPROM
■ LOW VOLTAGE READ OPERATION:
3V to 3.6V
■ FAST ACCESS TIME: 90ns
■ LOW POWER CONSUMPTION:
28
– Active Current 10mA at 5MHz
28
– Standby Current 10µA
1
1
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
FDIP28W (F)
PDIP28 (B)
■ PROGRAMMING TIME: 100µs/byte (typical)
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 8Dh
DESCRIPTION
The M27V256 is a low voltage 256 Kbit EPROM
offered in the two ranges UV (ultra violet erase)
and OTP (one time programmable). It is ideally
suited for microprocessor systems and is orga-
nized as 32,768 by 8 bits.
PLCC32 (K)
TSOP28 (N)
8 x 13.4mm
Figure 1. Logic Diagram
The M27V256 operates in the read mode with a
supply voltage as low as 3V. The decrease in op-
erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
The FDIP28W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
V
V
PP
CC
15
8
A0-A14
Q0-Q7
Table 1. Signal Names
E
M27V256
A0-A14
Q0-Q7
E
Address Inputs
Data Outputs
Chip Enable
Output Enable
Program Supply
Supply Voltage
Ground
G
G
V
SS
V
V
V
PP
CC
SS
AI01908
May 1998
1/15
M27V256
Figure 2A. DIP Pin Connections
Figure 2B. LCC Pin Connections
V
1
2
3
4
5
6
7
8
9
28
V
CC
PP
A12
A7
A6
A5
A4
A3
A2
A1
27 A14
26 A13
25 A8
24 A9
23 A11
1 32
A6
A8
A9
A11
NC
G
A5
A4
A3
22
G
M27V256
21 A10
20
A2
A1
A0
NC
Q0
9
M27V256
25
E
A10
E
A0 10
Q0 11
Q1 12
Q2 13
19 Q7
18 Q6
17 Q5
16 Q4
15 Q3
Q7
Q6
17
V
14
SS
AI01909
AI01910
Warning: NC = Not Connected, DU = Dont’t Use.
Figure 2C. TSOP Pin Connections
For applications where the content is programmed
only one time and erasure is not required, the
M27V256 is offered in PDIP28, PLCC32 and
TSOP28 (8 x 13.4 mm) packages.
G
A11
A9
22
21
A10
E
DEVICE OPERATION
The modes of operation of the M27V256 are listed
in the Operating Modes. A single power supply is
required in the read mode. All inputs are TTL lev-
Q7
Q6
Q5
Q4
Q3
A8
A13
A14
els except for V and 12V on A9 for Electronic
PP
Signature.
Read Mode
V
28
1
15
14
CC
M27V256
V
PP
V
The M27V256 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
SS
A12
Q2
Q1
Q0
A0
A1
A2
A7
A6
A5
A4
A3
7
8
(t
(t
of t
) is equal to the delay from E to output
). Data is available at the output after delay
AVQV
ELQV
AI01911
from the falling edge of G, assuming that
GLQV
E has been low and the addresses have been sta-
ble for at least t -t
.
AVQV GLQV
2/15
M27V256
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
Unit
°C
°C
°C
V
(3)
T
A
Ambient Operating Temperature
T
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
BIAS
T
STG
(2)
V
IO
V
–2 to 7
V
CC
(2)
A9 Voltage
–2 to 13.5
–2 to 14
V
V
A9
V
Program Supply Voltage
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
+0.5V with possible overshoot to V
+2V for a period less than 20ns.
CC
CC
Table 3. Operating Modes
Mode
V
E
G
A9
X
Q0-Q7
Data Out
Hi-Z
PP
V
V
V
Read
IL
IL
IL
CC
CC
Output Disable
Program
V
V
V
X
V
IH
IH
V
Pulse
V
V
V
V
X
Data In
Data Out
Hi-Z
IL
PP
PP
PP
Verify
V
V
V
X
IH
IH
IH
IL
V
V
Program Inhibit
Standby
X
IH
X
X
Hi-Z
CC
CC
V
V
V
V
Electronic Signature
Codes
IL
IL
ID
Note: X = V or V , V = 12V ± 0.5V.
IH IL ID
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
Q7
0
Q6
0
Q5
1
Q4
0
Q3
0
Q2
0
Q1
0
Q0
0
Hex Data
20h
V
IL
V
1
0
0
0
1
1
0
1
8Dh
IH
Standby Mode
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
The M27V256 has a standby mode which reduces
the supply current from 10mA to 10µA with low
voltage operation V ≤ 3.6V, see Read Mode DC
CC
Characteristics table for details. The M27V256 is
3/15
M27V256
Table 5. AC Measurement Conditions
High Speed
≤ 10ns
Standard
≤ 20ns
Input Rise and Fall Times
Input Pulse Voltages
0 to 3V
1.5V
0.4V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.4V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01822
AI01823B
(1)
Table 6. Capacitance
Symbol
(T = 25 °C, f = 1 MHz)
A
Parameter
Test Condition
= 0V
Min
Max
6
Unit
pF
C
V
IN
Input Capacitance
Output Capacitance
IN
C
OUT
V
= 0V
OUT
12
pF
Note: Sampled only, not 100% tested.
Two Line Output Control
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and hat the output pins are only active when
data is desired from a particular memory device.
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
System Considerations
The power switching characteristics of Advance
CMOS EPROMs require careful decoupling of the
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
devices. The supply current, I , has three seg-
CC
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
this transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.
For the most efficient use of these two control
lines, Eshould be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
4/15
M27V256
(1)
Table 7. Read Mode DC Characteristics
(TA = 0 to 70°C or –40 to 85°C; V = 3.3V ± 10%; V = V )
CC
CC
PP
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
±10
±10
Unit
µA
I
0V ≤ V ≤ V
LI
IN
CC
I
0V ≤ V
≤ V
OUT CC
µA
LO
E = V , G = V , I
= 0mA,
IL
IL OUT
I
Supply Current
10
mA
CC
f = 5MHz, V ≤ 3.6V
CC
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
1
mA
µA
µA
V
CC1
IH
I
10
10
0.8
E > V – 0.2V, V ≤ 3.6V
CC2
CC
CC
I
V
= V
PP CC
PP
V
Input Low Voltage
–0.3
2
IL
(2)
V
+ 1
Input High Voltage
V
V
CC
IH
V
I
I
= 2.1mA
= –400µA
= –100µA
Output Low Voltage
0.4
V
V
V
OL
OL
Output High Voltage TTL
Output High Voltage CMOS
2.4
OH
OH
V
OH
I
Vcc – 0.7V
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Maximum DC voltage on Output is V +0.5V.
CC
(1)
Table 8A. Read Mode AC Characteristics
(T = 0 to 70 °C or –40 to 85°; V = 3.3V ± 10%; V = V
)
CC
A
CC
PP
M27V256
Unit
(3)
Symbol
Alt
Parameter
Test Condition
-100
Min Max
-90
Min
Max
t
t
Address Valid to Output Valid
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
E = V , G = V
90
90
40
100
100
45
ns
ns
ns
AVQV
ACC
IL
IL
t
t
t
G = V
IL
ELQV
CE
t
E = V
IL
GLQV
(2)
OE
t
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
G = V
0
0
25
25
0
0
30
30
ns
ns
t
DF
IL
EHQZ
(2)
t
E = V
t
DF
IL
GHQZ
Address Transition to Output
Transition
t
t
E = V , G = V
IL IL
0
0
ns
AXQX
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1µF ceramic
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between V and V for every eight devic-
CC
SS
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
capacitor be used on every device between V
CC
and V . This should be a high frequency capaci-
SS
tor of low inherent inductance and should be
5/15
M27V256
(1)
Table 8B. Read Mode AC Characteristics
(T = 0 to 70°C or –40 to 85 °C; V = 3.3V ± 10%; V = Vcc)
A
CC
PP
M27V256
-150
Unit
Symbol Alt
Parameter
Test Condition
-120
-200
Min Max Min Max Min Max
t
t
E = V , G = V
Address Valid to Output Valid
120
120
150
150
200
200
ns
ns
AVQV
ACC
IL
IL
Chip Enable Low to Output
Valid
t
t
t
G = V
IL
ELQV
CE
Output Enable Low to Output
Valid
t
E = V
45
35
35
50
40
40
60
50
50
ns
ns
ns
ns
GLQV
OE
IL
Chip Enable High to Output
Hi-Z
(2)
t
t
t
G = V
0
0
0
0
0
0
0
0
0
t
DF
DF
IL
IL
EHQZ
Output Enable High to Output
Hi-Z
(2)
E = V
t
GHQZ
Address Transition to Output
Transition
t
E = VIL, G = VIL
AXQX
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
VALID
tGLQV
VALID
A0-A14
tAVQV
tAXQX
E
tEHQZ
tGHQZ
G
tELQV
Hi-Z
Q0-Q7
AI00758B
Programming
Although only ’0’s will be programmed, both ’1’s
and ’0’s can be present in the data word. The only
way to change a ’0’ to a ’1’ is by die exposition to
ultraviolet light (UV EPROM). The M27V256 is in
The M27V256 has been designed to be fully com-
patible with the M27C256B and has the same
electronic signature. As a result the M27V256 can
be programmed as the M27C256B on the same
programming equipments applying 12.75V on V
and 6.25V on V by the use of the same PRES-
TO II algorithm. When delivered (and after each
erasure for UV EPROM), all bits of the M27V256
are in the ’1’ state. Data is introduced by selective-
ly programming ’0’s into the desired bit locations.
the programming mode when V
input is at
PP
12.75V, G is at V and E is pulsed to V . The data
PP
IH
IL
to be programmed is applied to 8 bits in parallel to
the data output pins. The levels required for the
CC
address and data inputs are TTL. V is specified
CC
to be 6.25 V ± 0.25 V.
6/15
M27V256
(1)
Table 9. Programming Mode AC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)
A
CC
PP
Symbol
Parameter
Test Condition
Min
Max
±10
50
Unit
µA
mA
mA
V
I
Input Leakage Current
Supply Current
V
≤ V ≤ V
LI
IL
IN
IH
I
CC
I
PP
E = V
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
A9 Voltage
50
IL
V
–0.3
2
0.8
IL
V
V
+ 0.5
CC
V
IH
V
OL
I
= 2.1mA
= –1mA
0.4
V
OL
V
I
OH
3.6
V
OH
V
11.5
12.5
V
ID
Note: V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
(1)
Table 10. Programming Mode AC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V
A
CC
PP
Symbol
Alt
Parameter
Test Condition
Min
2
Max
Unit
µs
µs
µs
µs
µs
µs
µs
ns
t
t
AS
Address Valid to Chip Enable Low
Input Valid to Chip Enable Low
AVEL
t
t
2
QVEL
DS
t
t
V
V
High to Chip Enable Low
High to Chip Enable Low
2
VPHEL
VCHEL
VPS
VCS
PP
CC
t
t
2
t
t
Chip Enable Program Pulse Width
Chip Enable High to Input Transition
Input Transition to Output Enable Low
Output Enable Low to Output Valid
Output Enable High to Output Hi-Z
95
2
105
ELEH
PW
t
t
DH
EHQX
t
t
2
QXGL
GLQV
GHQZ
OES
t
t
100
130
OE
t
t
DFP
0
0
ns
Output Enable High to Address
Transition
t
t
ns
GHAX
AH
Note: V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
7/15
M27V256
Figure 6. rogramming and Verify Modes AC Waveforms
VALID
A0-A14
tAVEL
Q0-Q7
DATA IN
tQVEL
DATA OUT
tEHQX
V
PP
tVPHEL
tVCHEL
tELEH
tGLQV
tGHQZ
tGHAX
V
CC
E
tQXGL
G
PROGRAM
VERIFY
AI00759
Figure 7. Programming Flowchart
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows to pro-
gram the whole array with a guaranteed margin, in
a typical time of 3.5 seconds. Programming with
PRESTO II involves the application of a sequence
of 100µs program pulses to each byte until a cor-
rect verify occurs (see Figure 7). During program-
ming and verify operation, a MARGIN MODE
circuit is automatically activated in order to guar-
antee that each cell is programmed with enough
margin. No overprogram pulse is applied since the
V
= 6.25V, V
= 12.75V
PP
CC
n = 0
E = 100µs Pulse
verify in MARGIN MODE at V much higher than
CC
NO
3.6V provides necessary margin to each pro-
grammed cell.
Program Inhibit
NO
++n
= 25
VERIFY
YES
++ Addr
Programming of multiple M27V256s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27V256 may be common. A TTL low level pulse
YES
Last
NO
FAIL
Addr
applied to a M27V256’s E input, with V at 12.75
PP
YES
V, will program that M27V256. A high level E input
inhibits the other M27V256s from being pro-
grammed.
CHECK ALL BYTES
1st: V
2nd: V
= 6V
= 4.2V
CC
CC
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
AI00760B
at V , E at V , V at 12.75V and V at 6.25V.
IL
IH
PP
CC
8/15
M27V256
On-Board Programming
ERASURE OPERATION (applies for UV EPROM)
The M27V256 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
The erasure characteristics of the M27V256 is
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluo-
rescent lighting could erase a typical M27V256 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27V256 is to be exposed to these
types of lighting conditions for extended periods of
time, it is suggested that opaque labels be put over
the M27V256 window to prevent unintentional era-
sure. The recommended erasure procedure for
the M27V256 is exposure to short wave ultraviolet
light which has wavelength 2537Å. The integrated
dose (i.e. UV intensity x exposure time) for erasure
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am-
bient temperature range that is required when pro-
gramming theM27V256. To activate the ES mode,
the programming equipment must force 11.5V to
12.5V on address line A9 of the M27V256, with
V
= V = 5V. Two identifier bytes may then be
CC
PP
sequenced from the device outputs by toggling ad-
dress line A0 from V to V . All other address
2
IL
IH
should be a minimum of 15 W-sec/cm . The era-
lines must be held at V during Electronic Signa-
IL
sure time with this dosage is approximately 15 to
20 minutes using an ultraviolet lamp with 12000
ture mode. Byte 0 (A0=V ) represents the manu-
IL
facturer code and byte 1 (A0=V ) the device
2
IH
µW/cm power rating. The M27V256 should be
identifier code. For the STMicroelectronics
M27V256, these two identifier bytes are given in
Table 4 and can be read-out on outputs Q0 to Q7.
Note that the M27V256 and M27C256B have the
same identifier bytes.
placed within 2.5 cm (1 inch) of the lamp tubes
during the erasure. Some lamps have a filter on
their tubes which should be removed before era-
sure.
9/15
M27V256
Table 11. Ordering Information Scheme
Example:
M27V256
-90
K
1
TR
Device Type
Speed
(1)
-90
= 90 ns
-100 = 100 ns
-120 = 120 ns
-150 = 150 ns
-200 = 200 ns
Package
F = FDIP28W
B = PDIP28
K = PLCC32
N = TSOP28: 8 x 13.4mm
Temperature Range
1 = –0 to 70 °C
6 = –40 to 85 °C
Option
TR =Tape & Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
10/15
M27V256
Table 12. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
5.72
1.40
4.57
4.50
0.56
–
Typ
Min
Max
0.225
0.055
0.180
0.177
0.022
–
A
A1
A2
A3
B
0.51
3.91
3.89
0.41
–
0.020
0.154
0.153
0.016
–
B1
C
1.45
0.057
0.23
36.50
–
0.30
37.34
–
0.009
1.437
–
0.012
1.470
–
D
D2
E
33.02
15.24
1.300
0.600
–
–
–
–
E1
e
13.06
–
13.36
–
0.514
–
0.526
–
2.54
0.100
0.590
eA
eB
L
14.99
–
–
–
–
16.18
3.18
1.52
–
18.03
0.637
0.125
0.060
–
0.710
S
2.49
–
0.098
–
7.11
0.280
α
4°
11°
4°
11°
N
28
28
Figure 8. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Outline
A2
A3
A1
A
L
α
B1
B
e
C
eA
eB
D2
D
S
N
1
E1
E
FDIPW-a
Drawing is not to scale.
11/15
M27V256
Table 13. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Mechanical Data
mm
Min
–
inches
Min
–
Symb
Typ
Max
5.08
–
Typ
Max
0.200
–
A
A1
A2
B
0.38
3.56
0.38
–
0.015
0.140
0.015
–
4.06
0.51
–
0.160
0.020
–
B1
C
1.52
0.060
0.20
36.83
–
0.30
37.34
–
0.008
1.450
–
0.012
1.470
–
D
D2
E
33.02
15.24
1.300
0.600
–
–
–
–
E1
e1
eA
eB
L
13.59
–
13.84
–
0.535
–
0.545
–
2.54
0.100
0.590
14.99
–
–
–
–
15.24
3.18
1.78
0°
17.78
3.43
2.08
10°
0.600
0.125
0.070
0°
0.700
0.135
0.082
10°
S
α
N
28
28
Figure 9. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
Drawing is not to scale.
12/15
M27V256
Table 14. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data
mm
Min
2.54
1.52
–
inches
Min
0.100
0.060
–
Symb
Typ
Max
3.56
2.41
0.38
0.53
0.81
12.57
11.56
10.92
15.11
14.10
13.46
–
Typ
Max
0.140
0.095
0.015
0.021
0.032
0.495
0.455
0.430
0.595
0.555
0.530
–
A
A1
A2
B
0.33
0.66
12.32
11.35
9.91
14.86
13.89
12.45
–
0.013
0.026
0.485
0.447
0.390
0.585
0.547
0.490
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.89
0.050
0.035
F
0.00
–
0.25
–
0.000
–
0.010
–
R
N
32
32
Nd
Ne
CP
7
7
9
9
0.10
0.004
Figure 10. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline
D
A1
D1
A2
1 N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Drawing is not to scale.
13/15
M27V256
Table 15. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm, Package Mechanical Data
mm
Min
1.00
inches
Min
Symb
Typ
Max
1.25
0.20
1.05
0.30
0.21
13.70
11.90
8.25
-
Typ
Max
0.049
0.008
0.041
0.012
0.008
0.539
0.469
0.325
-
A
A1
A2
B
0.039
0.95
0.037
C
0.10
13.10
11.70
7.90
-
0.004
0.516
0.461
0.311
-
D
D1
E
e
0.55
0.022
L
0.30
0°
0.70
5°
0.012
0°
0.028
5°
α
N
28
28
CP
0.10
0.004
Figure 11. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm, Package Outline
A2
22
21
e
28
1
E
B
7
8
D1
D
A
CP
DIE
C
TSOP-c
A1
α
L
Drawing is not to scale
14/15
M27V256
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