M27C512_07 [STMICROELECTRONICS]
512 Kbit (64K x8) UV EPROM and OTP EPROM; 512千位（ 64K ×8 ） UV EPROM和OTP EPROM
| 型号： | M27C512_07 |
| 厂家： | 
ST |
| 描述： | 512 Kbit (64K x8) UV EPROM and OTP EPROM |
| 文件： | 总22页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M27C512
512 Kbit (64K x8) UV EPROM and OTP EPROM
Features
■ 5V ± 10% supply voltage in read operation
■ Access time: 45 ns
■ Low power “CMOS” consumption:
– Active current 30 mA
28
– Standby current 100 µA
1
■ Programming voltage: 12.75 V ± 0.25 V
■ Programming time around 6 s.
FDIP28W (F)
■ Electronic Signature
– Manufacturer code: 20h
– Device code: 3Dh
■ Packages
®
28
– ECOPACK versions
1
PDIP28 (B)
PLCC32 (C)
Table 1.
Package
PDIP28
Device summary
45 ns
70 ns
90 ns
100 ns
120 ns
150 ns
M27C512-90B6
M27C512-
10C6
M27C512-
12C3
PLCC32
M27C512-70C6
M27C512-90C1
M27C512-
12F1
M27C512-90F1
M27C512-90F6
M27C512-15F1
M27C512-15F6
M27C512-
10F1
FDIP28W M27C512-45XF1 M27C512-70XF1
M27C512-
12F3
May 2007
Rev 3
1/22
www.st.com
1
Contents
M27C512
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Two line output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
System considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PRESTO IIB programming algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Program Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Program Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
4
5
6
7
8
Erasure operation (applies for UV EPROM) . . . . . . . . . . . . . . . . . . . . . . 9
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/22
M27C512
Description
1
Description
The M27C512 is a 512 Kbit EPROM offered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited for applications where fast turn-around
and pattern experimentation are important requirements and is organized as 65536 by 8
bits.
The FDIP28W (window ceramic frit-seal package) has transparent lid which allows the user
to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be
written to the device by following the programming procedure.
For applications where the content is programmed only one time and erasure is not
required, the M27C512 is offered in FDIP28W, PDIP28, and PLCC32 packages. In order to
®
meet environmental requirements, ST offers the M27C512 in ECOPACK packages.
ECOPACK packages are Lead-free. The category of second Level Interconnect is marked
on the package and on the inner box label, in compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 1.
Logic diagram
V
CC
16
8
A0-A15
Q0-Q7
E
M27C512
GV
PP
V
SS
AI00761B
Table 2.
Signal names
Name
Description
Direction
A0-A15
Q0-Q7
E
Address Inputs
Data outputs
Chip Enable
Inputs
Outputs
Input
Input
Supply
Supply
-
GVPP
VCC
VSS
Output Enable / Program Supply
Supply Voltage
Ground
NC
Not Connected Internally
Don’t Use
DU
-
3/22
Description
M27C512
Figure 2.
DIP connections
A15
A12
A7
1
2
3
4
5
6
7
8
9
28
V
CC
27 A14
26 A13
25 A8
24 A9
23 A11
A6
A5
A4
A3
22 GV
PP
21 A10
20
M27C512
A2
A1
E
A0 10
Q0 11
Q1 12
Q2 13
19 Q7
18 Q6
17 Q5
16 Q4
15 Q3
V
14
SS
AI00762
Figure 3.
LCC connections
1 32
M27C512
17
A6
A8
A5
A4
A3
A2
A1
A0
NC
Q0
A9
A11
NC
9
25 GV
PP
A10
E
Q7
Q6
AI00763
4/22
M27C512
Device operation
2
Device operation
The modes of operations of the M27C512 are listed in the Operating Modes table. A single
power supply is required in the read mode. All inputs are TTL levels except for GV and
PP
12V on A9 for Electronic Signature.
2.1
2.2
Read mode
The M27C512 has two control functions, both of which must be logically active in order to
obtain data at the outputs. Chip Enable (E) is the power control and should be used for
device selection. Output Enable (G) is the output control and should be used to gate data to
the output pins, independent of device selection. Assuming that the addresses are stable,
the address access time (t
available at the output after a delay of t
) is equal to the delay from E to output (t
). Data is
AVQV
ELQV
from the falling edge of G, assuming that E has
GLQV
been low and the addresses have been stable for at least t
-t
.
AVQV GLQV
Standby mode
The M27C512 has a standby mode which reduces the active current from 30mA to 100µA
The M27C512 is placed in the standby mode by applying a CMOS high signal to the E input.
When in the standby mode, the outputs are in a high impedance state, independent of the
GV input.
PP
(1)
Table 3.
Operating modes
Mode
E
GVPP
A9
Q7-Q0
Read
VIL
VIL
VIL
VIH
VPP
VPP
X
X
X
Data Out
Hi-Z
Output Disable
Program
V
IL Pulse
X
Data In
Hi-Z
Program Inhibit
Standby
VIH
X
VIH
X
Hi-Z
Electronic Signature
VIL
VIL
VID
Codes
1. X = VIH or VIL, VID = 12V ± 0.5V.
Table 4. Electronic Signature
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0 Hex Data
Manufacturer’s
Code
VIL
VIH
0
0
0
0
1
1
0
1
0
1
0
1
0
0
0
1
20h
3Dh
Device Code
5/22
Device operation
M27C512
2.3
Two line output control
Because EPROMs are usually used in larger memory arrays, the product features a 2 line
control function which accommodates the use of multiple memory connection. The two line
control function allows:
■
■
The lowest possible memory power dissipation,
Complete assurance that output bus contention will not occur.
For the most efficient use of these two control lines, E should be decoded and used as the
primary device selecting function, while G should be made a common connection to all
devices in the array and connected to the READ line from the system control bus. This
ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is required from a particular memory device.
2.4
System considerations
The power switching characteristics of Advanced CMOS EPROMs require careful
decoupling of the devices. The supply current, I , has three segments that are of interest to
CC
the system designer: the standby current level, the active current level, and transient current
peaks that are produced by the falling and rising edges of E. The magnitude of the transient
current peaks is dependent on the capacitive and inductive loading of the device at the
output. The associated transient voltage peaks can be suppressed by complying with the
two line output control and by properly selected decoupling capacitors. It is recommended
that a 0.1µF ceramic capacitor be used on every device between V and V . This should
CC
SS
be a high frequency capacitor of low inherent inductance and should be placed as close to
the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used
between V and V for every eight devices. The bulk capacitor should be located near the
CC
SS
power supply connection point.The purpose of the bulk capacitor is to overcome the voltage
drop caused by the inductive effects of PCB traces.
6/22
M27C512
Device operation
Figure 4.
Programming flowchart
V
= 6.25V, V = 12.75V
PP
CC
SET MARGIN MODE
n = 0
E = 100µs Pulse
NO
NO
++n
= 25
VERIFY
++ Addr
YES
YES
Last
Addr
NO
FAIL
YES
RESET MARGIN MODE
CHECK ALL BYTES
1st: V
2nd: V
= 6V
= 4.2V
CC
CC
AI00738B
2.5
Programming
When delivered (and after each erasure for UV EPROM), all bits of the M27C512 are in the
'1' state. Data is introduced by selectively programming '0's into the desired bit locations.
Although only '0's will be programmed, both '1's and '0's can be present in the data word.
The only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The
M27C512 is in the programming mode when V input is at 12.75V and E is pulsed to V .
PP
IL
The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL. V is specified to be 6.25V ± 0.25V. The
CC
M27C512 can use PRESTO IIB Programming Algorithm that drastically reduces the
programming time (typically less than 6 seconds). Nevertheless to achieve compatibility with
all programming equipments, PRESTO Programming Algorithm can be used as well.
2.6
PRESTO IIB programming algorithm
PRESTO IIB Programming Algorithm allows the whole array to be programmed with a
guaranteed margin, in a typical time of 6.5 seconds. This can be achieved with
STMicroelectronics M27C512 due to several design innovations described in the M27C512
datasheet to improve programming efficiency and to provide adequate margin for reliability.
Before starting the programming the internal MARGIN MODE circuit is set in order to
guarantee that each cell is programmed with enough margin. Then a sequence of 100µs
program pulses are applied to each byte until a correct verify occurs. No overprogram
pulses are applied since the verify in MARGIN MODE provides the necessary margin.
7/22
Device operation
M27C512
2.7
Program Inhibit
Programming of multiple M27C512s in parallel with different data is also easily
accomplished. Except for E, all like inputs including GV of the parallel M27C512 may be
PP
common. A TTL low level pulse applied to a M27C512's E input, with V at 12.75V, will
PP
program that M27C512. A high level E input inhibits the other M27C512s from being
programmed.
2.8
2.9
Program Verify
A verify (read) should be performed on the programmed bits to determine that they were
correctly programmed. The verify is accomplished with G at V . Data should be verified with
IL
t
after the falling edge of E.
ELQV
Electronic Signature
The Electronic Signature (ES) mode allows the reading out of a binary code from an
EPROM that will identify its manufacturer and type. This mode is intended for use by
programming equipment to automatically match the device to be programmed with its
corresponding programming algorithm. The ES mode is functional in the 25°C ± 5°C
ambient temperature range that is required when programming the M27C512. To activate
the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of
the M27C512. Two identifier bytes may then be sequenced from the device outputs by
toggling address line A0 from V to V . All other address lines must be held at V during
IL
IH
IL
Electronic Signature mode. Byte 0 (A0 = V ) represents the manufacturer code and byte 1
IL
(A0 = V ) the device identifier code. For the STMicroelectronics M27C512, these two
IH
identifier bytes are given in <Blue>Table 4. and can be read-out on outputs Q7 to Q0.
8/22
M27C512
Erasure operation (applies for UV EPROM)
3
Erasure operation (applies for UV EPROM)
The erasure characteristics of the M27C512 is such that erasure begins when the cells are
exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted
that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å
range.
Research shows that constant exposure to room level fluorescent lighting could erase a
typical M27C512 in about 3 years, while it would take approximately 1 week to cause
erasure when exposed to direct sunlight. If the M27C512 is to be exposed to these types of
lighting conditions for extended periods of time, it is suggested that opaque labels be put
over the M27C512 window to prevent unintentional erasure. The recommended erasure
procedure for the M27C512 is exposure to short wave ultraviolet light which has wavelength
2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a
2
minimum of 15 W-sec/cm . The erasure time with this dosage is approximately 15 to 20
2
minutes using an ultraviolet lamp with 12000 µW/cm power rating. The M27C512 should be
placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter
on their tubes which should be removed before erasure.
9/22
Maximum rating
M27C512
4
Maximum rating
Stressing the device outside the ratings listed in <Blue>Table 5. may cause permanent
damage to the device. These are stress ratings only, and operation of the device at these, or
any other conditions outside those indicated in the Operating sections of this specification, is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may
affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
Table 5.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
TA
Ambient Operating Temperature(1)
Temperature Under Bias
Storage Temperature
–40 to 125
–50 to 125
–65 to 150
(note 1)
°C
°C
°C
°C
V
TBIAS
TSTG
TLEAD
Lead Temperature during Soldering
Input or Output Voltage (except A9)
Supply Voltage
(2)
VIO
–2 to 7
VCC
–2 to 7
V
(2)
VA9
A9 Voltage
–2 to 13.5
–2 to 14
V
VPP
Program Supply Voltage
V
1. Depends on range.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than
20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less
than 20ns.
10/22
M27C512
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 6.
AC measurement conditions
High Speed
Standard
Input Rise and Fall Times
≤ 10ns
0 to 3V
1.5V
≤ 20ns
Input Pulse Voltages
0.4V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 5.
Testing input/output waveform
High Speed
3V
1.5V
0V
Standard
2.4V
2.0V
0.8V
0.4V
AI01822
Figure 6.
AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
OUT
C
L
C
C
C
= 30pF for High Speed
L
L
L
= 100pF for Standard
includes JIG capacitance
AI01823B
11/22
DC and AC parameters
M27C512
Unit
Table 7.
Symbol
Capacitance
Parameter
Test Condition(1)(2)
Min
Max
CIN
Input Capacitance
Output Capacitance
VIN = 0V
6
pF
pF
COUT
VOUT = 0V
12
1. TA = 25°C, f = 1MHz
2. Sampled only, not 100% tested.
Table 8.
Symbol
Read mode DC characteristics
Parameter
Test Condition(1)
Min
Max
Unit
ILI
Input Leakage Current
Output Leakage Current
0V ≤ VIN ≤ VCC
±10
±10
µA
µA
ILO
0V ≤ VOUT ≤ VCC
E = VIL, G = VIL,
IOUT = 0mA, f = 5MHz
ICC
Supply Current
30
mA
ICC1
ICC2
IPP
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
E = VIH
E > VCC – 0.2V
VPP = VCC
1
100
mA
µA
µA
V
10
VIL
Input Low Voltage
–0.3
2
0.8
(2)
VIH
Input High Voltage
VCC + 1
0.4
V
VOL
VOH
Output Low Voltage
IOL = 2.1mA
IOH = –1mA
IOH = –100µA
V
Output High Voltage TTL
Output High Voltage CMOS
3.6
V
VCC – 0.7V
V
1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
2. Maximum DC voltage on Output is VCC +0.5V.
.
12/22
M27C512
Table 9.
DC and AC parameters
Read mode AC characteristics
M27C512
Symbol
Alt
Parameter
Test Condition(1)
-45(2)
Min Max
-70
Unit
Min
Max
Address Valid to Output
Valid
tAVQV
tELQV
tGLQV
tACC
tCE
tOE
tDF
E = VIL, G = VIL
G = VIL
45
45
25
25
25
70
ns
ns
ns
ns
ns
ns
Chip Enable Low to
Output Valid
70
35
30
30
Output Enable Low to
Output Valid
E = VIL
Chip Enable High to
Output Hi-Z
(3)
tEHQZ
G = VIL
0
0
0
0
0
0
Output Enable High to
Output Hi-Z
(3)
tGHQZ
tDF
E = VIL
Address Transition to
Output Transition
tAXQX
tOH
E = VIL, G = VIL
1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
2. Speed obtained with High Speed AC measurement conditions.
3. Sampled only, not 100% tested.
.
Table 10. Read mode AC characteristics
M27C512
Symbol Alt
Parameter
Test Condition(1)
-90
-10
-12
-15
Unit
Min Max Min Max Min Max Min Max
Address Valid to
Output Valid
tAVQV
tELQV
tGLQV
tACC
E = VIL, G = VIL
G = VIL
90
90
40
30
100
100
40
120
120
50
150
150
60
ns
ns
ns
ns
Chip Enable Low
to Output Valid
tCE
tOE
tDF
Output Enable Low
to Output Valid
E = VIL
Chip Enable High
to Output Hi-Z
(2)
tEHQZ
G = VIL
0
0
0
0
30
0
0
40
0
0
50
Output Enable
tDF High to Output Hi-
Z
(2)
tGHQZ
E = VIL
30
30
40
50
ns
ns
Address Transition
tOH to Output
Transition
tAXQX
E = VIL, G = VIL
0
0
0
0
1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
2. Sampled only, not 100% tested.
.
13/22
DC and AC parameters
M27C512
Figure 7.
Read mode AC waveforms
VALID
tAVQV
VALID
A0-A15
E
tAXQX
tEHQZ
tGHQZ
tGLQV
G
tELQV
Hi-Z
Q0-Q7
AI00735B
Table 11. Programming mode DC characteristics
Symbol
Parameter
Test Condition(1)(2)
Min
Max
Unit
ILI
ICC
IPP
Input Leakage Current
Supply Current
VIL ≤ VIN ≤ VIH
±10
50
µA
mA
mA
V
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
A9 Voltage
E = VIL
50
VIL
–0.3
2
0.8
VIH
VOL
VOH
VID
VCC + 0.5
0.4
V
IOL = 2.1mA
IOH = –1mA
V
3.6
V
11.5
12.5
V
1. TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V
2. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
Table 12. Margin Mode AC Characteristics
Test
Symbol
Alt
Parameter
Min
Max
Unit
Condition(1)(2)
tA9HVPH
tVPHEL
tA10HEH
tA10LEH
tAS9
tVPS
VA9 High to VPP High
VPP High to Chip Enable Low
2
2
1
1
µs
µs
µs
µs
tAS10 VA10 High to Chip Enable High (Set)
tAS10 VA10 Low to Chip Enable High (Reset)
Chip Enable Transition to VA10
Transition
tEXA10X
tAH10
1
µs
Chip Enable Transition to VPP
Transition
tEXVPX
tVPH
2
2
µs
µs
tVPXA9X
tAH9
VPP Transition to VA9 Transition
1. TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V
2. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
14/22
M27C512
Figure 8.
DC and AC parameters
Margin mode AC waveforms
V
CC
A8
A9
GV
E
tA9HVPH
tVPXA9X
PP
tVPHEL
tEXVPX
tA10HEH
tEXA10X
A10 Set
A10 Reset
tA10LEH
AI00736B
1. A8 High level = 5V; A9 High level = 12V.
15/22
DC and AC parameters
M27C512
Unit
Table 13. Programming mode AC characteristics
Test
Symbol
Alt
Parameter
Min
Max
Condition(1)(2)
tAVEL
tQVEL
tAS
tDS
Address Valid to Chip Enable Low
Input Valid to Chip Enable Low
VCC High to Chip Enable Low
VPP High to Chip Enable Low
VPP Rise Time
2
2
µs
µs
µs
µs
ns
tVCHEL
tVPHEL
tVPLVPH
tVCS
tOES
tPRT
2
2
50
Chip Enable Program Pulse Width
(Initial)
tELEH
tPW
tDH
95
105
µs
tEHQX
tEHVPX
tVPLEL
tELQV
Chip Enable High to Input Transition
2
2
2
µs
µs
µs
µs
ns
ns
tOEH Chip Enable High to VPP Transition
tVR
tDV
tDFP
tAH
VPP Low to Chip Enable Low
Chip Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Chip Enable High to Address Transition
1
(3)
tEHQZ
0
0
130
tEHAX
1. TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V
2. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
3. Sampled only, not 100% tested.
.
Figure 9.
Programming and Verify modes AC waveforms
A0-A15
VALID
tAVEL
tEHAX
DATA IN
Q0-Q7
DATA OUT
tQVEL
tVCHEL
tVPHEL
tEHQX
tEHQZ
V
CC
tELQV
tEHVPX
GV
PP
tVPLEL
E
tELEH
PROGRAM
VERIFY
AI00737
16/22
M27C512
Package mechanical
6
Package mechanical
Figure 10. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Outline
A2
A3
A1
A
L
α
B1
B
e
C
eA
eB
D2
D
S
N
1
E1
E
FDIPW-a
1. Drawing is not to scale.
Table 14. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
A3
B
5.72
1.40
4.57
4.50
0.56
–
0.225
0.055
0.180
0.177
0.022
–
0.51
3.91
3.89
0.41
–
0.020
0.154
0.153
0.016
–
B1
C
1.45
0.057
0.23
36.50
–
0.30
37.34
–
0.009
1.437
–
0.012
1.470
–
D
D2
E
33.02
15.24
1.300
0.600
–
–
–
–
E1
e
13.06
–
13.36
–
0.514
–
0.526
–
2.54
0.100
0.590
eA
eB
L
14.99
–
–
–
–
16.18
3.18
1.52
–
18.03
4.10
2.49
–
0.637
0.125
0.060
–
0.710
0.161
0.098
–
S
∅
7.11
0.280
α
4°
11°
4°
11°
N
28
28
17/22
Package mechanical
M27C512
Figure 11. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
1. Drawing is not to scale.
Table 15. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
B
4.445
0.630
3.810
0.450
1.270
0.1750
0.0248
0.1500
0.0177
0.0500
3.050
4.570
0.1201
0.1799
B1
C
0.230
36.580
–
0.310
37.080
–
0.0091
1.4402
–
0.0122
1.4598
–
D
36.830
33.020
15.240
13.720
2.540
1.4500
1.3000
0.6000
0.5402
0.1000
0.5906
D2
E
E1
e1
eA
eB
L
12.700
–
14.480
–
0.5000
–
0.5701
–
15.000
14.800
15.200
15.200
16.680
0.5827
0.5984
0.5984
0.6567
3.300
0.1299
S
1.78
0°
2.08
10°
0.070
0°
0.082
10°
α
N
28
28
18/22
M27C512
Package mechanical
Figure 12. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline
D
A1
D1
A2
1
N
B1
e
E2
E2
E3
E1 E
F
B
0.51 (.020)
1.14 (.045)
D3
A
R
CP
D2
D2
PLCC-A
1. Drawing is not to scale.
Table 16. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
B
3.18
1.53
0.38
0.33
0.66
3.56
2.41
–
0.125
0.060
0.015
0.013
0.026
0.140
0.095
–
0.53
0.81
0.10
12.57
11.51
5.66
–
0.021
0.032
0.004
0.495
0.453
0.223
–
B1
CP
D
12.32
11.35
4.78
–
0.485
0.447
0.188
–
D1
D2
D3
E
7.62
0.300
14.86
13.89
6.05
–
15.11
14.05
6.93
–
0.585
0.547
0.238
–
0.595
0.553
0.273
–
E1
E2
E3
e
10.16
1.27
0.400
0.050
–
–
–
–
F
0.00
–
0.13
–
0.000
–
0.005
–
R
0.89
0.035
N
32
32
19/22
Part numbering
M27C512
7
Part numbering
Table 17. Ordering Information Scheme
Example:
M27C512
-70
X C 1
Device Type
M27
Supply Voltage
C = 5V
Device Function
512 = 512 Kbit (64Kb x8)
Speed
-45 = 45 ns(1)
-70 = 70 ns
-90 = 90 ns
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
VCC Tolerance
blank = ± 10%
X = ± 5%
Package
F = FDIP28W
B = PDIP28
C = PLCC32
Temperature Range
1 = 0 to 70 °C
3 = –40 to 125 °C
6 = –40 to 85 °C
1. High Speed, see AC Characteristics section for further information.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST Sales Office.
20/22
M27C512
Revision history
8
Revision history
Table 18. Document revision history
Date
Revision
Changes
November
1998
1.0
First Issue
25-Sep-2000
02-Apr-2001
1.1
1.2
AN620 Reference removed
FDIP28W mechanical dimensions changed (<Blue>Table 14.)
Package mechanical data clarified for PDIP28 (Table 15),
PLCC32 (Table 16, Figure 12) and TSOP28 (Table 16., Figure 7.)
29-Aug-2002
08-Nov-2004
1.3
2.0
Details of ECOPACK lead-free package options added.
Additional Burn-in option removed
ECOPACK lead-free text updated in Section 1: Description. TLEAD
and Note 1 removed from Table 5: Absolute maximum ratings.
TSOP28 package removed.
18-May-2007
3
60, 80, 200 and 250 access times removed from the whole
document.
Blank, TR, E, and F Options removed from Table 17: Ordering
Information Scheme.
21/22
M27C512
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