M27512-3F1 [STMICROELECTRONICS]
NMOS 512K 64K x 8 UV EPROM; NMOS 512K 64K ×8 UV EPROM
| 型号： | M27512-3F1 |
| 厂家： | 
ST |
| 描述： | NMOS 512K 64K x 8 UV EPROM |
| 文件： | 总11页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M27512
NMOS 512 Kbit (64Kb x 8) UV EPROM
NOT FOR NEW DESIGN
■ FAST ACCESS TIME: 200ns
■ EXTENDED TEMPERATURE RANGE
■ SINGLE 5V SUPPLY VOLTAGE
■ LOW STANDBY CURRENT: 40mA max
■ TTL COMPATIBLE DURING READ and
PROGRAM
28
■ FAST PROGRAMMING ALGORITHM
■ ELECTRONIC SIGNATURE
1
■ PROGRAMMING VOLTAGE: 12V
FDIP28W (F)
DESCRIPTION
The M27512 is a 524,288 bit UV erasable and
electrically programmable memory EPROM. It is
organized as 65,536 words by 8 bits.
The M27512 is housed in a 28 Pin Window Ce-
ramic Frit-Seal Dual-in-Line package. The trans-
parent lid allows the user to expose the chip to
ultraviolet light to erase the bit pattern. A new pat-
tern can then be written to the device by following
the programming procedure.
Figure 1. Logic Diagram
V
CC
16
8
A0-A15
E
Q0-Q7
M27512
GV
PP
V
SS
AI00765B
November 2000
1/11
This is information on a product still in production but not recommended for new designs.
M27512
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Grade 1
Grade 6
0 to 70
–40 to 85
TA
Ambient Operating Temperature
Temperature Under Bias
°C
Grade 1
Grade 6
–10 to 80
–50 to 95
TBIAS
°C
TSTG
VIO
Storage Temperature
Input or Output Voltages
Supply Voltage
–65 to 125
–0.6 to 6.5
–0.6 to 6.5
–0.6 to 13.5
–0.6 to 14
°C
V
VCC
VA9
VPP
V
A9 Voltage
V
Program Supply
V
Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause
permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those
indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document.
Read Mode
Figure 2. DIP Pin Connections
The M27512 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, inde-
pendent of device selection. Assuming that the
A15
A12
A7
1
2
3
4
5
6
7
8
9
28
V
CC
27 A14
26 A13
25 A8
24 A9
23 A11
A6
A5
addresses are stable, address access time (tAVQV
)
A4
is equal to the delay from E to output (tELQV). Data
is available at the outputs after delay of tGLQV from
the falling edge ofG, assuming thatE has been low
and the addresses have been stable for at least
A3
22 GV
PP
21 A10
20
M27512
A2
A1
E
tAVQV-tGLQV
.
A0 10
Q0 11
Q1 12
Q2 13
19 Q7
18 Q6
17 Q5
16 Q4
15 Q3
Standby Mode
The M27512 has a standby mode which reduces
the maximum active power current from 125mA to
40mA. The M27512 is placed in the standby mode
by applying a TTL high signal to the E input. When
in the standby mode, the outputs are in a high
impedance state, independent of the GVPP input.
V
14
SS
AI00766
Two Line Output Control
Because EPROMs are usually used in larger mem-
ory arrays, the product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows :
DEVICE OPERATION
The six modes of operations of the M27512 are
listed in the Operating Modes table. A single 5V
power supply is required in the read mode. All
inputs are TTL levels except for GVPP and 12V on
A9 for Electronic Signature.
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
2/11
M27512
DEVICE OPERATION (cont’d)
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
For the most efficient use of these two control lines,
E should be decoded and used as the primary
device selecting function, while GVPP should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all dese-
lected memory devices are in their low power
standby mode and that the output pins are only
active when data is required from aparticularmem-
ory device.
Programming
When delivered, and after each erasure, all bits of
the M27512 are in the “1" state. Data is introduced
by selectively programming ”0s" into the desired bit
locations. Although only “0s” will be programmed,
both “1s” and “0s” can be present in the data word.
The only way to change a“0"toa ”1"isby ultraviolet
light erasure. The M27512 is in the programming
mode when GVPP input is at 12.5V and E is at
TTL-low. The data to be programmed is applied 8
bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL.
The M27512 can use PRESTO ProgrammingAlgo-
rithm that drastically reduces the programming
time (typically less than 50 seconds). Nevertheless
to achieve compatibility with all programming
equipment, the standard Fast Programming Algo-
rithm may also be used.
System Considerations
The power switching characteristics of fast
EPROMs require carefuldecouplingofthedevices.
The supply current, ICC, has three segments that
are of interest to the system designer : the standby
current level, the active current level, and transient
current peaks that are produced by the falling and
rising edges of E. The magnitude of the transient
current peaks is dependent on the capacitive and
inductive loading of the device at the output. The
associated transient voltage peaks can be sup-
pressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommenced that a 1µF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7µF bulk electrolytic capacitor should be used
between VCC and VSS for every eight devices. The
Fast Programming Algorithm
Fast Programming Algorithm rapidly programs
M27512 EPROMs using an efficient and reliable
method suited to the production programming en-
vironment. Programming reliability is also ensured
as the incremental program margin of each byte is
continually monitored to determine when it has
been successfully programmed. A flowchart of the
M27512 Fast Programming Algorithm is shown in
Figure 8.
Table 3. Operating Modes
Mode
E
VIL
GVPP
VIL
A9
X
Q0 - Q7
Data Out
Hi-Z
Read
Output Disable
Program
VIL
VIH
VPP
VIL
X
V
IL Pulse
X
Data In
Data Out
Hi-Z
Verify
VIH
X
Program Inhibit
Standby
VIH
VPP
X
X
VIH
X
Hi-Z
Electronic Signature
VIL
VIL
VID
Codes
Note: X = VIH or VIL, VID = 12V ± 0.5%.
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
VIL
VIH
Q7
Q6
0
Q5
1
Q4
Q3
0
Q2
Q1
0
Q0
0
Hex Data
0
0
0
0
0
1
20h
0
0
1
0
1
0Dh
3/11
M27512
Figure 4. AC Testing Load Circuit
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
≤ 20ns
1.3V
Input Pulse Voltages
0.45V to 2.4V
0.8V to 2.0V
Input and Output Timing Ref. Voltages
1N914
Note that Output Hi-Z is defined as the point where data
is no longer driven.
3.3kΩ
Figure 3. AC Testing Input Output Waveforms
DEVICE
UNDER
TEST
OUT
2.4V
2.0V
C
= 100pF
L
0.8V
0.45V
AI00827
C
includes JIG capacitance
L
AI00828
Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
6
Unit
pF
COUT
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
VALID
A0-A15
tAVQV
tAXQX
E
tEHQZ
tGHQZ
tGLQV
G
tELQV
Hi-Z
Q0-Q7
DATA OUT
AI00735
4/11
M27512
Table 6. Read Mode DC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC
)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Test Condition
0 ≤ VIN ≤ VCC
VOUT = VCC
Min
Max
±10
Unit
µA
µA
mA
mA
V
ILO
±10
ICC
E = VIL, G = VIL
E = VIH
125
ICC1
VIL
Supply Current (Standby)
Input Low Voltage
40
–0.1
2
0.8
VIH
Input High Voltage
VCC + 1
0.45
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 2.1mA
V
IOH = –400µA
2.4
V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
Table 7. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC
)
M27512
Test
Condition
Symbol
Alt
Parameter
Unit
-2, -20
blank,-25
-3
Min Max Min Max Min Max
E = VIL,
G = VIL
tAVQV
tACC Address Valid to Output Valid
200
250
300
ns
tELQV
tGLQV
tCE
tOE
tDF
tDF
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
G = VIL
E = VIL
G = VIL
E = VIL
200
75
250
100
60
300
120
105
105
ns
ns
ns
ns
(2)
tEHQZ
0
0
55
0
0
0
0
(2)
tGHQZ
55
60
Address Transition to Output
Transition
E = VIL,
G = VIL
tAXQX
tOH
0
0
0
ns
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
2. Sampled only, not 100% tested.
Table 8. Programming Mode DC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol
ILI
Parameter
Input Leakage Current
Supply Current
Test Condition
Min
Max
±10
Unit
VIL ≤ VIN ≤ VIH
µA
mA
mA
V
ICC
150
IPP
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
A9 Voltage
E = VIL
50
VIL
–0.1
2
0.8
VIH
VCC + 1
0.45
V
VOL
VOH
VID
IOL = 2.1mA
V
IOH = –400µA
2.4
V
11.5
12.5
V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
5/11
M27512
Table 9. MARGIN MODE AC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol
tA9HVPH
tVPHEL
Alt
tAS9
tVPS
Parameter
Test Condition
Min
2
Max
Unit
µs
VA9 High to VPP High
VPP High to Chip Enable Low
2
µs
VA10 High to Chip Enable
High (Set)
tA10HEH
tA10LEH
tEXA10X
tEXVPX
tAS10
tAS10
tAH10
tVPH
tAH9
1
1
1
2
2
µs
µs
µs
µs
µs
VA10 Low to Chip Enable High
(Reset)
Chip Enable Transition to
VA10 Transition
Chip Enable Transition to VPP
Transition
VPP Transition to VA9
Transition
tVPXA9X
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
Table 10. Programming Mode AC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
Address Valid to Chip Enable
Low
tAVEL
tAS
2
µs
tQVEL
tVCHEL
tVPHEL
tVPLVPH
tDS
Input Valid to Chip Enable Low
VCC High to Chip Enable Low
VPP High to Chip Enable Low
VPP Rise Time
2
2
µs
µs
µs
ns
tVCS
tOES
tPRT
2
50
Chip Enable Program Pulse
Width (Initial)
tELEH
tELEH
tEHQX
tPW
tOPW
tDH
Note 2
Note 3
0.95
2.85
2
1.05
ms
ms
µs
Chip Enable Program Pulse
Width (Overprogram)
78.75
Chip Enable High to Input
Transition
Chip Enable High to VPP
Transition
tEHVPX
tVPLEL
tELQV
tOEH
tVR
2
2
µs
µs
µs
VPP Low to Chip Enable Low
Chip Enable Low to Output
Valid
tDV
1
Chip Enable High to Output Hi-
Z
(4)
tEHQZ
tDF
tAH
0
0
130
ns
Chip Enable High to Address
Transition
tEHAX
n s
Notes. 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
2. The Initial Program Pulse width tolerance is 1 ms ± 5%.
3. The length of the Over-program Pulse varies from 2.85 ms to 78.95 ms, depending on the multiplication value of the iteration counter.
4. Sampled only, not 100% tested.
6/11
M27512
Figure 6. MARGIN MODE AC Waveform
V
CC
A8
A9
tA9HVPH
tVPXA9X
GV
E
PP
tVPHEL
tEXVPX
tA10HEH
tEXA10X
A10 Set
A10 Reset
tA10LEH
AI00736B
Note: A8 High level = 5V; A9 High level = 12V.
Figure 7. Programming and Verify Modes AC Waveforms
A0-A15
Q0-Q7
VALID
tAVEL
tQVEL
tEHAX
DATA IN
DATA OUT
tEHQX
tEHQZ
V
CC
tELQV
tVCHEL
tVPHEL
tEHVPX
GV
PP
tVPLEL
E
tELEH
PROGRAM
VERIFY
AI00737
7/11
M27512
Figure 8. Fast Programming Flowchart
Figure 9. PRESTO Programming Flowchart
V
= 6.25V, V
= 12.75V
PP
CC
V
= 6V, V
= 12.5V
PP
CC
SET MARGIN MODE
n = 0
n = 1
E = 1ms Pulse
E = 500µs Pulse
NO
NO
NO
++n
> 25
VERIFY
YES
E = 3ms Pulse by n
++ Addr
NO
++n
= 25
VERIFY
++ Addr
YES
YES
YES
FAIL
Last
Addr
NO
FAIL
Last
NO
Addr
YES
YES
RESET MARGIN MODE
CHECK ALL BYTES
= 5V, V = 5V
V
CHECK ALL BYTES
CC
PP
V
= 5V, V
= 5V
PP
AI00774B
CC
AI00773B
DEVICE OPERATION (cont’d)
for reliability. Before starting the programming the
internal MARGIN MODE circuit is set in order to
guarantee that each cell is programmed with
enough margin.
Then a sequence of 500µs program pulses are
applied to each byte until a correct verify occurs.
No overprogram pulses are applied since the verify
in MARGIN MODE provides the necessary margin
to each programmed cell.
The Fast Programming Algorithmutilizes two differ-
ent pulse types : initial and overprogram. The du-
ration of the initial E pulse(s) is 1ms, which will then
be followedbyalongeroverprogrampulseoflength
3ms by n (n is an iteration counter and is equal to
the number of the initial one millisecond pulses
applied to a particular M27512 location), before a
correct verify occurs. Up to 25 one-millisecond
pulses per byte are provided for before the over
program pulse is applied.
The entire sequence of program pulses is per-
formed at VCC = 6V and GVPP = 12.5V (byte verifi-
cations atVCC = 6V and GVPP = VIL). When the Fast
Programming cycle has been completed, all bytes
should be compared to the original data with
VCC = 5V.
Program Inhibit
Programming of multiple M27512s in parallel with
different data is also easily accomplished. Except
for E, all like inputs (including GVPP) of the parallel
M27512 may be common. A TTL low level pulse
applied to a M27512’sE input, with GVpp at 12.5V,
will program that M27512. A high level E input
inhibits the other M27512s from being pro-
grammed.
PRESTO Programming Algorithm
Program Verify
PRESTO Programming Algorithm allows to pro-
gram the whole array with a guaranted margin, in
a typical time of less than 50 seconds (to be com-
pared with 283 seconds for the Fast algorithm).
This can be achieved with the STMicroelectronics
M27512 due to several design innovations de-
scribed in the next paragraph that improves pro-
gramming efficiency and brings adequate margin
A verify (read) should be performed on the pro-
grammed bits to determine that they were correctly
programmed. The verify is accomplished withGVpp
and E at VIL. Data should be verified tDV after the
falling edge of E.
8/11
M27512
Electronic Signature
light with wavelengths shorter than approximately
4000 Å. It should be noted that sunlight and some
type of fluorescent lamps have wavelengths in the
3000-4000 Årange. Research shows that constant
exposure to room level fluorescent lighting could
erase a typical M27512 in about 3 years, while it
would take approximately 1 week to cause erasure
when expose to direct sunlight. If the M27512 is to
be exposed to these types of lighting conditions for
extended periods of time, it is suggested that
opaque labels be put over the M27512 window to
prevent unintentional erasure. The recommended
erasure procedure for the M27512 is exposure to
short wave ultraviolet light which has wavelength
2537 Å.
The integrated dose (i.e. UV intensity x exposure
time) for erasure should be a minimum of 15
W-sec/cm2. The erasure time with this dosage is
approximately 15 to 20 minutes using an ultraviolet
lamp with 12000 µW/cm2 power rating. The
M27512 should be placed within 2.5 cm (1 inch) of
the lamp tubes during the erasure. Some lamps
have a filter on their tubes which should be re-
moved before erasure.
The Electronic Signature mode allows the reading
out of a binary code from an EPROM that will
identify its manufacturer and type. This mode is
intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
This mode is functional in the 25°C± 5°Cambient
temperature range that is required when program-
ming the M27512. To activate this mode, the pro-
gramming equipment must force 11.5V to 12.5V on
address line A9 of the M27512. Two identifier bytes
may then be sequenced from the device outputs by
toggling address line A0 from VIL to VIH. All other
address lines must be held at V during Electronic
Signature mode, except for A14 and A15 which
should be high. Byte 0 (A0 = VIL) represents the
manufacturer code and byte 1 (A0 = V ) thedevice
identifier code.
IL
IH
ERASURE OPERATION (applies to UV EPROM)
The erasure characteristic of the M27512 is such
that erasure begins when the cells are exposed to
ORDERING INFORMATION SCHEME
Example:
M27512
-2
F
1
Speed and VCC Tolerance
Package
Temperature Range
-2
blank
-3
200 ns, 5V ±5%
250 ns, 5V ±5%
300 ns, 5V ±5%
200 ns, 5V ±10%
250 ns, 5V ±10%
F
FDIP28W
1
6
0 to 70 °C
–40 to 85 °C
-20
-25
For a list of available options (Speed, VCC Tolerance, Package, etc) refer to the current Memory Shortform
catalogue.
For further inform ation o n any aspect of this device, please cont act STMicroelectronics Sales Office nearest
to you.
9/11
M27512
FDIP28W - 28 pin Ceramic Frit-seal DIP, with window
mm
Min
inches
Min
Symb
Typ
Max
5.71
1.78
5.08
0.55
1.42
0.31
38.10
15.80
13.36
–
Typ
Max
0.225
0.070
0.200
0.022
0.056
0.012
1.500
0.622
0.526
–
A
A1
A2
B
0.50
3.90
0.40
1.17
0.22
0.020
0.154
0.016
0.046
0.009
B1
C
D
E
15.40
13.05
–
0.606
0.514
–
E1
e1
e3
eA
L
2.54
0.100
1.300
33.02
–
–
–
–
16.17
3.18
1.52
–
18.32
4.10
2.49
–
0.637
0.125
0.060
–
0.721
0.161
0.098
–
S
7.11
0.280
α
4°
15°
4°
15°
N
2
8
28
A2
A
A1
e1
L
B1
B
α
C
eA
e3
D
S
N
1
E1
E
FDIPW-a
Drawing is not to scale
10/11
M27512
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
2000 STMicroelectronics - All Rights Reserved
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www.st.com
11/11
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